Multilayer ceramic capacitor, package, and circuit board

Abstract

The present invention provides a multilayer ceramic capacitor having a dimension in a first axial direction of 1.5 times or more of a dimension in a second axial direction, the multilayer ceramic capacitor including a ceramic body and a pair of external electrodes. The ceramic body has: a laminated part having a plurality of internal electrodes laminated alternately with the ceramic layers in a lamination direction parallel to a first axis or a second axis; and a pair of edge parts which cover the laminated part from the width direction of the internal electrode, and which contain an additive element comprising at least one of Mg, Mn, Zr, Ti, Li, Mo, Nb, Cu, a rare earth element and Sn at a higher concentration than the laminated part. The plurality of internal electrodes are configured from a plurality of inner-layer internal electrodes and a plurality of outer-layer internal electrodes having a maximum width dimension smaller than a minimum width dimension of the inner-layer internal electrodes.

Description

Technical Field

[0001] The present invention relates to a high-profile multilayer ceramic capacitor. Background Art

[0002] In recent years, electronic devices such as portable information terminals have been miniaturized, and the mounting area of ​​multilayer ceramic capacitors on circuit boards has been limited. On the other hand, multilayer ceramic capacitors are required to have a higher capacity.

[0003] In order to realize the large capacity of the stacked ceramic capacitor, it is known to form a green sheet with a structure in which the internal electrode is exposed on the side, and a ceramic green sheet for the side is pasted on the side to form a ceramic protective layer (patent document 1). In such a technology, the green sheet with the internal electrode stacked is pressed by a method such as hydrostatic pressing, while the ceramic protective layer composed of the ceramic green sheet is not pressed. Therefore, after firing, the density of the ceramic protective layer tends to become lower than the density of the fired body (laminated portion) of the green sheet. In addition, in order to improve the bonding property of the green sheet, the ceramic green sheet for the side can contain a large amount of organic compounds such as adhesives. As a result, the density difference between the ceramic protective layer and the laminated portion may be further increased.

[0004] In order to solve such technical problems, there is a known technique for densifying the ceramic protective layer by adding Mg, Mn, Zr, Ti, Li, Mo, Nb, Cu, rare earth elements, etc. (Patent Document 2). Alternatively, there is also a known technique for adding Sn to the ceramic green sheet for the side surface in order to achieve both thinning of the ceramic protective layer and reliability (Patent Document 3).

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2012-209539

[0008] Patent Document 2: Japanese Patent Application Publication No. 2017-038036

[0009] Patent Document 3: Japanese Patent Application Publication No. 2021-044533 Summary of the invention

[0010] Technical problem to be solved by the invention

[0011] On the other hand, when elements such as Mg, Mn, Zr, Ti, Li, Mo, Nb, Cu, rare earth elements, and Sn are added to the ceramic green sheet on the side, the sinterability of the ceramic protective layer is improved, and the ceramic protective layer is easily shrunk by firing. As a result, the end of the internal electrode in contact with the ceramic protective layer is bent inward in the stacking direction, and the ends of the internal electrodes are easily in contact. As a result, the insulation resistance of the stacked ceramic capacitor may be reduced. The reduction in insulation resistance caused by such bending of the ends of the internal electrodes becomes more significant in a high-height structure with a large number of internal electrodes stacked.

[0012] In view of the above circumstances, an object of the present invention is to provide a multilayer ceramic capacitor, a package, and a circuit board that can suppress a decrease in insulation resistance in a high-profile structure.

[0013] Technical solutions for solving technical problems

[0014] To achieve the above object, a multilayer ceramic capacitor according to one embodiment of the present invention has a dimension in a first axis direction that is 1.5 times or more of a dimension in a second axis direction perpendicular to the first axis, and the multilayer ceramic capacitor can be mounted on a mounting surface perpendicular to the first axis.

[0015] The above-mentioned laminated ceramic capacitor includes a ceramic body and a pair of external electrodes.

[0016] The ceramic body has a pair of main surfaces perpendicular to the first axis, a pair of side surfaces perpendicular to the second axis, and a pair of end surfaces perpendicular to a third axis perpendicular to the first axis and the second axis.

[0017] The pair of external electrodes covers the pair of end surfaces.

[0018] The ceramic body further comprises:

[0019] a stacked portion having a plurality of internal electrodes alternately stacked with the ceramic layers along a stacking direction parallel to the first axis or the second axis and led out to the end surface; and

[0020] A pair of edge portions are formed along the above-mentioned stacking direction, covering the above-mentioned stacking portion from the width direction of the above-mentioned internal electrode orthogonal to the above-mentioned stacking direction and the above-mentioned third axis, and containing additive elements consisting of at least one of Mg, Mn, Zr, Ti, Li, Mo, Nb, Cu, rare earth elements or Sn at a higher concentration than the above-mentioned stacking portion.

[0021] The plurality of internal electrodes are composed of a plurality of inner layer internal electrodes located on the inner side in the stacking direction and a plurality of outer layer internal electrodes located on both outer sides in the stacking direction and having a maximum width dimension smaller than a minimum width dimension of the inner layer internal electrodes.

[0022] A multilayer ceramic capacitor according to another aspect of the present invention has a dimension in a first axis direction that is 1.3 times or more of a dimension in a second axis direction perpendicular to the first axis, and the multilayer ceramic capacitor can be mounted on a mounting surface perpendicular to the first axis.

[0023] The above-mentioned laminated ceramic capacitor includes a ceramic body and a pair of external electrodes.

[0024] The ceramic body has a pair of main surfaces perpendicular to the first axis, a pair of side surfaces perpendicular to the second axis, and a pair of end surfaces perpendicular to a third axis perpendicular to the first axis and the second axis.

[0025] The pair of external electrodes covers the pair of end surfaces.

[0026] The ceramic body further comprises:

[0027] a stacked portion having a plurality of internal electrodes alternately stacked with the ceramic layers along a stacking direction parallel to the first axis or the second axis and led out to the end surface; and

[0028] A pair of edge portions are formed along the above-mentioned stacking direction, covering the above-mentioned stacking portion from the width direction of the above-mentioned internal electrode orthogonal to the above-mentioned stacking direction and the above-mentioned third axis, and containing additive elements consisting of at least one of Mg, Mn, Zr, Ti, Li, Mo, Nb, Cu, rare earth elements or Sn at a higher concentration than the above-mentioned stacking portion.

[0029] The plurality of internal electrodes are composed of a plurality of inner layer internal electrodes located on the inner side in the stacking direction and a plurality of outer layer internal electrodes located on both outer sides in the stacking direction and having a maximum width dimension smaller than a minimum width dimension of the inner layer internal electrodes.

[0030] In the above structure, the maximum width dimension of the outer internal electrode is smaller than the minimum width dimension of the inner internal electrode, so the end of the outer internal electrode in the width direction can be spaced apart from the edge portion. As a result, even if the edge portion shrinks in the stacking direction due to the influence of the added element during firing, the end of the outer internal electrode can be prevented from bending inward in the stacking direction as the edge portion shrinks. Therefore, short circuits at the ends of the outer internal electrode can be prevented, and poor insulation of the laminated ceramic capacitor can be prevented.

[0031] For example, the maximum width dimension of the outer layer internal electrode may be at least twice the thickness dimension of the edge portion.

[0032] Furthermore, for example, the maximum width dimension of the outer layer internal electrode may be 10 times or less the thickness dimension of the edge portion.

[0033] For example, the distance between the end portion of the outer layer internal electrode in the width direction and the edge portion in the width direction may be greater than the thickness dimension of the edge portion.

[0034] Furthermore, for example, the distance between the end portion of the outer layer internal electrode in the width direction and the edge portion in the width direction may be 5 times or less of the thickness dimension of the edge portion.

[0035] For example, the number of stacked outer internal electrodes on one side in the stacking direction may be 5% or more and 25% or less of the number of stacked all internal electrodes.

[0036] In addition, the stacking direction may be parallel to the second axis.

[0037] The width direction of the internal electrode is parallel to the first axis.

[0038] In this structure, the cross-sectional area of ​​the internal electrode can be increased compared to the case where the width direction of the internal electrode is parallel to the second axis. Thus, the area of ​​the internal electrode exposed at the end surface can be increased, and poor connection between the internal electrode and the external electrode can be suppressed.

[0039] In this case, the main surface may have a higher flatness than the side surface.

[0040] This can improve the flatness of the main surface facing the mounting surface, and can improve the mounting stability of the multilayer ceramic capacitor.

[0041] A package body according to another embodiment of the present invention includes a multilayer ceramic capacitor, a carrier tape, and a top tape.

[0042] The multilayer ceramic capacitor has a dimension in a first axis direction that is 1.5 times or more of a dimension in a second axis direction perpendicular to the first axis, and the multilayer ceramic capacitor can be mounted on a mounting surface perpendicular to the first axis.

[0043] The above-mentioned laminated ceramic capacitor includes a ceramic body and a pair of external electrodes.

[0044] The ceramic body has a pair of main surfaces perpendicular to the first axis, a pair of side surfaces perpendicular to the second axis, and a pair of end surfaces perpendicular to a third axis perpendicular to the first axis and the second axis.

[0045] The pair of external electrodes covers the pair of end surfaces.

[0046] The ceramic body further comprises:

[0047] a stacked portion having a plurality of internal electrodes alternately stacked with the ceramic layers along a stacking direction parallel to the first axis or the second axis and led out to the end surface; and

[0048] A pair of edge portions are formed along the above-mentioned stacking direction, covering the above-mentioned stacking portion from the width direction of the above-mentioned internal electrode orthogonal to the above-mentioned stacking direction and the above-mentioned third axis, and containing additive elements consisting of at least one of Mg, Mn, Zr, Ti, Li, Mo, Nb, Cu, rare earth elements or Sn at a higher concentration than the above-mentioned stacking portion.

[0049] The plurality of internal electrodes are composed of a plurality of inner layer internal electrodes located on the inner side in the stacking direction and a plurality of outer layer internal electrodes located on both outer sides in the stacking direction and having a maximum width dimension smaller than a minimum width dimension of the inner layer internal electrodes.

[0050] The carrier tape includes: a sealing surface perpendicular to the first axis; and a recessed portion recessed from the sealing surface in the first axis direction and accommodating the multilayer ceramic capacitor.

[0051] The top tape is adhered to the sealing surface to cover the recessed portion.

[0052] A package body according to another embodiment of the present invention includes a multilayer ceramic capacitor, a carrier tape, and a top tape.

[0053] The multilayer ceramic capacitor has a dimension in a first axis direction that is 1.3 times or more of a dimension in a second axis direction perpendicular to the first axis, and the multilayer ceramic capacitor can be mounted on a mounting surface perpendicular to the first axis.

[0054] The above-mentioned laminated ceramic capacitor includes a ceramic body and a pair of external electrodes.

[0055] The ceramic body has a pair of main surfaces perpendicular to the first axis, a pair of side surfaces perpendicular to the second axis, and a pair of end surfaces perpendicular to a third axis perpendicular to the first axis and the second axis.

[0056] The pair of external electrodes covers the pair of end surfaces.

[0057] The ceramic body further comprises:

[0058] a stacked portion having a plurality of internal electrodes alternately stacked with the ceramic layers along a stacking direction parallel to the first axis or the second axis and led out to the end surface; and

[0059] A pair of edge portions are formed along the above-mentioned stacking direction, covering the above-mentioned stacking portion from the width direction of the above-mentioned internal electrode orthogonal to the above-mentioned stacking direction and the above-mentioned third axis, and containing additive elements consisting of at least one of Mg, Mn, Zr, Ti, Li, Mo, Nb, Cu, rare earth elements or Sn at a higher concentration than the above-mentioned stacking portion.

[0060] The plurality of internal electrodes are composed of a plurality of inner layer internal electrodes located on the inner side in the stacking direction and a plurality of outer layer internal electrodes located on both outer sides in the stacking direction and having a maximum width dimension smaller than a minimum width dimension of the inner layer internal electrodes.

[0061] The carrier tape includes: a sealing surface perpendicular to the first axis; and a recessed portion recessed from the sealing surface in the first axis direction and accommodating the multilayer ceramic capacitor.

[0062] The top tape is adhered to the sealing surface to cover the recessed portion.

[0063] A circuit board according to another embodiment of the present invention includes a multilayer ceramic capacitor and a mounting substrate.

[0064] The multilayer ceramic capacitor has a dimension in a first axis direction that is 1.5 times or more the dimension in a second axis direction that is perpendicular to the first axis.

[0065] The above-mentioned laminated ceramic capacitor includes a ceramic body and a pair of external electrodes.

[0066] The ceramic body has a pair of main surfaces perpendicular to the first axis, a pair of side surfaces perpendicular to the second axis, and a pair of end surfaces perpendicular to a third axis perpendicular to the first axis and the second axis.

[0067] The pair of external electrodes covers the pair of end surfaces.

[0068] The ceramic body further comprises:

[0069] a stacked portion having a plurality of internal electrodes alternately stacked with the ceramic layers along a stacking direction parallel to the first axis or the second axis and led out to the end surface; and

[0070] A pair of edge portions are formed along the above-mentioned stacking direction, covering the above-mentioned stacking portion from the width direction of the above-mentioned internal electrode orthogonal to the above-mentioned stacking direction and the above-mentioned third axis, and containing additive elements consisting of at least one of Mg, Mn, Zr, Ti, Li, Mo, Nb, Cu, rare earth elements or Sn at a higher concentration than the above-mentioned stacking portion.

[0071] The plurality of internal electrodes are composed of a plurality of inner layer internal electrodes located on the inner side in the stacking direction and a plurality of outer layer internal electrodes located on both outer sides in the stacking direction and having a maximum width dimension smaller than a minimum width dimension of the inner layer internal electrodes.

[0072] The mounting substrate includes: a mounting surface perpendicular to the first axis; and a pair of connection electrodes provided on the mounting surface and connected to the pair of external electrodes of the multilayer ceramic capacitor via solder.

[0073] A circuit board according to another embodiment of the present invention includes a multilayer ceramic capacitor and a mounting substrate.

[0074] A dimension of the multilayer ceramic capacitor in a first axis direction is 1.3 times or more of a dimension in a second axis direction perpendicular to the first axis.

[0075] The above-mentioned laminated ceramic capacitor includes a ceramic body and a pair of external electrodes.

[0076] The ceramic body has a pair of main surfaces perpendicular to the first axis, a pair of side surfaces perpendicular to the second axis, and a pair of end surfaces perpendicular to a third axis perpendicular to the first axis and the second axis.

[0077] The pair of external electrodes covers the pair of end surfaces.

[0078] The ceramic body further comprises:

[0079] a stacked portion having a plurality of internal electrodes alternately stacked with the ceramic layers along a stacking direction parallel to the first axis or the second axis and led out to the end surface; and

[0080] A pair of edge portions are formed along the above-mentioned stacking direction, covering the above-mentioned stacking portion from the width direction of the above-mentioned internal electrode orthogonal to the above-mentioned stacking direction and the above-mentioned third axis, and containing additive elements consisting of at least one of Mg, Mn, Zr, Ti, Li, Mo, Nb, Cu, rare earth elements or Sn at a higher concentration than the above-mentioned stacking portion.

[0081] The plurality of internal electrodes are composed of a plurality of inner layer internal electrodes located on the inner side in the stacking direction and a plurality of outer layer internal electrodes located on both outer sides in the stacking direction and having a maximum width dimension smaller than a minimum width dimension of the inner layer internal electrodes.

[0082] The mounting substrate includes: a mounting surface perpendicular to the first axis; and a pair of connection electrodes provided on the mounting surface and connected to the pair of external electrodes of the multilayer ceramic capacitor via solder.

[0083] Effects of the Invention

[0084] As described above, according to the present invention, a multilayer ceramic capacitor, a package, and a circuit board capable of suppressing a decrease in insulation resistance in a high-profile structure can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] Figure 1 It is a perspective view of a multilayer ceramic capacitor according to a first embodiment of the present invention.

[0086] Figure 2 The above-mentioned multilayer ceramic capacitor is along Figure 1 Cross-sectional view of line A-A'.

[0087] Figure 3 The above-mentioned multilayer ceramic capacitor is along Figure 1 Cross-sectional view of line BB'.

[0088] Figure 4 FIG. 1 is a diagram showing a partially exploded view of a ceramic body of the multilayer ceramic capacitor.

[0089] Figure 5 is a cross-sectional view of a multilayer ceramic capacitor according to a comparative example of the above-mentioned embodiment, and is a view showing Figure 3 Same cross-section diagram.

[0090] Figure 6 : is a flowchart showing a method for manufacturing the above-mentioned multilayer ceramic capacitor.

[0091] Fig. 7A and Figure 7B Each of them is a plan view of the ceramic sheet prepared in step S01.

[0092] Fig. 8A and Figure 8B is a plan view of the ceramic sheet prepared in step S01.

[0093] Fig. 9 is a plan view of the ceramic sheet prepared in step S01.

[0094] Fig.10 It is a schematic diagram showing step S02.

[0095] Fig.11 It is a plan view showing step S03.

[0096] Fig. 12A , Fig. 12B and Fig. 12C Each of them is a cross-sectional view showing step S03.

[0097] Fig.13A and Fig. 13B Each of them is a cross-sectional view showing step S04.

[0098] Fig.14This is a side view of a circuit board including the above-mentioned multilayer ceramic capacitor.

[0099] Fig.15 It is a partial plan view of the package of the above-mentioned multilayer ceramic capacitor.

[0100] Fig.16 The packaging body is along Fig.15 Cross-sectional view of the C-C' line.

[0101] Fig.17 The multilayer ceramic capacitor according to the second embodiment of the present invention is Figure 1 Cross-sectional view of line BB'.

[0102] Fig.18 The above-mentioned multilayer ceramic capacitor is along Figure 1 Cross-sectional view of the D-D' line.

[0103] Fig.19 FIG. 1 is a diagram showing a partially exploded view of a ceramic body of the multilayer ceramic capacitor.

[0104] Fig. 20A and Fig. 20B Each of them is a plan view of a ceramic sheet prepared in step S01 of the method for manufacturing the multilayer ceramic capacitor.

[0105] Fig.21A and Fig. 21B Each of them is a plan view of a ceramic sheet prepared in step S01 of the method for manufacturing the multilayer ceramic capacitor.

[0106] Fig. 22 : is a plan view of the ceramic sheet prepared in step S01 of the manufacturing method of the above-mentioned laminated ceramic capacitor.

[0107] Fig.23 1 is a schematic diagram showing step S02 of the method for manufacturing the multilayer ceramic capacitor.

[0108] Fig.24A and Fig. 24B are partial cross-sectional views for explaining a method for calculating the flatness of the main surface and the side surface of the above-mentioned multilayer ceramic capacitor, Fig.24A is a diagram showing a cross section of the central portion of the main surface, Fig. 24B It is a figure which shows the cross section of the center part of a side surface. DETAILED DESCRIPTION

[0109] Hereinafter, a multilayer ceramic capacitor 10 according to an embodiment of the present invention will be described with reference to the drawings. In the drawings, mutually orthogonal X-axis, Y-axis, and Z-axis are appropriately indicated. The X-axis, Y-axis, and Z-axis define a fixed coordinate system fixed to the multilayer ceramic capacitor 10.

[0110] <First Embodiment>

[0111] [Structure of Multilayer Ceramic Capacitor 10]

[0112] Figure 1 to Figure 3 FIG. 1 is a diagram showing a multilayer ceramic capacitor 10 according to an embodiment of the present invention. Figure 1 It is a perspective view of the multilayer ceramic capacitor 10 . Figure 2 The multilayer ceramic capacitor 10 is Figure 1 Cross-sectional view of line A-A'. Figure 3 The multilayer ceramic capacitor 10 is Figure 1 Cross-sectional view of line BB'.

[0113] Figure 2 , Figure 3 1 shows a longitudinal cross section of a region including a central portion of the multilayer ceramic capacitor 10. Specifically, Figure 2 FIG. 1 shows a cross section along the XZ plane of the center portion of the multilayer ceramic capacitor 10 in the Y-axis direction. Figure 3 FIG. 1 shows a cross section of the center portion of the multilayer ceramic capacitor 10 in the X-axis direction along the YZ plane.

[0114] The multilayer ceramic capacitor 10 includes a ceramic body 11, a first external electrode 14, and a second external electrode 15. The ceramic body 11 is configured as a hexahedron having first and second main faces M1, M2 orthogonal to the Z axis, first and second end faces E1, E2 orthogonal to the X axis, and first and second side faces S1, S2 orthogonal to the Y axis. In addition, the "hexahedron" may be substantially a hexahedron, for example, the edges connecting the faces of the ceramic body 11 may also be rounded.

[0115] The main surfaces M1, M2, end surfaces E1, E2 and side surfaces S1, S2 of the ceramic body 11 are all configured as flat surfaces. The flat surface of the present embodiment may not be a strict plane as long as it is a surface that is recognized as flat when observed as a whole, for example, it also includes a surface with tiny concave and convex shapes, a surface with a gently curved shape existing in a specified range, etc.

[0116] The multilayer ceramic capacitor 10 is a high-height type in which the dimension T in the Z-axis direction is 1.5 times or more the dimension W in the Y-axis direction. In the multilayer ceramic capacitor 10, the capacity is increased by increasing the dimension T corresponding to the height. Thus, the multilayer ceramic capacitor 10 can be mounted in a mounting space that is limited in the Y-axis direction.

[0117] The multilayer ceramic capacitor 10 may be of a high-profile type in which the dimension T in the Z-axis direction is 1.3 times or more the dimension W in the Y-axis direction.

[0118] In the multilayer ceramic capacitor 10, the dimension L of the ceramic body 11 in the X-axis direction may be larger than the dimension W or smaller than the dimension T. In the multilayer ceramic capacitor 10, the dimensions T, W, and L of the ceramic body 11 may be arbitrarily determined within the range satisfying the above conditions.

[0119] Specifically, in the multilayer ceramic capacitor 10 , for example, the dimension L can be set to be 0.2 mm to 1.2 mm, the dimension W can be set to be 0.1 mm to 0.7 mm, and the dimension T can be set to be 0.15 mm to 1.0 mm. The dimensions T, W, and L are all set to be the maximum dimensions of the multilayer ceramic capacitor 10 in each direction.

[0120] In the following description, "the inner side in the Z-axis direction" refers to the side close to the imaginary XY plane that bisects the multilayer ceramic capacitor 10 in the Z-axis direction, and "the outer side in the Z-axis direction" refers to the side away from the imaginary XY plane. Similarly, "the inner side in the Y-axis direction" refers to the side close to the imaginary XZ plane that bisects the multilayer ceramic capacitor 10 in the Y-axis direction, and "the outer side in the Y-axis direction" refers to the side away from the imaginary XZ plane.

[0121] The external electrodes 14 and 15 cover the end faces E1 and E2 of the ceramic body 11, respectively. In addition, in the present embodiment, the external electrodes 14 and 15 extend from the end faces E1 and E2 to the main faces M1 and M2 and the side faces S1 and S2, respectively. Thus, in the external electrodes 14 and 15, the cross-section parallel to the XZ plane and the cross-section parallel to the XY plane are both U-shaped. In addition, the shape of the external electrodes 14 and 15 is not limited to Figure 1 Example shown.

[0122] The external electrodes 14 and 15 contain a metal material as a main component. Examples of the metal material constituting the external electrodes 14 and 15 include copper (Cu), nickel (Ni), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), and alloys thereof. In addition, in the present embodiment, the main component refers to the component with the highest content ratio.

[0123] The ceramic body 11 has a stacked portion 20 and a pair of edge portions 18. The stacked portion 20 has a capacitor forming portion 16 and a pair of covering portions 17. The capacitor forming portion 16 includes a plurality of first and second internal electrodes 12, 13 alternately stacked along the Z-axis direction with a plurality of ceramic layers 19. In the present embodiment, the internal electrodes 12, 13 and the ceramic layers 19 are each configured in a sheet shape extending along the XY plane.

[0124] The internal electrodes 12 and 13 are alternately arranged along the Z-axis direction. The internal electrodes 12 and 13 are opposed to each other in the Z-axis direction in the opposing region at the center of the X-axis and Y-axis directions. The first internal electrode 12 is led out from the opposing region to the first end surface E1 and connected to the first external electrode 14. The second internal electrode 13 is led out from the opposing region to the second end surface E2 and connected to the second external electrode 15.

[0125] Here, the stacking direction of the internal electrodes 12 and 13 is defined as a “stacking direction”, the leading direction of the internal electrodes 12 and 13 is defined as a “leading direction”, and the direction orthogonal to the stacking direction and the leading direction is defined as a “width direction (of the internal electrodes 12 and 13)”. In the present embodiment, the stacking direction is a direction parallel to the Z axis, the leading direction is a direction parallel to the X axis, and the width direction is a direction parallel to the Y axis.

[0126] In the present embodiment, the width dimensions of the internal electrodes 12 and 13 in the Y-axis direction (width direction) are different between the inner layer portion 16a and the outer layer portion 16b of the capacitance forming portion 16. The detailed structure will be described later.

[0127] The internal electrodes 12 and 13 contain a metal material as a main component. Typical examples of the metal material include nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), and alloys thereof.

[0128] With such a structure, in the multilayer ceramic capacitor 10, when a voltage is applied between the external electrodes 14 and 15, a voltage is applied to the plurality of ceramic layers 19 between the internal electrodes 12 and 13 in the facing region. Thus, in the multilayer ceramic capacitor 10, charges corresponding to the voltage between the external electrodes 14 and 15 are accumulated.

[0129] In the laminated portion 20, a dielectric ceramic with a high dielectric constant is used to increase the electrostatic capacitance of each ceramic layer 19 between the internal electrodes 12 and 13. Examples of dielectric ceramic with a high dielectric constant include materials having a perovskite structure containing barium (Ba) and titanium (Ti), such as barium titanate (BaTiO3).

[0130] In addition, the dielectric ceramic may be a composition of strontium titanate (SrTiO3), calcium titanate (CaTiO3), magnesium titanate (MgTiO3), calcium zirconate (CaZrO3), calcium zirconate titanate (Ca(Zr, Ti)O3), barium calcium zirconate titanate ((Ba, Ca)(Zr, Ti)O3), barium zirconate (BaZrO3), titanium oxide (TiO2), etc. In addition to the dielectric ceramic, the laminated portion 20 may also contain the additive elements described later.

[0131] A pair of covering portions 17 covers the capacitor forming portion 16 from both sides in the stacking direction, i.e., the Z-axis direction. The covering portion 17 is composed of, for example, a stack of ceramic sheets extending along the XY plane. From the viewpoint of suppressing internal stress, the dielectric ceramic constituting the covering portion 17 is preferably of the same composition as the ceramic layer 19.

[0132] A pair of edge portions 18 are formed along the Z-axis direction and cover the laminated portion 20 from the Y-axis direction. As described later, the edge portion 18 is later mounted on the surface of the laminated portion 20 perpendicular to the Y-axis. For example, the edge portion 18 is formed of a ceramic sheet and is configured in a sheet shape extending along the XZ plane. From the viewpoint of suppressing internal stress, the dielectric ceramic constituting the edge portion 18 is preferably of the same composition as the ceramic layer 19.

[0133] The laminated portion 20 is integrated by being pressed in the lamination direction, i.e., the Z-axis direction, during the manufacturing process. In contrast, the edge portion 18 mounted later does not undergo the pressing process, and therefore may have lower density than the laminated portion 20. In addition, in order to improve the adhesion to the laminated portion 20, a large amount of organic compounds such as adhesives may be added to the material forming the edge portion 18. As a result, the content ratio of the dielectric ceramic in the material is reduced, and therefore the density of the edge portion 18 after firing may be further reduced. In the case where the density of the edge portion 18 is low, the moisture resistance, impact resistance, and crack resistance are reduced, and the reliability of the laminated ceramic capacitor 10 may be reduced.

[0134] Therefore, the edge portion 18 contains an additive element consisting of at least one of magnesium (Mg), manganese (Mn), zirconium (Zr), titanium (Ti), lithium (Li), molybdenum (Mo), niobium (Nb), copper (Cu), a rare earth element, or tin (Sn) at a higher concentration than the laminated portion 20. That is, the concentration of the additive element in the edge portion 18 is higher than the concentration of the additive element in the ceramic layer 19 and the cover portion 17. Examples of the rare earth element include lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), yttrium (Y), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), and scandium (Sc). The additive element contained in the edge portion 18 may be one element of Mg, Mn, Zr, Ti, Li, Mo, Nb, Cu, rare earth elements or Sn, or may contain a plurality of these elements. In addition, the concentration of the additive element refers to the total concentration of the additive element.

[0135] By adding a large amount of Mg, Mn, Zr, Ti, Li, Mo, Nb, Cu, rare earth elements or Sn to the edge portion 18, the sintering of the edge portion 18 can be promoted and the edge portion 18 can be densified. As a result, the density of the edge portion 18 can be improved, and the moisture resistance, impact resistance and crack resistance of the edge portion 18 can be improved.

[0136] On the other hand, in a general high-height multilayer ceramic capacitor in which all internal electrodes have substantially the same width dimension in the Y-axis direction, when more additive elements are added to the edge portion than to the stacked portion, insulation failure may occur. The following is an example of a multilayer ceramic capacitor 10A as a comparative example of the present embodiment.

[0137] Figure 5 1 is a longitudinal cross-sectional view of a high-height multilayer ceramic capacitor 10A as a comparative example of the present embodiment. In the multilayer ceramic capacitor 10A, all the internal electrodes 12 and 13 have substantially the same width dimension in the Y-axis direction. In addition, the composition of each part of the ceramic body 11A of the multilayer ceramic capacitor 10A is the same as that of the multilayer ceramic capacitor 10 of the present embodiment.

[0138] In the multilayer ceramic capacitor 10A, due to the influence of the additive element, the sintering of the edge portion 18 can be promoted during firing, and the edge portion 18 can shrink in the Z-axis direction relative to the laminated portion 20. Therefore, the ends 12e and 13e of the internal electrodes 12 and 13 in the Y-axis direction are easily bent inward in the Z-axis direction as the edge portion 18 shrinks. In addition, since the edge portion 18 shrinks from the outer side in the Z-axis direction to the central part, the bending of the ends 12e and 13e of the internal electrodes 12 and 13 can become larger as it goes to the outer side in the Z-axis direction.

[0139] In addition, in the high-height ceramic body 11A in which the number of stacked layers of the internal electrodes 12 and 13 is large, the relative shrinkage amount of the edge portion 18 with respect to the stacked portion 20 becomes large, and the bending of the ends 12e and 13e of the internal electrodes 12 and 13 on the outside in the Z-axis direction can become larger. Since the ends 12e and 13e of the internal electrodes 12 and 13 are bent, the distance between the ends 12e and 13e of the internal electrodes 12 and 13 adjacent to each other in the Z-axis direction becomes small, and poor insulation is likely to occur.

[0140] In contrast, in this embodiment, if Figure 3 As shown, in order to suppress insulation failure caused by bending of the ends 12e and 13e of the internal electrodes 12 and 13, the width dimension of the internal electrodes 12 and 13 in the outer layer portion 16b of the capacitance forming portion 16 is reduced. The detailed structure of the capacitance forming portion 16 is described below.

[0141] Figure 4 1 is a diagram showing the ceramic layers 19 on which the internal electrodes 12 and 13 are formed layer by layer. Figure 4 Also shown is an edge portion 18 adjacent to the ceramic layer 19 .

[0142] like Figure 3 and Figure 4As shown, the first and second internal electrodes 12, 13 are composed of first and second inner internal electrodes 12a, 13a located on the inner side in the Z-axis direction and first and second outer internal electrodes 12b, 13b located on both outer sides in the Z-axis direction. In the internal electrodes 12, 13, the shapes of the inner internal electrodes 12a, 13a and the outer internal electrodes 12b, 13b are different.

[0143] In addition, if Figure 3 As shown, the capacitor forming portion 16 of the present embodiment is divided into an inner layer portion 16a on the inner side in the Z-axis direction where the inner layer internal electrodes 12a and 13a are stacked, and a pair of outer layer portions 16b on both outer sides in the Z-axis direction where the outer layer internal electrodes 12b and 13b are stacked. That is, in the capacitor forming portion 16, the pair of outer layer portions 16b are adjacent to the pair of covering portions 17, and the inner layer portion 16a is located between the pair of outer layer portions 16b.

[0144] exist Figure 4 In the example shown, the inner layer internal electrodes 12a and 13a have the same planar shape. Figure 4 The first inner layer internal electrode 12a and the second inner layer internal electrode 13a shown in the figure are in a mutually reversed positional relationship with respect to a central axis parallel to the Y axis and passing through the center of the ceramic layer 19 in the X axis direction. Figure 4 In the example shown, the inner-layer internal electrodes 12a and 13a are configured in a rectangular shape, and the width dimension in the Y-axis direction is configured to be substantially constant along the X-axis direction.

[0145] exist Figure 4 In the example shown, the outer internal electrodes 12b and 13b have the same planar shape. Figure 4 The first outer layer internal electrode 12b and the second outer layer internal electrode 13b shown in the figure are in a mutually reversed positional relationship with respect to a central axis parallel to the Y axis and passing through the center of the ceramic layer 19 in the X axis direction. Figure 4 In the example shown, the outer internal electrodes 12b and 13b are configured in a rectangular shape, and the width dimension in the Y-axis direction is configured to be substantially constant along the X-axis direction.

[0146] like Figure 4 As shown, the outer layer internal electrodes 12b, 13b have a maximum width dimension D2 that is smaller than the minimum width dimension D1 of the inner layer internal electrodes 12a, 13a. The minimum width dimension D1 of the inner layer internal electrodes 12a, 13a is the minimum width dimension along the Y-axis direction as the width direction in the inner layer internal electrodes 12a, 13a. The maximum width dimension D2 of the outer layer internal electrodes 12b, 13b is the minimum width dimension along the Y-axis direction as the width direction in the outer layer internal electrodes 12b, 13b.

[0147] like Figure 3 and Figure 4 As shown in the figure, the maximum width dimension D2 of the outer internal electrodes 12b, 13b is smaller than the minimum width dimension D1 of the inner internal electrodes 12a, 13a, so that the end portions 12e, 13e of the outer internal electrodes 12b, 13b can be separated from the edge portion 18. In addition, an electrode non-existent region F of the capacitor forming portion 16 is arranged between the end portions 12e, 13e of the outer internal electrodes 12b, 13b and the edge portion 18. The electrode non-existent region F is composed of a laminate of the ceramic layer 19, or a laminate of the ceramic layer 19 and a dielectric layer of a composition equivalent thereto.

[0148] The concentration of the additive element in the electrode non-existing region F is lower than that in the edge portion 18, so the amount of contraction in the Z-axis direction of the electrode non-existing region F due to firing is suppressed to be smaller than that of the edge portion 18. Therefore, the end portions 12e and 13e of the outer layer internal electrodes 12b and 13b in contact with the electrode non-existing region F are less likely to bend inward in the Z-axis direction. As a result, short circuits between adjacent outer layer internal electrodes 12b and 13b are suppressed, and insulation failure of the multilayer ceramic capacitor 10 is suppressed.

[0149] As described above, according to the multilayer ceramic capacitor 10 of the present embodiment, even when the edge portion 18 shrinks due to the influence of the added element, the end portions 12e and 13e of the outer layer internal electrodes 12b and 13b can be suppressed from bending inward in the Z-axis direction, thereby suppressing insulation failure. Therefore, in a high-height multilayer ceramic capacitor 10 that can achieve a large capacity with a small mounting area, the reliability of the multilayer ceramic capacitor 10 can be improved.

[0150] In order to more reliably prevent the ends 12e, 13e of the outer internal electrodes 12b, 13b from bending, it is preferred that the ends 12e, 13e of the outer internal electrodes 12b, 13b are sufficiently spaced from the edge portion 18. From such a viewpoint, the distance between the ends 12e, 13e of the outer internal electrodes 12b, 13b and the edge portion 18 in the width direction (Y-axis direction) is preferably equal to or greater than the thickness dimension of the edge portion 18, and more preferably equal to or greater than 1.5 times the thickness dimension. In addition, the thickness dimension of the edge portion 18 is the maximum dimension in the width direction (Y-axis direction) of the edge portion 18 covering the inner layer portion 16a.

[0151] On the other hand, from the perspective of ensuring the maximum width dimension D2 of the outer internal electrodes 12b, 13b and expanding the effective area of ​​the outer internal electrodes 12b, 13b, the distance in the width direction (Y-axis direction) between the end portions 12e, 13e of the outer internal electrodes 12b, 13b and the edge portion 18 is preferably less than 5 times the thickness dimension of the edge portion 18 covering the inner layer portion 16a, and more preferably less than 3 times the thickness dimension.

[0152] Similarly, from the viewpoint of increasing the effective area of ​​the outer internal electrodes 12b, 13b, the maximum width dimension D2 of the outer internal electrodes 12b, 13b is preferably at least twice the thickness dimension in the width direction (Y-axis direction) of the edge portion 18 covering the inner layer portion 16a.

[0153] In order to ensure a sufficient distance between the end portions 12e and 13e of the outer internal electrodes 12b and 13b and the edge portion 18, the maximum width D2 is preferably 10 times or less the thickness of the edge portion 18 covering the inner layer portion 16a.

[0154] In addition, from the perspective of more effectively suppressing poor insulation of the stacked ceramic capacitor 10, the number of stacked outer internal electrodes 12b, 13b on one side in the Z-axis direction, i.e., in one outer layer portion 16b, is preferably greater than 5% of the number of stacked layers of all internal electrodes 12, 13, and more preferably greater than 10%.

[0155] In order to ensure the electrostatic capacitance of the ceramic body 11, the number of stacked outer internal electrodes 12b, 13b in one outer layer portion 16b is preferably 25% or less of the number of stacked internal electrodes 12, 13, more preferably 20% or less.

[0156] [Method of Manufacturing Multilayer Ceramic Capacitor 10]

[0157] Figure 6 1 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor 10 according to the present embodiment. Figure 7A to Figure 1 3 is a diagram showing a manufacturing process of the multilayer ceramic capacitor 10. Hereinafter, a method for manufacturing the multilayer ceramic capacitor 10 will be described with reference to these drawings as appropriate.

[0158] (Step S01: preparing ceramic sheet)

[0159] In step S01, the first and second inner ceramic sheets 101a, 102a for forming the inner layer portion 16a of the capacitor forming portion 16, the first and second outer ceramic sheets 101b, 102b for forming a pair of outer layer portions 16b of the capacitor forming portion 16, and the covering ceramic sheet 103 for forming the covering portion 17 are prepared.

[0160] The ceramic sheets 101a, 102a, 101b, 102b, and 103 are all made of unfired dielectric green sheets with dielectric ceramic as the main component. The material of the ceramic sheet includes, for example, ceramic powder, organic compounds such as a binder and an organic solvent, and other additives. In addition, the ceramic sheet may also contain the above-mentioned additive elements. The ceramic sheets 101a, 102a, 101b, 102b, and 103 are formed into sheets using, for example, a roll coater, a doctor blade, and the like.

[0161] Fig. 7A is a plan view of the first inner layer ceramic sheet 101a. Figure 7B is a plan view of the second inner layer ceramic sheet 102a. Fig. 8A is a plan view of the first outer ceramic sheet 101b. Figure 8B is a plan view of the second outer ceramic sheet 102b. Fig. 9 is a plan view of the cover ceramic sheet 103.

[0162] At this stage, each of the ceramic sheets 101a, 102a, 101b, 102b, and 103 is constituted as a large sheet that has not been singulated. Figure 7A to Figure 9 In FIG. 1 , a first cutting line Lx parallel to the X axis and a second cutting line Ly parallel to the Y axis are indicated by dashed lines as cutting lines when each of the multilayer ceramic capacitors 10 is singulated.

[0163] Unfired conductor patterns 112a and 113a corresponding to the inner internal electrodes 12a and 13a are formed on the inner ceramic sheets 101a and 102a. Unfired conductor patterns 112b and 113b corresponding to the outer internal electrodes 12b and 13b are formed on the outer ceramic sheets 101b and 102b. No unfired conductor pattern is formed on the cover ceramic sheet 103 corresponding to the cover portion 17 where no internal electrode is provided.

[0164] The conductor patterns 112a, 113a, 112b, 113b are formed by applying a conductor paste to the ceramic sheets 101a, 102a, 101b, 102b. The method for applying the conductive paste can be arbitrarily selected from known techniques, and for example, screen printing or gravure printing can be used.

[0165] The conductor patterns 112a, 112b and the conductor patterns 113a, 113b are each provided with a gap along the X-axis direction of the cutting line Ly. The conductor patterns 112a, 112b and the conductor patterns 113a, 113b are arranged so that the gaps are mutually offset along the X-axis direction.

[0166] The conductor patterns 112a and 113a are formed continuously in the Y-axis direction and are formed in a strip shape along the Y-axis direction. On the other hand, a gap in the Y-axis direction along the cutting line Lx is formed in the conductor patterns 112b and 113b. The gap in the Y-axis direction forms an electrode non-existent region F.

[0167] (Step S02: stacking)

[0168] In step S02, the ceramic sheets 101a, 102a, 101b, 102b, 103 prepared in step S01 are Fig.10The laminated sheet 104 is produced by laminating the laminated ceramic sheets 101a, 102a, 101b, 102b, and 103 as shown. The laminated sheet 104 is obtained by integrating the laminated ceramic sheets 101a, 102a, 101b, 102b, and 103 by hydrostatic pressure, uniaxial pressure, or the like.

[0169] In the laminated sheet 104, inner ceramic sheets 101a and 102a are alternately laminated in the Z-axis direction at positions corresponding to the inner layer portion 16a of the capacitor forming portion 16. In addition, in the laminated sheet 104, outer ceramic sheets 101b and 102b are alternately laminated in the Z-axis direction at positions corresponding to the outer layer portion 16b of the capacitor forming portion 16.

[0170] In the laminated sheet 104, cover ceramic sheets 103 corresponding to the cover portion 17 are stacked on both sides of the upper and lower sides in the Z-axis direction of the ceramic sheets 101a, 102a, 101b, and 102b stacked at positions corresponding to the capacitor forming portion 16. The cover ceramic sheets 103 are stacked continuously in a number corresponding to the thickness of the cover portion 17.

[0171] (Step S03: Cutting off)

[0172] In step S03, the laminated sheet 104 obtained in step S02 is Fig.11 By cutting along the cutting lines Lx and Ly, unfired laminated small pieces 120 corresponding to the laminated portion 20 are obtained. For cutting the laminated sheet 104 in step S03, for example, a cutting device with a press cutter or a dicing device with a rotary blade can be used.

[0173] Fig. 12A , Fig. 12B and Fig. 12C Each of them is a schematic cross-sectional view showing an example of step S03. Fig. 12A , Fig. 12B and Fig. 12C 2 shows an example in which the laminated sheet 104 is cut using a cutting blade Q as a press cutter.

[0174] First, if Fig. 12A As shown, the cutting blade Q directed downward in the Z-axis direction is arranged above the laminated sheet 104 in the Z-axis direction. The lower surface of the laminated sheet 104 in the Z-axis direction is bonded to the tape T1.

[0175] Then, if Fig. 12BAs shown in FIG. 1 , the cutting blade Q is moved downward in the Z-axis direction until the cutting blade Q reaches the tape T1, thereby cutting the laminated sheet 104. At this time, the conductor patterns 112a and 113a corresponding to the inner layer internal electrodes 12a and 13a are cut by the cutting blade Q. On the other hand, the cutting blade Q passes through the gap between the conductor patterns 112b and 113b corresponding to the outer layer internal electrodes 12b and 13b, so the conductor patterns 112b and 113b are not cut by the cutting blade Q.

[0176] And, if Fig. 12C As shown, the cutting blade Q is moved upward in the Z-axis direction to be pulled out from the laminated sheet 104 .

[0177] Thus, the stacked sheet 104 is singulated into a plurality of stacked small pieces 120. The stacked small pieces 120 have cut surfaces 120s substantially perpendicular to the Y-axis direction and cut surfaces substantially perpendicular to the X-axis direction. Fig. 12C As shown, the conductor patterns 112a and 113a corresponding to the inner internal electrodes 12a and 13a are exposed from the cut surface 120s of the laminated small piece 120. On the other hand, the conductor patterns 112b and 113b corresponding to the outer internal electrodes 12b and 13b are not exposed from the cut surface 120s.

[0178] As described above, in this step, the conductor patterns 112b, 113b corresponding to the outer layer internal electrodes 12b, 13b are not cut by the cutting blade Q. As a result, near the upper surface in the Z-axis direction of the laminated sheet 104 into which the cutting blade Q is inserted, the conductor patterns 112b, 113b can be prevented from being deformed by a large stress from the cutting blade Q. Therefore, this structure can also effectively prevent the end portions 12e, 12e of the outer layer internal electrodes 12b, 13b after firing from being bent and the insulation failure associated therewith.

[0179] (Step S04: Forming an edge portion)

[0180] In step S04, the cut surface 120s of the laminated small piece 120 obtained in step S03 forms the unfired edge portion 118. In this way, the unfired ceramic body 11 is manufactured.

[0181] The edge portion 118 is formed, for example, by pasting ceramic sheets together, applying ceramic slurry, etc. The material of the edge portion 118 includes, for example, ceramic powder, the above-mentioned additive elements, organic compounds such as adhesives and organic solvents, other additives, etc. The additive elements are added to the edge portion 118 in a manner that makes the concentration higher than that of the ceramic sheets 101a, 102a, 101b, 102b, and 103 that form the stacked small piece 120.

[0182] From the viewpoint of making the thickness of the edge portion 18 uniform and thin, the edge portion 18 is preferably formed of a ceramic sheet. Fig.13Aand Fig. 13B Provide explanation.

[0183] like Fig.13A As shown, first, one cut surface 120s of the stacked small piece 120 is made to face the ceramic sheet 118s. The ceramic sheet 118s is arranged on the elastic body R. The other cut surface 120s of the stacked small piece 120 is held by the tape T2.

[0184] Then, if Fig.13A and Fig. 13B As shown, the stacked small piece 120 is pressed against the ceramic piece 118s in the Y-axis direction, and the ceramic piece 118s is punched out using the cut surface 120s. Thus, the ceramic piece 118s punched out along the periphery of the cut surface 120s is attached to the cut surface 120s, forming an unfired edge portion 118 on the cut surface 120s.

[0185] Similarly, a ceramic sheet 118s is punched out on the other cut surface 120s of the stacked small piece 120, and an unfired edge portion 118 is formed on the cut surface 120s. Thus, an unfired ceramic body 11 having the stacked small pieces 120 and a pair of edge portions 18 is formed.

[0186] (Step S05: Firing)

[0187] In step S05, the ceramic body 11 obtained in step S04 is fired. The firing temperature in step S05 may be about 1000 to 1300° C. when using a barium titanate (BaTiO 3 ) material. The firing may be performed in a reducing atmosphere or a low oxygen partial pressure atmosphere.

[0188] In this step, due to the influence of the added elements, the edge portion 18 can shrink in the Z-axis direction relative to the stacked small piece 120. In contrast, in this embodiment, since the outer layer internal electrodes 12b and 13b are not in contact with the edge portion 18, the end portions 12e and 13e of the outer layer internal electrodes 12b and 13b can be suppressed from bending in the Z-axis direction.

[0189] (Step S06: Forming External Electrodes)

[0190] In step S06, external electrodes 14 and 15 are formed at both ends of the ceramic body 11 obtained in step S05 in the X-axis direction, thereby producing Figure 1 to Figure 3 The multilayer ceramic capacitor 10 shown in FIG. 1 is formed by applying a conductor paste to a ceramic body 11 and sintering the paste.

[0191] [Mounting of Multilayer Ceramic Capacitor 10]

[0192] Fig.141 is a side view of a circuit board 200 including a multilayer ceramic capacitor 10 of the present embodiment. The circuit board 200 has a mounting substrate 210 on which the multilayer ceramic capacitor 10 is mounted. The mounting substrate 210 has: a base material 211 extending along the XY plane and having a mounting surface G perpendicular to the Z axis; and a pair of connection electrodes 212 provided on the mounting surface G.

[0193] In the wiring board 200 , the external electrodes 14 and 15 of the multilayer ceramic capacitor 10 are connected to a pair of connection electrodes 212 of the mounting substrate 210 via solder H. Thus, in the wiring board 200 , the multilayer ceramic capacitor 10 is fixed to the mounting substrate 210 and electrically connected thereto.

[0194] Here, it is known that in the laminated ceramic capacitor 10, when the circuit board 200 is driven, if a voltage is applied to the external electrodes 14 and 15 via the connection electrodes 212 of the mounting substrate 210, electrostrain (electrostriction) is generated in the ceramic body 11 due to the piezoelectric effect. Among the electrostrain generated in the ceramic body 11, the internal electrodes 12 and 13 are deformed relatively greatly in the stacking direction.

[0195] In circuit board 200, since electro-induced deformation is repeatedly generated in multilayer ceramic capacitor 10 to which an AC voltage is applied, vibration in the thickness direction may occur in base material 211 of mounting substrate 210. In circuit board 200, when the vibration generated in base material 211 increases, a phenomenon called "howling" may occur in which noise is generated from base material 211.

[0196] In this regard, in the multilayer ceramic capacitor 10 of the present embodiment, there is an electrode non-existent region F outside the outer internal electrodes 12b and 13b in the Y-axis direction. Since the piezoelectric effect is not generated in the electrode non-existent region F, the deformation amount of the ceramic body 11 caused by electro-strain can be suppressed in the multilayer ceramic capacitor 10. Therefore, in the present embodiment, howling in the circuit board 200 can be suppressed.

[0197] When the multilayer ceramic capacitor 10 is mounted on the mounting substrate 210 , it is prepared in a packaged state as the package body 300 . Fig.15 , Fig.16 It is a figure which shows the package 300. Fig.15 It is a partial plan view of the packaging body 300. Fig.16 It is along Fig.15 A cross-sectional view of the package body 300 taken along line CC'.

[0198] The package 300 includes a multilayer ceramic capacitor 10, a carrier tape 310, and a top tape 320. The carrier tape 310 is configured as a long strip extending in the Y-axis direction. In the carrier tape 310, a plurality of recesses 311 are arranged at intervals in the Y-axis direction, and each of the plurality of recesses 311 accommodates one multilayer ceramic capacitor 10.

[0199] Carrier tape 310 has a sealing surface P that faces upward and is perpendicular to the Z axis, and a plurality of recesses 311 are recessed downward in the Z axis direction from sealing surface P. That is, carrier tape 310 is configured so that multilayer ceramic capacitors 10 in recesses 311 can be taken out from sealing surface P side.

[0200] In the carrier tape 310, a plurality of feed holes 312 are arranged at intervals in the Y-axis direction and penetrate in the Z-axis direction at positions offset from the rows of the plurality of recesses 311 in the X-axis direction. The feed holes 312 are configured as engagement holes for the tape conveying mechanism to convey the carrier tape 310 in the Y-axis direction.

[0201] In package 300 , top tape 320 is attached to sealing surface P of carrier tape 310 along the row of recesses 311 , and recesses 311 containing multilayer ceramic capacitors 10 are collectively covered by top tape 320 . Thus, multilayer ceramic capacitors 10 are held in recesses 311 .

[0202] like Fig.16 As shown, regarding the laminated ceramic capacitor 10 in the recess 311 of the carrier tape 310, the first main surface M1 of the ceramic body 11 facing upward in the Z-axis direction faces the top tape 320. In addition, the second main surface M2 of the ceramic body 11 facing downward in the Z-axis direction faces the bottom surface of the recess 311.

[0203] When installing the multilayer ceramic capacitor 10 packaged as the package 300, the top tape 320 is peeled off from the sealing surface P of the carrier tape 310 in the Y-axis direction. Thus, in the package 300, the plurality of recesses 311 containing the plurality of multilayer ceramic capacitors 10 can be opened sequentially upward in the Z-axis direction.

[0204] The multilayer ceramic capacitor 10 accommodated in the open recess 110 is taken out in a state where the first main surface M of the ceramic body 11 facing upward in the Z-axis direction is adsorbed to the front end of the adsorption nozzle of the mounting device. Then, the mounting device moves the multilayer ceramic capacitor 10 to the mounting surface G of the mounting substrate 210 by moving the adsorption nozzle.

[0205] The mounting device releases the suction nozzle from the first main surface M1 of the ceramic body 11 while the second main surface M2 of the ceramic body 11 faces the mounting surface G and the external electrodes 14 and 15 are positioned on the pair of connection electrodes 212 coated with solder paste.

[0206] Then, the solder paste is melted and solidified in a reflow furnace or the like on the mounting substrate 210 with the multilayer ceramic capacitor 10 placed on the mounting surface G. Thus, the external electrodes 14 and 15 of the multilayer ceramic capacitor 10 are connected to the pair of connection electrodes 212 of the mounting substrate 210 via the solder H, thereby obtaining Fig.14 The circuit board 200 is shown.

[0207] <Second Embodiment>

[0208] The multilayer ceramic capacitor 10 of the second embodiment of the present invention is different from the multilayer ceramic capacitor 10 of the first embodiment only in the structure of the internal electrodes 12 and 13. Figure 1 In this embodiment, the same reference numerals are given to the same or corresponding structures as those in the first embodiment described above, and detailed descriptions thereof are omitted.

[0209] [Structure of Multilayer Ceramic Capacitor 10]

[0210] Figure 17 to Figure 19 FIG. 1 is a diagram showing a multilayer ceramic capacitor 10 according to a second embodiment of the present invention. Fig.17 The multilayer ceramic capacitor 10 is Figure 1 Longitudinal section view of line BB'.

[0211] Fig.18 The multilayer ceramic capacitor 10 is Figure 1 Cross-sectional view of the D-D' line. Fig.19 1 is a diagram showing a ceramic body 11 of a laminated ceramic capacitor 10 partially exploded for each ceramic layer 19. Fig.19 Also shown is an edge portion 18 adjacent to the ceramic layer 19 .

[0212] In the capacitor forming portion 16 of the first embodiment, the stacking direction of the internal electrodes 12 and 13 is parallel to the Z axis, and the width direction of the internal electrodes 12 and 13 is parallel to the Y axis. In contrast, in the capacitor forming portion 16 of the present embodiment, the stacking direction is parallel to the Y axis, the extraction direction of the internal electrodes 12 and 13 is parallel to the X axis, and the width direction of the internal electrodes 12 and 13 is parallel to the Z axis.

[0213] The internal electrodes 12 and 13 of the capacitance forming portion 16 are formed in a sheet shape extending along the XZ plane, and are alternately stacked in the Y-axis direction with the ceramic layers 19. In the present embodiment, a pair of covering portions 17 covers the capacitance forming portion 16 in the Y-axis direction.

[0214] In the present embodiment, the edge portion 18 is formed along the Y-axis direction and covers the laminated portion 20 from the Z-axis direction. As in the first embodiment, the edge portion 18 contains an additive element consisting of at least one of Mg, Mn, Zr, Ti, Li, Mo, Nb, Cu, a rare earth element, or Sn at a higher concentration than the laminated portion 20.

[0215] like Fig.17 and Fig.19 As shown, the first and second internal electrodes 12 and 13 are composed of the first and second inner internal electrodes 12a and 13a located on the inner side in the Y-axis direction, and the first and second outer internal electrodes 12b and 13b located on both outer sides in the Y-axis direction. Accordingly, the capacitor forming portion 16 of the present embodiment is divided into an inner layer portion 16a on the inner side in the Y-axis direction stacked with the inner layer internal electrodes 12a and 13a, and a pair of outer layer portions 16b on both outer sides in the Y-axis direction stacked with the outer layer internal electrodes 12b and 13b.

[0216] like Fig.19 As shown in FIG. 1 , the outer internal electrodes 12b and 13b have a maximum width dimension D2 that is smaller than the minimum width dimension D1 of the inner internal electrodes 12a and 13a. Fig.17 As shown, the capacitor forming portion 16 has an electrode non-existent region F disposed between the end portions 12e, 13e of the outer layer internal electrodes 12b, 13b in the Z-axis direction and the edge portion 18. Thus, even when the edge portion 18 shrinks in the Y-axis direction during firing, the end portions 12e, 13e of the outer layer internal electrodes 12b, 13b are not easily bent in the Y-axis direction, and poor insulation in the outer layer internal electrodes 12b, 13b can be suppressed.

[0217] In addition, in this embodiment, since the stacking direction is parallel to the Y axis, the total number of stacked internal electrodes 12 and 13 is reduced compared to the first embodiment in which the stacking direction is parallel to the Z axis. On the other hand, since each internal electrode 12 and 13 extends along the XZ plane, the area of ​​each internal electrode 12 and 13 can be increased compared to the first embodiment. As a result, the electrostatic capacitance of the multilayer ceramic capacitor 10 can be sufficiently ensured.

[0218] In addition, in the present embodiment, since the width direction of the internal electrodes 12 and 13 is parallel to the Z axis, the maximum width dimension D2 of the outer internal electrodes 12b and 13b can be made larger than that of the first embodiment. Therefore, the width dimension and area of ​​the end portions of the outer internal electrodes 12b and 13b at the end faces E1 and E2 can be sufficiently ensured. Therefore, in the present embodiment, even if the maximum width dimension D2 of the outer internal electrodes 12b and 13b is made smaller than the minimum width dimension D1 of the inner internal electrodes 12a and 13a, poor connection between the outer internal electrodes 12b and 13b and the external electrodes 14 and 15 can be suppressed. As a result, according to the present embodiment, a decrease in the electrostatic capacitance of the multilayer ceramic capacitor 10 caused by such poor connection can be suppressed.

[0219] [Method of Manufacturing Multilayer Ceramic Capacitor 10]

[0220] Hereinafter, a method for manufacturing the multilayer ceramic capacitor 10 according to the present embodiment will be described. The method for manufacturing the multilayer ceramic capacitor 10 according to the present embodiment is as follows: Figure 6 However, the manufacturing method of this embodiment is different from that of the first embodiment in the planar shape of the conductor pattern, the number of ceramic sheets stacked, and the like.

[0221] In step S01, Figure 20A to Figure 22 As shown, the first and second inner ceramic sheets 101a, 102a for forming the inner layer portion 16a of the capacitor forming portion 16, the first and second outer ceramic sheets 101b, 102b for forming a pair of outer layer portions 16b of the capacitor forming portion 16, and the covering ceramic sheet 103 for forming the covering portion 17 are prepared.

[0222] like Figure 20A to Figure 22 As shown in FIG. 1 , the ceramic sheets 101a, 102a, 101b, 102b, and 103 of this embodiment do not extend along the XY plane but extend along the XZ plane. Therefore, the ceramic sheets 101a, 102a, 101b, 102b, and 103 of this embodiment are configured such that Figure 7A to Figure 9 The shape of each ceramic sheet shown is stretched in the Y-axis direction as a whole. Figure 7A to Figure 9 The Y axis in FIG. 1 is changed to the Z axis. The cutting lines when individualizing the multilayer ceramic capacitors 10 are formed by first cutting lines Lx parallel to the X axis and second cutting lines Lz parallel to the Z axis.

[0223] Next, in step S02, Fig.23As shown, the laminated sheet 104 is manufactured by laminating and pressing ceramic sheets 101a, 102a, 101b, 102b, and 103 in the Y-axis direction. The number of laminated ceramic sheets 101a, 102a, 101b, 102b, and 103 is appropriately set according to the size of the ceramic body 11 in the Y-axis direction, and is typically set to be less than that in the first embodiment.

[0224] Next, in step S03 , the laminated sheet 104 obtained in step S02 is cut along cutting lines Lx and Lz to obtain unfired laminated small pieces 120 .

[0225] Next, in step S04, an unfired edge portion 118 is formed on a cut surface 120s substantially perpendicular to the Z axis of the stacked small piece 120 obtained in step S03. In this way, an unfired ceramic body 11 is produced.

[0226] Then, the same step S05 (firing) as in the first embodiment is performed, and in the same step S6 (external electrode formation) as in the first embodiment, external electrodes 14 and 15 are formed at both ends of the ceramic body 11 in the X-axis direction, thereby producing Figure 17 to Figure 19 A stacked ceramic capacitor 10 is shown.

[0227] Here, in the ceramic body 11 of the present embodiment, since the stacking direction is parallel to the Y axis, it is possible to have a structure in which the main surfaces M1 and M2 have a higher flatness than the side surfaces S1 and S2 as described below.

[0228] The side surfaces S1 and S2 are formed by surfaces that are substantially perpendicular to the Y-axis of the laminate 104. Fig. 20A , Fig. 20B , Fig.21A and Fig. 21B As shown in FIG. 1 , the ceramic sheets 101a, 102a, 101b, and 102b have areas where the conductor patterns 112a, 112b, 113a, and 113b are not formed. Therefore, the height difference and undulation caused by the thickness of the conductor patterns 112a, 112b, 113a, and 113b are easily formed on the surface of the laminated sheet 104 on which these are laminated and which is substantially perpendicular to the Y axis. That is, the flatness of the side surfaces S1 and S2 is easily reduced.

[0229] On the other hand, the main surfaces M1 and M2 are formed by the edge portion 18. In the present embodiment, the edge portion 18 is formed by attaching a ceramic sheet 118s to a cut surface 120s of the stacked small piece 120 that is substantially perpendicular to the Z axis. Since it is difficult to form a height difference or undulation on the cut surface 120s and the ceramic sheet 118s, the main surfaces M1 and M2 can be made flatter than the side surfaces S1 and S2.

[0230] Reference Fig.14, the main surfaces M1 and M2 are opposite to the mounting substrate 210 when mounted on the mounting substrate 210. Therefore, by making the main surfaces M1 and M2 have high flatness, the posture of the multilayer ceramic capacitor 10 on the mounting substrate 210 can be stabilized. As a result, the multilayer ceramic capacitor 10 is a high-height type with a high center of gravity, and can be suppressed from tilting on the mounting substrate 210. By suppressing the tilt of the multilayer ceramic capacitor 10, the contact between the multilayer ceramic capacitor 10 and the adjacent electronic components is suppressed, and defects such as short circuits can be suppressed.

[0231] In addition, by making the main surfaces M1 and M2 have high flatness, Fig.16 The multilayer ceramic capacitor 10 can be easily sucked from the package 300 including the multilayer ceramic capacitor 10 by a chip mounter for mounting.

[0232] If there is a height difference or undulation on the first main surface M1, it is difficult for the suction nozzle of the chip mounter to stably suck the first main surface M1. In contrast, in the present embodiment, the main surfaces M1 and M2 have high flatness, so that the suction nozzle can stably suck the first main surface M1. Therefore, in the multilayer ceramic capacitor 10, poor suction during mounting can be effectively suppressed.

[0233] In addition, the flatness of each surface can be compared as follows. Fig.24A The cross-sectional view of exemplifies an example in which the first principal surface M1 is a measurement target surface. Fig. 24B The cross-sectional view shows an example in which the first side surface S1 is a measurement target surface.

[0234] First, if Fig.24A As shown, a cross section perpendicular to the first principal surface M1 and parallel to the XZ plane that bisects the first principal surface M1 is exposed. In addition, in this cross section, a first imaginary line L1 that passes through the center point C1 of the first principal surface M1 in the X-axis direction and is parallel to the X-axis direction, and a second imaginary line L2 that is parallel to the first imaginary line L1 and has an interval of 1% (T*0.01) of the dimension T in the Z-axis direction of the ceramic body 11 are defined. In addition, the distance between the two points where the second imaginary line L2 intersects the first principal surface M1 is measured as the dimension D3 of the flat area of ​​the first principal surface M1. In addition, the dimension D3 of the second principal surface M2 is measured in the same manner.

[0235] In addition, if Fig. 24BAs shown, a cross section perpendicular to the first side surface S1 and parallel to the XY plane that bisects the first side surface S1 is exposed. And, in this cross section, a third imaginary line L3 passing through the center point C2 of the first side surface S1 in the X-axis direction and parallel to the X-axis direction, and a fourth imaginary line L4 parallel to the third imaginary line L3 and having an interval of 1% (T*0.01) of the dimension T in the Z-axis direction of the ceramic body 11 are defined. And, the distance between the two points where the fourth imaginary line L4 intersects the first side surface S1 is measured as the dimension D4 of the flat area of ​​the first side surface S1. In addition, the dimension D4 of the second side surface S2 is measured in the same manner.

[0236] Then, the average value of the dimension D3 of the main surfaces M1 and M2 and the average value of the dimension D4 of the side surfaces S1 and S2 are calculated for five or more multilayer ceramic capacitors 10. The calculated average value of the dimension D3 is compared with the average value of the dimension D4. When the average value of the dimension D3 is larger than the average value of the dimension D4, it can be determined that the main surfaces M1 and M2 have a higher flatness than the side surfaces S1 and S2.

[0237] Furthermore, as described below, multilayer ceramic capacitor 10 according to the present embodiment can effectively suppress howling in circuit board 200 .

[0238] In the laminated ceramic capacitor 10 of the present embodiment, the stacking direction of the internal electrodes 12 and 13 is in the in-plane direction of the substrate 211, so it is not easy to generate vibration in the substrate 211 due to the electro-strain of the ceramic body 11. In addition, the ceramic body 11 of the present embodiment not only has the electrode non-existent region F as in the first embodiment, but also can reduce the number of stacking of the internal electrodes 12 and 13. Therefore, in the present embodiment, in the ceramic body 11, the deformation amount caused by the electro-strain can be suppressed to a smaller extent, and the howling in the circuit board 200 can be suppressed more effectively.

[0239] <Example>

[0240] As Example 1 of the present invention, a sample of the laminated ceramic capacitor 10 of the first embodiment described above was prepared. Also, as Example 2 of the present invention, a sample of the laminated ceramic capacitor 10 of the second embodiment described above was prepared. As a comparative example of the present invention, a sample of the laminated ceramic capacitor 10 of the second embodiment described above was prepared. Figure 5 100 samples of each of Examples 1 and 2 and the comparative example were produced.

[0241] As Example 3 of the present invention, a sample of the laminated ceramic capacitor 10 of the first embodiment described above was produced. Also, as Example 4 of the present invention, a sample of the laminated ceramic capacitor 10 of the second embodiment described above was produced. 100 samples of each of Examples 3 and 4 were produced.

[0242] In the samples of Examples 1, 2 and the comparative example, the dimension L in the X-axis direction is 0.6 mm, the dimension W in the Y-axis direction is 0.3 mm, and the dimension T in the Z-axis direction is 0.5 mm. In addition, in the samples of Examples 1, 2 and the comparative example, the thickness of each cover portion 17 is 25 μm, the thickness of each edge portion 18 is 20 μm, and the thickness of each internal electrode 12, 13 and each ceramic layer 19 is 0.5 μm.

[0243] In the samples of Examples 3 and 4, the dimension L in the X-axis direction is 0.6 mm, the dimension W in the Y-axis direction is 0.3 mm, and the dimension T in the Z-axis direction is 0.4 mm. In addition, in the samples of Examples 3 and 4, the thickness of each cover portion 17 is 25 μm, the thickness of each edge portion 18 is 20 μm, and the thickness of each internal electrode 12, 13 and each ceramic layer 19 is 0.5 μm.

[0244] In the sample of Example 1, the minimum width dimension D1 of the inner layer internal electrodes 12a and 13a is 260 μm, and the maximum width dimension D2 of the outer layer internal electrodes 12b and 13b is 200 μm. In addition, in the sample of Example 1, the total number of layers of the internal electrodes 12 and 13 is 450. The number of layers of the outer layer internal electrodes 12b and 13b in each outer layer portion 16b is 50 each, and the number of layers of the inner layer internal electrodes 12a and 13a in the inner layer portion 16a is 350.

[0245] In the sample of Example 2, the minimum width dimension D1 of the inner layer internal electrodes 12a and 13a is 460 μm, and the maximum width dimension D2 of the outer layer internal electrodes 12b and 13b is 400 μm. In addition, in the sample of Example 2, the total number of layers of the internal electrodes 12 and 13 is 250. The number of layers of the outer layer internal electrodes 12b and 13b in each outer layer portion 16b is 50 each, and the number of layers of the inner layer internal electrodes 12a and 13a in the inner layer portion 16a is 150.

[0246] In the sample of the comparative example, the width dimension of all the internal electrodes 12 and 13 was set to 260 μm, and the total number of stacked layers of the internal electrodes 12 and 13 was set to 450.

[0247] In the sample of Example 3, the minimum width dimension D1 of the inner layer internal electrodes 12a and 13a is 260 μm, and the maximum width dimension D2 of the outer layer internal electrodes 12b and 13b is 200 μm. In addition, in the sample of Example 1, the total number of layers of the internal electrodes 12 and 13 is 350. The number of layers of the outer layer internal electrodes 12b and 13b in each outer layer portion 16b is 50 each, and the number of layers of the inner layer internal electrodes 12a and 13a in the inner layer portion 16a is 250.

[0248] In the sample of Example 4, the minimum width dimension D1 of the inner layer internal electrodes 12a and 13a is 360 μm, and the maximum width dimension D2 of the outer layer internal electrodes 12b and 13b is 300 μm. In addition, in the sample of Example 2, the total number of layers of the internal electrodes 12 and 13 is 250. The number of layers of the outer layer internal electrodes 12b and 13b in each outer layer portion 16b is 50 each, and the number of layers of the inner layer internal electrodes 12a and 13a in the inner layer portion 16a is 150.

[0249] In the samples of Examples 1, 2 and the comparative example, any one of Mg, Mn, Zr, rare earth elements (Y, Dy, Ho), and Sn is added to the ceramic sheet 118s constituting the edge portion 18 in a manner such that its concentration is higher than that of the ceramic sheet constituting the stacking portion 20 (stacking sheet 104).

[0250] In the samples of Examples 3 and 4, any one of Mg, Mn, Zr, rare earth elements (Y, Dy, Ho), and Sn is added to the ceramic sheet 118s constituting the edge portion 18 in a manner such that its concentration is higher than that of the ceramic sheet constituting the stacking portion 20 (stacking sheet 104).

[0251] For the samples of Examples 1 and 2 and the comparative example, a reliability test was performed in which a DC voltage of 10V was applied in an environment of 105°C. Among the samples of the comparative example, there were samples that reached insulation breakdown in less than 500 hours, but for the samples of Examples 1 and 2, there were no samples that reached insulation breakdown in less than 500 hours. It can be seen from this that the samples of Examples 1 and 2 can suppress insulation failure compared with the samples of the comparative example.

[0252] The samples of Examples 3 and 4 were subjected to a reliability test in which a DC voltage of 10 V was applied in an environment of 105° C. No sample of Examples 3 and 4 reached insulation breakdown in less than 500 hours. It can be seen that the samples of Examples 3 and 4 can suppress insulation failure compared to the samples of the comparative examples.

[0253] In addition, the electrostatic capacitance was measured under the conditions of 1kHz·0.5Vrms for 100 samples of each of Examples 1 and 2. Furthermore, the maximum and minimum values ​​relative to the average value of the electrostatic capacitance were calculated for Examples 1 and 2, respectively, and it was confirmed whether the maximum and minimum values ​​were within ±5% or ±10% relative to the average value. In Example 2, the maximum and minimum values ​​of the electrostatic capacitance were within ±5% of the average value. On the other hand, in Example 1, although the maximum and minimum values ​​of the electrostatic capacitance were within ±10% of the average value, they were not within ±5%.

[0254] From this result, it is found that the sample of Example 2 can suppress the variation of electrostatic capacitance compared with the sample of Example 1. The reason for this is presumably that in the sample of Example 2, the connection failure between the external electrodes 14 and 15 and the internal electrodes 12 and 13 is suppressed.

[0255] In addition, the electrostatic capacitance was measured under the conditions of 1kHz·0.5Vrms for 100 samples of each of Examples 3 and 4. Furthermore, the maximum and minimum values ​​relative to the average value of the electrostatic capacitance were calculated for Examples 3 and 4, respectively, and it was confirmed whether the maximum and minimum values ​​were within ±5% or ±10% relative to the average value. In Example 4, the maximum and minimum values ​​of the electrostatic capacitance were within ±5% of the average value. On the other hand, in Example 3, although the maximum and minimum values ​​of the electrostatic capacitance were within ±10% of the average value, they were not within ±5%.

[0256] From this result, it is found that the sample of Example 4 can suppress the variation of electrostatic capacitance compared with the sample of Example 3. The reason for this is presumably that in the sample of Example 4, the connection failure between the external electrodes 14 and 15 and the internal electrodes 12 and 13 is suppressed.

[0257] As an important factor causing the poor connection between the external electrodes 14, 15 and the internal electrodes 12, 13, the area of ​​the internal electrodes 12, 13 exposed at the end faces E1, E2 can be cited. For example, in the outer internal electrodes 12b, 13b of Example 2, since the thickness is 0.5 μm and the width is 400 μm, the area is 200 μm obtained by multiplying these two. 2 In the second embodiment, the inner electrodes 12a and 13a have a thickness of 0.5 μm and a width of 460 μm, so the area is 230 μm obtained by multiplying these two. 2 .

[0258] On the other hand, in the outer layer internal electrodes 12b and 13b of Example 1, since the thickness is 0.5 μm and the width is 200 μm, the area is 100 μm obtained by multiplying these two. 2 In the inner layer internal electrodes 12a and 13a of Example 1, the thickness is 0.5 μm and the width is 260 μm, so the area is 130 μm obtained by multiplying these two. 2 .

[0259] In the outer layer internal electrodes 12b and 13b of Example 4, the thickness is 0.5 μm and the width is 300 μm. Therefore, the area is 150 μm obtained by multiplying these two. 2In the fourth embodiment, the inner electrodes 12a and 13a have a thickness of 0.5 μm and a width of 360 μm, so the area is 180 μm obtained by multiplying these two. 2 .

[0260] On the other hand, in the outer layer internal electrodes 12b and 13b of Example 3, since the thickness is 0.5 μm and the width is 200 μm, the area is 100 μm obtained by multiplying these two. 2 In the inner layer internal electrodes 12a and 13a of Example 3, the thickness is 0.5 μm and the width is 260 μm, so the area is 130 μm obtained by multiplying these two. 2 .

[0261] As described above, in the sample of Example 2, the area of ​​the internal electrodes 12 and 13 exposed at the end faces E1 and E2 is increased by more than 1.7 times compared with the sample of Example 1, and the internal electrodes 12 and 13 are easily and stably connected to the external electrodes 14 and 15. As a result, it is inferred that in the sample of Example 2, the variation of the electrostatic capacitance is suppressed compared with the sample of Example 1.

[0262] Similarly, in the sample of Example 4, the area of ​​the internal electrodes 12 and 13 exposed at the end faces E1 and E2 increases by more than 1.3 times relative to the sample of Example 3, and the internal electrodes 12 and 13 are easily and stably connected to the external electrodes 14 and 15. As a result, it is inferred that in the sample of Example 4, the variation in electrostatic capacitance is suppressed compared with the sample of Example 3.

[0263] <Other Implementation Methods>

[0264] As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, It is a matter of course that various changes can be added.

[0265] For example, the shape of the internal electrodes 12 and 13 is not limited to a rectangular shape, and can be changed within the scope of achieving the effect of the present invention. For example, the internal electrodes 12 and 13 may include an electrode main body located in the opposing region and a lead portion extending from the electrode main body to the end faces E1 and E2, and the width dimension of the lead portion may be smaller than the width dimension of the electrode main body. In this case, the maximum width dimension D2 of the outer internal electrodes 12b and 13b may be smaller than the minimum width dimension D1 of the inner internal electrodes 12a and 13a.

[0266] In addition, in the multilayer ceramic capacitor 10, the first main surface M1 and the second main surface M2 of the ceramic body 11 may be reversed. Fig.14 The circuit board 200 and Fig.16In the ceramic body 11 of the multilayer ceramic capacitor 10 in the package 300 shown, the first principal surface M1 may face downward in the Z-axis direction, and the second principal surface M2 may face upward in the Z-axis direction.

[0267] Description of Reference Numerals

[0268] 10…Multilayer ceramic capacitors

[0269] 11…Ceramic body

[0270] 12, 13…Internal electrodes

[0271] 12a, 13a…Inner layer internal electrodes

[0272] 12b, 13b…Outer inner electrode

[0273] 14, 15…External electrodes

[0274] 16…Capacitor forming part

[0275] 16a…Inner layer

[0276] 16b…Outer layer

[0277] 17… Covering

[0278] 18…Edge

[0279] 19…Ceramic layer

[0280] 20…Lamination

[0281] 200...Circuit Board

[0282] 300…Packaging

[0283] M1, M2…main surface

[0284] E1, E2…end face

[0285] S1, S2…side

[0286] F…Electrode does not exist area.

Claims

1. A laminated ceramic capacitor, characterized in that: The dimension in the first axis direction is 1.5 times or more of the dimension in the second axis direction perpendicular to the first axis, and the multilayer ceramic capacitor can be mounted on a mounting surface perpendicular to the first axis. The stacked ceramic capacitor comprises: a ceramic body having a pair of main surfaces perpendicular to the first axis, a pair of side surfaces perpendicular to the second axis, and a pair of end surfaces perpendicular to a third axis orthogonal to the first axis and the second axis; and a pair of external electrodes covering the pair of end faces, The ceramic body also has: a stacked portion having a plurality of internal electrodes alternately stacked with ceramic layers along a stacking direction parallel to the first axis or the second axis and led out to the end surface; and a pair of edge portions formed along the stacking direction, covering the stacking portion from a width direction of the internal electrode orthogonal to the stacking direction and the third axis, and containing an additive element consisting of at least one of Mg, Mn, Zr, Ti, Li, Mo, Nb, Cu, a rare earth element, or Sn at a higher concentration than that of the stacking portion, The plurality of internal electrodes are composed of a plurality of inner layer internal electrodes located on the inner side in the stacking direction and a plurality of outer layer internal electrodes located on both outer sides in the stacking direction and having a maximum width dimension smaller than a minimum width dimension of the inner layer internal electrodes.

2. The multilayer ceramic capacitor according to claim 1, wherein: The maximum width dimension of the outer layer internal electrode is at least twice the thickness dimension of the edge portion.

3. The multilayer ceramic capacitor according to claim 1, wherein: The maximum width dimension of the outer layer internal electrode is not more than 10 times the thickness dimension of the edge portion.

4. The multilayer ceramic capacitor according to claim 1, wherein: A distance between an end portion of the outer layer internal electrode in the width direction and the edge portion in the width direction is equal to or greater than a thickness dimension of the edge portion.

5. The multilayer ceramic capacitor according to claim 1, wherein: A distance between an end portion of the outer layer internal electrode in the width direction and the edge portion in the width direction is not more than 5 times a thickness dimension of the edge portion.

6. The multilayer ceramic capacitor according to claim 1, wherein: The number of stacked outer internal electrodes on one side in the stacking direction is 5% or more and 25% or less of the number of stacked all internal electrodes.

7. The multilayer ceramic capacitor according to any one of claims 1 to 6, wherein: The stacking direction is parallel to the second axis, The width direction of the internal electrode is parallel to the first axis.

8. The multilayer ceramic capacitor according to claim 7, wherein: The main surface has a higher flatness than the side surface.

9. A packaging body, characterized in that: include: The laminated ceramic capacitor according to claim 1; a carrier tape having a sealing surface perpendicular to the first axis and a recessed portion recessed from the sealing surface in the direction of the first axis and accommodating the multilayer ceramic capacitor; and A top tape is adhered to the sealing surface and covers the recessed portion.

10. A circuit board, characterized in that: include: The multilayer ceramic capacitor according to claim 1; and The mounting substrate includes the mounting surface and a pair of connection electrodes provided on the mounting surface, wherein the pair of connection electrodes are connected to the pair of external electrodes of the multilayer ceramic capacitor via solder.

11. A laminated ceramic capacitor, characterized in that: The dimension in the first axis direction is 1.3 times or more of the dimension in the second axis direction perpendicular to the first axis, and the multilayer ceramic capacitor can be mounted on a mounting surface perpendicular to the first axis. The stacked ceramic capacitor comprises: a ceramic body having a pair of main surfaces perpendicular to the first axis, a pair of side surfaces perpendicular to the second axis, and a pair of end surfaces perpendicular to a third axis orthogonal to the first axis and the second axis; and a pair of external electrodes covering the pair of end faces, The ceramic body also has: a stacked portion having a plurality of internal electrodes alternately stacked with ceramic layers along a stacking direction parallel to the first axis or the second axis and led out to the end surface; and a pair of edge portions formed along the stacking direction, covering the stacking portion from a width direction of the internal electrode orthogonal to the stacking direction and the third axis, and containing an additive element consisting of at least one of Mg, Mn, Zr, Ti, Li, Mo, Nb, Cu, a rare earth element, or Sn at a higher concentration than that of the stacking portion, The plurality of internal electrodes are composed of a plurality of inner layer internal electrodes located on the inner side in the stacking direction and a plurality of outer layer internal electrodes located on both outer sides in the stacking direction and having a maximum width dimension smaller than a minimum width dimension of the inner layer internal electrodes.

12. The multilayer ceramic capacitor according to claim 11, wherein: The maximum width dimension of the outer layer internal electrode is at least twice the thickness dimension of the edge portion.

13. The multilayer ceramic capacitor according to claim 11, wherein: The maximum width dimension of the outer layer internal electrode is not more than 10 times the thickness dimension of the edge portion.

14. The multilayer ceramic capacitor according to claim 11, wherein: A distance between an end portion of the outer layer internal electrode in the width direction and the edge portion in the width direction is equal to or greater than a thickness dimension of the edge portion.

15. The multilayer ceramic capacitor according to claim 11, wherein: A distance between an end portion of the outer layer internal electrode in the width direction and the edge portion in the width direction is not more than 5 times a thickness dimension of the edge portion.

16. The multilayer ceramic capacitor according to claim 11, wherein: The number of stacked outer internal electrodes on one side in the stacking direction is 5% or more and 25% or less of the number of stacked all internal electrodes.

17. The multilayer ceramic capacitor according to any one of claims 11 to 16, wherein: The stacking direction is parallel to the second axis, The width direction of the internal electrode is parallel to the first axis.

18. The multilayer ceramic capacitor according to claim 17, wherein: The main surface has a higher flatness than the side surface.

19. A packaging body, characterized in that: include: The laminated ceramic capacitor according to claim 11; a carrier tape having a sealing surface perpendicular to the first axis and a recessed portion recessed from the sealing surface in the direction of the first axis and accommodating the multilayer ceramic capacitor; and A top tape is adhered to the sealing surface and covers the recessed portion.

20. A circuit board, characterized in that: include: The laminated ceramic capacitor according to claim 11; and The mounting substrate includes the mounting surface and a pair of connection electrodes provided on the mounting surface, wherein the pair of connection electrodes are connected to the pair of external electrodes of the multilayer ceramic capacitor via solder.

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