Analog-digital multiplier, data processing method and device, equipment and medium

Abstract

The embodiment of the invention provides an analog-to-digital multiplier, a data processing method and device, equipment and a medium, and relates to the field of quantum computing, the analog-to-digital multiplier comprises a plurality of analog-to-digital constant adders, an analog-to-digital multiplying point arithmetic unit and an inverse multiplying point arithmetic unit; the modulus constant adders are in one-to-one correspondence with the quantum bits in the first register; the quantum state of each quantum bit in the first register is An-1gt; , A < n-2gt >; ... A0gt; representing a quantum superposition state Agt; a bit from high to low; according to an execution time sequence, a modulus multiple point arithmetic unit exists between two adjacent modulus constant adders; each modulus multiple point arithmetic unit is used for executing the evolution of * 2mod R on the superposition state represented by the second register; and a quantum state Amgt; the corresponding modulus constant adder is used in a quantum state Amgt; the weight is 1gt; and if yes, performing evolution of + Kmod R on the superposition state represented by the second register. In this way, multiplication for the specified modulus can be achieved.

Description

Technical Field

[0001] The present application relates to the field of quantum technology, and in particular to a modulus multiplier, a data processing method, a device, a equipment and a medium. Background Art

[0002] With the rapid development of quantum computing, the application scenarios of quantum technology are increasing. For example, data encryption and decryption based on quantum technology can realize quantum communication.

[0003] In various application scenarios, it is often necessary to implement quantum state multiplication operations for specified moduli through quantum circuits. For example, the quantum states of the qubits in a register represent the bits from high to low of the quantum superposition state |A>, and the quantum state of the qubits in another register is |B>. Then, it is necessary to implement |B> to |(B+AK)modR> through quantum circuits, where R represents the specified modulus and K represents the specified coefficient.

[0004] How to realize multiplication operations for specified moduli through quantum circuits is a problem that needs to be solved urgently. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a modulus multiplier, a data processing method, an apparatus, a device and a medium to implement a multiplication operation for a specified modulus. The specific technical solution is as follows:

[0006] In a first aspect of an embodiment of the present application, a modulus multiplier is first provided, comprising: a plurality of modulus constant adders, a modulus doubling operator and an inverse doubling operator; the inverse doubling operator is inverse to the modulus doubling operator and has the same number; each modulus constant adder corresponds to a quantum bit in a first register; the quantum state of each quantum bit in the first register |A n-1 >、|A n-2 >…|A0> respectively represent the bits of the quantum superposition state |A> from high to low; the execution sequence of each modulus constant adder is consistent with the order of the corresponding quantum state from high to low; according to the execution sequence, there is a modulus multiplication operator between two adjacent modulus constant adders; the modulus constant adder is located after the inverse multiplication operator; multiple inverse multiplication operators are adjacent in execution sequence;

[0007] Each modular multiplication point operator is used to perform ×2 mod R evolution on the superposition state represented by the second register;

[0008] and quantum state |A m >The corresponding modulus constant adder is used in the quantum state |A mWhen > is |1>, the superposition state represented by the second register is subjected to the evolution of +Kmod R; wherein R represents the first preset value, K represents the second preset value; and m≤n-1.

[0009] Optionally, a modulus point multiplication operator includes: a non-modulus constant adder, an X gate, and a non-modulus constant subtractor that is inverse to the non-modulus constant adder;

[0010] Each modulus multiplication point operator is used to perform the superposition state represented by the second register through the non-modulus constant subtractor of evolution; among them, Indicates rounding up;

[0011] After the non-modular constant subtractor operates, if the quantum state of the highest bit in the second register is |1>, the non-modular constant adder performs the superposition state represented by the other quantum states in the second register except the quantum state of the highest bit. evolution;

[0012] After the non-modular constant adder operates, evolving the quantum state of the highest bit in the second register through the X gate;

[0013] After the X-gate operation, the quantum state of the highest bit in the second register is adjusted to the lowest bit, and the other quantum states except the quantum state of the highest bit are adjusted to a higher bit respectively.

[0014] Optionally, a modulus constant adder includes: a first axis flip operator for RK, a second axis flip operator for R, and a third axis flip operator for K;

[0015] and quantum state |A m >The corresponding modulus constant adder is used in the quantum state |A m When > is |1>, the first axis flip operator performs axis flip processing on the superposition state represented by the second register for RK;

[0016] After the first axis flip operator performs operation, the second axis flip operator performs axis flip processing on R on the superposition state represented by the second register;

[0017] After the second axis flip operator performs operation, the third axis flip operator performs axis flip processing for K on the superposition state represented by the second register.

[0018] Optionally, the first axis flip operator is used to calculate the value of each calculation basis vector less than RK contained in the superposition state represented by the second register modulo RK-1, invert the calculated value, and replace the calculation basis vector with the calculation basis vector obtained by inverting it.

[0019] Optionally, the second axis flip operator is used to calculate the value of each calculation basis vector less than R contained in the superposition state represented by the second register modulo R-1, invert the calculated value, and replace the calculation basis vector with the calculation basis vector obtained by inverting it.

[0020] Optionally, the third axis flip operator is used to calculate the value of each calculation basis vector less than K contained in the superposition state represented by the second register modulo K-1, invert the calculated value, and replace the calculation basis vector with the calculation basis vector obtained by inverting it.

[0021] According to a second aspect of an embodiment of the present application, a quantum circuit is provided, wherein the quantum circuit includes a first register, a second register, and the modulus multiplier described in the first aspect.

[0022] A third aspect of the embodiments of the present application provides a data processing method, the method comprising:

[0023] Performing evolution operations according to the pre-constructed quantum circuit as described in the second aspect above;

[0024] The quantum bits in the second register are measured to obtain a result of the multiplication operation for the specified modulus.

[0025] According to a fourth aspect of the embodiments of the present application, a data processing device is provided, the device comprising:

[0026] An evolution module, used to perform evolution operations according to the pre-constructed quantum circuit as described in the second aspect;

[0027] The measurement module is used to measure the quantum bits in the second register to obtain the operation result of the multiplication operation for the specified modulus.

[0028] A fifth aspect of the embodiments of the present application provides a quantum computer device, comprising the quantum circuit as described in the second aspect; the quantum computer device implements any of the above-mentioned data processing methods when running.

[0029] According to a sixth aspect of an embodiment of the present application, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, any of the above-mentioned data processing methods is implemented.

[0030] An embodiment of the present application also provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any of the above-mentioned data processing methods.

[0031] Beneficial effects of the embodiments of the present application:

[0032] The modulus multiplier provided in the embodiment of the present application includes: a plurality of modulus constant adders, a modulus multiplication point operator and an inverse multiplication point operator; the inverse multiplication point operator is inverse to the modulus multiplication point operator and has the same number; each modulus constant adder corresponds to a quantum bit in the first register one by one; the quantum state of each quantum bit in the first register |A n-1 >、|A n-2 >…|A0> respectively represent the bits of the quantum superposition state |A> from high to low; the execution sequence of each modulus constant adder is consistent with the order of the corresponding quantum state from high to low; according to the execution sequence, there is a modulus multiplication operator between two adjacent modulus constant adders; the modulus constant adder is located after the inverse multiplication operator; multiple inverse multiplication operators are adjacent in execution sequence;

[0033] Each modular multiplication point operator is used to perform ×2 mod R evolution on the superposition state represented by the second register;

[0034] and quantum state |A m >The corresponding modulus constant adder is used in the quantum state |A n When > is |1>, the superposition state represented by the second register is subjected to the evolution of +Kmod R; wherein R represents the first preset value, K represents the second preset value; and m≤n-1.

[0035] According to the execution sequence, there is a modulus doubling operator between two adjacent modulus constant adders, that is, the number of modulus constant adders is one more than the number of modulus doubling operators. The modulus doubling operator is used to realize the evolution of ×2modR, and the inverse doubling operator is used to realize ×2 -1 Therefore, if we assume that the initial state of the quantum bit in the second register is |B>, then after each inverse doubling operator, |B> can be evolved into |B×(2 -1 ) n-1 mod R>, that is, the input of the first modulus constant adder includes |B×(2 -1 ) n-1 mod R>. Then, after the evolution of each modulus constant adder and each modulus multiplication point operator, we can get |((((B×(2 -1 ) n-1 +A n-1 K)2+A n-2 K)2+A n-3 K)+..)2+A0Kmod R>, that is, we can get |(B+A n-1 K2 n-1 +A n-2 K2 n-2 +A n-3K2 n-3 …A0K2 0 )mod R>. Since the quantum state |A n-1 >、|A n-2 >…|A0> represent the bits of the quantum superposition state |A> from high to low, that is, A is expanded into binary form and can be expressed as A n-1 2 n-1 +A n- twenty two n-2 +A n-3 2 n-3 …A02 0 Therefore, the final evolution result of the second register is |(B+AK) mod R>. It can be seen that the modulus multiplier provided in the embodiment of the present application can implement the multiplication operation for the specified modulus.

[0036] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0038] Figure 1 A schematic diagram of a quantum circuit provided in an embodiment of the present application;

[0039] Figure 2 A schematic diagram of a modulus multiplier provided in an embodiment of the present application;

[0040] Figure 3 A schematic diagram of a modulus multiplication point operator provided in an embodiment of the present application;

[0041] Figure 4 A schematic diagram of a modulus multiplication point operator provided in an embodiment of the present application;

[0042] Figure 5 A structural diagram of an axis flip operator provided in an embodiment of the present application;

[0043] Figure 6 A schematic diagram of a non-modulus constant adder provided in an embodiment of the present application;

[0044] Figure 7 A flowchart of a data processing method provided in an embodiment of the present application;

[0045] Figure 8A structural diagram of a data processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0047] The embodiment of the present application provides a modulus multiplier, comprising: a plurality of modulus constant adders, a modulus multiplication operator and an inverse multiplication operator; the inverse multiplication operator is inverse to the modulus multiplication operator and has the same number; each modulus constant adder corresponds to a quantum bit in a first register; the quantum state of each quantum bit in the first register |A n-1 >、|A n-2 >…|A0> respectively represent the bits of the quantum superposition state |A> from high to low; the execution sequence of each modulus constant adder is consistent with the order of the corresponding quantum state from high to low; according to the execution sequence, there is a modulus multiplication operator between two adjacent modulus constant adders; the modulus constant adder is located after the inverse multiplication operator; multiple inverse multiplication operators are adjacent in execution sequence;

[0048] Each modular multiplication point operator is used to perform ×2 mod R evolution on the superposition state represented by the second register;

[0049] and quantum state |A m > The corresponding modulus constant adder is used in the quantum state |A m When >is|1>, the superposition state represented by the second register is subjected to the evolution of +Kmod R; wherein R represents the first preset value, K represents the second preset value; and m≤n-1.

[0050] According to the execution sequence, there is a modulus doubling operator between two adjacent modulus constant adders, that is, the number of modulus constant adders is one more than the number of modulus doubling operators. The modulus doubling operator is used to realize the evolution of ×2modR, and the inverse doubling operator is used to realize ×2 -1 Therefore, if we assume that the initial state of the quantum bit in the second register is |B>, then after each inverse doubling operator, |B> can be evolved into |B×(2 -1 ) n-1 mod R>, that is, the input of the first modulus constant adder is |B×(2 -1 ) n-1mod R>. Then, after the evolution of each modulus constant adder and each modulus multiplication point operator, we can get |((((B×(2 -1 ) n-1 +A n-1 K)2+A n-2 K)2+A n-3 K)+..)2+A0Kmod R>, that is, we can get |(B+A n-1 K2 n-1 +A n-2 K2 n-2 +A n-3 K2 n-3 …A0K2 0 )mod R>.

[0051] Since the quantum state |A n-1 >、|A n-2 >…|A0> represent the bits of the quantum superposition state |A> from high to low, that is, A is expanded into binary form and can be expressed as A n-1 2 n-1 +A n-2 2 n-2 +A n-3 2 n-3 …A02 0 Therefore, the final evolution result of the second register is |(B+AK) mod R>. It can be seen that the modulus multiplier provided in the embodiment of the present application can implement the multiplication operation for the specified modulus.

[0052] The inverse doubling operator is the inverse of the modulus doubling operator, that is, the inverse doubling operator is used to achieve an evolution inverse to the modulus doubling operator. In other words, the inverse doubling operator represents the dagger circuit of the modulus doubling operator. For example, the inverse doubling operator is obtained by applying a transpose conjugate operation to the modulus doubling operator.

[0053] In one embodiment, K is smaller than R, and K and R are relatively prime.

[0054] See also Figure 1 , Figure 1 A schematic diagram of a quantum circuit provided in an embodiment of the present application.

[0055] Figure 1 In, |A n-1 >、|A n-2 >…|A0> represents the quantum state of each qubit in the first register, and |B> represents the initial state of the qubit in the second register. The number of qubits in the first register is n, that is, the number of modulus constant adders included in the modulus multiplier is n. Figure 1 The n-3 in the above means that except for |A n-1 >、|An-2 In addition to the quantum bits corresponding to > and |A0>, there are n-3 quantum bits.

[0056] exist Figure 1 In the quantum circuit, the dotted boxes from left to right represent the inverse doubling point operator, the modulus constant adder (modulus constant adder for K), and the modulus doubling point operator respectively. Figure 1 The quantum circuit in contains n modulus constant adders. According to the execution sequence, there is a modulus multiplication operator between every two modulus constant adders, that is, Figure 1 The quantum circuit in contains n-1 modulus multiplication operators, and the number of inverse multiplication operators is also n-1. The execution sequence is the order in which each operator evolves the quantum bit in the quantum circuit. Figure 1 The order of the operators from left to right in the quantum circuit reflects the execution sequence of the operators.

[0057] In |A n-1 >、|A n-2 >…|A0>, |A n-1 > represents the quantum state of the highest-order qubit, and |A0> represents the quantum state of the lowest-order qubit. It can be seen that the execution timing of the modulus constant adder corresponding to the highest-order qubit is the earliest, and the execution timing of the modulus constant adder corresponding to the lowest-order qubit is the latest.

[0058] The input of the first modulus constant adder includes: the evolution result of the last inverse point operator evolving the second register. That is to say, the timing of each inverse point operator is earlier than the modulus constant adder and the modulus point operator.

[0059] and quantum state |A m >The corresponding modulus constant adder, in the quantum state |A m When > is |1>, the evolution of +Kmod R can be performed in the superposition state represented by the second register.

[0060] That is to say, for any modulus constant adder, its corresponding qubit can be used as the control qubit of the modulus constant adder. When the quantum state of the control qubit is |1>, the modulus constant adder evolves the corresponding register; when the quantum state of the control qubit is |0>, the modulus constant adder does not evolve the corresponding register.

[0061] It is understandable that when the first modulus constant adder in the execution sequence is evolved, the superposition state that needs to be evolved is the evolution result of the last inverse doubling point operator evolving the second register.

[0062] According to the execution timing, there is a modulus multiplication operator between every two modulus constant adders. Therefore, for each modulus constant adder except the first modulus constant adder, when evolving according to the modulus constant adder, the superposition state that needs to be evolved at this time is the evolution result of the previous modulus multiplication operator evolving the second register.

[0063] See also Figure 2 , Figure 2 A simplified diagram of a modulus multiplier provided in an embodiment of the present application.

[0064] Figure 2 In the example, input A indicates that no evolution is performed on the quantum bits of this path. If the n above represents n quantum bits in a register (i.e., the first register), and their respective quantum states represent the bits from high to low of the quantum superposition state |A>, and the n below represents n quantum bits in another register (i.e., the second register), and the initial state is |B>, then the modular multiplier in this application can realize the evolution of |A>|B> to |A>|(B+AK)mod R>. That is, the quantum state of the quantum bits in the second register is evolved to |(B+AK)mod R>, and the quantum state of the quantum bits in the first register remains unchanged.

[0065] In one embodiment, a modulus point multiplication operator includes: a non-modulus constant adder, a non-modulus constant subtractor for implementing the inverse evolution of the non-modulus constant adder, and an X gate. The non-modulus constant adder and the non-modulus constant subtractor are both for of.

[0066] Each modulus multiplication point operator is used to perform a superposition state represented by the second register through a non-modulus constant subtractor. The evolution of Indicates rounding up.

[0067] After the non-modular constant subtractor operates, if the quantum state of the highest bit in the second register is |1>, the superposition state represented by the quantum states other than the highest bit in the current second register is performed by the non-modular constant adder. evolution.

[0068] After the non-modular constant adder operation, the quantum state of the highest bit in the current second register is evolved through the X gate.

[0069] After the X-gate operation, the quantum state of the highest bit in the current second register is adjusted to the lowest bit, and the quantum state of each bit in the other parts is adjusted to the higher bit by one bit.

[0070] The non-modular constant subtractor is used to realize the inverse evolution of the non-modular constant adder, that is, the non-modular constant subtractor represents the dagger circuit of the non-modular constant adder. For example, the non-modular constant subtractor is obtained by applying a transposed conjugate operation to the non-modular constant adder.

[0071] See also Figure 3 , Figure 3 A schematic diagram of a modulus point multiplication operator provided in an embodiment of the present application.

[0072] Figure 3 In the figure, from left to right are the non-modular constant subtractor, the non-modular constant adder, and the X gate. The non-modular constant subtractor needs to evolve the lowest qubit among the qubits, which is the highest qubit in the second register. The non-modular constant subtractor performs an evolution on all qubits in the second register. Evolution. The number of quantum bits is n.

[0073] The highest-order qubit is used as the control qubit of the non-modular constant adder. When the quantum state of the control qubit is |1>, the non-modular constant adder performs the superposition state represented by the quantum states other than the highest-order qubit in the second register. evolution.

[0074] When the quantum state of the control qubit is |0>, the non-modular constant adder does not perform the superposition state represented by other quantum states except the highest bit in the current second register. evolution, that is, the quantum state remains unchanged.

[0075] Figure 3 The rightmost dashed box in the figure indicates that the quantum state of the highest bit in the second register is adjusted to the lowest bit, and the quantum state of each bit in the other parts is adjusted to a higher bit. That is, the quantum state of each bit in the other parts is multiplied by 2.

[0076] See also Figure 4 , Figure 4 A simplified diagram of a modulus point multiplication operator provided in an embodiment of the present application.

[0077] If the quantum states of the n quantum bits in the register that needs to be evolved represent the bits from high to low of the quantum superposition state |A>, then the modulus multiplication point operator in the present application can realize the evolution from |A> to |A×2mod R>.

[0078] against In this case, the highest bit of register |A> is 0. When the register is evolved, it borrows one from the higher bit because it is not enough to subtract. Then, the highest bit of the register becomes 1. Therefore, the rest of the register except the highest bit is The evolution of , also makes the other part can be restored. Then, it is evolved through the X gate, so that the highest bit is also restored. The last step is to perform a shift operation, shifting the other part (carrying all the information of A) down by one bit, thus completing the multiplication by 2 operation, and since A is less than half of R, the result does not need further operation.

[0079] For example, if |A>=|5>, R=13, the binary expansion of A is 0101, 7 is expanded into binary form as 0111, and |A> is subtracted by a non-modulus constant subtractor. Evolution, we get |1110>. Since the highest bit is 1, the non-modulus constant adder is triggered to perform addition on the rest of the bits except the highest bit. Evolve to get |1101>. At this time, since the highest bit is 1, the highest bit is evolved through the X gate to get |0101>. Then, the highest quantum bit is adjusted to the lowest bit, and each quantum bit in the other parts is adjusted one bit to the higher position, to get |1010>, 1010 is 10 in decimal, and |A×2mod R>=|10mod 13>. It can be seen that the modulus multiplication point operator provided in the embodiment of the present application can realize the evolution of |A> to |A×2mod R>.

[0080] against In the case of, if R is limited to an odd number, the equal sign cannot be obtained. Therefore, After the evolution, the highest bit of the register is 0. Then, the evolution is performed through the X gate, and the shift operation is equivalent to performing a multiplication by 2 and a +1 operation. That is, it can be realized The value obtained is twice A modulo R.

[0081] For example, if |A>=|5>, R=7, the binary expansion of A is 0101, 4 is expanded into binary form as 0100, and |A> is subtracted by a non-modulus constant subtractor. Evolve to get |0001>. Since the highest bit is 0, the non-modular constant adder will not be triggered. Then, the highest bit is evolved through the X gate to get |1001>. Furthermore, the highest quantum bit is adjusted to the lowest bit, and each quantum bit in the other parts is adjusted one bit to the higher position, to get |0011>, 0011 is 3 in decimal, and |A×2mod R>=|3mod 7>. It can be seen that the modulus multiplication point operator provided in the embodiment of the present application can realize the evolution of |A> to |A×2mod R>.

[0082] In one embodiment, a modulus constant adder (ie, a modulus constant adder for K) includes: a first axis flip operator for RK, a second axis flip operator for R, and a third axis flip operator for K.

[0083] and quantum state |A m >The corresponding modulus constant adder is used in the quantum state |A m When > is |1>, the first axis flip operator performs axis flip processing on the superposition state represented by the current second register for RK. After the first axis flip operator performs operation, the second axis flip operator performs axis flip processing on the superposition state represented by the current second register for R. After the second axis flip operator performs operation, the third axis flip operator performs axis flip processing on the superposition state represented by the current second register for K.

[0084] In the embodiment of the present application, the axis flip operator for any value Z is equivalent to an operator that realizes the following functions:

[0085]

[0086] That is, when the quantum superposition state is evolved using the axis flip operator for Z, for any calculation basis |M> contained in the quantum superposition state, if the calculation basis |M> is greater than or equal to Z, the calculation basis |M> remains unchanged; if the calculation basis |M> is less than Z, the value obtained by taking the calculation basis |M> modulo Z-1 is calculated, and the calculated value is inverted, that is, |(-M)mod(Z-1)> is obtained, and the calculation basis |M> is replaced with the calculation basis |(-M)mod(Z-1)> obtained by taking the inversion. It can be understood that the inversion here refers to taking the inverse of addition, that is, taking the inversion for M is -M.

[0087] For multiple quantum bits used to represent each bit of the quantum superposition state, if the number of the multiple quantum bits is L, the maximum value that can be represented by the multiple quantum bits is 2 L -1, the calculation basis vectors include |0>, |1>, |2>…|2 L -1>. Any quantum superposition state represented by the multiple quantum bits may contain at least one of the above-mentioned computational basis vectors. Therefore, for any quantum superposition state, the computational basis vector contained therein may be determined.

[0088] For example: (Flip<4)(|0>+|1>+|2>+|3>+|4>+|5>+|6>+|7>)=(|3>+|2>+|1>+|0>+|4>+|5>+|6>+|7>)

[0089] It can be seen that, since Z=4, among the calculation basis vectors of |0>, |1>, |2>, |3>, |4>, |5>, |6>, |7>, |4>, |5>, |6>, |7> remain unchanged. For |0>, |(-0)mod 3>=|3>, therefore, |0> is replaced by |3>; for |1>, |(-1)mod3>=|2>, therefore, |1> is replaced by |2>; for |2>, |(-2)mod3>=|1>, therefore, |2> is replaced by |1>; for |3>, |(-3)mod3>=|0>, therefore, |3> is replaced by |0>.

[0090] Therefore, for each calculation basis vector less than RK contained in the superposition state represented by the current second register, the first axis flip operator can calculate the value obtained by taking the calculation basis vector modulo RK-1, invert the calculated value, and replace the calculation basis vector with the inverted calculation basis vector, so as to implement axis flipping processing for RK on the superposition state represented by the current second register.

[0091] Similarly, after the first axis flip operator, for each calculation basis vector less than R contained in the superposition state represented by the current second register, the second axis flip operator calculates the value obtained by taking the calculation basis vector modulo R-1, inverts the calculated value, and replaces the calculation basis vector with the inverted calculation basis vector, so as to implement axis flip processing for R on the superposition state represented by the current second register.

[0092] After the second axis flip operator, for each calculation basis vector less than K contained in the superposition state represented by the current second register, the third axis flip operator is used to calculate the value obtained by taking the calculation basis vector modulo K-1, the calculated value is inverted, and the calculation basis vector is replaced with the inverted calculation basis vector to implement axis flip processing for K on the superposition state represented by the current second register.

[0093] In one implementation, the axis flip operator for Z may include: two constant comparators for Z and two non-modulus constant subtractors for Z.

[0094] See also Figure 5 , Figure 5 A structural diagram of an axis flip operator for any value Z provided in an embodiment of the present application.

[0095] Figure 5 In FIG. 1 , the dashed boxes from left to right represent the first constant comparator for Z, the first non-modulus constant subtractor for Z, the second constant comparator for Z, and the second non-modulus constant subtractor for Z. In addition, the axis flip operator also includes two X gates.

[0096] Figure 5 The constant comparator in the circuit has two input registers. The upper register contains n qubits, and the quantum state of the n qubits is used to represent the quantum superposition state |A>. The lower register contains a dirty qubit. The constant comparator can compare the size relationship between Z and A, and determine whether to perform the X-gate evolution (i.e., flip) on the dirty qubit of the path according to the comparison result. For example, if A is less than Z, the X-gate evolution is performed on the dirty qubit of the path; if A is not less than Z, the X-gate evolution is not performed on the dirty qubit of the path, that is, the upper register remains unchanged. Figure 5 The non-modulus constant subtractor in can realize the evolution of |A> to |AZ>. Figure 5 In the example, the lower register (i.e., dirty qubit) can also serve as the control qubit of the non-modular constant subtractor for Z.

[0097] It is understandable that if we want to obtain the first axis flip operator for RK, we need to Figure 5 In the example, if we want to get the first axis flip operator for R, we can set Figure 5 In the example, Z is set to R. To obtain the first axis flip operator for K, set Figure 5 Just set Z in to K.

[0098] against Figure 5 For the constant comparator, in addition to the qubits used to represent |A> and |Z>, it only needs one qubit with a known state (also called a clean qubit) to store the comparison result. Accordingly, the modulus constant adder provided in the embodiment of the present application only needs one qubit with a known state. Furthermore, the modulus multiplier only needs one qubit with a known state, that is, only a few clean qubits are needed, which can save the number of clean qubits required and reduce the computing cost.

[0099] In one embodiment, a schematic diagram of a non-modular constant adder for any value Z can be found in Figure 6 .

[0100] Figure 6 In the figure, the dotted boxes from left to right represent the non-modulus constant adder for 1, the constant carry, the non-modulus constant adder for 1, the constant carry, and the Z L A non-modulus constant adder for Z H In addition, it also contains two X gates. A non-modulus constant adder for 1 and a non-modulus constant adder for Z L A non-modulus constant adder for Z HThe non-modular constant adder requires one dirty qubit each, and the constant carry requires n dirty qubits.

[0101] Figure 6 The left side of the line contains two registers. The upper register contains 2n+e qubits, whose quantum state represents the quantum superposition state |A> from high to low. The lower register contains 1 dirty qubit. e is 0 or 1, depending on the total number of qubits in the upper register. Correspondingly, Z can also be decomposed into Z according to the high and low bits according to the value of e. HL .

[0102] For the corresponding Z L A non-modulus constant adder can be used to convert Z L Divide again to get the corresponding high and low bits, and use Figure 6 That is, this method uses the idea of ​​continuous iterative adder to process, that is, Z L The high bit is continuously divided into the low bit and the high bit until the high bit and the low bit are only 1 bit. In another way, it can also be realized by using the Fourier constant adder in the related technology. H The non-modulus constant adder can also be implemented using the above two methods.

[0103] against Figure 6 The constant carry in the constant carry can determine the difference between A and Z. L Will the addition generate a carry (i.e., a carry to Z)? L If a carry is generated, the register is evolved through the X gate, that is, the register is flipped; if a carry is not required, the register is not evolved.

[0104] For example, if |>=11=|1011>, Z=6=0110, and assuming that the quantum state of the dirty qubit of the register below is |1>, the initial state is |11011>. Divide X into two parts, high bit |10>, low bit |11>. Divide Z into two parts, high bit |01>, low bit |10>.

[0105] In the first step, since the quantum state of the dirty quantum bit of the register below is |1>, the controlled execution increases the high bit by 1, and the high bit |11> is obtained.

[0106] The second step is to control the X gate and get the high bit |00>.

[0107] The third step is to execute the constant carry. Since the addition of the low bit of Z and the low bit of A will produce a carry, the quantum state of the dirty quantum bit of the register below is flipped to |0>.

[0108] In the fourth step, since the quantum state of the dirty quantum bit (i.e., the control bit) of the register below is |0>, the addition operation (for the non-modulus constant adder of 1) is not performed.

[0109] In the fifth step, the constant carry is executed, and the quantum state of the dirty quantum bit in the register below is flipped and restored to |1>.

[0110] Step 6: The controlled X gate is executed above, and the high position becomes |11>;

[0111] Then, add the high bit of the upper register and the high bit of Z |11>+|01>=|00>, and add the low bit of the upper register and the low bit of Z |11>+|10>=|01>. After addition, the high bit and the low bit form |0001>, and the result is consistent with the result of 11+6=17=1mod 16 (since the upper register has only four quantum bits, it will overflow if it is greater than 16. Therefore, it is equivalent to a modulo 16 operation).

[0112] Figure 6 The two constant carry devices in each require n dirty qubits. However, when performing the constant carry operation, the high-order qubits in the upper register are "idle", that is, the high-order qubits in the upper register (i.e., the qubits corresponding to n+e) are not evolved. Therefore, n qubits can be selected from the high-order qubits to be used temporarily as dirty qubits. In turn, the number of qubits required can be reduced to reduce the cost of calculation.

[0113] Based on the same inventive concept, an embodiment of the present application further provides a quantum circuit, which includes a first register, a second register, and the modulus multiplier in the above embodiment.

[0114] Based on the same inventive concept, the present application also provides a data processing method, see Figure 7 , Figure 7 A flowchart of a data processing method provided in an embodiment of the present application, the method may include the following steps:

[0115] S701: Execute an evolution operation according to a pre-constructed quantum circuit, such as the quantum circuit described in the above embodiment.

[0116] S702: Perform quantum measurement on the quantum bits in the second register to obtain a result of a multiplication operation for a specified modulus.

[0117] Based on the same inventive concept, the present application also provides a data processing device, see Figure 8 , Figure 8 A structural diagram of a data processing device provided in an embodiment of the present application, the device comprising:

[0118] The evolution module 801 is used to perform evolution operations according to a pre-built quantum circuit, such as the quantum circuit described in the above embodiment.

[0119] The measurement module 802 is used to perform quantum measurement on the quantum bits in the second register to obtain a result of a multiplication operation for a specified modulus.

[0120] Based on the same inventive concept, an embodiment of the present application further provides a quantum computer device, comprising the quantum circuit in the above embodiment; the quantum computer device implements the data processing method in the above embodiment when running.

[0121] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned data processing methods are implemented.

[0122] In another embodiment of the present invention, a computer program product including instructions is provided. When the computer program product is run on a computer, the computer executes any one of the data processing methods in the above embodiments.

[0123] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0124] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0125] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the implementation of quantum circuits, methods, devices, equipment, computer-readable storage media, and computer program products, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0126] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A modulus multiplier, characterized in that: include: A plurality of modulus constant adders, modulus doubling operators and inverse doubling operators; the inverse doubling operators are inverse to the modulus doubling operators and have the same number; each modulus constant adder corresponds to a quantum bit in the first register one by one; the quantum state of each quantum bit in the first register |A n-1 >、|A n-2 >…|A0> respectively represent the bits of the quantum superposition state |A> from high to low; the execution sequence of each modulus constant adder is consistent with the order of the corresponding quantum state from high to low; according to the execution sequence, there is a modulus multiplication operator between two adjacent modulus constant adders; the modulus constant adder is located after the inverse multiplication operator; multiple inverse multiplication operators are adjacent in execution sequence; Each modular multiplication point operator is used to perform ×2 mod R evolution on the superposition state represented by the second register; and quantum state |A m >The corresponding modulus constant adder is used in the quantum state |A m When > is |1>, the superposition state represented by the second register is subjected to the evolution of +Kmod R; wherein R represents the first preset value, K represents the second preset value; and m≤n-1.

2. The modulus multiplier according to claim 1, characterized in that: A modulus point multiplication operator includes: a non-modulus constant adder, an X gate, and a non-modulus constant subtractor which is the inverse of the non-modulus constant adder; Each modulus multiplication point operator is used to perform the superposition state represented by the second register through the non-modulus constant subtractor of evolution; among them, Indicates rounding up; After the non-modular constant subtractor operates, if the quantum state of the highest bit in the second register is |1>, the non-modular constant adder performs the superposition state represented by the other quantum states in the second register except the quantum state of the highest bit. evolution; After the non-modular constant adder operates, evolving the quantum state of the highest bit in the second register through the X gate; After the X-gate operation, the quantum state of the highest bit in the second register is adjusted to the lowest bit, and the other quantum states except the quantum state of the highest bit are adjusted to a higher bit respectively.

3. The modulus multiplier according to claim 1, characterized in that: A modulus constant adder includes: a first axis flip operator for RK, a second axis flip operator for R, and a third axis flip operator for K; and quantum state |A m >The corresponding modulus constant adder is used in the quantum state |A m When > is |1>, the first axis flip operator performs axis flip processing on the superposition state represented by the second register for RK; After the first axis flip operator performs operation, the second axis flip operator performs axis flip processing on R on the superposition state represented by the second register; After the second axis flip operator performs operation, the third axis flip operator performs axis flip processing for K on the superposition state represented by the second register.

4. The modulus multiplier according to claim 3, characterized in that: The first axis flip operator is used to calculate the value obtained by taking the calculation basis vector modulo RK-1 for each calculation basis vector less than RK contained in the superposition state represented by the second register, invert the calculated value, and replace the calculation basis vector with the calculation basis vector obtained by taking the inversion.

5. The modulus multiplier according to claim 3, characterized in that: The second axis flip operator is used to calculate the value obtained by taking the calculation basis vector modulo R-1 for each calculation basis vector less than R contained in the superposition state represented by the second register, invert the calculated value, and replace the calculation basis vector with the calculation basis vector obtained by taking the inversion.

6. The modulus multiplier according to claim 3, characterized in that: The third axis flip operator is used to calculate the value of each calculation basis vector less than K contained in the superposition state represented by the second register modulo K-1, invert the calculated value, and replace the calculation basis vector with the calculation basis vector obtained by inverting it.

7. A quantum circuit, characterized in that: The quantum circuit comprises a first register, a second register and a modulus multiplier as claimed in any one of claims 1 to 6.

8. A data processing method, characterized in that: The method comprises: Performing evolution operations according to the pre-constructed quantum circuit as claimed in claim 7; The quantum bits in the second register are measured to obtain a result of the multiplication operation for the specified modulus.

9. A data processing device, characterized in that: The device comprises: An evolution module, for performing an evolution operation according to a pre-constructed quantum circuit as claimed in claim 7; The measurement module is used to measure the quantum bits in the second register to obtain the operation result of the multiplication operation for the specified modulus.

10. A quantum computer device, characterized in that: The device comprises the quantum circuit as claimed in claim 7; the quantum computer device implements the method as claimed in claim 8 when running.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to claim 8 is implemented.

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