Time synchronization method and brake system applied to electronic mechanical brake system

Abstract

The embodiment of the present application provides a time synchronization method and a braking system for an electronic mechanical braking system, including: a main controller, at least one auxiliary controller; a first clock set on the main controller, and at least one second clock set on at least one auxiliary controller in a one-to-one correspondence; the main controller sends a first level signal and a second level signal to at least one auxiliary controller synchronously at a first moment and a second moment respectively through a hard line; when the second level signal received by at least one auxiliary controller is different from the first level signal, the at least one second clock is set to be the same as the first clock. The main controller and the auxiliary controller are connected by a hard line, and the hard line is used to replace the CAN line for time synchronization, which reduces the CAN bus load overhead, and the time synchronization is performed through the change of the level signal, which does not require the CPU to calculate, does not occupy CPU resources, reduces the CPU load, and improves the synchronization accuracy.

Description

Technical Field

[0001] The present application relates to the field of vehicle braking, and in particular to a time synchronization method and a braking system applied to an electronic mechanical braking system. Background Art

[0002] The Electronic Mechanical Brake (EMB) system is an advanced automotive braking technology. The system uses electrical energy to drive the brake and controls the braking action through a motor, thereby eliminating the traditional hydraulic pipelines and hydraulic components and simplifying the structure of the braking system. It uses electrical signals to transmit control signals and energy, has the characteristics of rapid response, and is very suitable for highly electrified applications.

[0003] In a typical EMB system, such as Figure 1 As shown, it is composed of a central controller and four wheel-side controllers. Specifically, the four wheel-side controllers include: a left front wheel wheel-side controller, a right front wheel wheel-side controller, a left rear wheel wheel-side controller and a right rear wheel wheel-side controller. These wheel-side controllers are respectively connected to the wheel speed sensors (Wheel Speed ​​Sensor, WSS) in a one-to-one correspondence. For example, the left front wheel wheel-side controller is connected to WSS-0, the right front wheel wheel-side controller is connected to WSS-1, the left rear wheel wheel-side controller is connected to WSS-2, and the right rear wheel wheel-side controller is connected to WSS-3, wherein WSS-0 represents the left front wheel speed sensor, WSS-1 represents the right front wheel speed sensor, WSS-2 represents the left rear wheel speed sensor, and WSS-3 represents the right rear wheel speed sensor. The direction of signal transmission is indicated by the direction of the arrow.

[0004] In the EMB system, the central controller is responsible for calculating the target clamping force, the release / clamping requirements of the Electronic Park Brake (EPB), the target wheel speed / slip ratio and other signals, and sends these signals to the four wheel-side controllers through the Controller Area Network (CAN) line. All wheel-side controllers obtain the actual wheel speed and calculate the slip ratio based on it. The wheel-side controllers can also obtain the actual clamping force, the actual release / clamping status of the EPB, the actual wheel speed / slip ratio and other signals, and send these signals to the central controller through CAN.

[0005] However, in Figure 1 In the EMB solution shown, there are two main technical problems in actual application: first, the communication signal between the central controller and the wheel-side controller does not respond in time; second, the communication signal sent by the central controller cannot be synchronously executed by the wheel-side controllers on the left and right sides.

[0006] Therefore, there is a problem of communication signal response delay between the central controller and the wheel-side controllers in the prior art, and time synchronization is required between the central controller and the wheel-side controllers. Summary of the invention

[0007] The purpose of the present application is to solve the problem of delayed response of communication signals between the central controller and the wheel-side controller in the prior art. Therefore, the present application provides a time synchronization method and a braking system applied to an electronic mechanical braking system, which reduces the synchronization error of the time synchronization between the main controller and the auxiliary controller in the electronic mechanical braking system, and thereby reduces the response speed of the communication signal between the main controller and the auxiliary controller.

[0008] An embodiment of the present application provides a time synchronization method applied to an electronic mechanical braking system. The electronic mechanical braking system includes: a main controller, at least one auxiliary controller connected to the main controller by a hard line, the hard line transmitting signals by high and low level changes; a first clock set on the main controller, and at least one second clock set on the at least one auxiliary controller in a one-to-one correspondence; the main controller sends a first level signal and a second level signal to the at least one auxiliary controller synchronously at a first moment and a second moment through the hard line, respectively, the first moment and the second moment are in the same synchronization cycle of the main controller, and the second moment is later than the first moment; when the at least one auxiliary controller receives a second level signal that is different from the first level signal, sets the at least one second clock to be the same as the first clock.

[0009] By adopting the above technical scheme, the main controller is connected to at least one auxiliary controller through a hard wire, and the hard wire is used instead of the CAN line for time synchronization. The main controller sends the first level signal and the second level signal through the hard wire at the first moment and the second moment respectively, so that when at least one auxiliary controller captures that the second level signal is different from the first level signal, at least one second clock is set to be the same as the first clock. There is no need to transmit messages through the CAN line, which reduces the CAN bus load overhead. The second clock is synchronized with the first clock through the change of the level signal. The level signal is output at the main controller end through the comparison output module of the general timer module, and the level signal is captured at the auxiliary controller end through the general timer module. The CPU does not need to participate in the output and capture of the level signal, the CPU does not need to perform calculations, does not occupy CPU resources, and reduces the CPU load.

[0010] In some embodiments, the main controller sends a first level signal and a second level signal to at least one auxiliary controller synchronously at a first time and a second time respectively through a hard line, and the at least one auxiliary controller sets at least one second clock to be the same as the first clock when the received second level signal is different from the first level signal, including:

[0011] At a first moment, the main controller sends a first level signal to the hard line;

[0012] The hard line sends the first level signal to at least one auxiliary controller synchronously respectively;

[0013] At least one auxiliary controller receives a first level signal;

[0014] At a second moment, the main controller sends a second level signal to the hard line;

[0015] The hard wire sends the second level signal to at least one auxiliary controller synchronously respectively;

[0016] At least one auxiliary controller receives a second level signal;

[0017] When the second level signal is different from the first level signal, at least one second clock is set to be the same as the first clock.

[0018] By adopting the above technical solution, the main controller sends a first level signal and a second level signal to at least one auxiliary controller. If the second level signal is different from the first level signal, at least one second clock is set to be the same as the first clock. The CPU does not need to be involved in calculations and operations, which can effectively improve the time synchronization efficiency. In addition, by using a hard-wired method to transmit signals through level changes, there is no need to perform time synchronization after calculation based on the sent message, which can effectively improve the accuracy of time synchronization and reduce synchronization errors.

[0019] In some embodiments, it further includes: a first micro control unit integrated on the main controller;

[0020] The first micro control unit on the main controller is connected to the hard line;

[0021] The main controller sends a first level signal and a second level signal to at least one auxiliary controller synchronously at a first moment and a second moment through a hard line, including:

[0022] Through the universal timer module of the first micro control unit on the main controller, a first level signal and a second level signal are synchronously sent to the hard line at a first moment and a second moment respectively.

[0023] By adopting the above technical solution, the first micro control unit integrated in the main controller end outputs the first level signal and the second level signal, and the first micro control unit is connected to the hard line, and the output of the level signal is realized through the hardware module (universal timer module) provided by the first micro control unit. It does not require CPU participation, does not occupy the CPU resources in the main controller, does not require CPU calculation, and can greatly reduce the CPU load. In addition, the combination of the first micro control unit and the hard line reduces the load overhead of the CAN bus.

[0024] In some embodiments, the invention further comprises: at least one second micro control unit integrated in at least one auxiliary controller in a one-to-one correspondence;

[0025] At least one second micro control unit is connected to the hard wire in a one-to-one correspondence;

[0026] When the received second level signal is different from the first level signal, at least one auxiliary controller sets at least one second clock to be the same as the first clock, including:

[0027] When receiving a second level signal sent by a hard line that is different from the first level signal, the universal timer module of the at least one second micro control unit sets at least one second clock to be the same as the first clock.

[0028] By adopting the above technical solution, at least one auxiliary controller end receives the first level signal and the second level signal through a universal timer module of at least one second micro control unit connected in a one-to-one correspondence, and responds, without the need for CPU participation or CPU calculation, which can greatly reduce the CPU load. In addition, the combination of at least one second micro control unit and hard wiring reduces the load overhead of the CAN bus.

[0029] In some embodiments, it further includes: a first noise reduction module connected to the first micro control unit;

[0030] The first micro control unit on the main controller synchronously sends a first level signal and a second level signal to the hard line at a first moment and a second moment, respectively, including:

[0031] The first micro control unit synchronously sends a first level signal and a second level signal to the hard line through the first noise reduction module at a first moment and a second moment respectively.

[0032] By adopting the above technical solution, the first microcontroller unit at the main controller end outputs the high / low level to the external hard line through the first noise reduction module, so that the on and off time of the first noise reduction module can be accurately controlled by adjusting the first level signal and / or the second level signal output by the first microcontroller unit, and the first microcontroller unit is electrically isolated from the external circuit, thereby isolating external noise and interference, improving stability and reliability, and further improving the accuracy of time synchronization. In addition, the time delay when the main controller and at least one auxiliary controller communicate through the first noise reduction module is very small, which can greatly improve the accuracy of time synchronization and reduce accuracy errors.

[0033] In some embodiments, the invention further comprises: at least one second noise reduction module connected in a one-to-one correspondence with at least one second micro control unit;

[0034] When the at least one second micro control unit receives a second level signal sent by a hard line that is different from the first level signal, setting at least one second clock to be the same as the first clock includes:

[0035] At least one second micro control unit receives the first level signal and the second level signal sent by the hard line through the corresponding at least one second noise reduction module;

[0036] When the second level signal is different from the first level signal, at least one second clock is set to be the same as the first clock.

[0037] By adopting the above technical solution, the hard wire electrically isolates the second microcontroller unit from the external circuit by controlling the switch of the second noise reduction module, thereby isolating external noise and interference, improving stability and reliability, and further improving the accuracy of time synchronization. In addition, the time delay when the main controller and at least one auxiliary controller communicate through the second noise reduction module is very small, which can greatly improve the accuracy of time synchronization and reduce precision errors.

[0038] In some embodiments, the system further includes: a first counter disposed in the first microcontroller unit, the first counter being connected to the first clock, the first counter counting from 0 to N, the value of N being set according to the synchronization period;

[0039] At a first moment, the count of the first counter is M, and the first micro control unit synchronously sends a first level signal to at least one auxiliary controller through a hard line, and the value of M is greater than 0 and less than N;

[0040] At the second moment, the count of the first counter returns from N to 0, and the first micro control unit synchronously sends a second level signal to at least one auxiliary controller through a hard line.

[0041] By adopting the above technical solution, the time for sending the first level signal and the second level signal is determined according to the count of the first timer connected to the first clock in the main controller. There is no need for CPU participation. Only the register needs to be set during initialization, which can effectively improve the efficiency of time synchronization.

[0042] In some embodiments, the system further comprises: at least one second counter disposed in at least one second microcontroller unit in a one-to-one correspondence, the at least one second counter being connected to at least one second clock in a one-to-one correspondence, the at least one second counter counting from 0 to N, the value of N being set according to the synchronization period;

[0043] When the second level signal received by the at least one second micro control unit is different from the first level signal, the count of the at least one second counter is synchronously set to 0.

[0044] By adopting the above technical solution, when at least one auxiliary controller receives a second level signal different from the first level signal, it responds to the second level signal and forcibly sets the count of the second counter to 0. This can instantly achieve time synchronization between at least one auxiliary controller and the main controller without the need for CPU participation and calculation, thereby reducing the CPU load and effectively achieving time synchronization.

[0045] In some embodiments, M is set to N / 2.

[0046] With the above technical solution, when M is set to N / 2, the first level signal and the second level signal in the first micro control unit each account for half, the output is relatively stable, and it helps to reduce noise interference, and can better achieve time synchronization.

[0047] An embodiment of the present application also provides a braking system, including the above-mentioned time synchronization method applied to an electronic mechanical braking system.

[0048] The present application provides a time synchronization method and a braking system applied to an electronic mechanical braking system, wherein a main controller and at least one auxiliary controller in the electronic mechanical braking system are connected by a hard line, and the main controller and the at least one auxiliary controller communicate through changes in a level signal. When at least one auxiliary controller receives a change in the level signal, the method immediately responds to the level signal and sets at least one second clock that is set in the at least one auxiliary controller in a one-to-one correspondence to be the same as the first clock in the main controller, thereby achieving time synchronization between the main controller and the at least one auxiliary controller, and achieving output and capture of the level signal through a general timer module in the main controller and the auxiliary controller, without CPU participation and calculation, without occupying CPU resources, and reducing CPU load, and replacing the traditional CAN line, not only reducing the CAN line load overhead, but also solving the problem of large synchronization error when performing time synchronization through the CAN line, and improving the time synchronization accuracy.

[0049] Other features and corresponding beneficial effects of the present invention are described in the latter part of the specification, and it should be understood that at least some of the beneficial effects become obvious from the records in this utility model. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 is a schematic diagram of an electromechanical braking system in the prior art;

[0051] Figure 2 It is a schematic diagram of the principle of time synchronization through a CAN line in the prior art;

[0052] Figure 3 A schematic diagram of another electromechanical braking system according to an embodiment of the present application;

[0053] Figure 4 A schematic diagram of another electromechanical braking system according to an embodiment of the present application;

[0054] Figure 5 A schematic diagram of another electromechanical braking system according to an embodiment of the present application;

[0055] Figure 6 This is a time synchronization sequence diagram of an embodiment of the present application. DETAILED DESCRIPTION

[0056] The following specific embodiments illustrate the implementation of the present application, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Although the description of the present application will be introduced in conjunction with some embodiments, this does not mean that the features of this application are limited to the implementation. On the contrary, the purpose of introducing the application in conjunction with the implementation is to cover other options or modifications that may be extended based on the claims of the present application. In order to provide a deep understanding of the present application, the following description will include many specific details. The present application can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present application, some specific details will be omitted in the description. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0057] It should be noted that in this specification, similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0058] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0059] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0060] In the description of the present application, it should be understood that in the present application, "electrical connection" can be understood as physical contact and electrical conduction between components; it can also be understood as a form in which different components in the circuit structure are connected through physical lines such as printed circuit board (PCB) copper foil or wires that can transmit electrical signals. "Coupled by..." can be understood as electrical conduction through air by indirect coupling. Indirect coupling can be understood as contactless coupling, in which those skilled in the art can understand that the coupling phenomenon refers to the phenomenon that there is close cooperation and mutual influence between the input and output of two or more circuit elements or electrical networks, and energy is transmitted from one side to the other through interaction.

[0061] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0062] It is known that in the EMB system, the communication between the central controller and the wheel-side controller requires time synchronization. Generally, the central controller is called the master controller (Master), and the wheel-side controller is called the slave controller (Slave). Regarding the time synchronization problem, the industry generally requires that the communication signal between the master controller and the slave controller should be responded within 2ms, that is, the communication message cycle between the Master and the Slave must be less than 2ms. In fact, considering the CPU load, 1ms is the best. For the wheel-side controllers at the left and right ends, the higher the execution synchronization rate, the better the EMB system performance is considered. Generally, the controller area network bus (Controller Area Network, CAN) based on the Automotive Open System Architecture (AUTOSAR) is used to achieve time synchronization. In theory, when the Master and four Slaves of the EMB are on the same time basis, the instructions with timestamps sent by the Master can be accurately executed by the four Slaves at the same time point.

[0063] Specifically, the time synchronization principle of AUTOSAR CAN line is as follows: Figure 2As shown in the figure, the CAN line of the master controller (CANMaster) reads its own time t0 at time t0, sends a synchronization message (SYNC) at time t1, and the SYNC message carries information (Signal) t0. The CAN line of the slave controller (CAN Slave) receives the SYNC message at time t2 and obtains information t0. Subsequently, the Master sends a Follow-Up Message (FUP), which carries information (Signal) t4 (Signal=t4=t1-t0). The Slave receives the FUP message and obtains information t4. The Slave performs time synchronization at time t3 (time t3 is the time synchronization point of the Slave). Without considering the delay of the SYNC message (that is, the Master sends the SYNC message and the Slave receives the SYNC at the same time point), the Slave can assume that at time t3, the Master's time is T=t4+t0+(t3-t2). Therefore, the Slave only needs to set T to its current time to complete the time synchronization between the Master and the Slave.

[0064] However, time synchronization through the AUTOSAR CAN line is a commonly used technical solution to meet the real-time requirements of EMB, but this solution has many problems in actual implementation: First, due to Figure 2 It can be seen that each time synchronization requires sending two frames of messages. When the load rate of the CAN bus of the EMB system is already very high, using CAN for time synchronization further increases the CAN load. Secondly, the 1ms periodic message sending leads to a high CPU load, and the actual task has to run in the 500us periodic operating system task (OS TASK). The use of CAN time synchronization (each synchronization requires two additional frames of messages) further increases the CPU overhead. Thirdly, when the time synchronization message is executed in a millisecond (ms) level periodic task, the error between the Master sending at time t1 and the actual sending completion is at the millisecond level, and the error between the Slave receiving the message and the actual reading of the time value at time t2 is also at the millisecond level. Therefore, the actual accuracy error of the entire time synchronization is at the millisecond level, which is poor. This is unacceptable in the EMB system.

[0065] Therefore, the existing technical solutions for achieving time synchronization between the main controller and the auxiliary controller have technical problems such as high CAN bus load rate, large CPU overhead, and poor synchronization accuracy.

[0066] In order to solve the above technical problems, the present application proposes a time synchronization method that combines hard wiring and MCU peripheral functions, and performs time synchronization through changes in level signals to replace traditional CAN lines for time synchronization, thereby improving the accuracy of time synchronization.

[0067] The present application embodiment provides a time synchronization method applied to an electronic mechanical brake system, such as Figure 3 As shown, the electronic mechanical brake system includes: a master controller (Master), at least one slave controller (Slave) connected to the master controller via a hard line, a first clock set on the master controller, and at least one second clock set on at least one slave controller in a one-to-one correspondence.

[0068] in, Figure 3 The dotted line without an arrow indicates a hard line, and the dotted line with an arrow indicates the transmission direction of the level signal.

[0069] It is known that hard wires usually refer to physical cables or wires, which are made of metal conductors and insulating materials. They can be copper wires, aluminum wires or other metal materials, which are used to directly connect the physical connection between devices; hard wires transmit high and low level signals, and transmit signals through high and low level changes.

[0070] Specifically, in the EMB system, the main controller and the auxiliary controller play a vital role. The main controller is usually an electronic control unit (ECU), which is the core component of the EMB system. The ECU is responsible for receiving information from sensors and other input devices, processing this information, and controlling the operation of actuators. The auxiliary controller, in the EMB system, can also be an ECU, or a controller specially designed for a specific function. Such as a controller for an anti-lock braking system (ABS) or an electronic stability program (ESC). These controllers usually work in conjunction with the main controller to ensure the precise control and efficient operation of the EMB system.

[0071] It should be noted that in the embodiment of the present application, there is no restriction on the types of the main controller and the auxiliary controller. It is mainly used in situations where time synchronization is required between the main controller and multiple or one auxiliary controller.

[0072] Furthermore, the first clock in the main controller is used to generate accurate timing signals to control the operation of other clocks and possibly devices. The at least one second clock set in at least one auxiliary controller in a one-to-one correspondence provides a stable time reference for the corresponding auxiliary controller to ensure the synchronous operation between the modules in each auxiliary controller.

[0073] In the embodiment of the present application, there is no restriction on the types of the first clock and at least one second clock, and the corresponding second clock in each auxiliary controller may use a clock source similar to that of the main controller, but the specific implementation may vary depending on the manufacturer and design. Common clock types include: internal clock, external clock, and programmable clock.

[0074] In one embodiment, the main controller sends a first level signal and a second level signal to at least one auxiliary controller synchronously at a first moment and a second moment respectively through a hard line, and when the at least one auxiliary controller receives a second level signal that is different from the first level signal, sets at least one second clock to be the same as the first clock.

[0075] The first moment and the second moment are in the same synchronization cycle of the main controller, and the second moment is later than the first moment.

[0076] In an embodiment of the present application, the synchronization period of the main controller can be set according to the specific situation. For example, it can be set according to the timeout period of the corresponding device, or it can be set according to the counting period of the counter. The synchronization can be performed once for each counting period or several counting periods to set the corresponding synchronization period.

[0077] It is known that the hard line transmits a level signal, therefore, in the embodiment of the present application, the first level signal and the second level signal are high level signals or low level signals. The specific situation can be set according to the actual situation.

[0078] In the embodiment of the present application, time synchronization is mainly performed through the changes of the two received level signals (the first level signal and the second level signal). If the first level signal is a low level signal, time synchronization is performed when the second level signal is received as a high level signal. Conversely, if the first level signal is a high level signal, time synchronization is performed when the second level signal is received as a low level signal.

[0079] In a specific embodiment, at a first moment, the main controller sends a first level signal to the hard wire; the hard wire sends the first level signal to at least one auxiliary controller synchronously; at least one auxiliary controller receives the first level signal; at a second moment, the main controller sends a second level signal to the hard wire; the hard wire sends the second level signal to at least one auxiliary controller synchronously; at least one auxiliary controller receives the second level signal; when the second level signal is different from the first level signal, at least one second clock is set to be the same as the first clock.

[0080] For example, when the Master outputs a high-level signal, it is sent to an external hardwire, which then inputs the high-level signal to four Slaves (note that the simple circuit in the figure is only used for logic illustration). The external hardwire outputs the high-level signal to the four Slaves, and the four Slaves receive the high-level signal synchronously; when the Master outputs a low-level signal, the four Slaves receive the low-level signal.

[0081] Therefore, after receiving a low-level signal, if the Slave receives a high-level signal at a certain moment thereafter, the corresponding second clock in the Slave is set to be the same as the first clock, and at least one second clock is forcibly set to be the same as the first clock. There is no need for message transmission and CPU calculation. In addition, since the main controller and at least one auxiliary controller are connected by a hard wire, each auxiliary controller can receive the level signal at the same time and respond synchronously, which can effectively improve the accuracy of time synchronization and reduce synchronization errors.

[0082] In the above technical scheme, the main controller is connected to at least one auxiliary controller through a hard wire, and the hard wire is used instead of the CAN line for time synchronization. The main controller sends the first level signal and the second level signal at the first moment and the second moment respectively through the hard wire, so that when the at least one auxiliary controller captures the second level signal and the first level signal are different, at least one second clock is set to be the same as the first clock at the same time. There is no need to transmit messages through the CAN line, which reduces the CAN bus load overhead; and the second clock is synchronized with the first clock through the change of the level signal, which does not require the CPU to calculate, does not occupy CPU resources, and reduces the CPU load; and the use of hard wires to transmit signals through level changes does not require time synchronization after calculation based on the sent message, which can effectively improve the accuracy of time synchronization and reduce synchronization errors.

[0083] In some specific embodiments, the EMB further includes: a first micro control unit (MCU-1) integrated on the main controller, and the first micro control unit (MCU-1) on the main controller is connected to the hard line.

[0084] Furthermore, if Figure 4 As shown, a first level signal and a second level signal are synchronously sent to a hard line at a first moment and a second moment respectively through a Generic Timer Module (GTM) of a first microcontroller unit (MCU-1) on a main controller.

[0085] Specifically, the advanced timer output module (ARU-connected TimerOutput Module, ATOM) in the GTM module can be used to perform comparison output without CPU participation and calculation.

[0086] In the embodiment of the present application, the first level signal and the second level signal are output by the GTM module of the first micro control unit (MCU-1) integrated in the main controller end, and the first micro control unit (MCU-1) is connected to the hard line, which does not need to occupy the CPU resources in the main controller and does not require CPU calculation, which can greatly reduce the CPU load, and the combination of the first micro control unit and the hard line reduces the load overhead of the CAN bus.

[0087] Furthermore, if Figure 4 As shown, it also includes: at least one second micro control unit (MCU-20, MCU-21, MCU-22, MCU-23) integrated in a one-to-one correspondence on at least one auxiliary controller.

[0088] Specifically, Figure 4 As shown in, taking four second micro control units (MCU-20, MCU-21, MCU-22, MCU-23) as an example, at least one second micro control unit is connected to the hard wire one by one; when the GTM module of at least one second micro control unit receives a second level signal sent by the hard wire that is different from the first level signal, it sets at least one second clock to be the same as the first clock.

[0089] Exemplarily, a timer input module (TIM) can be used to place the first level signal and the second level signal, and through a direct memory access (DMA) module, when the second level signal is different from the first level signal, at least one second clock can be set to be the same as the first clock without the participation and calculation of the CPU.

[0090] In an embodiment of the present application, at least one auxiliary controller end receives the first level signal and the second level signal through the GTM module of at least one second micro control unit connected in a one-to-one correspondence, and responds, without the need for the CPU to participate in the calculation, which can greatly reduce the CPU load. In addition, the combination of at least one second micro control unit and hard wiring reduces the load overhead of the CAN bus.

[0091] In some optional embodiments, such as Figure 5As shown, it also includes: a first noise reduction module (NR-1) connected to the first micro control unit (MCU-1); the first micro control unit (MCU-1) on the main controller, at a first moment and a first moment, synchronously sends a first level signal and a second level signal to the hard line respectively, including: the first micro control unit (MCU-1), at a first moment and a second moment, synchronously sends a first level signal and a second level signal to the hard line respectively through the first noise reduction module (NR-1).

[0092] Specifically, the first noise reduction module is mainly used to electrically isolate the MCU-1 from the external circuit, isolate the noise and interference of the external circuit outside the MCU-1, and improve the stability and reliability of the MCU-1.

[0093] In the embodiment of the present application, there is no restriction on the type of the first noise reduction module, which can be selected according to actual conditions. For example, the first noise reduction module can be: a transistor circuit, an operational amplifier, a digital filter, an analog filter, a power supply filter, and a grounding process, etc.

[0094] In an embodiment of the present application, the first microcontroller unit (MCU-1) at the main controller end outputs a high / low level to an external hard line through a first noise reduction module (NR-1), and can achieve precise control of the on and off time of the first noise reduction module (NR-1) by adjusting the first level signal and / or the second level signal output by the first microcontroller unit, and electrically isolate the first microcontroller unit from the external circuit, thereby isolating external noise and interference, improving stability and reliability, and further improving the accuracy of time synchronization. In addition, the time delay when the main controller and at least one auxiliary controller communicate through the first noise reduction module (NR-1) is very small, which can greatly improve the accuracy of time synchronization and reduce accuracy errors.

[0095] In some optional embodiments, such as Figure 5As shown, it also includes: at least one second noise reduction module (NR-20, NR-21, NR-22, NR-23) connected to at least one second micro control unit (MCU-20, MCU-21, MCU-22, MCU-23) in a one-to-one correspondence; when the at least one second micro control unit (MCU-20, MCU-21, MCU-22, MCU-23) receives a second level signal sent by a hard line that is different from the first level signal, sets at least one second clock to be the same as the first clock, including: at least one second micro control unit (MCU-20, MCU-21, MCU-22, MCU-23) receives the first level signal and the second level signal sent by the hard line through the corresponding at least one second noise reduction module (NR-20, NR-21, NR-22, NR-23); when the second level signal is different from the first level signal, sets at least one second clock to be the same as the first clock.

[0096] Figure 5 Taking four second microcontroller units as an example, four second noise reduction modules are required. For example, MCU-20 is connected to NR-20, MCU-21 is connected to NR-21, MCU-22 is connected to NR-22, and MCU-23 is connected to NR-23.

[0097] Specifically, at least one second noise reduction module (NR-20, NR-21, NR-22, NR-23) is mainly used to electrically isolate at least one second microcontroller unit (MCU-20, MCU-21, MCU-22, MCU-23) from an external circuit in a one-to-one correspondence, isolate the noise and interference of the external circuit outside the at least one second microcontroller unit (MCU-20, MCU-21, MCU-22, MCU-23), and improve the stability and reliability of at least one second microcontroller unit (MCU-20, MCU-21, MCU-22, MCU-23).

[0098] In the embodiment of the present application, there is no restriction on the type of at least one second noise reduction module (NR-20, NR-21, NR-22, NR-23), which can be selected according to actual conditions. For example, at least one second noise reduction module is configured as: a transistor circuit, an operational amplifier, a digital filter, an analog filter, a power supply filter, and a grounding process, etc.

[0099] In an embodiment of the present application, the hard wire electrically isolates at least one second microcontroller unit (MCU-20, MCU-21, MCU-22, MCU-23) from the external circuit one by one by controlling the switch of at least one second noise reduction module (NR-20, NR-21, NR-22, NR-23), thereby isolating external noise and interference, improving stability and reliability, and further improving the accuracy of time synchronization. In addition, the time delay between the main controller and at least one auxiliary controller during communication through at least one second noise reduction module (NR-20, NR-21, NR-22, NR-23) is very small, which can greatly improve the accuracy of time synchronization and reduce accuracy errors.

[0100] In some embodiments, it also includes: a first counter set in a first microcontroller, at a first moment, the count of the first counter is M, and the first microcontroller sends a first level signal to at least one auxiliary controller synchronously through a hard line, wherein the value of M is greater than 0 and less than N; at a second moment, the count of the first counter returns from N to 0, and the first microcontroller sends a second level signal to at least one auxiliary controller synchronously through a hard line.

[0101] Specifically, the first counter is connected to the first clock, and the first counter counts from 0 to N, where the value of N is set according to the synchronization cycle.

[0102] In an embodiment of the present application, the time for sending the first level signal and the second level signal is determined according to the count of the first timer connected to the first clock in the main controller. There is no need for CPU participation, and only the register needs to be set during initialization, which can effectively improve the efficiency of time synchronization.

[0103] In some embodiments, it also includes: at least one second counter is set in at least one second micro control unit in a one-to-one correspondence, at least one second counter is connected to at least one second clock in a one-to-one correspondence, at least one second counter counts from 0 to N, and the value of N is set according to the synchronization period; when the second level signal received by at least one second micro control unit is different from the first level signal, the count of at least one second counter is synchronously set to 0.

[0104] For example, assuming that the frequencies of the first counter (Timer) and at least one second counter used for time synchronization of the Master and Slave are both 10M, and the counting deviation (Δt) between the Master and Slave is 0.00000001s, if the deviation between the two is required to be no greater than 1ms, then M=100000 and N=50000.

[0105] In an embodiment of the present application, when at least one auxiliary controller receives a second level signal different from the first level signal, it responds to the second level signal and forcibly sets the count of the second counter to 0, thereby instantly achieving time synchronization between at least one auxiliary controller and the main controller without the need for CPU participation and calculation, thereby reducing the CPU load and effectively achieving time synchronization.

[0106] In some embodiments, M is set to N / 2. When M is set to N / 2, the first level signal and the second level signal in the first micro control unit each account for half, the output is relatively stable, and it helps to reduce noise interference, and can better achieve time synchronization.

[0107] The following is an explanation through a specific embodiment.

[0108] like Figure 5 As shown, in order to achieve higher time synchronization accuracy between the Master and Slave of the EMB without affecting the CAN line communication load rate between the Master and Slave and the CPU load, the present application adopts a combination of hard wire and the peripheral functions of the microcontroller unit (MCU) to replace the CAN line for time synchronization.

[0109] Specifically, when a transistor is selected as the first noise reduction unit and at least one second noise reduction unit, the Master outputs a high-level signal, which is output to an external hard line through the transistor, and the external hard line inputs the high-level signal to four Slaves. The external hard line signal controls the transistor switches in the four Slaves. When the Master outputs a high-level signal, the four Slaves receive the high-level signal; when the Master outputs a high-level signal, the four Slaves receive a low-level signal.

[0110] In an embodiment of the present application, within a certain period of time, the first counter (Timer) and at least one second counter used by the Master and Slave of the EMB system to obtain the timestamp are forced to be pulled to the same starting point. In order to force the hard-wired signal output by the Master to be associated with the first counter, the advanced timer output module (ARU-connected Timer Output Module, ATOM) in the Generic Timer Module (GTM) of MCU-1 is used. Through initialization configuration, the ATOM module can enable the MCU to automatically output a logic level signal (a high level signal or a low level signal, i.e., a first level signal or a second level signal) when the first counter counts to a certain specific value. In this way, the output time point of the Master does not need to be calculated by the CPU.

[0111] In the embodiments of the present application, it is not limited to using the ATOM module of the GTM in the MCU-1. Any module that can achieve clock synchronous output can be used in the embodiments of the present application. Exemplarily, a timer output module (Timer Output Module, TOM) module can be used, etc.

[0112] In the Slave, in order to forcibly associate the first level signal and the second level signal input by the hard wire with the corresponding at least one second counter, the timer input module (Timer Input Module, TIM) module of the GTM自带 by the corresponding at least one second microcontroller unit is used to capture the first level signal or the second level signal. When the TIM module receives a transition edge (that is, a low level signal becomes a high level signal, or a high level signal becomes a low level signal), it will trigger an interrupt request, and the interrupt request is associated with a direct memory access (Direct Memory Access, DMA) module. The DMA is set to write the value 0 to the corresponding at least one second counter each time it is triggered. The interrupt request and the DMA writing data to the corresponding at least one second counter are both completed by the TIM module itself without the participation of the CPU.

[0113] In the embodiments of the present application, it is not limited to using the TIM module and the DMA module. Any module that can trigger the reset of at least one second counter when receiving the first level signal or the second level signal can be used in the embodiments of the present application.

[0114] As Figure 6 shown, the embodiments of the present application will be described in detail below through a timing diagram.

[0115] The first counter in the Master and the at least one second counter corresponding to each Slave have the same frequency. (In Figure 6 and hereinafter, Timer is used to represent the first counter and the at least one second counter) The Timer starts counting from 0, counts to N, and then returns to 0; this Timer is used as the timestamp for communication between the Master and the Slave.

[0116] For the Master, the Timer is associated with the ATOM module of the GTM. When the Timer returns from N to 0, the MCU-1 hardware of the Master automatically triggers the output of a high level signal; when the Timer value reaches the value M (M < N), the MCU-1 hardware automatically triggers the output of a low level signal. The Master simultaneously outputs a high level signal and a low level signal through the hard wire to the MCU ends of 4 Slaves (including at least one of MCU-20, MCU-21, MCU-22, MCU-23).

[0117] For the Slave, when the TIM module of the GTM captures the rising edge of the Master input through the hard line (that is, the low-level signal changes to a high-level signal), the TIM module generates a DMA request, and the DMA request changes the current value of the Timer to 0.

[0118] The entire process is completed by the microcontroller (the first microcontroller or at least one second microcontroller) hardware autonomously, without the CPU involvement. The software only needs to set the registers during initialization. When the Master outputs a high-level signal, the Master's own Timer returns to 0, and then outputs a high-level signal to the Slave, setting the Slave's Timer to 0, thereby achieving time synchronization. All Slaves receive the same signal, so the purpose of synchronization is also achieved between Slaves.

[0119] Among them, when the slave's timer does not receive a jump edge, it counts according to its own counter rule until it receives a jump edge. Therefore, the values ​​of P and Q are greater than or equal to 0 and less than or equal to N.

[0120] It is known that when the Master and Slave communicate through transistors, there is a certain delay. The typical transistor delay is less than 1us. For example, there are two transistors in the serial communication circuit between the Master and Slave, and the delay is: T1<2 microseconds (us). In addition, it takes time to trigger the DMA to rewrite the Timer register, which is set to T2. This time is usually in the nanosecond level, so T2<1us. It can be seen that the theoretical error of synchronization between the Master and Slave is T3=T1+T2, and T3<3us. That is, in this application, the time interval between the Master time synchronization trigger point and the Slave time synchronization response point is less than 3us. When the Master's Timer synchronizes back to 0, the Slave's Timer must be forced to synchronize after T3 time, but T3 is very small relative to the system requirements (generally in the ms level) and can be ignored.

[0121] An embodiment of the present application also provides a braking system, including the above-mentioned time synchronization method applied to an electronic mechanical braking system.

[0122] A time synchronization method and a braking system for an electronic mechanical braking system provided in an embodiment of the present application use a combination of hard wires and peripheral functions of an MCU (such as the ATOM module of a GTM) to control time synchronization, thereby reducing the CAN bus load overhead compared to a traditional CAN line time synchronization method; and, the output of a level signal is achieved through the ATOM module in a first microcontroller unit in a main controller, and the capture of a level signal is achieved through a TIM module and a DMA module in a second microcontroller unit in an auxiliary controller, without the need for CPU participation or CPU calculation, without occupying CPU resources, and thus reducing CPU load; a voltage signal is transmitted through a hard wire, and through the combination of changes in the voltage signal and a noise reduction module, the time synchronization between the main controller and the auxiliary controller is achieved, with a smaller synchronization error and higher precision on a stable basis.

[0123] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and modifications of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and modifications.

Claims

1. A time synchronization method applied to an electromechanical braking system, characterized in that: The electronic mechanical braking system comprises: A main controller and at least one auxiliary controller connected to the main controller via a hard line, the hard line transmitting signals via high and low level changes; A first clock arranged on the main controller and at least one second clock arranged on the at least one auxiliary controller in a one-to-one correspondence; The main controller sends a first level signal and a second level signal to the at least one auxiliary controller synchronously at a first moment and a second moment through the hard line, respectively, wherein the first moment and the second moment are within the same synchronization cycle of the main controller, and the second moment is later than the first moment; When the received second level signal is different from the first level signal, the at least one auxiliary controller sets the at least one second clock to be the same as the first clock; Also includes: a first micro control unit integrated on the main controller; and at least one second micro control unit integrated on the at least one auxiliary controller in a one-to-one correspondence; a first counter provided in the first micro control unit, the first counter being connected to the first clock, the first counter counting from 0 to N, the value of N being set according to the synchronization period; At the first moment, the count of the first counter is M, the first micro control unit synchronously sends the first level signal to the at least one auxiliary controller through the hard line, and the value of M is greater than 0 and less than N; At the second moment, the count of the first counter returns from N to 0, and the first micro control unit synchronously sends the second level signal to the at least one auxiliary controller through the hard line; At least one second counter is arranged in the at least one second micro control unit in a one-to-one correspondence, the at least one second counter is connected to the at least one second clock in a one-to-one correspondence, the at least one second counter counts from 0 to N, and the value of N is set according to the synchronization period; When the second level signal received by the at least one second micro control unit is different from the first level signal, the count of the at least one second counter is synchronously set to 0.

2. The time synchronization method applied to an electronic mechanical brake system according to claim 1, characterized in that: The main controller sends a first level signal and a second level signal to the at least one auxiliary controller synchronously at a first moment and a second moment through the hard line, and the at least one auxiliary controller sets the at least one second clock to be the same as the first clock when the second level signal received is different from the first level signal, including: At the first moment, the main controller sends the first level signal to the hard line; The hard line sends the first level signal to the at least one auxiliary controller synchronously respectively; The at least one auxiliary controller receives the first level signal; At the second moment, the main controller sends the second level signal to the hard line; The hard line sends the second level signal to the at least one auxiliary controller synchronously respectively; The at least one auxiliary controller receives the second level signal; When the second level signal is different from the first level signal, the at least one second clock is set to be the same as the first clock.

3. The time synchronization method applied to an electronic mechanical braking system according to claim 1 or 2, characterized in that: The first micro control unit on the main controller is connected to the hard line; The main controller synchronously sends a first level signal and a second level signal to the at least one auxiliary controller at a first moment and a second moment through the hard line, respectively, including: The first level signal and the second level signal are sent to the hard line synchronously at the first moment and the second moment respectively through the universal timer module of the first micro control unit on the main controller.

4. The time synchronization method applied to an electronic mechanical braking system according to claim 1 or 2, characterized in that: The at least one second micro control unit is connected to the hard wire in a one-to-one correspondence; When the received second level signal is different from the first level signal, the at least one auxiliary controller sets the at least one second clock to be the same as the first clock, including: When the second level signal sent by the hard line is different from the first level signal, the universal timer module of the at least one second micro control unit sets the at least one second clock to be the same as the first clock.

5. The time synchronization method applied to an electronic mechanical brake system as claimed in claim 3, characterized in that: It also includes: a first noise reduction module connected to the first micro control unit; The first micro control unit on the main controller synchronously sends the first level signal and the second level signal to the hard line at the first moment and the second moment respectively, including: The first micro control unit, at a first moment and a second moment, synchronously sends the first level signal and the second level signal to the hard line through the first noise reduction module respectively.

6. The time synchronization method applied to an electronic mechanical brake system according to claim 4, characterized in that: Also included: at least one second noise reduction module connected to the at least one second micro control unit in a one-to-one correspondence; When the at least one second micro control unit receives the second level signal sent by the hard line and the second level signal is different from the first level signal, setting the at least one second clock to be the same as the first clock includes: The at least one second micro control unit receives the first level signal and the second level signal sent by the hard line through the corresponding at least one second noise reduction module; When the second level signal is different from the first level signal, the at least one second clock is set to be the same as the first clock.

7. The time synchronization method for an electronic mechanical brake system according to claim 1, characterized in that: The M is set to N / 2.

8. A braking system, characterized in that: The invention comprises a time synchronization method applied to an electronic mechanical braking system as described in any one of claims 1 to 7.

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