Parallel current summing system and control method thereof

Abstract

The invention discloses a parallel current adding system, belongs to the technical field of electronic equipment for measurement and test, and solves the problem of how to design a parallel current adding system which is simple in hardware circuit and high in control precision. The parallel-connection current adding system comprises a plurality of single-machine current sampling circuits and a parallel-connection current adding circuit, the single-machine current sampling circuit comprises a first differential amplification circuit, a first proportional adjustment circuit, a first unit phase inverter circuit and a first digital potentiometer; the parallel current summing circuit comprises an instrument amplifier circuit, a second proportional adjusting circuit, a second unit phase inverting circuit, a second digital potentiometer and a plurality of proportional input end resistors; the digital potentiometers are applied to the parallel operation circuit, the amplification factor is adjusted by assigning the resistance values of the potentiometers according to the set parallel operation number, the mode that the amplification factor is adjusted by switching the resistance value of a single proportional resistor of a traditional resistance proportional circuit is replaced, a hardware circuit is simple, and amplification factor control is accurate.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic equipment for measuring and testing, and relates to a parallel current adding system and a control method thereof. Background Art

[0002] In AC and DC power supply and load systems, high-precision resistors and operational amplifiers are generally used to form current sampling circuits. The device reads the current code value through the ADC chip, and the chip calculates the actual current through the calibration coefficient. Most parallel power supplies and load parallel methods are divided into two types: analog parallel and digital parallel.

[0003] The analog parallel mode mainly uses a differential amplifier to sample the current of each device, converts the current signal into a voltage signal, and finally connects it to the host current summing circuit, and then the host ADC collects the total current signal to calculate the total parallel current. This method needs to change the summing op amp proportional resistor when multiple devices are paralleled to generate a large current, which affects the parallel current sampling accuracy. In addition, when changing the number of parallel units, the summing ratio needs to be switched, the circuit is complex, the control is cumbersome, and the calibration is difficult. In the digital parallel system, after each unit collects the current of the unit through the ADC, the current values ​​collected by each part of the unit are summed up and calculated in the host through digital communication methods such as CAN and SPI, and then sent to each slave. This method solves the interference problem in transmission, but ADC acquisition and digital communication require a certain amount of time, which introduces delay and cannot achieve real-time acquisition.

[0004] The difficulty of the current technology is that when multiple machines are connected in parallel, it is necessary to switch the proportional coefficient in the parallel adding circuit through analog switches or other switching devices. Each time a device is added, the differential gain needs to be adjusted. The problem at this time is that the hardware circuit is complicated, more control interfaces are required, and it is difficult to calibrate. Summary of the invention

[0005] The technical solution of the present invention is used to solve the problem of how to design a parallel current addition system with simple hardware circuit and high control accuracy.

[0006] The present invention solves the above technical problems through the following technical solutions:

[0007] A parallel current summing system comprises: a plurality of single-machine current sampling circuits and a parallel current summing circuit; the single-machine current sampling circuit comprises: a first differential amplifier circuit, a first proportional adjustment circuit, a first unit inverter circuit, and a first digital potentiometer; the parallel current summing circuit comprises: an instrument amplifier circuit, a second proportional adjustment circuit, a second unit inverter circuit, a second digital potentiometer, and a plurality of proportional input resistors; the input end of the first differential amplifier circuit samples the single-machine current flowing through the sampling resistor, the output end of the first differential amplifier circuit is connected to the B end of the first digital potentiometer, the W end of the first digital potentiometer is connected to the inverting input end of the first proportional adjustment circuit, and the A end of the first digital potentiometer is connected to the output end of the first proportional adjustment circuit; the output end of the first proportional adjustment circuit is connected to the input end of the first unit inverter circuit, wherein the output end of the first proportional adjustment circuit outputs a PARA+ signal, and the output end of the first unit inverter circuit outputs a PARA- signal; the P of the plurality of single-machine current sampling circuits The ARA+ signal terminal is connected to the PARA+ signal terminal of the parallel current summing circuit, and the PARA- signal terminals of multiple single-machine current sampling circuits are connected to the PARA- signal terminal of the parallel current summing circuit; the number of proportional input terminal resistors is twice that of the single-machine current sampling circuit, and the multiple proportional input terminal resistors are divided into two groups. The first group of proportional input terminal resistors are all connected in parallel, and a parallel common terminal after parallel connection serves as the PARA+ signal terminal of the parallel current summing circuit, and another parallel common terminal after parallel connection is connected to the first input terminal of the instrument amplifier circuit. The second group of proportional input terminal resistors are also all connected in parallel, and a parallel common terminal after parallel connection serves as the PARA- signal terminal of the parallel current summing circuit, and another parallel common terminal after parallel connection is connected to the second input terminal of the instrument amplifier circuit; the output terminal of the instrument amplifier circuit is connected to the A terminal of the second digital potentiometer, the W terminal of the second digital potentiometer is connected to the inverting input terminal of the second proportional adjustment circuit, and the B terminal of the second digital potentiometer is connected to the input terminal of the second unit inverting circuit;

[0008] When the stand-alone mode is set, the stand-alone current passes through the sampling resistor and is converted into a stand-alone ADC1 signal through the first differential amplifier circuit (1). The ADC1 signal is directly connected to the current ADC sampling chip to read the ammeter current, and the calibration coefficients k1 and b1 are calculated together with the ADC code value and saved in the CPU; ADC code value = actual current Ir1*k1+b1;

[0009] During calibration, adjust the code value of the first digital potentiometer of each stand-alone current sampling circuit so that PARA+ and PARA- are equal to the target value; at this time, connect PARA+ and PARA- of each stand-alone current sampling circuit to the parallel current summing circuit, and adjust the second digital potentiometer of the parallel current summing circuit so that the voltage at point B of the parallel current summing circuit is equal to the PARA+ of the stand-alone current sampling circuit; disconnect the connection between ADC1 of the stand-alone current sampling circuit and the ADC chip, connect ADC2 of the parallel current summing circuit to the ADC chip, calculate the k2 and b2 coefficients at this time, ADC code value = actual current Ir2*k2+b2, and the calibration is completed;

[0010] When set to parallel mode, after each single machine completes the calibration of two sets of coefficients, n single machines are connected in parallel. At this time, the parallel configuration information is sent down, and the setting value of the second digital potentiometer is changed according to the number of parallel machines to achieve the effect of parallel current addition.

[0011] Furthermore, the first differential amplifier circuit includes: a sampling resistor R3, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, and a first operational amplifier U1; one end of the resistor R5 is connected to the inverting input end of the first operational amplifier U1, one end of the resistor R6 is connected to the non-inverting input end of the first operational amplifier U1, and the other end of the resistor R5 and the other end of the resistor R6 are respectively connected to the two ends of the sampling resistor R3; one end of the resistor R7 is connected to the inverting input end of the first operational amplifier U1, and the other end of the resistor R7 is connected to the output end of the first operational amplifier U1; one end of the resistor R8 is connected to the non-inverting input end of the first operational amplifier U1, the other end of the resistor R8 is grounded, one end of the resistor R9 is connected to the output end of the first operational amplifier U1, and the other end of the resistor R9 is connected to the B end of the first digital potentiometer; the output end signal of the first operational amplifier U1 is used as a single-machine ADC1 signal.

[0012] Furthermore, the first proportional adjustment circuit includes: a resistor R10 and a second operational amplifier U2; the W end of the first digital potentiometer is connected to the inverting input end of the second operational amplifier U2, the non-inverting input end of the second operational amplifier U2 is grounded, the A end of the first digital potentiometer is connected to one end of the resistor R10, and the other end of the resistor R10 is connected to the output end of the second operational amplifier U2; the output end signal of the second operational amplifier U2 is used as the PARA+ signal.

[0013] Furthermore, the first unit inverter circuit includes: a resistor R14, a resistor R15, and a third operational amplifier U3; one end of the resistor R14 is connected to the output end of the second operational amplifier U2, and the other end of the resistor R14 is connected to the inverting input end of the third operational amplifier U3; one end of the resistor R15 is connected to the inverting input end of the third operational amplifier U3, and the other end of the resistor R15 is connected to the output end of the third operational amplifier U3, and the non-inverting input end of the third operational amplifier U3 is grounded; the output end signal of the third operational amplifier U3 is used as the PARA- signal.

[0014] Furthermore, the instrument amplifier circuit includes: resistor R16, resistor R17, resistor R18, resistor R19, resistor R20, resistor R21, a fourth operational amplifier U4, a fifth operational amplifier U5, and a sixth operational amplifier U6; another parallel common end of the first group of proportional input terminal resistors connected in parallel is connected to the inverting input terminal of the fourth operational amplifier U4, the non-inverting input terminal of the fourth operational amplifier U4 is grounded, one end of the resistor R16 is connected to the inverting input terminal of the fourth operational amplifier U4, and the other end of the resistor R16 is connected to the output terminal of the fourth operational amplifier U4; another parallel common end of the second group of proportional input terminal resistors connected in parallel is connected to the inverting input terminal of the fifth operational amplifier U5, and the non-inverting input terminal of the fifth operational amplifier U5 is grounded. The first end of the resistor R17 is connected to the inverting input terminal of the fifth operational amplifier U5, and the other end of the resistor R17 is connected to the output terminal of the fifth operational amplifier U5; the first end of the resistor R18 is connected to the output terminal of the fourth operational amplifier U4, and the other end of the resistor R18 is connected to the inverting input terminal of the sixth operational amplifier U6; the first end of the resistor R19 is connected to the output terminal of the fifth operational amplifier U5, and the other end of the resistor R19 is connected to the positive input terminal of the sixth operational amplifier U6; the first end of the resistor R20 is connected to the inverting input terminal of the sixth operational amplifier U6, and the other end of the resistor R20 is connected to the output terminal of the sixth operational amplifier U6; the first end of the resistor R21 is connected to the positive input terminal of the sixth operational amplifier U6, and the other end of the resistor R21 is grounded.

[0015] Furthermore, the second proportional adjustment circuit includes: a seventh operational amplifier U7; the A terminal of the second digital potentiometer is connected to the output terminal of the sixth operational amplifier U6, the W terminal of the second digital potentiometer is connected to the inverting input terminal of the seventh operational amplifier U7, the B terminal of the second digital potentiometer is connected to the output terminal of the seventh operational amplifier U7, and the non-inverting input terminal of the seventh operational amplifier U7 is grounded.

[0016] Furthermore, the second unit inverting circuit includes: a resistor R24, a resistor R25, and an eighth operational amplifier U8; one end of the resistor R24 ​​is connected to the output end of the seventh operational amplifier U7, the other end of the resistor R24 ​​is connected to the inverting input end of the eighth operational amplifier U8, one end of the resistor R25 is connected to the inverting input end of the eighth operational amplifier U8, the other end of the resistor R25 is connected to the output end of the eighth operational amplifier U8, the non-inverting input end of the eighth operational amplifier U8 is grounded, and the output end of the eighth operational amplifier U8 serves as the ADC2 signal output end.

[0017] A control method for the above parallel current summing system, when set to stand-alone mode, the single current passes through a sampling resistor, and is converted into a single ADC1 signal through a first differential amplifier circuit (1), the ADC1 signal is directly connected to a current ADC sampling chip, the ammeter current is read, and the calibration coefficients k1 and b1 are calculated together with the ADC sampling code value and saved to a CPU; the ADC code value = actual current Ir1*k1+b1; during calibration, the first digital potentiometer code value of each single current sampling circuit is adjusted so that PARA+ and PARA- are equal to the target value; at this time, the PARA+ and PARA- of each single current sampling circuit are connected to the parallel current summing circuit. The circuit adjusts the second digital potentiometer of the parallel current summing circuit so that the voltage at point B of the parallel current summing circuit is equal to the PARA+ in the single-machine current sampling circuit; disconnects the ADC1 of the single-machine current sampling circuit from the ADC chip, connects the ADC2 of the parallel current summing circuit to the ADC chip, calculates the k2 and b2 coefficients at this time, and the ADC code value = actual current Ir2*k2+b2, and the calibration is completed; when set to parallel mode, after each single machine completes the calibration of the two sets of coefficients, n single machines are connected in parallel, and the parallel configuration information is sent down at this time, and the setting value of the second digital potentiometer is changed according to the number of parallel machines to achieve the function of parallel current summing.

[0018] Furthermore, the amplification factor of the first proportional adjustment circuit is:

[0019]

[0020] Among them, A V1 is the gain of the first proportional regulation circuit, R AW1 is the resistance between the A and W terminals of the first digital potentiometer, R BW1 is the resistance between the B terminal and the W terminal of the first digital potentiometer.

[0021] Furthermore, the amplification factor of the second proportional adjustment circuit is:

[0022]

[0023] Among them, AV2 is the gain of the second proportional regulation circuit, R AW2 is the resistance between the A and W terminals of the second digital potentiometer, R BW2 is the resistance between the B terminal and the W terminal of the second digital potentiometer.

[0024] The advantages of the present invention are:

[0025] The present invention combines analog and digital parallel operation, sends configuration parameters through a digital channel, and uses a digital potentiometer to calibrate and adjust the analog current signal sum, thereby achieving the advantages of simple hardware circuit and high current accuracy after calibration; using a digital potentiometer to replace a traditional resistance proportional circuit, in a single-machine configuration, after calculating the calibration coefficient according to the above calibration method, a current value with higher accuracy can be obtained by changing the parallel digital potentiometer when multiple power supplies or loads are connected in parallel; the present invention applies a digital potentiometer to a parallel circuit, and adjusts the amplification factor by assigning the resistance value of the potentiometer according to the set number of parallel units, replacing the traditional resistance proportional circuit that switches a single proportional resistor value to adjust the amplification factor, thereby achieving simple hardware circuit, and only needs to control the digital potentiometer to achieve precise control of the parallel sum and amplification factor, which has the advantages of high current accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic diagram of a single-machine current sampling circuit of a parallel current summing system according to an embodiment of the present invention;

[0027] Figure 2 is a schematic diagram of a parallel current summing circuit of a parallel current summing system according to an embodiment of the present invention;

[0028] Figure 3 1. It is a pin package diagram of a digital potentiometer used in a parallel current summing system according to an embodiment of the present invention;

[0029] Figure 4 1 is an internal circuit structure diagram of a digital potentiometer used in a parallel current summing system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described in combination with the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and specific embodiments:

[0032] Embodiment 1

[0033] The parallel current summing system of the embodiment of the present invention comprises: a plurality of single-machine current sampling circuits and a parallel current summing circuit.

[0034] like Figure 1 As shown, the stand-alone current sampling circuit includes: a first differential amplifier circuit, a first proportional adjustment circuit, a first unit inverter circuit, and a first digital potentiometer; the first differential amplifier circuit includes: a sampling resistor R3, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, and a first operational amplifier U1; the first proportional adjustment circuit includes: a resistor R10 and a second operational amplifier U2; the first unit inverter circuit includes: a resistor R14, a resistor R15, and a third operational amplifier U3.

[0035] One end of the resistor R5 is connected to the inverting input terminal of the first operational amplifier U1, one end of the resistor R6 is connected to the non-inverting input terminal of the first operational amplifier U1, and the other end of the resistor R5 and the other end of the resistor R6 are respectively connected to the two ends of the sampling resistor R3; one end of the resistor R7 is connected to the inverting input terminal of the first operational amplifier U1, and the other end of the resistor R7 is connected to the output terminal of the first operational amplifier U1; one end of the resistor R8 is connected to the non-inverting input terminal of the first operational amplifier U1, and the other end of the resistor R8 is grounded; one end of the resistor R9 is connected to the output terminal of the first operational amplifier U1, and the other end of the resistor R9 is connected to the B end of the first digital potentiometer, and the W end of the first digital potentiometer is connected to the inverting input terminal of the second operational amplifier U2. 2 is grounded, the A end of the first digital potentiometer is connected to one end of the resistor R10, the other end of the resistor R10 is connected to the output end of the second operational amplifier U2, one end of the resistor R14 is connected to the output end of the second operational amplifier U2, and the other end of the resistor R14 is connected to the inverting input end of the third operational amplifier U3; one end of the resistor R15 is connected to the inverting input end of the third operational amplifier U3, the other end of the resistor R15 is connected to the output end of the third operational amplifier U3, and the non-inverting input end of the third operational amplifier U3 is grounded; the output end signal of the first operational amplifier U1 is used as the stand-alone ADC1 signal, the output end signal of the second operational amplifier U2 is used as the PARA+ signal, and the output end signal of the third operational amplifier U3 is used as the PARA- signal.

[0036] like Figure 2As shown, taking the addition of two currents as an example, the composition of the parallel current addition circuit is described in detail. The parallel current addition circuit includes: an instrument amplifier circuit, a second proportional adjustment circuit, a second unit inverter circuit, and a second digital potentiometer; the instrument amplifier circuit includes: resistor R16, resistor R17, resistor R18, resistor R19, resistor R20, resistor R21, a fourth operational amplifier U4, a fifth operational amplifier U5, and a sixth operational amplifier U6; the second proportional adjustment circuit includes: a seventh operational amplifier U7; the second unit inverter circuit includes: resistor R24, resistor R25, and an eighth operational amplifier U8; when the two currents are added, the proportional input terminal resistors of the instrument amplifier circuit are two pairs of parallel resistors, a total of four resistors, such as Figure 2 As shown, they are resistor R26, resistor R27, resistor R28, and resistor R29 respectively.

[0037] The resistor R26 and the resistor R28 are connected in parallel to a common terminal connected to a PARA+ signal, and the other common terminal connected to the inverting input terminal of the fourth operational amplifier U4. The non-inverting input terminal of the fourth operational amplifier U4 is grounded. One end of the resistor R16 is connected to the inverting input terminal of the fourth operational amplifier U4, and the other end of the resistor R16 is connected to the output terminal of the fourth operational amplifier U4. The resistor R27 and the resistor R29 are connected in parallel to a common terminal connected to a PARA- signal, and the other common terminal connected to the inverting input terminal of the fifth operational amplifier U5. The non-inverting input terminal of the fifth operational amplifier U5 is grounded. One end of the resistor R17 is connected to the inverting input terminal of the fifth operational amplifier U5, and the other end of the resistor R17 is connected to the output terminal of the fifth operational amplifier U5. One end of the resistor R18 is connected to the output terminal of the fourth operational amplifier U4, and the other end of the resistor R18 is connected to the inverting input terminal of the sixth operational amplifier U6. One end of the resistor R19 is connected to the output terminal of the fifth operational amplifier U5, and the other end of the resistor R19 is connected to the output terminal of the sixth operational amplifier U6. The positive phase input terminal of the operational amplifier U6 is connected, one end of the resistor R20 is connected to the inverting input terminal of the sixth operational amplifier U6, the other end of the resistor R20 is connected to the output terminal of the sixth operational amplifier U6, one end of the resistor R21 is connected to the positive phase input terminal of the sixth operational amplifier U6, and the other end of the resistor R21 is grounded; the A end of the second digital potentiometer is connected to the output terminal of the sixth operational amplifier U6, the W end of the second digital potentiometer is connected to the inverting input terminal of the seventh operational amplifier U7, the B end of the second digital potentiometer is connected to the output terminal of the seventh operational amplifier U7, and the positive phase input terminal of the seventh operational amplifier U7 is grounded; one end of the resistor R24 ​​is connected to the output terminal of the seventh operational amplifier U7, the other end of the resistor R24 ​​is connected to the inverting input terminal of the eighth operational amplifier U8, one end of the resistor R25 is connected to the inverting input terminal of the eighth operational amplifier U8, the other end of the resistor R25 is connected to the output terminal of the eighth operational amplifier U8, the positive phase input terminal of the eighth operational amplifier U8 is grounded, and the output terminal of the eighth operational amplifier U8 serves as the ADC2 signal output terminal.

[0038] like Figure 3 and Figure 4 Shown are the pin package diagram and internal circuit structure diagram of the digital potentiometer, and the model of the digital potentiometer is AD5292.

[0039] Here’s how it works:

[0040] When the stand-alone mode is set, the stand-alone current passes through the sampling resistor R3 and is converted into a stand-alone ADC1 signal through the first differential amplifier circuit (1). The ADC1 signal is directly connected to the current ADC sampling chip to read the ammeter current, and the calibration coefficients k1 and b1 are calculated together with the ADC sampling code value and saved to the CPU; ADC code value = actual current Ir1*k1+b1;

[0041] The A, W, and B positions in the first proportional regulation circuit are connected to the first digital potentiometer, and the code value is sent through SPI. A 1024-bit digital potentiometer is used, R AB The resistance is 20k, then R AW1 With R BW1 The value of can be set by sending a code value of 0-1023. The amplification factor of the first proportional adjustment circuit is:

[0042]

[0043] Among them, A V1 is the gain of the first proportional regulation circuit, R AW1 is the resistance between the A and W terminals of the first digital potentiometer, R BW1 is the resistance between the B terminal and the W terminal of the first digital potentiometer.

[0044] During calibration, the first digital potentiometer code value of each stand-alone current sampling circuit is adjusted so that PARA+ and PARA- are equal to the target value;

[0045] At this time, connect PARA+ and PARA- of each single-machine current sampling circuit to the parallel current summing circuit, and adjust the second digital potentiometer of the parallel current summing circuit so that the voltage at point B of the parallel current summing circuit is equal to the PARA+ of the single-machine current sampling circuit; the amplification factor of the second proportional adjustment circuit of the parallel current summing circuit is:

[0046]

[0047] Among them, A V2 is the gain of the second proportional regulation circuit, R AW2 is the resistance between the A and W terminals of the second digital potentiometer, R BW2 is the resistance between the B terminal and the W terminal of the second digital potentiometer.

[0048] Disconnect the ADC1 of the stand-alone current sampling circuit from the ADC chip, connect the ADC2 of the parallel current summing circuit to the ADC chip, calculate the k2 and b2 coefficients at this time, ADC code value = actual current Ir2*k2+b2, and the calibration is complete; assuming that the stand-alone digital potentiometer is set to 512, then R AW =R BW =10K, at this time, the amplification factor of U2 inverting amplifier is -1, PARA+ is obtained, and then PARA- is obtained after inversion. Here, two currents are reloaded to obtain two sets of data, and the calibration value of the parallel machine is calculated according to the single machine calibration coefficient calculation method.

[0049] The calibration adopts the two-point calibration method, such as first pulling the DC current positive 30A, then reading the ammeter data and recording the corresponding ADC code value, then pulling the DC negative 30A, reading the ammeter data and recording the corresponding ADC code value, a total of two sets of data, calculating the coefficients k1 and b1, and obtaining the corresponding relationship between the ADC sampling code value and the actual current, ADC code value = actual current Ir*k1+b1; during calibration, adjust the digital potentiometer code value so that PARA+ and PARA- are equal to the target value. The target value is the theoretical calibration voltage. With a current of 30A, assuming that the internal proportional coefficient is 0.1 after passing through the sampling resistor, 3V needs to be output.

[0050] When set to parallel calibration mode, after each single machine completes the calibration of two sets of coefficients, n single machines are connected in parallel. At this time, the parallel configuration information is sent down, and the setting value of the second digital potentiometer is changed according to the number of parallel machines to achieve the effect of parallel current addition.

[0051] At this time, the fourth operational amplifier U4, the fifth operational amplifier U5, and the sixth operational amplifier U6 form a current summing circuit, and a second digital potentiometer is set. When the number of parallel machines is 1, the multiple of the digital potentiometer is set to 10 times. Similarly, when multiple machines are used in parallel, the number of parallel machines is 2, 3, 4..., and the multiple of the second proportional adjustment circuit is 5 times, 10 / 3 times, 2.5 times, 2 times..., and finally the parallel current sampling signal is obtained.

[0052] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A parallel current summing system, characterized in that: include: Multiple single-machine current sampling circuits and parallel current summing circuits; The single-machine current sampling circuit comprises: a first differential amplifier circuit, a first proportional adjustment circuit, a first unit inverter circuit, and a first digital potentiometer; the parallel current summing circuit comprises: an instrument amplifier circuit, a second proportional adjustment circuit, a second unit inverter circuit, a second digital potentiometer, and a plurality of proportional input resistors; the input end of the first differential amplifier circuit samples the single-machine current flowing through the sampling resistor, the output end of the first differential amplifier circuit is connected to the B end of the first digital potentiometer, the W end of the first digital potentiometer is connected to the inverting input end of the first proportional adjustment circuit, and the A end of the first digital potentiometer is connected to the output end of the first proportional adjustment circuit; the output end of the first proportional adjustment circuit is connected to the input end of the first unit inverter circuit, wherein the output end of the first proportional adjustment circuit outputs a PARA+ signal, and the output end of the first unit inverter circuit outputs a PARA- signal; the PARA+ signal ends of the plurality of single-machine current sampling circuits are all connected to the parallel current summing circuit The PARA+ signal terminal of the single-machine current sampling circuit is connected, and the PARA- signal terminals of the multiple single-machine current sampling circuits are all connected to the PARA- signal terminal of the parallel current summing circuit; the number of proportional input terminal resistors is twice that of the single-machine current sampling circuit, and the multiple proportional input terminal resistors are divided into two groups. The first group of proportional input terminal resistors are all connected in parallel, and a parallel common terminal after parallel connection serves as the PARA+ signal terminal of the parallel current summing circuit, and another parallel common terminal after parallel connection is connected to the first input terminal of the instrument amplifier circuit. The second group of proportional input terminal resistors are also all connected in parallel, and a parallel common terminal after parallel connection serves as the PARA- signal terminal of the parallel current summing circuit, and another parallel common terminal after parallel connection is connected to the second input terminal of the instrument amplifier circuit; the output terminal of the instrument amplifier circuit is connected to the A terminal of the second digital potentiometer, the W terminal of the second digital potentiometer is connected to the inverting input terminal of the second proportional adjustment circuit, and the B terminal of the second digital potentiometer is connected to the input terminal of the second unit inverting circuit; When the stand-alone mode is set, the stand-alone current passes through the sampling resistor and is converted into a stand-alone ADC1 signal through the first differential amplifier circuit (1). The ADC1 signal is directly connected to the current ADC sampling chip to read the ammeter current, and the calibration coefficients k1 and b1 are calculated together with the ADC code value and saved in the CPU; ADC code value = actual current Ir1*k1+b1; During calibration, adjust the code value of the first digital potentiometer of each stand-alone current sampling circuit so that PARA+ and PARA- are equal to the target value; at this time, connect PARA+ and PARA- of each stand-alone current sampling circuit to the parallel current summing circuit, and adjust the second digital potentiometer of the parallel current summing circuit so that the voltage at point B of the parallel current summing circuit is equal to the PARA+ of the stand-alone current sampling circuit; disconnect the connection between ADC1 of the stand-alone current sampling circuit and the ADC chip, connect ADC2 of the parallel current summing circuit to the ADC chip, calculate the k2 and b2 coefficients at this time, ADC code value = actual current Ir2*k2+b2, and the calibration is completed; When set to parallel mode, after each single machine completes the calibration of two sets of coefficients, n single machines are connected in parallel. At this time, the parallel configuration information is sent down, and the setting value of the second digital potentiometer is changed according to the number of parallel machines to achieve the effect of parallel current addition.

2. The parallel current summing system according to claim 1, characterized in that: The first differential amplifier circuit includes: a sampling resistor R3, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, and a first operational amplifier U1; one end of the resistor R5 is connected to the inverting input end of the first operational amplifier U1, one end of the resistor R6 is connected to the non-inverting input end of the first operational amplifier U1, and the other end of the resistor R5 and the other end of the resistor R6 are respectively connected to the two ends of the sampling resistor R3; one end of the resistor R7 is connected to the inverting input end of the first operational amplifier U1, and the other end of the resistor R7 is connected to the output end of the first operational amplifier U1; one end of the resistor R8 is connected to the non-inverting input end of the first operational amplifier U1, and the other end of the resistor R8 is grounded, one end of the resistor R9 is connected to the output end of the first operational amplifier U1, and the other end of the resistor R9 is connected to the B end of the first digital potentiometer; the output end signal of the first operational amplifier U1 is used as the single-machine ADC1 signal.

3. The parallel current summing system according to claim 2, characterized in that: The first proportional adjustment circuit includes: a resistor R10 and a second operational amplifier U2; the W end of the first digital potentiometer is connected to the inverting input end of the second operational amplifier U2, the non-inverting input end of the second operational amplifier U2 is grounded, the A end of the first digital potentiometer is connected to one end of the resistor R10, and the other end of the resistor R10 is connected to the output end of the second operational amplifier U2; the output end signal of the second operational amplifier U2 is used as the PARA+ signal.

4. The parallel current summing system according to claim 3, characterized in that: The first unit inverting circuit includes: a resistor R14, a resistor R15, and a third operational amplifier U3; one end of the resistor R14 is connected to the output end of the second operational amplifier U2, and the other end of the resistor R14 is connected to the inverting input end of the third operational amplifier U3; one end of the resistor R15 is connected to the inverting input end of the third operational amplifier U3, and the other end of the resistor R15 is connected to the output end of the third operational amplifier U3, and the non-inverting input end of the third operational amplifier U3 is grounded; the output end signal of the third operational amplifier U3 is used as the PARA- signal.

5. The parallel current summing system according to claim 4, characterized in that: The instrument amplifier circuit includes: resistor R16, resistor R17, resistor R18, resistor R19, resistor R20, resistor R21, a fourth operational amplifier U4, a fifth operational amplifier U5, and a sixth operational amplifier U6; another parallel common end of the first group of proportional input terminal resistors connected in parallel is connected to the inverting input end of the fourth operational amplifier U4, the non-inverting input end of the fourth operational amplifier U4 is grounded, one end of the resistor R16 is connected to the inverting input end of the fourth operational amplifier U4, and the other end of the resistor R16 is connected to the output end of the fourth operational amplifier U4; another parallel common end of the second group of proportional input terminal resistors connected in parallel is connected to the inverting input end of the fifth operational amplifier U5, and the non-inverting input end of the fifth operational amplifier U5 is connected to the ground. ground, one end of the resistor R17 is connected to the inverting input terminal of the fifth operational amplifier U5, and the other end of the resistor R17 is connected to the output terminal of the fifth operational amplifier U5; one end of the resistor R18 is connected to the output terminal of the fourth operational amplifier U4, and the other end of the resistor R18 is connected to the inverting input terminal of the sixth operational amplifier U6, one end of the resistor R19 is connected to the output terminal of the fifth operational amplifier U5, and the other end of the resistor R19 is connected to the non-inverting input terminal of the sixth operational amplifier U6, one end of the resistor R20 is connected to the inverting input terminal of the sixth operational amplifier U6, and the other end of the resistor R20 is connected to the output terminal of the sixth operational amplifier U6, one end of the resistor R21 is connected to the non-inverting input terminal of the sixth operational amplifier U6, and the other end of the resistor R21 is grounded.

6. The parallel current summing system according to claim 5, characterized in that: The second proportional adjustment circuit includes: a seventh operational amplifier U7; the A terminal of the second digital potentiometer is connected to the output terminal of the sixth operational amplifier U6, the W terminal of the second digital potentiometer is connected to the inverting input terminal of the seventh operational amplifier U7, the B terminal of the second digital potentiometer is connected to the output terminal of the seventh operational amplifier U7, and the non-inverting input terminal of the seventh operational amplifier U7 is grounded.

7. The parallel current summing system according to claim 6, characterized in that: The second unit inverting circuit includes: a resistor R24, a resistor R25, and an eighth operational amplifier U8; one end of the resistor R24 ​​is connected to the output end of the seventh operational amplifier U7, the other end of the resistor R24 ​​is connected to the inverting input end of the eighth operational amplifier U8, one end of the resistor R25 is connected to the inverting input end of the eighth operational amplifier U8, the other end of the resistor R25 is connected to the output end of the eighth operational amplifier U8, the non-inverting input end of the eighth operational amplifier U8 is grounded, and the output end of the eighth operational amplifier U8 serves as the ADC2 signal output end.

8. A control method applied to the parallel current addition system according to any one of claims 1 to 7, characterized in that: When the single-machine mode is set, the single-machine current passes through the sampling resistor and is converted into a single-machine ADC1 signal through the first differential amplifier circuit (1). The ADC1 signal is directly connected to the current ADC sampling chip to read the ammeter current. The calibration coefficients k1 and b1 are calculated together with the ADC sampling code value and saved to the CPU; the ADC code value = the actual current Ir1*k1+b1; during calibration, the first digital potentiometer code value of each single-machine current sampling circuit is adjusted so that PARA+ and PARA- are equal to the target value; at this time, the PARA+ and PARA- of each single-machine current sampling circuit are connected to the parallel current adding circuit to adjust the parallel current adding circuit. The second digital potentiometer of the summing circuit makes the voltage at point B of the parallel current summing circuit equal to PARA+ in the single-machine current sampling circuit; disconnect ADC1 of the single-machine current sampling circuit from the ADC chip, connect ADC2 of the parallel current summing circuit to the ADC chip, calculate the k2 and b2 coefficients at this time, ADC code value = actual current Ir2*k2+b2, and the calibration is completed; when set to parallel mode, after each single machine completes the calibration of two sets of coefficients, n single machines are connected in parallel, and the parallel configuration information is sent down at this time, and the setting value of the second digital potentiometer is changed according to the number of parallel machines to achieve the function of parallel current summing.

9. The control method of the parallel current addition system according to claim 8, characterized in that: The amplification factor of the first proportional regulation circuit is: Among them, A V1 is the gain of the first proportional regulation circuit, R AW1 is the resistance between the A and W terminals of the first digital potentiometer, R BW1 is the resistance between the B terminal and the W terminal of the first digital potentiometer.

10. The control method of the parallel current addition system according to claim 8, characterized in that: The amplification factor of the second proportional adjustment circuit is: Among them, A V2 is the gain of the second proportional regulation circuit, R AW2 is the resistance between the A and W terminals of the second digital potentiometer, R BW2 is the resistance between the B terminal and the W terminal of the second digital potentiometer.

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