A multiplier based on base-4 booth encoding and an improved wallace compression tree
By using Radix-4 Booth encoding and an improved Wallace tree compression structure for the multiplier, the problems of high power consumption and long latency of existing multipliers are solved, resulting in reduced circuit area and increased operation speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-01
- Publication Date
- 2026-03-17
AI Technical Summary
Existing multipliers suffer from high power consumption and long latency, especially in Booth and Wallace tree structures where the number of adders is large, the structure is complex, and resource consumption and latency are significant.
The multiplier is re-encoded using Radix-4 Booth encoding to generate a compact partial product array. An improved Wallace tree compression structure is used for fast compression via 3-2 and 4-2 compressors. Finally, a high-speed adder is used for summation.
It reduces circuit area, improves compression efficiency, reduces critical path delay, and increases multiplication speed.
Smart Images
Figure CN119512501B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic devices, and more particularly to a multiplier based on radix-4 Booth encoding and an improved Wallace compressed tree. Background Technology
[0002] Multipliers are widely used in digital systems, but they typically suffer from high power consumption and long latency. Current high-efficiency and low-power multiplier algorithms and architectures mainly fall into two categories: Booth and Wallace tree structures. The Booth algorithm generates addition and subtraction operations by encoding consecutive bits of the multiplier, thus reducing the number of partial products and improving multiplication speed. Common examples include the Radix-4 and Radix-8 based Booth algorithms, suitable for processing numbers with many consecutive identical bits. The Wallace tree structure employs parallel processing and multi-level compression to improve multiplication speed. It generates a partial product matrix, then uses a multi-level tree-structured adder to compress the partial products, and finally uses a high-speed multiplier to sum the results. However, existing multipliers have a large number of adders, complex structures, and still suffer from significant resource consumption and latency issues during partial product generation and compression. Summary of the Invention
[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a multiplier based on radix-4 Booth encoding and improved Wallace compressed tree, thus solving the deficiencies of the prior art.
[0004] The objective of this invention is achieved through the following technical solution: a multiplier based on radix-4 Booth encoding and an improved Wallace compressed tree, the multiplier comprising a partial product generation module, a partial product compression module, and a final summation module;
[0005] The partial product generation module: re-encodes the input multiplier into multiple partial products using the Radix-4 Booth algorithm, forming a compact partial product array;
[0006] The partial product compression module utilizes an improved Wallace tree compression structure to rapidly compress partial products using two compressors, reducing computation path latency.
[0007] The final summation module uses a high-speed adder to sum the compressed partial products to obtain the final multiplication result.
[0008] The Radix-4 Booth algorithm re-encodes the multipliers and generates corresponding control signals. Based on the number of multipliers, groups are formed by combining every three multipliers, with each group overlapping by one bit. Each group follows the formula B = B0. n-1 ×(-2) n-1 +Bn-2 ×2 n-2 +…+B1×2 1 +B0×2 0 +B -1 The encoding is done in the manner described above, where B represents the multiplier.
[0009] The two compressors include a carry-hold adder and a one-bit full adder with carry, and both compressors have delays of two XOR gates on the critical path.
[0010] The improved Wallace tree compression structure consists of two carry-retaining adders and two one-bit full adders with carry. The partial product generation module generates eight partial products from P0 to P8. The partial products of P0 and P1 are added by 1 and then input to the first carry-retaining adder. The partial product of P1 is directly input to the first carry-retaining adder. The partial products of P3 to P5 are input to the second carry-retaining adder. Both carry-retaining adders are input to the first one-bit full adder with carry. The first one-bit full adder with carry and the partial products of P6 and P7 are input to the second one-bit full adder with carry.
[0011] This invention has the following advantages: a multiplier based on radix-4 Booth encoding and an improved Wallace compressed tree. The radix-4 Booth encoding algorithm makes the partial product array more regular, reducing the circuit area. The Wallace tree is implemented using a new tree-type compression structure that combines 3-2 and 4-2 compressors, which improves compression efficiency and reduces critical latency. Attached Figure Description
[0012] Figure 1 This is a schematic diagram of the structure of the present invention;
[0013] Figure 2 This is a schematic diagram of the partial product summation structure;
[0014] Figure 3 The optimized XOR gate logic circuit diagram;
[0015] Figure 4 The optimized logic circuit diagram of the 3-2 compressor;
[0016] Figure 5 A schematic diagram of the improved Wallace tree compression structure;
[0017] Figure 6 This is a schematic diagram of the compression process of an additive tree. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of this application provided below with reference to the accompanying drawings is not intended to limit the scope of protection of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. The present invention will be further described below with reference to the accompanying drawings.
[0019] like Figure 1 As shown, this invention specifically relates to a multiplier based on radix-4 Booth encoding and an improved Wallace compressed tree, used for multiplication of two 16-bit signed numbers. It includes partial product generation, partial product compression, and the final fast summation of the two sets of partial products. To obtain a well-compressed partial product array with a tree structure, the partial product generation module employs radix-4 Booth encoding, generating a compact and regularly arranged array of eight partial products from two 16-bit binary numbers. The partial product compression module uses an improved Wallace tree structure to quickly compress the partial product array. This structure rearranges optimized 3-2 and 4-2 compressors according to the number of partial products, resulting in a compressed structure with low critical path latency and low resource consumption.
[0020] This invention employs radix-4 Booth multiplication, followed by one-hot encoding using Booth encoding, and performs a partial product selection of one out of four. Compared to traditional multiplication operations (or radix-2 Booth), radix-4 Booth multiplication requires only n / 2-1 additions, where n is the bit width, significantly increasing the speed.
[0021] The radix-4 Booth encoding algorithm uses the formula
[0022] B = B n-1 ×(-2) n-1 +B n-2 ×2 n-2 +…+B1×2 1 +B0×2 0 +B -1 The multiplier is re-encoded, and corresponding control signals are generated, as shown in Table 1. For a 16-bit multiplier, a 0 is padded to the least significant bit to make it a 17-bit multiplier. The multipliers are grouped into 8 groups of three bits each, with each group overlapping by one bit. Each group is re-encoded according to Table 1, where B represents the multiplier and A represents the multiplicand.i-1 B i B i+1 Since all of them are single digits, there are only 8 possible partial products.
[0023] Table 1. Booth Encoding Table
[0024] <![CDATA[B i+1 ]]> <![CDATA[B i ]]> <![CDATA[B i-1 ]]> <![CDATA[-2B i-1 +B i +B i-1 ]]> PP 0 0 0 +0 0 0 0 1 +1 +A 0 1 0 +1 +A 0 1 1 +2 +2A 1 0 0 -2 -2A 1 0 1 -1 -A 1 1 0 -1 -A 1 1 1 -0 0
[0025] Therefore, for multiplication of any number of bits, at most w+1+3 = w+4 bits are needed to determine each partial product (the remaining bits are all 0), where w represents the bit width of the multiplier (multiplicand), i.e., the number of bits in the operand. For example... Figure 2 As shown, h is the mantissa, and s represents the sign bit of the final partial product, which is obtained by the XOR operation of the original sign bit of the multiplicand and the XOR operation of the multiplicand + / - (1 for +, 0 for -).
[0026] A 3-2 compressor is a carry-retaining adder, and a 4-2 compressor is a one-bit full adder with carry. Its critical path has two XOR gates with delays, and its logical expression is: and Sum represents summation, C out Indicates carry-out, C in Indicates a borrow input, such as Figure 3 and Figure 4 As shown, parts and items can be output to the next level.
[0027] like Figure 5 As shown, P0 to P7 are eight partial products generated by the partial product generation module. This structure, through the combination of full adders and half adders and parallel operation, compresses the eight partial products using only two CSAs (circuit-optimized 3-2 compressors) and two 4-2 compressors, shortening the path length of the addition operation. Furthermore, it has corresponding scalability, allowing for convenient application to higher bit-width calculations.
[0028] The additive tree compression process based on the above improved compression structure is as follows: Figure 6 As shown, the whole is divided into 5 parts: add1_7, 32A, 32B, 42A, and 42B. The blank circle represents the data 0, h represents the add signal added after the partial product in pp_generate, the solid circle, C, and S represent data that is present or generated, HA indicates that a half adder is used, FA indicates that a full adder is used, and the black box marked with a 42 compressor indicates that a 4-2 compressor is used for addition.
[0029] In the add1_7 section, pp0 and pp1 are 21-bit input signals. The increment signal of the eighth partial product is placed at the 15th bit. Six half-adders are used at HA to generate S1-S6 and C1-C6. The weight of signal C is 2, so it needs to be shifted left by one bit. Therefore, the 15th bit pp0_1 will be empty. The increment signal h is filled in, and the new 21-bit pp0_1 and pp1_1 are output.
[0030] During the 32A compression process, the `add1_7` method is used in bits 3 and 4 to fill in the increment signal using two half adders. Bits 5 to 21 use 17 full adders to achieve a 3-to-2 reduction, while the full adders generate C and S signals. In the 32B module compression process, the lower bits contain only two signals, which are directly output. Bits 9 and 10 use two half adders, bits 11 to 25 use 15 full adders, and bits 26 and 27 use half adders. The aforementioned carry-left shift and then filling in the blank spaces achieves the 32B 3-to-2 reduction operation.
[0031] In the 42A module, the data in bits 5 and 6 are carried left-shifted. Cout is used as the carry of the full adder in bit 24 to achieve 4-2 compression. The carry left shift is used, and the blank is filled with the carry of the half adder. This method achieves 4-2 compression. The 4-2 compressor in bit 29 will generate three signals Cout, C, and S. C is shifted left by one bit, and S is retained in its original position. Cout is used as the carry of the full adder in bit 30 to achieve 4-2 compression. Bit 31 uses a half adder to achieve 3-2 compression.
[0032] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and improvements, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.
Claims
1. A multiplier based on base-4 Booth encoding and an improved Wallace compression tree, characterized by: The multiplier comprises a partial product generation module, a partial product compression module and a final summation module; The partial product generation module re-encodes the input multiplier into a plurality of partial products by using a Radix-4 Booth algorithm to form a compact partial product array; The partial product compression module uses an improved Wallace tree compression structure to quickly compress the partial products by two compressors to reduce the calculation path delay; The final summation module uses a high-speed adder to sum the compressed partial products to obtain the final multiplication result; The two compressors comprise a carry-save adder and a one-bit full adder with carry, and there are 2 delays of XOR gates on the critical path of the two compressors; The improved Wallace tree compression structure is composed of two carry-save adders and two one-bit full adders with carry; the partial product generation module generates 8 partial products P0-P7, P0 and P1 partial products are input to the first carry-save adder after being added by 1, P2 partial product is directly input to the first carry-save adder, P3-P5 partial products are input to the second carry-save adder, the two carry-save adders are input to the first one-bit full adder with carry, and the first one-bit full adder with carry and P6 and P7 partial products are input to the second one-bit full adder with carry.
2. The multiplier based on base-4 booth encoding and modified Wallace compression tree as claimed in claim 1, wherein: The Radix-4 Booth algorithm re-encodes the multiplier and generates corresponding control signals, and according to the number of the multiplier, each three-bit multiplier is taken as a group, each two groups overlap one bit, and each group is encoded in the manner of , wherein B represents the multiplier.