Booth multipliers, arithmetic circuits, processors and computing devices

Abstract

The present disclosure relates to Booth multipliers, arithmetic circuits, processors, and computing devices. A Booth multiplier includes one or more partial product generation circuits, each partial product generation circuit including: a negation circuit configured to selectively negate a second number based on a highest bit of three adjacent bits of a first number; an encoding circuit configured to generate a selection signal for selecting an operation to perform on an output of the negation circuit based on the three adjacent bits of the first number; a selection circuit configured to apply the selection signal received from the encoding circuit to the output of the negation circuit received from the negation circuit to generate a partial product; a carry compensation circuit configured to generate a carry compensation corresponding to a sign of the Booth encoding of the three adjacent bits. The Booth multiplier further includes a partial product summation circuit configured to sum outputs of the selection circuits and the carry compensation circuits of the one or more partial product generation circuits to generate a product of the first number and the second number.

Description

Technical Field

[0001] This disclosure relates to the field of data processing technology, and more specifically, to a Booth multiplier, arithmetic circuit, processor, and computing device. Background Technology

[0002] Multipliers are used to calculate logarithmic products and are crucial components for operations such as vector multiplication, matrix multiplication, and vector-matrix multiplication. They are widely used in processors such as coprocessors, digital signal processors, central processing units (CPUs), dedicated instruction processors (DIPMs), and neural network processors. In particular, the rapid development of artificial intelligence has highlighted the important role of neural network processors, making them a cornerstone of intelligent computing technology. The convolutional computation unit (CMU) is the core unit of a neural network processor, requiring multipliers to perform multiplication and accumulation operations on activation data and weight data. Since the CMU is also the power consumption center of a neural network processor, the design of low-power multipliers is crucial and key to the large-scale application of neural network processors containing them.

[0003] Multiplication generally involves partial product generation and partial product summation. In partial product summation, partial product compression can be performed before adding the final results. In partial product generation, Booth encoding can be used to reduce the number of partial products. For example, radix-4 Booth encoding can reduce the number of partial products by half. Therefore, multipliers using Booth encoding (called Booth multipliers) can have improved performance compared to multipliers without Booth encoding. Summary of the Invention

[0004] According to a first aspect of this disclosure, a Booth multiplier is provided for calculating the product of a first number and a second number. The Booth multiplier includes one or more partial product generation circuits, each configured to receive three adjacent bits of the first number and the second number, and includes: an inversion circuit configured to selectively invert the second number based on the most significant bit of the three adjacent bits of the first number; an encoding circuit configured to generate a selection signal based on the three adjacent bits of the first number for selecting an operation to be performed on the output of the inversion circuit; a selection circuit configured to apply the selection signal received from the encoding circuit to the output of the inversion circuit received from the inversion circuit to generate a partial product; and a carry compensation circuit configured to generate carry compensation corresponding to the sign of the Booth-encoded three adjacent bits of the first number. The Booth multiplier further includes a partial product summing circuit configured to sum the outputs of the selection circuit and the carry compensation circuit of the one or more partial product generation circuits to generate the product of the first number and the second number.

[0005] In some embodiments, the selection signal includes a first selection signal for selecting a single version of the output of the inverting circuit and a second selection signal for selecting a double version of the output of the inverting circuit, and the encoding circuit includes a first encoding circuit configured to generate the first selection signal and the second selection signal based on the three adjacent bits of the first number.

[0006] In some embodiments, the first Booth encoding when all three adjacent bits are 0 has the same symbol as the second Booth encoding when all three adjacent bits are 1.

[0007] In some embodiments, the selection circuit is configured to: perform a first AND operation on the first selection signal and a version of the output of the inverting circuit; perform a second AND operation on the second selection signal and a version of the output of the inverting circuit; perform a first OR operation on the result of the first AND operation and the result of the second AND operation; and perform a first NOT operation on the result of the first OR operation to generate the partial product.

[0008] In some embodiments, the carry compensation circuit is configured to: perform a second OR operation on the middle bit and the least significant bit among the three adjacent bits; perform a third AND operation on the result of the second OR operation and the inverted version of the most significant bit among the three adjacent bits; and perform a second NOT operation on the result of the third AND operation to generate the carry compensation.

[0009] In some embodiments, the inverting circuit is configured to perform an XOR operation on the inverted version of the highest bit among the three adjacent bits of the first number and the second number to generate the output of the inverting circuit.

[0010] In some embodiments, the inverting circuit is configured to perform an XOR operation on the highest bit of the three adjacent bits of the first number and the second number to generate the output of the inverting circuit.

[0011] In some embodiments, the inverting circuit is configured to: perform a fourth AND operation on the highest bit of the three adjacent bits of the first number and the inverted version of the second number; perform a fifth AND operation on the inverted version of the three adjacent bits of the first number and the second number; perform a third OR operation on the result of the fourth AND operation and the result of the fifth AND operation; and perform a third NOT operation on the result of the third OR operation to generate the output of the inverting circuit.

[0012] In some embodiments, the inverting circuit is configured to: perform a sixth AND operation on the inverted version of the highest bit among the three adjacent bits of the first number and the inverted version of the second number; perform a seventh AND operation on the highest bit among the three adjacent bits of the first number and the second number; and perform a fourth OR operation on the result of the sixth AND operation and the result of the seventh AND operation to generate the output of the inverting circuit.

[0013] In some embodiments, the selection circuit is configured to: perform a first AND operation on the first selection signal and a version of the output of the inverting circuit; perform a second AND operation on the second selection signal and a version of the output of the inverting circuit; and perform a first OR operation on the result of the first AND operation and the result of the second AND operation to generate the partial product.

[0014] In some embodiments, the carry compensation circuit is configured to: perform a third AND operation on the middle bit and the least significant bit among the three adjacent bits; perform a second OR operation on the result of the third AND operation and the inverted version of the most significant bit among the three adjacent bits; and perform a first NOT operation on the result of the second OR operation to generate the carry compensation.

[0015] In some embodiments, the inverting circuit is configured to perform an XOR operation on the highest bit of the three adjacent bits of the first number and the second number to generate the output of the inverting circuit.

[0016] In some embodiments, the inverting circuit is configured to perform an XOR operation on the inverted version of the highest bit among the three adjacent bits of the first number and the second number to generate the output of the inverting circuit.

[0017] In some embodiments, the inverting circuit is configured to: perform a fourth AND operation on the inverted version of the highest bit among the three adjacent bits of the first number and the inverted version of the second number; perform a fifth AND operation on the highest bit among the three adjacent bits of the first number and the second number; perform a third OR operation on the result of the fourth AND operation and the result of the fifth AND operation; and perform a second NOT operation on the result of the third OR operation to generate the output of the inverting circuit.

[0018] In some embodiments, the inverting circuit is configured to: perform a sixth AND operation on the highest bit of the three adjacent bits of the first number and the inverted version of the second number; perform a seventh AND operation on the inverted version of the three adjacent bits of the first number and the second number; and perform a fourth OR operation on the result of the sixth AND operation and the result of the seventh AND operation to generate the output of the inverting circuit.

[0019] In some embodiments, the first Booth encoding when all three adjacent bits are 0 has the opposite sign to the second Booth encoding when all three adjacent bits are 1.

[0020] In some embodiments, the selection signal further includes a third selection signal for selecting symbols of the first Booth encoding and the second Booth encoding, and the encoding circuit further includes a second encoding circuit configured to generate the third selection signal based on the three adjacent bits of the first number.

[0021] In some embodiments, the selection circuit is configured to: perform a first AND operation on the first selection signal and a version of the output of the inverting circuit; perform a second AND operation on the second selection signal and a version of the output of the inverting circuit; perform a first OR operation on the result of the first AND operation, the result of the second AND operation, and the third selection signal; and perform a first NOT operation on the result of the first OR operation to generate the partial product.

[0022] In some embodiments, the inverting circuit is configured to perform an XOR operation on the highest bit of the three adjacent bits of the first number and the second number to generate the output of the inverting circuit.

[0023] In some embodiments, the inverting circuit is configured to: perform a third AND operation on the highest bit of the three adjacent bits of the first number and the inverted version of the second number; perform a fourth AND operation on the inverted version of the three adjacent bits of the first number and the second number; perform a second OR operation on the result of the third AND operation and the result of the fourth AND operation; and perform a second NOT operation on the result of the second OR operation to generate the output of the inverting circuit.

[0024] In some embodiments, the second encoding circuit is configured to perform a first NOR operation on the three adjacent bits of the first number to generate the third selection signal, and the carry compensation circuit is configured to receive and output the highest bit among the three adjacent bits as the carry compensation.

[0025] In some embodiments, the second encoding circuit is configured to perform a fifth AND operation on the three adjacent bits of the first number to generate the third selection signal; and the carry compensation circuit is configured to: perform a third OR operation on the middle and least significant bits of the three adjacent bits, perform a sixth AND operation on the result of the third OR operation and the inverted version of the most significant bit of the three adjacent bits, perform a seventh AND operation on the three adjacent bits of the first number, and perform a second NOR operation on the result of the sixth AND operation and the result of the seventh AND operation to generate the carry compensation.

[0026] In some embodiments, the selection circuit is configured to: perform a first AND operation on the first selection signal and a version of the output of the inverting circuit; perform a second AND operation on the second selection signal and a version of the output of the inverting circuit; and perform a first OR operation on the result of the first AND operation, the result of the second AND operation, and the third selection signal to generate the partial product.

[0027] In some embodiments, the inverting circuit is configured to perform an XOR operation on the highest bit of the three adjacent bits of the first number and the second number to generate the output of the inverting circuit.

[0028] In some embodiments, the inverting circuit is configured to: perform a third AND operation on the highest bit of the three adjacent bits of the first number and the inverted version of the second number; perform a fourth AND operation on the inverted version of the three adjacent bits of the first number and the second number; and perform a second OR operation on the result of the third AND operation and the result of the fourth AND operation to generate the output of the inverting circuit.

[0029] In some embodiments, the second encoding circuit is configured to perform a fifth AND operation on the three adjacent bits of the first number to generate the third selection signal, and the carry compensation circuit is configured to receive and output the highest bit among the three adjacent bits as the carry compensation.

[0030] In some embodiments, the second encoding circuit is configured to perform a first NOR operation on the three adjacent bits of the first number to generate the third selection signal; and the carry compensation circuit is configured to: perform a third OR operation on the middle and least significant bits of the three adjacent bits, perform a sixth AND operation on the result of the third OR operation and the inverted version of the most significant bit of the three adjacent bits, perform a seventh AND operation on the three adjacent bits of the first number, and perform a second NOR operation on the result of the sixth AND operation and the result of the seventh AND operation to generate the carry compensation.

[0031] In some embodiments, the first encoding circuit is configured to: perform an XOR operation on the highest bit and the middle bit of the three adjacent bits of the first number; perform an XNOR operation on the lowest bit and the middle bit of the three adjacent bits of the first number; perform an AND operation on the result of the XOR operation and the result of the XNOR operation to generate the second selection signal; and perform a NOT operation on the result of the XNOR operation to generate the first selection signal.

[0032] According to a second aspect of this disclosure, an arithmetic circuit is provided, which includes the Booth multiplier according to any embodiment of the first aspect of this disclosure.

[0033] According to a third aspect of this disclosure, a processor is provided that includes a Booth multiplier according to any embodiment of the first aspect of this disclosure or an arithmetic circuit according to any embodiment of the second aspect of this disclosure.

[0034] According to a fourth aspect of this disclosure, a computing device is provided, which includes a processor according to any embodiment of a third aspect of this disclosure.

[0035] Other features and advantages of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0036] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0037] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein: Figure 1This is a schematic block diagram illustrating a Booth multiplier according to some embodiments of the present disclosure; Figures 2 to 17 These are examples illustrating some embodiments of the present disclosure for implementation. Figure 1 A schematic circuit diagram of the partial product generation circuit of the Booth multiplier; Figure 18 A schematic block diagram of an operational circuit according to some embodiments of the present disclosure is shown.

[0038] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0039] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0040] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0041] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this disclosure or its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in this disclosure. However, those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement this disclosure, and not exhaustive ways. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components.

[0042] In addition, techniques, methods and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods and equipment should be considered part of the specification.

[0043] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0044] In this article, for ease of description, the symbol "~" is used to represent negation or NOT operation, "&" is used to represent AND operation, "|" is used to represent OR operation, "⊕" is used to represent XOR operation, and "⊙" is used to represent XNOR operation.

[0045] In this article, for reference only, each diagram is numbered to distinguish similar logical operations within that diagram; this is not intended to be restrictive. For example, as... Figure 2 The example shown involves four AND operations, referred to as AND1, AND2, AND3, and AND4 respectively, and two OR operations, referred to as OR1 and OR2 respectively, and so on.

[0046] In this paper, when operations involve single-bit and multi-bit inputs, the operations are performed bitwise. For example, when performing a bitwise AND operation between a 1-bit number and a 32-bit number, the bitwise AND operation is performed on each bit of the 32-bit number based on the 1-bit number.

[0047] Furthermore, in this document, the desired logical operation or its equivalent logical operation can be implemented using any suitable logic circuit elements or combinations thereof. Multiple logical operations described may be combined into a single logical operation, or a single logical operation may be distributed among additional logical operations.

[0048] For example, the XOR operation can be implemented using XOR gates. Since the XOR operation X=A⊕B is equivalent to the logical operation X=(A&~B)|(~A&B), the XOR operation can also be implemented using an AO22 gate (which implements the logical operation "(A1&A2)|(B1&B2)", where A1, A2, B1, and B2 are the four inputs of the AO22 gate), or it can be implemented using a combination of two AND gates and one OR gate. Furthermore, since the XOR operation X=A⊕B is equivalent to the logical operation X=~(A⊙B), the XOR operation can also be implemented using an XNOR gate or its equivalent, a combination of a NOT gate.

[0049] For example, the XNOR operation can be implemented using an XNOR gate. Since the XNOR operation X=A⊙B is equivalent to the logical operation X=~[(A&~B)|(~A&B)], the XNOR operation can also be implemented using an AOI22 gate (which implements the logical operation "~[(A1&A2)|(B1&B2)]", where A1, A2, B1, and B2 are the four inputs of the AOI22 gate), or it can be implemented using a combination of two AND gates, one OR gate, and one NOT gate. Furthermore, since the XNOR operation X=A⊙B is equivalent to the logical operation X=~(A⊕B), the XNOR operation can also be implemented using an XOR gate or its equivalent form, a combination of a NOT gate.

[0050] For example, the AND operation can be implemented using an AND gate. Similarly, it can be implemented using other logic gates or combinations thereof, based on logical operations equivalent to the AND operation. For example, it can also be implemented using a combination of NAND gates and NOT gates.

[0051] For example, the OR operation can be implemented using an OR gate. Similarly, it can be implemented using other logic gates or combinations thereof, based on logical operations equivalent to the OR operation. For example, it can also be implemented using a combination of NOR gates and NOT gates.

[0052] For example, the NOT operation can be implemented using a NOT gate (which can be implemented as an inverter, for example). Similarly, it can be implemented using other logic gates or combinations thereof, based on logical operations equivalent to the NOT operation. For example, it can be implemented by shorting the inputs of a NAND gate together, or by shorting the inputs of a NOR gate together.

[0053] For example, the NOR operation can be implemented using a NOR gate. Similarly, it can be implemented using other logic gates or combinations thereof, based on logical operations equivalent to the NOR operation. For example, it can also be implemented using a combination of OR gates and NOT gates.

[0054] For example, the NAND operation can be implemented using NAND gates. Similarly, it can be implemented using other logic gates or combinations thereof, based on logical operations equivalent to NAND. For example, it can also be implemented using combinations of AND and NOT gates.

[0055] In Booth multipliers, the partial product generation circuit employs Booth encoding, which reduces the number of partial products generated, thereby simplifying the partial product summation circuit and optimizing its area and power consumption. However, the partial product generation circuit uses multi-stage logic operation modules to implement Booth encoding, which may result in numerous delay stages and high area and power consumption. Therefore, an improved Booth multiplier is desired.

[0056] Figure 1 A Booth multiplier 100 according to some embodiments of the present disclosure is illustrated. The Booth multiplier 100 can be used to compute the product of a first number a and a second number b. For example, the first number a and the second number b can be binary numbers. The Booth multiplier 100 may include a partial product generation circuit 110 and a partial product summing circuit 120. The partial product generation circuit 110 can be configured to receive the first number a and the second number b to generate a partial product, and the partial product summing circuit 120 can be configured to receive the partial product generated by the partial product generation circuit 110 and sum them to generate the product of the first number a and the second number b.

[0057] The partial product generation circuit 110 can use Booth encoding, such as radix-4 Booth encoding. For ease of illustration, Figure 1A partial product generation circuit 110 is depicted, but this is by no means intended to be limiting. Booth multiplier 100 may include one or more partial product generation circuits 110, each configured to receive a first number a with three adjacent bits and a second number b. Here, the first number a may be the multiplier, and the second number b may be the multiplicand. For example, in the case where Booth multiplier 100 includes a single partial product generation circuit 110, this circuit may receive a set of three adjacent bits in each cycle, thus requiring multiple cycles to generate multiple partial products. The generated partial products may be stored in a register. For example, in the case where Booth multiplier 100 includes multiple partial product generation circuits 110, these circuits may operate in parallel, each receiving a corresponding set of three adjacent bits, thus generating multiple partial products within one cycle.

[0058] Taking the case where both the first number a and the second number b have 32 bits (specifically represented as a[31:0], b[31:0], where [31:0] indicates all 32 bits and [i] indicates the i-th bit) as an example, in order to perform Booth encoding, the first number a, which is used as the multiplier, can be padded with a least significant bit 0. The partial product generation circuit 110 will generate a total of 16 partial products. For example, 16 partial product generation circuits 110 can be set up, where the first partial product generation circuit 110 receives bits 0, a[0], a[1], the second partial product generation circuit 110 receives a[1], a[2], a[3], the third partial product generation circuit 110 receives a[3], a[4], a[5], the fourth partial product generation circuit 110 receives a[5], a[6], a[7], and so on, with the 16th partial product generation circuit 110 receiving a

[29] , a

[30] , a

[31] . These 16 partial product generation circuits 110 can operate in parallel, so that 16 partial products can be generated in one cycle. For example, if n partial product generation circuits 110 are set up (n is a positive integer not exceeding 16), then 16 / n cycles are needed to generate all 16 partial products, where each cycle feeds the corresponding n groups of three adjacent bits into these n partial product generation circuits 110 respectively. For ease of description, this paper represents a set of three adjacent bits of the first number a as a[i+1], a[i], a[i-1] (where i=0,2,4,6,…), where a[-1] can represent 0 padded in the lowest bit.

[0059] like Figure 1As shown, the partial product generation circuit 110 includes an inverting circuit 112, an encoding circuit 114, a selection circuit 116, and a carry compensation circuit 118. The outputs of the inverting circuit 112 and the encoding circuit 114 are respectively coupled to the inputs of the selection circuit 116. The outputs of the selection circuit 116 and the carry compensation circuit 118 are respectively coupled to the inputs of the partial product summing circuit 120.

[0060] The inverting circuit 112 is configured to selectively invert the second number b based on the highest bit a[i+1] of the three adjacent bits a[i+1], a[i], and a[i-1] of the first number a.

[0061] In some embodiments, the inverting circuit 112 is configured to invert the second number b when the highest bit a[i+1] is 1. In some embodiments, the inverting circuit 112 is configured to invert the second number b when the highest bit a[i+1] is 0.

[0062] The encoding circuit 114 is configured to generate a selection signal based on three adjacent bits a[i+1], a[i], a[i-1] of the first number a for selecting the operation to be performed on the output of the inverting circuit 112 (denoted as B in this document, which may be b or its inverted version ~b).

[0063] In some embodiments, the selection signal generated by the selection circuit 116 includes a first selection signal (denoted as m1 herein) for selecting a one-fold version of the output B of the inverting circuit 112 and a second selection signal (denoted as m2 herein) for selecting a two-fold version of the output B of the inverting circuit 112. For example, the encoding circuit 114 may include a first encoding circuit configured to generate the first selection signal m1 and the second selection signal m2 based on three adjacent bits a[i+1], a[i], a[i-1] of the first number a. In some embodiments, the selection signal generated by the selection circuit 116 includes a third selection signal (denoted as m0 herein) for selecting the sign of the Booth code where a[i+1], a[i], a[i-1] are all 0 (i.e., 000) and the Booth code where a[i+1], a[i], a[i-1] are all 1 (i.e., 111). For example, the encoding circuit 114 may include a second encoding circuit configured to generate a third selection signal m0 based on three adjacent bits a[i+1], a[i], a[i-1] of the first number a.

[0064] The selection circuit 116 is configured to apply the selection signal received from the encoding circuit 114 to the output B of the inverting circuit 112 received from the inverting circuit 112 to generate a partial product (denoted as md herein).

[0065] In some embodiments, for example, when the selection signal includes a first selection signal m1 and a second selection signal m2 but not a third selection signal m0, the selection circuit 116 is configured to selectively output one of 0 (or ~0, i.e., 1), B, or 2B based on the selection signal. For example, when the first selection signal m1 is invalid (e.g., 0) and the second selection signal m2 is invalid (e.g., 0), the selection circuit 116 outputs 0 (or 1); when the first selection signal m1 is valid (e.g., 1) and the second selection signal m2 is invalid (e.g., 0), the selection circuit 116 outputs B; when the first selection signal m1 is invalid (e.g., 0) and the second selection signal m2 is valid (e.g., 1), the selection circuit 116 outputs 2B.

[0066] In some embodiments, such as when the selection signal includes a first selection signal m1, a second selection signal m2, and a third selection signal m0, the selection circuit 116 is configured to selectively output one of 0, ~0 (i.e., 1), B, and 2B based on the selection signal. For example, when the first selection signal m1 is invalid (e.g., 0), the second selection signal m2 is invalid (e.g., 0), and the third selection signal m0 is invalid (e.g., 0), the selection circuit 116 outputs 1 (or 0); when the first selection signal m1 is invalid (e.g., 0), the second selection signal m2 is invalid (e.g., 0), and the third selection signal m0 is valid (e.g., 1), the selection circuit 116 outputs 0 (or 1); when the first selection signal m1 is valid (e.g., 1), the second selection signal m2 is invalid (e.g., 0), and the third selection signal m0 is invalid (e.g., 0), the selection circuit 116 outputs B; and when the first selection signal m1 is invalid (e.g., 0), the second selection signal m2 is valid (e.g., 1), and the third selection signal m0 is invalid (e.g., 0), the selection circuit 116 outputs 2B.

[0067] Carry compensation circuit 118 is configured to generate carry compensation (referred to as ci in this document) corresponding to the sign of the Booth encoding of the three adjacent bits a[i+1], a[i], a[i-1] of the first number a.

[0068] In some embodiments, the carry compensation circuit 118 is configured to generate a carry compensation as 0 when the sign of the Booth encoding of the three adjacent bits a[i+1], a[i], a[i-1] of the first number a is positive, and to generate a carry compensation as 1 when the sign of the Booth encoding of the three adjacent bits a[i+1], a[i], a[i-1] of the first number a is negative.

[0069] The partial product summing circuit 120 is configured to sum the outputs of the selection circuit 116 and the carry compensation circuit 118 of all partial product generation circuits 110 to generate the product of the first number a and the second number b.

[0070] In some embodiments, the partial product summing circuit 120 may include a compression tree and an adder. The compression tree can be used to compress the partial product. The adder can be used to sum the final results. For example, the compression tree may include a multi-input dual-output compression tree, wherein the number of inputs depends on the number of outputs of all selection circuits 116 and carry compensation circuits 118. A larger-scale compression tree may also be implemented alternatively as a cascade of multiple smaller-scale compression trees. In some embodiments, the partial product summing circuit 120 may also include a cascade of multiple full adders and an adder.

[0071] In such Figure 1 In the partial product generation circuit 110 of the Booth multiplier 100 shown, the inverting circuit 112 and the encoding circuit 114 can be located in parallel before the selection circuit 116, and the carry compensation circuit 118 can also operate independently. Therefore, the partial product generation circuit 110 has fewer delay stages, which optimizes the performance of the Booth multiplier 100 and achieves reduced power consumption.

[0072] The partial product generator circuit 110 can be implemented according to different Booth encoding rules. For example, the difference between these Booth encoding rules can be the Booth encoding of 000 and the Booth encoding of 111. In some cases, the Booth encoding of 000 and the Booth encoding of 111 can have the same symbol. In other cases, the Booth encoding of 000 and the Booth encoding of 111 can have different symbols.

[0073] In some embodiments, the partial product generation circuit 110 can be implemented according to the first Booth encoding rule shown in Table 1, wherein the Booth encoding of 000 and 111 is -0.

[0074] Table 1

[0075] Figure 2 A first example of a partial product generation circuit 110 implemented according to the first Booth encoding rule is shown.

[0076] like Figure 2As shown, the encoding circuit 114 includes a first encoding circuit 1142, which is used to receive three adjacent bits a[i+1], a[i], and a[i-1] of the first number a to generate a first selection signal m1 and a second selection signal m2. For example, the first encoding circuit 1142 is configured to: perform an XOR operation XOR1 on the highest bit a[i+1] and the middle bit a[i]; perform an XNOR operation XNR1 on the lowest bit a[i-1] and the middle bit a[i]; perform an AND operation AND1 on the result of the XOR operation XOR1 and the result of the XNOR operation XNR1 to generate the second selection signal m2; and perform a NOT operation NOT1 on the result of the XNOR operation XNR1 to generate the first selection signal m1.

[0077] The inverting circuit 112 is configured to perform an XOR operation (XOR2) on the inverted version ~a[i+1] of the highest bit a[i+1] and the second number b to generate the output B of the inverting circuit. When ~a[i+1] is 1 (i.e., a[i+1] is 0), B = ~b. When ~a[i+1] is 0 (i.e., a[i+1] is 1), B = b.

[0078] The selection circuit 116 is configured to: perform an AND operation AND3 on the first selection signal m1 and a single version B of the output of the inverting circuit 112; perform an AND operation AND2 on the second selection signal m2 and a double version 2B of the output of the inverting circuit 112; perform an OR operation OR1 on the result of the AND operation AND3 and the result of the AND operation AND2; and perform a NOT operation NOT2 on the result of the OR operation OR1 to generate a partial product md. Here, 2B is obtained by shifting the output B of the inverting circuit 112 one bit to the left, which can be implemented, for example, by a shifter (not shown).

[0079] The carry compensation circuit 118 is configured to: perform an OR operation OR2 on the least significant bit a[i-1] and the middle bit a[i]; perform an AND operation AND4 on the result of the OR operation OR2 and the inverted version ~a[i+1] of the most significant bit a[i+1]; and perform a NOT operation NOT3 on the result of the AND operation AND4 to generate the carry compensation ci.

[0080] As a non-restrictive example, in Figure 2 In this circuit, the inverting circuit 112 may include an XOR gate, the encoding circuit 114 may include a combination of XOR gates, XNOR gates, AND gates, and NOT gates, the selection circuit 116 may include an AOI22 gate, and the carry compensation circuit 118 may include an OAI21 gate (which is used to implement the logical operation "~[(A1|A2)&(B)]", where A1, A2, and B are the three inputs of the OAI21 gate). In this way, a three-level logic circuit with a smaller area and less delay can be implemented, thereby reducing the power consumption of the Booth multiplier 100.

[0081] Table 2 shows Figure 2 The correspondence between the three adjacent bits a[i+1], a[i], and a[i-1] input in the circuit and the logical operation performed by the AOI22 gate of the selection circuit 116, and the generated md and ci.

[0082] Table 2

[0083] As shown in Table 2, the partial products generated by 111 and 000 are both 1, which will be added to the carry compensation 1 to achieve "-0". The partial product generated by 100 is ~2b, which will be added to the carry compensation 1 to achieve "-2b". The partial products generated by 101 and 110 are both ~b, which will be added to the carry compensation 1 to achieve "-b".

[0084] Figure 3 A second example of a partial product generation circuit 110 implemented according to the first Booth encoding rule is shown. Figure 3 Compared to Figure 2 The difference lies in the implementation of the inverting circuit 112. For example... Figure 3 As shown, the inverting circuit 112 is configured to: perform an AND operation AND5 on the inverted version ~a[i+1] of the highest bit a[i+1] and the inverted version ~b of the second number b; perform an AND operation AND6 on the highest bit a[i+1] and the second number b; and perform an OR operation OR3 on the result of the AND operation AND5 and the result of the AND operation AND6 to generate the output B of the inverting circuit 112. As a non-limiting example, in Figure 3 In the inverting circuit 112, the AO22 gate may be included.

[0085] Figure 4 A third example of a partial product generation circuit 110 implemented according to the first Booth encoding rule is shown. Figure 4 Compared to Figure 2 The difference lies in the implementation of the inverting circuit 112. For example... Figure 4 As shown, the inverting circuit 112 is configured to perform an XOR operation XNR2 on the highest bit a[i+1] and the second number b to generate the output B of the inverting circuit 112. As a non-limiting example, in Figure 4 In the above, the inverting circuit 112 may include an XOR gate.

[0086] Figure 5 A fourth example of a partial product generation circuit 110 implemented according to the first Booth encoding rule is shown. Figure 5 Compared to Figure 2 The difference lies in the implementation of the inverting circuit 112. For example... Figure 5As shown, the inverting circuit 112 is configured to: perform an AND operation AND5 on the highest bit a[i+1] and the inverted version ~b of the second number b; perform an AND operation AND6 on the inverted version ~a[i+1] of the highest bit a[i+1] and the second number b; perform an OR operation OR3 on the result of the AND operation AND5 and the result of the AND operation AND6; and perform a NOT operation NOT4 on the result of the OR operation OR3 to generate the output B of the inverting circuit 112. As a non-limiting example, in Figure 5 In this circuit, the inverting circuit 112 may include an AOI22 gate.

[0087] In some embodiments, the partial product generation circuit 110 can be implemented according to the second Booth encoding rule shown in Table 3, wherein the Booth encoding of 000 and 111 is 0.

[0088] Table 3

[0089] Figure 6 A fifth example of a partial product generation circuit 110 implemented according to the second Booth encoding rule is shown.

[0090] like Figure 6 As shown, the encoding circuit 114 includes a first encoding circuit 1142, which is used to receive three adjacent bits a[i+1], a[i], and a[i-1] of the first number a to generate a first selection signal m1 and a second selection signal m2. For example, the first encoding circuit 1142 is configured to: perform an XOR operation XOR1 on the highest bit a[i+1] and the middle bit a[i]; perform an XNOR operation XNR1 on the lowest bit a[i-1] and the middle bit a[i]; perform an AND operation AND1 on the result of the XOR operation XOR1 and the result of the XNOR operation XNR1 to generate the second selection signal m2; and perform a NOT operation NOT1 on the result of the XNOR operation XNR1 to generate the first selection signal m1.

[0091] The inverting circuit 112 is configured to perform an XOR operation XNR2 on the inverted version ~a[i+1] of the highest bit a[i+1] and the second number b to generate the output B of the inverting circuit. When ~a[i+1] is 0 (i.e., a[i+1] is 1), B = ~b. When ~a[i+1] is 1 (i.e., a[i+1] is 0), B = b.

[0092] The selection circuit 116 is configured to: perform an AND operation AND3 on the first selection signal m1 and a single version B of the output of the inverting circuit 112; perform an AND operation AND2 on the second selection signal m2 and a double version 2B of the output of the inverting circuit 112; and perform an OR operation OR1 on the result of the AND operation AND3 and the result of the AND operation AND2 to generate a partial product md. Here, 2B is obtained by shifting the output B of the inverting circuit 112 one bit to the left, which can be implemented, for example, by a shifter (not shown).

[0093] The carry compensation circuit 118 is configured to: perform an AND operation AND4 on the least significant bit a[i-1] and the middle bit a[i]; perform an OR operation OR2 on the result of the AND operation AND4 and the inverted version ~a[i+1] of the most significant bit a[i+1]; and perform a NOT operation NOT2 on the result of the OR operation OR2 to generate the carry compensation ci.

[0094] As a non-restrictive example, in Figure 6 In this circuit, the inverting circuit 112 may include an XNOR gate, the encoding circuit 114 may include a combination of XOR gates, XNOR gates, AND gates, and NOT gates, the selection circuit 116 may include an AO22 gate, and the carry compensation circuit 118 may include an AOI21 gate (which is used to implement the logical operation "~[(A1&A2) | (B)]", where A1, A2, and B are the three inputs of the AOI21 gate). This allows for a smaller area and less delay in the three-level logic circuit, thereby reducing the power consumption of the Booth multiplier 100.

[0095] Table 4 shows Figure 6 The correspondence between the three adjacent bits a[i+1], a[i], and a[i-1] input and the logical operation performed by the AO22 gate of the selection circuit 116, and the generated md and ci.

[0096] Table 4

[0097] As shown in Table 4, the partial product generated by 100 is ~2b, which will be "-2b" by adding it to the carry compensation 1. The partial products generated by 101 and 110 are both ~b, which will be "-b" by adding it to the carry compensation 1.

[0098] Figure 7 A sixth example of a partial product generation circuit 110 implemented according to the second Booth encoding rule is shown. Figure 7 Compared to Figure 6 The difference lies in the implementation of the inverting circuit 112. For example... Figure 7As shown, the inverting circuit 112 is configured to: perform an AND operation AND5 on the inverted version ~a[i+1] of the highest bit a[i+1] and the inverted version ~b of the second number b; perform an AND operation AND6 on the highest bit a[i+1] and the second number b; perform an OR operation OR3 on the result of the AND operation AND5 and the result of the AND operation AND6; and perform a NOT operation NOT3 on the result of the OR operation OR3 to generate the output B of the inverting circuit 112. As a non-limiting example, in Figure 7 In the middle, the inverting circuit 112 may include AOI 22 gates. Figure 8 A seventh example of a partial product generation circuit 110 implemented according to the second Booth encoding rule is shown. Figure 8 Compared to Figure 6 The difference lies in the implementation of the inverting circuit 112. For example... Figure 8 As shown, the inverting circuit 112 is configured to perform an XOR operation (XOR2) on the highest bit a[i+1] and the second number b to generate the output B of the inverting circuit 112. As a non-limiting example, in Figure 8 In the above, the inverting circuit 112 may include an XOR gate.

[0099] Figure 9 An eighth example of a partial product generation circuit 110 implemented according to the second Booth encoding rule is shown. Figure 9 Compared to Figure 6 The difference lies in the implementation of the inverting circuit 112. For example... Figure 9 As shown, the inverting circuit 112 is configured to: perform an AND operation AND5 on the highest bit a[i+1] and the inverted version ~b of the second number b; perform an AND operation AND6 on the inverted version ~a[i+1] of the highest bit a[i+1] and the second number b; and perform an OR operation OR3 on the result of the AND5 and AND6 operations to generate the output B of the inverting circuit 112. As a non-limiting example, in Figure 9 In the inverting circuit 112, the AO22 gate may be included.

[0100] In some embodiments, the partial product generation circuit 110 can be implemented according to the third Booth encoding rule shown in Table 5, wherein the Booth encoding of 000 is 0 and the Booth encoding of 111 is -0.

[0101] Table 5

[0102] Figure 10 A ninth example of a partial product generation circuit 110 implemented according to the third Booth encoding rule is shown.

[0103] like Figure 10As shown, the encoding circuit 114 includes a first encoding circuit 1142, which is used to receive three adjacent bits a[i+1], a[i], and a[i-1] of the first number a to generate a first selection signal m1 and a second selection signal m2. For example, the first encoding circuit 1142 is configured to: perform an XOR operation XOR1 on the highest bit a[i+1] and the middle bit a[i]; perform an XNOR operation XNR1 on the lowest bit a[i-1] and the middle bit a[i]; perform an AND operation AND1 on the result of the XOR operation XOR1 and the result of the XNOR operation XNR1 to generate the second selection signal m2; and perform a NOT operation NOT1 on the result of the XNOR operation XNR1 to generate the first selection signal m1.

[0104] The encoding circuit 114 further includes a second encoding circuit 1144 for receiving three adjacent bits a[i+1], a[i], and a[i-1] of the first number a to generate a third selection signal m0. For example, the second encoding circuit 1144 is configured to perform a NOR operation on the three adjacent bits a[i+1], a[i], and a[i-1] of the first number a to generate the third selection signal m0.

[0105] The inverting circuit 112 is configured to perform an XOR operation XNR2 on the highest bit a[i+1] and the second number b to generate the output B of the inverting circuit. When a[i+1] is 0, B = ~b. When a[i+1] is 1, B = b.

[0106] The selection circuit 116 is configured to: perform an AND operation AND3 on the first selection signal m1 and a single version B of the output of the inverting circuit 112; perform an AND operation AND2 on the second selection signal m2 and a double version 2B of the output of the inverting circuit 112; perform an OR operation OR1 on the result of the AND operation AND3, the result of the AND operation AND2, and the third selection signal m0; and perform a NOT operation NOT2 on the result of the OR operation OR1 to generate a partial product md. Here, 2B is obtained by shifting the output B of the inverting circuit 112 one bit to the left, which can be implemented, for example, by a shifter (not shown).

[0107] The carry compensation circuit 118 is configured to receive and output the highest bit a[i+1] as carry compensation ci.

[0108] As a non-restrictive example, in Figure 10In this circuit, the inverting circuit 112 may include an XNOR gate; the first encoding circuit 1142 may include a combination of XOR gates, XNOR gates, AND gates, and NOT gates; the second encoding circuit 1144 may include a NOR gate; the selection circuit 116 may include an AOI221 gate (which is used to implement the logical operation "~[(A1&A2) | (B1&B2) | (C)]", where A1, A2, B1, B2, and C are the five inputs of the AOI221 gate); and the carry compensation circuit 118 may include a pass-through. In this way, a three-level logic circuit with a smaller area and less delay can be implemented, thereby reducing the power consumption of the Booth multiplier 100.

[0109] Table 6 shows Figure 10 The correspondence between the three adjacent bits a[i+1], a[i], a[i-1] input and the logical operation performed by the AOI221 gate of the selection circuit 116, and the generated md and ci.

[0110] Table 6

[0111] As shown in Table 6, the partial product generated by 111 is 1, which will be "-0" by adding it to the carry compensation 1. The partial product generated by 100 is ~2b, which will be "-2b" by adding it to the carry compensation 1. The partial products generated by 101 and 110 are both ~b, which will be "-b" by adding them to the carry compensation 1.

[0112] Figure 11 A tenth example of a partial product generation circuit 110 implemented according to the third Booth encoding rule is shown. Figure 11 Compared to Figure 10 The difference lies in the implementation of the inverting circuit 112. For example... Figure 11 As shown, the inverting circuit 112 is configured to: perform an AND operation AND5 on the highest bit a[i+1] and the inverted version ~b of the second number b; perform an AND operation AND4 on the inverted version ~a[i+1] of the highest bit a[i+1] and the second number b; perform an OR operation OR2 on the result of the AND operation AND5 and the result of the AND operation AND4; and perform a NOT operation NOT3 on the result of the OR operation OR2 to generate the output B of the inverting circuit 112. As a non-limiting example, in Figure 11 In this circuit, the inverting circuit 112 may include an AOI22 gate.

[0113] Figure 12 An eleventh example of a partial product generation circuit 110 implemented according to the third Booth encoding rule is shown. Figure 12 Compared to Figure 10 The difference lies in the implementation of the inverting circuit 112, the second encoding circuit 1144, and the selection circuit 116.

[0114] like Figure 12 As shown, the inverting circuit 112 is configured to perform an XOR operation (XOR2) on the highest bit a[i+1] and the second number b to generate the output B of the inverting circuit 112. When a[i+1] is 1, B = ~b. When a[i+1] is 0, B = b. The second encoding circuit 1144 is configured to perform an AND operation (AND4) on the three adjacent bits a[i+1], a[i], and a[i-1] of the first number a to generate the third selection signal m0. The selection circuit 116 is configured to: perform an AND operation (AND3) on the first selection signal m1 and a double version B of the output of the inverting circuit 112; perform an AND operation (AND2) on the second selection signal m2 and a double version 2B of the output of the inverting circuit 112; and perform an OR operation (OR1) on the result of the AND operation (AND3), the result of the AND operation (AND2), and the third selection signal m0 to generate a partial product md. Here, 2B is obtained by shifting the output B of the inverting circuit 112 one bit to the left, which can be implemented, for example, by a shifter (not shown).

[0115] As a non-restrictive example, in Figure 12 In this circuit, the inverting circuit 112 may include an XOR gate; the first encoding circuit 1142 may include a combination of XOR gates, XNOR gates, AND gates, and NOT gates; the second encoding circuit 1144 may include an AND gate; the selection circuit 116 may include an AO221 gate (which is used to implement the logical operation "(A1&A2) | (B1&B2) | (C)", where A1, A2, B1, B2, and C are the five inputs of the AO221 gate); and the carry compensation circuit 118 may include a pass-through. In this way, a three-level logic circuit with a smaller area and less delay can be implemented, thereby reducing the power consumption of the Booth multiplier 100.

[0116] Table 7 shows Figure 12 The correspondence between the three adjacent bits a[i+1], a[i], and a[i-1] input in the circuit and the logical operation performed by the AO221 gate of the selection circuit 116, and the generated md and ci.

[0117] Table 7

[0118] As shown in Table 7, the partial product generated by 111 is 1, which will be "-0" by adding it to the carry compensation 1. The partial product generated by 100 is ~2b, which will be "-2b" by adding it to the carry compensation 1. The partial products generated by 101 and 110 are both ~b, which will be "-b" by adding them to the carry compensation 1.

[0119] Figure 13A twelfth example of a partial product generation circuit 110 implemented according to the third Booth encoding rule is shown. Figure 13 Compared to Figure 12 The difference lies in the implementation of the inverting circuit 112. For example... Figure 13 As shown, the inverting circuit 112 is configured to: perform an AND operation AND5 on the highest bit a[i+1] and the inverted version ~b of the second number b; perform an AND operation AND6 on the inverted version ~a[i+1] of the highest bit a[i+1] and the second number b; and perform an OR operation OR2 on the result of the AND operation AND5 and the result of the AND operation AND6 to generate the output B of the inverting circuit 112. As a non-limiting example, in Figure 13 In the inverting circuit 112, the AO22 gate may be included.

[0120] In some embodiments, the partial product generation circuit 110 can be implemented according to the fourth Booth encoding rule shown in Table 8, wherein the Booth encoding of 000 is -0 and the Booth encoding of 111 is 0.

[0121] Table 8

[0122] Figure 14 The thirteenth example of a partial product generation circuit 110 implemented according to the fourth Booth encoding rule is shown.

[0123] like Figure 14 As shown, the encoding circuit 114 includes a first encoding circuit 1142, which is used to receive three adjacent bits a[i+1], a[i], and a[i-1] of the first number a to generate a first selection signal m1 and a second selection signal m2. For example, the first encoding circuit 1142 is configured to: perform an XOR operation XOR1 on the highest bit a[i+1] and the middle bit a[i]; perform an XNOR operation XNR1 on the lowest bit a[i-1] and the middle bit a[i]; perform an AND operation AND1 on the result of the XOR operation XOR1 and the result of the XNOR operation XNR1 to generate the second selection signal m2; and perform a NOT operation NOT1 on the result of the XNOR operation XNR1 to generate the first selection signal m1.

[0124] The encoding circuit 114 further includes a second encoding circuit 1144, which is used to receive three adjacent bits a[i+1], a[i], and a[i-1] of the first number a to generate a third selection signal m0. For example, the second encoding circuit 1144 is configured to perform an AND operation AND4 on the three adjacent bits a[i+1], a[i], and a[i-1] of the first number a to generate the third selection signal m0.

[0125] The inverting circuit 112 is configured to perform an XOR operation XNR2 on the highest bit a[i+1] and the second number b to generate the output B of the inverting circuit. When a[i+1] is 0, B = ~b. When a[i+1] is 1, B = b.

[0126] The selection circuit 116 is configured to: perform an AND operation AND3 on the first selection signal m1 and a single version B of the output of the inverting circuit 112; perform an AND operation AND2 on the second selection signal m2 and a double version 2B of the output of the inverting circuit 112; perform an OR operation OR1 on the result of the AND operation AND3, the result of the AND operation AND2, and the third selection signal m0; and perform a NOT operation NOT2 on the result of the OR operation OR1 to generate a partial product md. Here, 2B is obtained by shifting the output B of the inverting circuit 112 one bit to the left, which can be implemented, for example, by a shifter (not shown).

[0127] The carry compensation circuit 118 is configured to: perform an OR operation OR2 on the lowest bit a[i-1] and the middle bit a[i]; perform an AND operation AND6 on the result of the OR operation OR2 and the inverted version ~a[i+1] of the highest bit a[i+1]; perform an AND operation AND5 on three adjacent bits a[i+1], a[i], and a[i-1]; and perform a NOR operation NOR on the result of the AND operation AND6 and the result of the AND operation AND5 to generate the carry compensation ci.

[0128] As a non-restrictive example, in Figure 14 In this circuit, the inverting circuit 112 may include an XNOR gate; the first encoding circuit 1142 may include a combination of an XOR gate, an XNOR gate, an AND gate, and a NOT gate; the second encoding circuit 1144 may include an AND gate; the selection circuit 116 may include an AOI221 gate; and the carry compensation circuit 118 may include an OA21 gate (which is used to implement the logical operation "(A1|A2)&(B)", where A1, A2, and B are the three inputs of the OA21 gate), a combination of an AND gate, and a NOR gate. In this way, a three-level logic circuit with a smaller area and less delay can be implemented, thereby reducing the power consumption of the Booth multiplier 100.

[0129] Table 9 shows... Figure 14 The correspondence between the three adjacent bits a[i+1], a[i], a[i-1] input and the logical operation performed by the AOI221 gate of the selection circuit 116, and the generated md and ci.

[0130] Table 9

[0131] As shown in Table 9, the partial product generated by 000 is 1, which will be added to the carry compensation 1 to achieve "-0". The partial product generated by 100 is ~2b, which will be added to the carry compensation 1 to achieve "-2b". The partial products generated by 101 and 110 are both ~b, which will be added to the carry compensation 1 to achieve "-b".

[0132] Figure 15 The fourteenth example of a partial product generation circuit 110 implemented according to the fourth Booth encoding rule is shown. Figure 15 Compared to Figure 14 The difference lies in the implementation of the inverting circuit 112. For example... Figure 15 As shown, the inverting circuit 112 is configured to: perform an AND operation AND7 on the highest bit a[i+1] and the inverted version ~b of the second number b; perform an AND operation AND8 on the inverted version ~a[i+1] of the highest bit a[i+1] and the second number b; perform an OR operation OR3 on the result of the AND operation AND7 and the result of the AND operation AND8; and perform a NOT operation NOT3 on the result of the OR operation OR3 to generate the output B of the inverting circuit 112. As a non-limiting example, in Figure 15 In this circuit, the inverting circuit 112 may include an AOI22 gate.

[0133] Figure 16 The fifteenth example of a partial product generation circuit 110 implemented according to the fourth Booth encoding rule is shown. Figure 16 Compared to Figure 14 The difference lies in the implementation of the inverting circuit 112, the second encoding circuit 1144, and the selection circuit 116. Additionally, Figure 16 Carry compensation circuit 118 and Figure 14 The carry compensation circuit is the same as 118, except that the corresponding NOT, AND, and OR NOT operations use different numerical labels to distinguish them. Figure 16 The remaining operations of the same kind in the code.

[0134] like Figure 16As shown, the inverting circuit 112 is configured to perform an XOR operation (XOR2) on the highest bit a[i+1] and the second number b to generate the output B of the inverting circuit 112. When a[i+1] is 1, B = ~b. When a[i+1] is 0, B = b. The second encoding circuit 1144 is configured to perform a NOR operation (NOR1) on the three adjacent bits a[i+1], a[i], and a[i-1] of the first number a to generate the third selection signal m0. The selection circuit 116 is configured to: perform an AND operation (AND3) on the first selection signal m1 and a double version B of the output of the inverting circuit 112; perform an AND operation (AND2) on the second selection signal m2 and a double version 2B of the output of the inverting circuit 112; and perform an OR operation (OR1) on the result of the AND operation (AND3), the result of the AND operation (AND2), and the third selection signal m0 to generate a partial product md. Here, 2B is obtained by shifting the output B of the inverting circuit 112 one bit to the left, which can be implemented, for example, by a shifter (not shown).

[0135] As a non-restrictive example, in Figure 16 In this circuit, the inverting circuit 112 may include an XOR gate, the first encoding circuit 1142 may include a combination of XOR gates, XNOR gates, AND gates, and NOT gates, the second encoding circuit 1144 may include a NOR gate, the selection circuit 116 may include an AO221 gate, and the carry compensation circuit 118 may include a combination of an OA21 gate, AND gates, and NOR gates. This allows for a smaller area and less delay in the three-level logic circuit, thereby reducing the power consumption of the Booth multiplier 100.

[0136] Table 10 shows Figure 16 The correspondence between the three adjacent bits a[i+1], a[i], and a[i-1] input in the circuit and the logical operation performed by the AO221 gate of the selection circuit 116, and the generated md and ci.

[0137] Table 10

[0138] As shown in Table 10, the partial product generated by 000 is 1, which will be added to the carry compensation 1 to achieve "-0". The partial product generated by 100 is ~2b, which will be added to the carry compensation 1 to achieve "-2b". The partial products generated by 101 and 110 are both ~b, which will be added to the carry compensation 1 to achieve "-b".

[0139] Figure 17 The sixteenth example of a partial product generation circuit 110 implemented according to the fourth Booth encoding rule is shown. Figure 17 Compared to Figure 16 The difference lies in the implementation of the inverting circuit 112. For example... Figure 17As shown, the inverting circuit 112 is configured to: perform an AND operation AND7 on the highest bit a[i+1] and the inverted version ~b of the second number b; perform an AND operation AND6 on the inverted version ~a[i+1] of the highest bit a[i+1] and the second number b; and perform an OR operation OR3 on the result of the AND operation AND7 and the result of the AND operation AND6 to generate the output B of the inverting circuit 112. As a non-limiting example, in Figure 17 In the inverting circuit 112, the AO22 gate may be included.

[0140] Figures 2 to 9 The partial product generation circuit 110 shown is compared to Figures 10 to 17 The partial product generation circuit 110 can have a further reduced circuit area. This is because... Figures 2 to 9 The partial product generation circuit 110 shown does not require the third selection signal m0, thus reducing one input in the first-stage AND operation of the selection circuit 116, and consequently eliminating the use of many circuit elements. This reduction in circuit area can lead to a further reduction in circuit power consumption. Considering that the second-stage OR operation involves bitwise OR operations, this advantage increases with the number of bits in the second number b.

[0141] Figures 10 to 13 The partial product generation circuit 110 shown is compared to Figures 2 to 9 , Figures 14 to 17 The partial product generation circuit 110 can have a simplified carry compensation circuit. In fact, Figures 10 to 13 The carry compensation circuit of the partial product generation circuit 110 shown only needs to transmit the highest bit a[i+1] without performing any logical operations.

[0142] This disclosure also provides, in another aspect, an arithmetic circuit that may include the Booth multiplier according to any of the foregoing embodiments. In some embodiments, the arithmetic circuit may include a multiply-accumulate circuit. For example, Figure 18 An arithmetic circuit 200 is shown, which can operate as a multiply-accumulate circuit. The arithmetic circuit 200 includes a multiplication circuit 210, an addition circuit 220, and a register circuit 230. The multiplication circuit 210 includes a Booth multiplier 100 according to any of the foregoing embodiments. The addition circuit 220 includes an adder to sum the output of the multiplication circuit 210 and the output of the register circuit 230. The register circuit 230 includes a register to store the output of the adder circuit 220. Suppose the arithmetic circuit 200 wants to calculate the multiply-accumulate of the logarithm x (a1·b1 + a2·b2 + ... + a...). x ·b x (where x is a positive integer), then in each of the x periods, the corresponding pair of numbers a from these x pairs can be represented. k b k(k=1,2,...,x) are fed into Booth multiplier 100 to compute the product of these logarithms, a. k ·b k Then a k ·b k The numbers are accumulated via adder circuit 220 and register circuit 230. For example, if these x pairs are fed sequentially from 1 to x, then at the end of the first cycle, the result stored in register circuit 230 is a1·b1; at the end of the second cycle, the result stored in register circuit 230 is a1·b1+a2·b2, and so on until the end of the xth cycle, when the result stored in register circuit 230 is a1·b1+a2·b2+…a x ·b x In some embodiments, the multiplication circuit 210 may include multiple Booth multipliers 100 operating in parallel. For example, when the multiplication circuit 210 includes y Booth multipliers 100 operating in parallel (y is a positive integer greater than 1), only x / y cycles are needed to calculate the logarithmic multiplication and accumulation of x. In such a case, the adder circuit 220 may include a cascaded combination of a compressed tree or full adders, as well as an adder, to sum the outputs of the y Booth multipliers 100 and the output of the register circuit 230. When y = x, only one cycle is needed to calculate the logarithmic multiplication and accumulation of x, thus eliminating the need for the register circuit 230.

[0143] This disclosure also provides a processor that may include a Booth multiplier or an arithmetic circuit as described in any of the foregoing embodiments. For example, such a processor may be a coprocessor, digital signal processor, central processing unit, dedicated instruction processor, neural network processor, or various other processors. In the case of a neural network processor, its convolution calculation unit may include a Booth multiplier or an arithmetic circuit (e.g., a multiply-accumulate circuit) as described in any of the foregoing embodiments.

[0144] In another aspect, this disclosure also provides a computing device that may include the processor described in any of the foregoing embodiments. Examples of computing devices may include, but are not limited to, consumer electronics products, components of consumer electronics products, electronic testing equipment, cellular communication infrastructure such as base stations, etc. Examples of computing devices may include, but are not limited to, mobile phones such as smartphones, wearable computing devices such as smartwatches or headphones, telephones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal digital assistants (PDAs), microwave ovens, refrigerators, in-vehicle electronic systems such as automotive electronic systems, stereo systems, DVD players, CD players, digital music players such as MP3 players, radios, portable video cameras, cameras such as digital cameras, portable storage chips, washing machines, dryers, washer / dryer systems, peripheral devices, clocks, etc. Furthermore, computing devices may include incomplete products.

[0145] The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “upper,” “lower,” “high,” “lower,” etc., used in the specification and claims, if present, are for descriptive purposes and not necessarily for describing constant relative positions. It should be understood that such terms are interchangeable where appropriate, so that embodiments of this disclosure described herein can operate, for example, in orientations different from those shown or otherwise described herein. For example, when the device in the drawings is reversed, a feature previously described as “above” other features may now be described as “below” other features. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), in which case the relative spatial relationships will be interpreted accordingly.

[0146] In the specification and claims, when an element is described as being "on top of," "attached to," "connected to," "coupled to," or "in contact with" another element, the element may be directly located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or one or more intermediate elements may be present. Conversely, when an element is described as being "directly" located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with another element, no intermediate elements are present. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that a feature has a portion overlapping with the adjacent feature or a portion located above or below the adjacent feature.

[0147] As used herein, the term "exemplary" means "serving as an example, instance, or illustration," and not as a "model" to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this disclosure is not limited to any theory expressed or implied as given in the art, background, summary of the invention, or detailed description.

[0148] As used herein, the term "substantially" means any minor variation resulting from design or manufacturing defects, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for differences from the perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in the actual implementation.

[0149] Additionally, terms such as “first,” “second,” etc., may be used in this document for reference purposes only and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the words “first,” “second,” and other such numerical terms relating to structures or elements do not imply order or sequence.

[0150] It should also be understood that when the term “including / contains” is used herein, it indicates the presence of the indicated feature, whole, step, operation, unit and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units and / or components and / or combinations thereof.

[0151] Additionally, when used in this application, the terms "here," "above," "below," "below," "in the preceding text," and similar terms should refer to the entire application and not any particular part of it. Furthermore, unless explicitly stated otherwise or otherwise understood in the context in which they are used, conditional language used herein, such as "may," "possibly," "for example," "such as," etc., is generally intended to express that certain embodiments include certain features, elements, and / or states, while other embodiments do not. Therefore, such conditional language is not generally intended to imply that one or more embodiments require features, elements, and / or states in any way, or whether such features, elements, and / or states are included or performed in any particular embodiment.

[0152] In this disclosure, the term “provide” is used broadly to cover all ways of obtaining an object, and therefore “provide an object” includes, but is not limited to, “purchasing,” “preparing / manufacturing,” “arranging / setting up,” “installing / assembling,” and / or “ordering” an object.

[0153] As used herein, the term “and / or” includes any and all combinations of one or more of the listed items in association. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0154] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Aspects and elements of all the embodiments disclosed above may be combined in any way and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive. In fact, the novel devices, methods, and systems described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and changes may be made to the form of the methods and systems described herein without departing from the spirit of this disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in various different ways.

[0155] The various embodiments of this disclosure can be described in a progressive manner, with references made to similar or identical parts between embodiments. Each embodiment focuses on describing the differences from other embodiments. In this disclosure, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this disclosure. In this disclosure, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0156] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. The various embodiments disclosed herein can be combined in any way without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A Booth multiplier, characterized in that, The Booth multiplier is used to calculate the product of the first number and the second number. The Booth multiplier includes: One or more partial product generation circuits, each partial product generation circuit being configured to receive three adjacent bits of the first number and the second number, and including: The inverting circuit is configured to selectively invert the second number based on the most significant bit of the three adjacent bits of the first number. The encoding circuit is configured to generate a selection signal based on the three adjacent bits of the first number for selecting the operation to be performed on the output of the inverting circuit. The selection circuit is configured to apply the selection signal received from the encoding circuit to the output of the inverting circuit received from the inverting circuit to generate a partial product. Carry compensation circuitry is configured to generate carry compensation corresponding to the sign of the Booth-encoded three adjacent bits of the first number; and A partial product summing circuit is configured to sum the outputs of the selection circuit and the carry compensation circuit of the one or more partial product generation circuits to generate the product of the first number and the second number.

2. The Booth multiplier according to claim 1, characterized in that, The selection signal includes a first selection signal for selecting a single version of the output of the inverting circuit and a second selection signal for selecting a double version of the output of the inverting circuit, and the encoding circuit includes: A first encoding circuit is configured to generate a first selection signal and a second selection signal based on the three adjacent bits of the first number.

3. The Booth multiplier according to claim 2, characterized in that, The first Booth code, where all three adjacent bits are 0, has the same symbol as the second Booth code, where all three adjacent bits are 1.

4. The Booth multiplier according to claim 3, characterized in that, The selection circuit is configured as follows: Perform a first AND operation on the first selection signal and a version of the output of the inverting circuit; Perform a second AND operation on the second selection signal and a double version of the output of the inverting circuit; Perform a first OR operation on the result of the first AND operation and the result of the second AND operation; as well as Perform a first NOT operation on the result of the first OR operation to generate the partial product.

5. The Booth multiplier according to claim 4, characterized in that, The carry compensation circuit is configured as follows: Perform a second OR operation on the middle and least significant bits of the three adjacent bits; Perform a third AND operation on the result of the second OR operation and the inverted version of the highest bit among the three adjacent bits; A second NOT operation is performed on the result of the third AND operation to generate the carry compensation.

6. The Booth multiplier according to claim 5, characterized in that, The inverting circuit is configured as follows: Perform an XOR operation on the inverted version of the highest bit of the three adjacent bits of the first number and the second number to generate the output of the inverting circuit; or Perform an XOR operation on the highest bit of the three adjacent bits of the first number and the second number to generate the output of the inverting circuit; or Perform a fourth AND operation on the highest bit of the three adjacent bits of the first number and the inverted version of the second number. Perform a fifth AND operation on the second number and the inverted version of the three adjacent bits of the first number. Perform a third OR operation on the result of the fourth AND operation and the result of the fifth AND operation, and Perform a third NOT operation on the result of the third OR operation to generate the output of the inverting circuit; or Perform a sixth AND operation on the inverted version of the three adjacent bits of the first number and the inverted version of the second number. Perform a seventh AND operation on the highest bit of the three adjacent bits of the first number and the second number. A fourth OR operation is performed on the result of the sixth AND operation and the result of the seventh AND operation to generate the output of the inverting circuit.

7. The Booth multiplier according to claim 3, characterized in that, The selection circuit is configured as follows: Perform a first AND operation on the first selection signal and a version of the output of the inverting circuit; Perform a second AND operation on the second selection signal and a double version of the output of the inverting circuit; A first OR operation is performed on the result of the first AND operation and the result of the second AND operation to generate the partial product.

8. The Booth multiplier according to claim 7, characterized in that, The carry compensation circuit is configured as follows: Perform a third AND operation on the middle and least significant bits of the three adjacent bits; Perform a second OR operation on the result of the third AND operation and the inverted version of the highest bit among the three adjacent bits; Perform a first NOT operation on the result of the second OR operation to generate the carry compensation.

9. The Booth multiplier according to claim 8, characterized in that, The inverting circuit is configured as follows: Perform an XOR operation on the highest bit of the three adjacent bits of the first number and the second number to generate the output of the inverting circuit; or Perform an XOR operation on the inverted version of the highest bit of the three adjacent bits of the first number and the second number to generate the output of the inverting circuit; or Perform a fourth AND operation on the inverted version of the three adjacent bits of the first number and the inverted version of the second number. Perform a fifth AND operation on the highest bit of the three adjacent bits of the first number and the second number. Perform a third OR operation on the result of the fourth AND operation and the result of the fifth AND operation, and Perform a second NOT operation on the result of the third OR operation to generate the output of the inverting circuit; or Perform a sixth AND operation on the highest bit of the three adjacent bits of the first number and the inverted version of the second number. Perform a seventh AND operation on the second number using the inverted version of the three adjacent bits of the first number. A fourth OR operation is performed on the result of the sixth AND operation and the result of the seventh AND operation to generate the output of the inverting circuit.

10. The Booth multiplier according to claim 2, characterized in that, The first Booth code, where all three adjacent bits are 0, has the opposite sign to the second Booth code, where all three adjacent bits are 1.

11. The Booth multiplier according to claim 10, characterized in that, The selection signal further includes a third selection signal for selecting the symbols of the first Booth code and the second Booth code, and the encoding circuit further includes: The second encoding circuit is configured to generate the third selection signal based on the three adjacent bits of the first number.

12. The Booth multiplier according to claim 11, characterized in that: The selection circuit is configured as follows: A first AND operation is performed on the first selection signal and a version of the output of the inverting circuit. A second AND operation is performed on the second selection signal and a double version of the output of the inverting circuit. Perform a first OR operation on the result of the first AND operation, the result of the second AND operation, and the third selection signal. Perform a first NOT operation on the result of the first OR operation to generate the partial product; and The inverting circuit is configured as follows: Perform an XOR operation on the highest bit of the three adjacent bits of the first number and the second number to generate the output of the inverting circuit; or Perform a third AND operation on the highest bit of the three adjacent bits of the first number and the inverted version of the second number. Perform a fourth AND operation on the second number and the inverted version of the three adjacent bits of the first number. Perform a second OR operation on the result of the third AND operation and the result of the fourth AND operation, and A second NOT operation is performed on the result of the second OR operation to generate the output of the inverting circuit.

13. The Booth multiplier according to claim 12, characterized in that: The second encoding circuit is configured as follows: Perform a first NOR operation on the three adjacent bits of the first number to generate the third selection signal; and The carry compensation circuit is configured to receive and output the highest bit among the three adjacent bits as the carry compensation.

14. The Booth multiplier according to claim 12, characterized in that: The second encoding circuit is configured as follows: Perform a fifth AND operation on the three adjacent bits of the first number to generate the third selection signal; and The carry compensation circuit is configured as follows: Perform a third OR operation on the middle and least significant bits of the three adjacent bits; Perform a sixth AND operation on the result of the third OR operation and the inverted version of the highest bit among the three adjacent bits; Perform a seventh AND operation on the three adjacent bits of the first number; A second NOR operation is performed on the result of the sixth AND operation and the result of the seventh AND operation to generate the carry compensation.

15. The Booth multiplier according to claim 11, characterized in that: The selection circuit is configured as follows: A first AND operation is performed on the first selection signal and a version of the output of the inverting circuit. Perform a second AND operation on the second selection signal and a double version of the output of the inverting circuit, and Perform a first OR operation on the result of the first AND operation, the result of the second AND operation, and the third selection signal to generate the partial product; and The inverting circuit is configured as follows: Perform an XOR operation on the highest bit of the three adjacent bits of the first number and the second number to generate the output of the inverting circuit; or Perform a third AND operation on the highest bit of the three adjacent bits of the first number and the inverted version of the second number. Perform a fourth AND operation on the second number and the inverted version of the three adjacent bits of the first number. A second OR operation is performed on the result of the third AND operation and the result of the fourth AND operation to generate the output of the inverting circuit.

16. The Booth multiplier according to claim 15, characterized in that: The second encoding circuit is configured as follows: Perform a fifth AND operation on the three adjacent bits of the first number to generate the third selection signal; and The carry compensation circuit is configured to receive and output the highest bit among the three adjacent bits as the carry compensation.

17. The Booth multiplier according to claim 15, characterized in that: The second encoding circuit is configured as follows: Perform a first NOR operation on the three adjacent bits of the first number to generate the third selection signal; and The carry compensation circuit is configured as follows: Perform a third OR operation on the middle and least significant bits of the three adjacent bits; Perform a sixth AND operation on the result of the third OR operation and the inverted version of the highest bit among the three adjacent bits; Perform a seventh AND operation on the three adjacent bits of the first number; A second NOR operation is performed on the result of the sixth AND operation and the result of the seventh AND operation to generate the carry compensation.

18. The Booth multiplier according to any one of claims 2 to 17, characterized in that, The first encoding circuit is configured as follows: Perform an XOR operation on the highest and middle bits of the three adjacent bits of the first number; Perform an XOR operation on the least significant bit and the middle bit of the three adjacent bits of the first number; Perform a bitwise AND operation on the result of the XOR operation and the result of the XNOR operation to generate the second selection signal; and The result of the XOR operation is NOT operated to generate the first selection signal.

19. An operational circuit, characterized in that, The arithmetic circuit includes the Booth multiplier according to any one of claims 1 to 18.

20. A processor, characterized in that, The processor includes a Booth multiplier according to any one of claims 1 to 18 or an arithmetic circuit according to claim 19.

21. A computing device, characterized in that, The computing device includes the processor according to claim 20.

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