Configurable PCIE (Peripheral Component Interface Express) network communication middleware based on multiple partitions and multiple tasks

Abstract

The invention discloses configurable PCIE (Peripheral Component Interface Express) network communication middleware based on multiple partitions and multiple tasks, which comprises a system initialization module, a partition cache region management module and a PCIE channel management module, and is characterized in that the system initialization module is used for completing initialization and initializing the size of a partition cache region and the number and size of PCIE space channels according to analyzed configuration data; the partition cache region management module is used for managing a partition cache region and providing a transceiving interface for an upper-layer application; and the PCIE channel management module is used for managing a receiving and transmitting channel of the PCIE space channel and finishing copying from the partition cache region to the PCIE space channel and copying from the PCIE space channel to the partition cache region. Traditional communication software is decomposed into a multi-layer design, each layer of sub-function module is single in responsibility, and a communication framework which is easy to expand, upgrade and customize and supports efficient development is provided for development of various kinds of high-complexity middleware software.

Description

Technical Field

[0001] The invention belongs to the field of avionics technology and computer software architecture, and relates to a configurable PCIE network communication middleware based on multi-partition and multi-tasking. Background Art

[0002] The aircraft cockpit system is a complex system composed of multiple tasks, multiple operating systems, and multiple resources (storage, bus, sensors, etc.), which are interrelated, communicated, and mutually supported. It has complex system characteristics such as high integration and intelligence.

[0003] As the system complexity of military / civilian aircraft cockpit systems increases, functions and tasks become more and more diverse, the complexity of communication software also increases accordingly, the communication content becomes more diverse, and the communication data becomes more and more massive. For the sake of concurrency and transmission speed, PCIE will be used as the preferred communication method between the CPUs inside the cockpit system. The biggest feature of traditional cockpit PCIE communication software development is that it is based on a single application and a single operating system as the development center. This development method has the following three disadvantages: First, it is not conducive to the expansion and development of communication functions, and has low development efficiency and low reliability; second, PCIE communication is carried out between multiple partitions and multiple tasks at the same time, and the communication software does not manage the PCIE space uniformly, which is prone to abnormal errors; third, there are multiple operating systems in the cockpit system that need to maintain multiple sets of code. Each configuration change requires re-modification and compilation of multiple sets of code, which brings many inconveniences to development and maintenance. Summary of the invention

[0004] In order to solve the three drawbacks of the above-mentioned traditional cockpit PCIE communication software development, the invention aims to provide a configurable PCIE network communication middleware based on multi-partition and multi-task, and provide an easily expandable and upgradeable communication framework that supports efficient development for the development of modern cockpit communication middleware of various types, and decompose the traditional cockpit PCIE communication software into a multi-layer design, and each layer of sub-functional modules has a single responsibility, namely, caching the upper-layer partition application multi-task application communication data, forwarding the application communication data to the PCIE channel, and forwarding the data from the PCIE channel to the corresponding partition cache area. The first part needs to use semaphores to control the simultaneous access of multiple tasks within the partition; the second part adopts different copying methods for different operating systems and different CPUs; in the partition cache area, due to the large and small data volumes, for large data volume transmission, it is necessary to support the pre-fetching of data blocks and provide them to the upper-layer application. Here, a linked list structure is used for transmission, and the transmission of small data volumes adopts the traditional message queue method.

[0005] The object of the present invention is achieved through the following technical solutions:

[0006] A configurable PCIE network communication middleware based on multi-partition and multi-task, comprising a system initialization module, a partition buffer management module, and a PCIE channel management module;

[0007] The system initialization module is used to complete initialization, obtain configuration data and parse it, and initialize the partition buffer size and the number and size of PCIE space channels according to the parsed configuration data;

[0008] The partition cache management module is used to manage the partition cache, complete the data copy from the upper application buffer to the partition cache, and the data copy from the partition cache to the upper application buffer;

[0009] The PCIE channel management module is used to manage the transceiver channels of the PCIE space channel, and complete the copying from the partition buffer area to the PCIE space channel and from the PCIE space channel to the partition buffer area.

[0010] Preferably, when the partition cache management module is called by the upper-level partition application to send small packet data, the application data is copied from the application buffer to the sending partition cache; when it is called by the upper-level partition application to receive small packet data, the application data is copied from the receiving partition cache to the application buffer; when it is called by the upper-level partition application to send large packet data, a large packet data space is requested in the sending partition cache sending linked list and returned to the upper-level partition, and when the call to send the large packet data by the upper-level partition application ends, the large packet data space in the sending partition cache is marked as to be sent; when it is called by the upper-level partition application to receive large packet data, a packet of receiving large packet data space is obtained in the receiving partition cache receiving linked list and returned to the partition application, and when the call to receive large packet data by the upper-level partition ends, the large packet data space in the receiving partition cache is released as free space.

[0011] Preferably, the PCIE space channel uses message queues to transmit both small packet data and large packet data. The PCIE channel management module pre-fetches packet header data from the sending queue of small packet data and the sending linked list of large packet data to parse the destination CPU and copy the data to the corresponding PCIE space sending message queue; pre-fetches packet header data from each PCIE space receiving message queue to parse the destination partition and copy the data to the receiving queue of small packet data and the receiving linked list of large packet data in the corresponding partition buffer area.

[0012] Preferably, the PCIE channel management module uses the NEON instructions of the ARM architecture to copy small packet data; the PCIE channel management module and the partition buffer management module constrain the storage space address and length of the data packet, thereby using DMA technology to complete the large packet data copy; for a specific CPU architecture, the PCIE channel management module uses the assembly instruction copy unique to the architecture.

[0013] The beneficial effects of the present invention are:

[0014] 1. Allocate different buffers to different partitions, and transmit and receive in parallel between partitions without using semaphores, thus improving the efficiency of multi-partition transmission and reception;

[0015] 2. Select the corresponding configuration table according to the device information, configure different buffer sizes on different devices, use the same library, and reduce the difficulty of later maintenance;

[0016] 3. The underlying copy of different CPUs and operating systems can also select the corresponding copy method according to the configuration information to improve the copy efficiency;

[0017] 4. Small packet data and large packet data are transmitted using queues and linked lists respectively, which improves space utilization from a practical engineering perspective.

[0018] The present invention can be well applied to airborne cockpit or automobile cockpit systems, especially to large and complex systems, and can effectively improve development efficiency, software integration efficiency, transmission efficiency and high customizability. The invention has significant market prospects and economic benefits. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The structural block diagram of the cockpit system is specifically implemented.

[0020] Figure 2 The structure diagram of the configurable PCIE network communication middleware based on multi-partition and multi-tasking is shown.

[0021] Figure 3 The present invention is a workflow diagram of a configurable multi-partition and multi-task based PCIE network communication middleware.

[0022] Figure 4 Schematic diagram of the software and hardware layout of the specific implementation. DETAILED DESCRIPTION

[0023] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0024] As an example, see Figure 1 The aircraft cockpit system shown includes: 1) hardware, including CPU, GPU, bus types (such as PCIE, optical fiber, 1394, 1553B, etc.), interactive devices (touch, gesture recognition, etc.), sensors (radar, infrared, etc.); 2) operating system and related drivers, including operating system (such as Linux, Kylin, Tianmai, Yihui and other desktop or embedded systems), graphics driver, device driver; 3) middleware, including communication middleware; 4) application, including each partition application.

[0025] See also Figure 2As shown, a configurable multi-partition and multi-task based PCIE network communication middleware shown in this embodiment includes a system initialization module, a partition buffer management module and a PCIE channel management module.

[0026] The system initialization module is used to complete system initialization. It obtains and parses configuration data based on the CPU, operating system and other related device information; initializes the partition buffer size and the number and size of PCIE space channels based on the parsed configuration data. Among them, the configuration data can adjust the partition buffer size and the size of the PCIE space large and small packet data transmission channels according to the actual communication data volume characteristics of the partition task. Figure 4 As shown, in this embodiment, the PCIE space channel needs to configure queues of 3 channels.

[0027] The partition cache management module is used to manage the partition cache and complete data copying from the upper application buffer to the partition cache, and data copying from the partition cache to the upper application buffer.

[0028] When the partition cache management module is called by the upper-level partition application to send small packet data, the application data is copied from the application buffer to the sending partition cache; when it is called by the upper-level partition application to receive small packet data, the application data is copied from the receiving partition cache to the application buffer; when it is called by the upper-level partition application to send large packet data, a large packet data space is requested in the sending partition cache sending linked list and returned to the upper-level partition, and the sending of the large packet data is completed by the upper-level partition application, and the large packet data space in the sending partition cache is marked as waiting to be sent; when it is called by the upper-level partition application to receive large packet data, a packet of receiving large packet data space is obtained in the receiving partition cache receiving linked list and returned to the partition application, and the receiving of the large packet data is completed by the upper-level partition, and the large packet data space in the receiving partition cache is released as free space.

[0029] Small data packets are characterized by large numbers and small data lengths, so a relatively simple message queue data structure is used for sending and receiving; large data packets are characterized by small numbers and large data lengths, so a linked list data structure is used to complete data sending and receiving by applying for free space. Due to frequent applications for free space, in order to reduce system overhead, a dynamic memory management function is developed inside the partition cache management module, which does not require frequent calls to the system's memory management function, thereby reducing system overhead. Since the data in the partition cache will be copied to the PCIE channel through DMA technology, the cache data needs to be written back to the memory after the upper-level application calls the sending interface.

[0030] The PCIE channel management module is used to manage the transceiver channels of the PCIE space channel, and complete the copying from the partition buffer area to the PCIE space channel and from the PCIE space channel to the partition buffer area.

[0031] Due to the single function, the PCIE space channel uses message queues for both small and large packet data transmission. The PCIE channel management module pre-fetches the packet header data from the sending queue of small packet data and the sending linked list of large packet data to parse the destination CPU and copy the data to the corresponding PCIE space sending message queue; pre-fetches the packet header data from each PCIE space receiving message queue to parse the destination partition and copy the data to the receiving queue of small packet data and the receiving linked list of large packet data in the corresponding partition buffer area.

[0032] Since the system's own copy function is slow, the Feiteng FT2000 chip is a processor based on the ARMv8-A architecture, so the NEON instructions of the ARM architecture are used to increase the copy speed. After testing, the speed of copying small packet data can be doubled on the same CPU and ten times across CPUs. Copying large packet data takes a long time due to the large data size, which affects the CPU execution time of the application. The PCIE channel management module can constrain the storage space address and length of the data packet with the partition buffer management module, so that the DMA technology can be used directly to complete the cross-CPU copy, thereby reducing CPU occupancy and giving more CPU time to the upper-level application. After testing, the speed of copying large packet data has not increased on the same CPU, but can be increased ten to one hundred times across CPUs. In addition, for a specific CPU architecture, the unique assembly instructions of the architecture can be used to increase the copy speed. Special note: In this example, 4 CPUs are used, of which CPU1 communicates with CPU2, CPU3 and CPU4 at the same time.

[0033] See also Figure 3 As shown, the workflow of the above configurable multi-partition multi-task based PCIE network communication middleware is as follows:

[0034] The first step is to complete the system initialization by the system initialization module;

[0035] In the second step, the system initialization module obtains the CPU and other device information;

[0036] In the third step, the system initialization module selects the corresponding configuration table for parsing;

[0037] Step 4: The system initialization module initializes the partition buffer area and PCIE space channel;

[0038] Step 5: The partition buffer management module is called by the partition application to complete the copying of application data to the sending partition buffer and the copying of the receiving partition buffer to the application;

[0039] Step 6: The PCIE channel management module forwards the sending partition buffer data to the PCIE sending channel and forwards the PCIE receiving channel data to the receiving partition buffer;

[0040] Step 7: Determine whether the current sending partition buffer and PCIE receiving channel data are empty. If they are empty, wait and jump to step 7; if they are not empty, jump to step 6.

[0041] It is understandable that those skilled in the art can make equivalent substitutions or changes based on the technical solution and inventive concept of the present invention, and all these changes or substitutions should fall within the protection scope of the claims attached to the present invention.

Claims

1. A configurable multi-partition and multi-task based PCIE network communication middleware, comprising a system initialization module, a partition buffer management module, and a PCIE channel management module, characterized in that: The system initialization module is used to complete initialization, obtain configuration data and parse it, and initialize the partition buffer size and the number and size of PCIE space channels according to the parsed configuration data; The partition cache management module is used to manage the partition cache, complete the data copy from the upper application buffer to the partition cache, and the data copy from the partition cache to the upper application buffer; The PCIE channel management module is used to manage the transceiver channels of the PCIE space channel, and complete the copying from the partition buffer area to the PCIE space channel and from the PCIE space channel to the partition buffer area.

2. A configurable multi-partition and multi-tasking based PCIE network communication middleware according to claim 1, characterized in that When the partition buffer management module is called by the upper partition application to send packet data, the application data is copied from the application buffer to the sending partition buffer; When called by the upper-level partition application to receive small packet data, the application data is copied from the receiving partition cache to the application buffer; when called by the upper-level partition application to send large packet data, a large packet data space is requested in the sending partition cache sending linked list and returned to the upper-level partition, and the sending of the large packet data is completed by the upper-level partition application, and the large packet data space in the sending partition cache is marked as waiting to be sent; when called by the upper-level partition application to receive large packet data, a packet of receiving large packet data space is obtained in the receiving partition cache receiving linked list and returned to the partition application, and the receiving of the large packet data is completed by the upper-level partition, and the large packet data space in the receiving partition cache is released as free space.

3. A configurable multi-partition and multi-tasking based PCIE network communication middleware according to claim 2, characterized in that The PCIE space channel uses message queues to transmit both small and large packet data. The PCIE channel management module pre-fetches the packet header data from the sending queue of small packet data and the sending linked list of large packet data to parse the destination CPU and copy the data to the corresponding PCIE space sending message queue; The message queues received from each PCIE space pre-fetch the packet header data to parse the destination partition and copy the data to the receiving queue for small packet data and the receiving linked list for large packet data in the corresponding partition buffer area.

4. According to the configurable multi-partition multi-tasking PCIE network communication middleware described in claim 3, the PCIE channel management module uses the NEON instruction of the ARM architecture to copy small packet data; the PCIE channel management module and the partition buffer management module constrain the storage space address and length of the data packet, thereby using DMA technology to complete the large packet data copy; for a specific CPU architecture, the PCIE channel management module uses the assembly instruction copy unique to the architecture.

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