Energy-saving high-speed clock transmission device and method

Abstract

The invention provides an energy-saving high-speed clock transmission device and method. A clock transfer circuit includes: a voltage-to-current converter to convert a first clock into a first current; the main transmission line is used for transmitting the first current into second current; the transformer comprises a primary inductor and a secondary inductor, and is used for converting a second current received by the primary inductor into a second clock output by the secondary inductor; the tuning capacitor is used for forming resonance with the secondary inductor; and the regeneration network is connected with the secondary inductor and is used for providing negative resistance to enhance resonance.

Description

Technical Field

[0001] The present disclosure relates to clock transmission, and more particularly to energy-saving high-speed clock transmission. Background Art

[0002] A clock is a voltage signal that oscillates between a low level and a high level. Clocks are widely used in synchronous digital circuits to coordinate the operation of synchronous digital circuits. An integrated circuit containing several synchronous digital circuits usually has a clock generation circuit (such as a phase-locked loop) to generate the clock. The clock usually needs to be transmitted to the several synchronous digital circuits through a transmission line to coordinate their operation. If the physical distance between the clock generation circuit and the synchronous digital circuits that need to receive the clock from the clock generation circuit is very long, it may be difficult to transmit the clock. Long-distance transmission of the clock usually produces a large loss, resulting in a weak signal at the receiving end. In particular, if the clock is a high-speed clock, this problem will be more serious because the insertion loss of the transmission line will increase with the increase of the frequency of the transmitted signal. In some cases, the receiving end has several local circuits that all need clocks, but the physical distance between them is short.

[0003] In the case of US Patent Publication No. 11269371, a clock transmission circuit is described, which uses a current buffer to provide low impedance at the end of the transmission line to enable current mode clock transmission. The disclosed clock transmission circuit can effectively reduce the insertion loss of the transmission line, but the current buffer needs to consume a lot of power to provide low impedance.

[0004] What those skilled in the art desire is a method for transmitting a high-speed clock over a long transmission line in an energy-efficient manner. Summary of the invention

[0005] An object of the present invention is to provide a clock transmission circuit that can transmit a high-speed clock from a remote transmitter to a local receiver through a transmission line in an energy-saving manner without causing a large insertion loss in the transmission line.

[0006] Another object of the present invention is to provide a clock transmission circuit that can transmit a high-speed clock from a remote transmitter to a plurality of local receivers through a transmission line and a plurality of capacitive drive conductors in an energy-saving manner without causing a large insertion loss in the transmission line.

[0007] In one embodiment, the clock transmission circuit includes: a voltage-current converter for converting a first clock into a first current; a main transmission line for transmitting the first current into a second current; a transformer including a primary inductor and a secondary inductor, and for converting a second current received through the primary inductor into a second clock output through the secondary inductor; a tuning capacitor for forming a resonant network with the secondary inductor; and a regeneration network connected to the resonant network and used to provide a negative resistance to enhance the resonance of the resonant network. In another embodiment, the clock transmission circuit also includes: a first capacitive driving wire for driving the second clock into a third clock; and a first self-biased inverter for receiving the third clock and outputting a fourth clock. In yet another embodiment, the clock transmission circuit also includes: a second capacitive driving wire for driving the second clock into a fifth clock; and a second self-biased inverter for receiving the fifth clock and outputting a sixth clock.

[0008] In one embodiment, the clock transmission method includes: using a voltage-current converter to convert a first clock into a first current; using a main transmission line to transfer the first current into a second current; using a transformer including a primary inductor and a secondary inductor to convert the second current received through the primary inductor into a second clock output through the secondary inductor; using a tuning capacitor to resonate with the secondary inductor; and using a regenerative network to enhance the resonance. In one embodiment, the clock transmission method also includes: using a first capacitive drive wire to transfer the second clock into a third clock; using a first self-biased inverter to amplify the third clock into a fourth clock; using a second capacitive drive wire to transfer the second clock into a fifth clock; using a second self-biased inverter to amplify the fifth clock into a sixth clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A schematic diagram of a clock transmission circuit according to an embodiment of the present invention is shown.

[0010] Figure 2 The present invention is shown according to an embodiment of the present invention. Figure 1 Top view of the layout of the transformer in the clock transmission circuit.

[0011] Figure 3 A flow chart of a clock transmission method according to an embodiment of the present invention is shown.

[0012] Explanation of symbols

[0013] 100: Clock transmission circuit

[0014] V1: First Clock

[0015] V 1+ 、V 1-:Voltage

[0016] 110: Voltage-to-current converter (V2I)

[0017] I1: First current

[0018] I'1: Current

[0019] TL: Main Transmission Line

[0020] I2: Second current

[0021] TXF: Transformer

[0022] L1: primary inductance

[0023] L2: Secondary inductor

[0024] TC: Tuning capacitor

[0025] 120: Resonant Network

[0026] RN: Regeneration Network

[0027] V2: Second Clock

[0028] V 2+ 、V 2- :Voltage

[0029] BUF1: First buffer

[0030] BUF2: Second buffer

[0031] V7: Seventh Clock

[0032] V 7+ 、V 7- :Voltage

[0033] V8: Eighth Clock

[0034] V 8+ 、V 8- :Voltage

[0035] CDW1: First capacitive drive wire

[0036] AC1: The first AC coupling capacitor

[0037] W1: First wire

[0038] CDW2: Second capacitive drive wire

[0039] AC2: Second AC coupling capacitor

[0040] W2: Second wire

[0041] V3: Third Clock

[0042] V 3+ 、V 3- :Voltage

[0043] V5: The Fifth Clock

[0044] V 5+ 、V 5- :Voltage

[0045] SBI1: First self-biased inverter

[0046] SBI2: Second self-biased inverter

[0047] V4: Fourth Clock

[0048] V 4+ 、V 4- :Voltage

[0049] V6: Sixth Clock

[0050] V 6+ 、V 6- :Voltage

[0051] M1: First metal layer

[0052] M2: Second metal layer

[0053] via: path layer

[0054] L1_1: Left foot

[0055] L1_2: Left access

[0056] L1_3: Single-turn loop

[0057] L1_4: Right access

[0058] L1_5: Right foot

[0059] L2_1: Single-turn half loop

[0060] L2_2: Upper path

[0061] L2_3: Staggered routing

[0062] L2_4: Lower passage

[0063] L2_5: Half-turn loop

[0064] 310~390: Steps DETAILED DESCRIPTION

[0065] The present disclosure relates to clock transmission. Although the specification describes several embodiments of the present disclosure, and these embodiments are considered to be preferred ways of implementing the present invention. However, it should be understood that the present invention can be implemented in many ways and is not limited to the specific examples described below, or to the specific ways of implementing any features of these examples. In other cases, well-known details are not shown or described to avoid obscuring aspects of the present disclosure.

[0066] Those skilled in the art can understand the terms and basic concepts related to microelectronics used in this document, such as "voltage", "current", "clock", "transmission line", "transformer", "capacitor", "inductor", "resistor", "resonance", "resonant network", "frequency", "impedance", "via", "inverter", "AC", "AC coupling" and "cross-coupling". Such terms are used in the context of microelectronics, and the related concepts are obvious to those skilled in the art, so they are not explained in detail here.

[0067] A person skilled in the art can recognize symbols for capacitors, inductors, inverters, and transmission lines. A person skilled in the art can read schematic diagrams of circuits containing components and devices, such as capacitors, inductors, resistors, and inverters, without the need for a redundant description of how one component in the schematic diagram is connected to another component.

[0068] The present disclosure is expressed in the terms of engineering concepts. For example, with respect to two variables X and Y, when it is mentioned that "X is equal to Y", it means "X is approximately equal to Y", that is, "the difference between X and Y is less than a specific engineering error"; when it is mentioned that "X is zero", it means "X is approximately zero", that is, "X is less than a specific engineering error"; when it is mentioned that "X is substantially smaller than Y", it means "X is negligible with respect to Y", that is, "the ratio between X and Y is less than an engineering error, so X is negligible compared to Y".

[0069] In the present disclosure, a signal is a voltage with a variable level, which carries information and can change over time. The level of a signal at a certain moment represents the state of the signal at that moment.

[0070] A logic signal is a voltage signal with two states, a low state and a high state. The low state is also called the "0" state, and the high state is also called the "1" state. Regarding the logic signal Q, when we say "Q is high" or "Q is low", it means "Q is in a high state" or "Q is in a low state". Similarly, when we say "Q is 1" or "Q is 0", it means "Q is in a 1 state" or "Q is in a 0 state".

[0071] When a logic signal switches from a low level to a high level, the logic signal undergoes a transition from a low level to a high level. When a logic signal switches from a high level to a low level, the logic signal undergoes a transition from a high level to a low level.

[0072] If the first logic signal and the second logic signal are always in opposite states, it means that the first logic signal is the logical inversion of the second logic signal. That is to say, when the first logic signal is 0 (or low level), the second logic signal is 1 (or high level); when the first logic signal is 1 (or high level), the second logic signal is 0 (or low level). When the first logic signal is the logical inversion of the second logic signal, it means that the first logic signal and the second logic signal are complementary.

[0073] A clock is a logic signal that periodically switches between a low state and a high state.

[0074] A circuit is a collection of transistors, resistors, inductors, capacitors and / or other electronic devices interconnected in a specific way to achieve a specific function.

[0075] An inductor includes an electrical conduction path, which is usually implemented by a metal wire (or trace) through which current flows and excites a magnetic field. An inductor is usually implemented by a metal wire (or trace), which is a loop structure configured with two open ends, including a first end and a second end, wherein current can flow from the first end to the second end.

[0076] An inverter is a circuit that takes an input signal and produces an output signal that is the inverse of the input signal. An inverter can act as an amplifier because it can make the output signal have a larger swing and / or switch faster than the input signal. When the output of the inverter is connected to a low impedance node, the inverter can also act as a voltage-to-current converter, in which case the output current is the focus, not the output voltage.

[0077] A “self-biased inverter” is an inverter that has a feedback resistor connected between its input and output to form negative feedback and establish a DC voltage between the input and output signals.

[0078] As used herein, a "buffer" is a circuit that receives an input signal and outputs an output signal such that the output signal is the same logic as the input signal (in the case of a non-inverting buffer) or the output signal is the inverse of the input signal (in the case of an inverting buffer) but has a larger swing or faster transitions. An inverter can be used as an inverting buffer.

[0079] In this article, differential signaling schemes are widely used. When implemented with differential signaling schemes, the signal includes two voltages, suffixed with "+" and "-" and represented by subscripts, and the two voltages are complementary. For example, in the differential signaling embodiment, the signal V x Contains two voltages V x+ and V x- , where the two voltages V x+ and V x- Complement each other.

[0080] Reference Figure 1 , showing a schematic diagram of a clock transmission circuit 100 according to an embodiment of the present invention. The clock transmission circuit 100 includes a voltage-to-current converter (V2I) 110 for converting a first clock V1 (which includes two voltages V 1+ and V 1- ) is converted into a first current I1; a main transmission line TL is used to transfer the first current I1 into a second current I2; a transformer TXF includes a primary inductor L1 and a secondary inductor L2, and is used to convert the second current I2 received through the primary inductor L1 into a second clock V2 (which includes two voltages V 2+ and V 2- ); a tuning capacitor TC connected in parallel with the secondary inductor L2 to form a resonant network 120; and a regeneration network RN connected to the resonant network 120. The second clock V2 is an output clock that can be used by an adjacent subsequent circuit (not shown).

[0081] In another embodiment, the second clock V2 needs to be transmitted to the first local receiver. The clock transmission circuit 100 further includes: a first capacitive driving wire CDW1, which is used to directly or indirectly receive the second clock V2 through a first buffer BUF1 that can be used as appropriate, and output a third clock V3 (which includes two voltages V 3+ and V 3- ); and a first self-biased inverter SBI1, for receiving a third clock V3 and outputting a fourth clock V4 (which includes two voltages V 4+ and V 4- ).

[0082] In another embodiment, the second clock V2 also needs to be transmitted to a second local receiver. The clock transmission circuit 100 further includes: a second capacitive driving wire CDW2, which is used to directly or indirectly receive the second clock V2 through a second buffer BUF2 that can be used as appropriate, and output a fifth clock V5 (which includes two voltages V 5+ and V 5- ); and a second self-biased inverter SBI2, for receiving the fifth clock V5 and outputting the sixth clock V6 (which includes two voltages V 6+ and V 6- ).

[0083] The voltage-to-current converter 110 performs a voltage-to-current conversion function and is implemented by, for example but not limited to, two inverters, one of which receives a voltage V 1+ And output the first current I1, the other of the two inverters receives the voltage V 1- And output current I'1, which is the logical inversion of the first current I1 and is therefore complementary to the first current I1. In this implementation of the current mode transmission scheme, the transformer TXF presents a low impedance at the terminal of the main transmission line TL, so that the first current I1 is delivered as the second current I2 and easily flows into the primary inductor L1. The current mode transmission scheme has the advantage of low loss, because the insertion loss of the main transmission line TL mainly causes voltage drop (rather than current loss), and voltage drop is not a problem in the current mode transmission scheme, because the current mode transmission scheme focuses on current rather than voltage. The main transmission line TL transfers the first current I1 to the second current I2, because the main transmission line TL provides a conduction path for the first current I1 to flow, and finally becomes the second current I2 with minimal loss.

[0084] In one embodiment, the primary inductor L1 and the secondary inductor L2 are both spiral structures, which are arranged in a co-located manner (e.g., stacked or interleaved) in very close proximity to have strong mutual coupling. In order to make the transformer TXF present a low impedance (viewed from the primary inductor L1 at the terminal of the main transmission line TL), the number of turns of the secondary inductor L2 is greater than the number of turns of the primary inductor L1.

[0085] In one embodiment, the clock transmission circuit 100 is integrated and manufactured on a substrate using a multi-layer process technology, and the multi-layer process technology includes a first metal layer M1, a second metal layer M2, and a "path" layer via, and the path layer via is used to provide a metal layer connection between the first metal layer M1 and the second metal layer M2. In one embodiment, for example but not limited to, the primary inductor L1 is a single-turn inductor, the secondary inductor L2 is a double-turn inductor, and the impedance conversion ratio of the transformer TXF is approximately 1:4.

[0086] Reference Figure 2 , showing the present invention according to an embodiment (for Figure 1 1 is a top view of the layout of the transformer TXF in the clock transmission circuit 100. As shown in the figure, the primary inductor L1 includes a left leg L1_1 arranged on the second metal layer M2, a left path L1_2, a single-turn loop L1_3 arranged on the first metal layer M1, a right path L1_4, and a right leg L1_5 arranged on the second metal layer M2. The secondary inductor L2 includes a one-and-half turn loop (one-turn and half loop) L2_1 arranged on the first metal layer M1, an upper path L2_2, an interlaced trace L2_3 arranged on the second metal layer M2, a lower path L2_4, and a half-turn loop L2_5 arranged on the first metal layer M1. It is obvious that the primary inductor L1 is a single turn, the secondary inductor L2 is a double turn, and there is a strong coupling between the primary inductor L1 and the secondary inductor L2 because they are arranged in an interlaced structure in a co-located manner.

[0087] In an alternative embodiment (not shown but obvious to a person skilled in the art), the primary inductor L1 and the secondary inductor L2 are arranged in a stacked structure, wherein a portion of the secondary inductor L2 is arranged on the second metal layer M2 and stacked on a portion of the primary inductor L1, and the portion of the primary inductor L1 is arranged on the first metal layer M1. Both the "staggered" and "stacked" structures are used in the prior art to implement the transformer TXF, and thus will not be described in detail herein.

[0088] The tuning capacitor TC is used to resonate with the secondary inductor L2, and the resonant frequency is approximately equal to the frequency of the second clock V2 (which is the same as the frequency of the first clock V1), so that the second clock V2 can have a larger swing due to the resonance. The regeneration network RN provides a negative resistance to enhance the resonance between the secondary inductor L2 and the tuning capacitor TC, and thereby increase the swing of the second clock V2. In one embodiment, the regeneration network RN includes two interactively coupled inverters, which establish positive feedback of regenerative properties. Those skilled in the art understand the concept of interactively coupled inverters and why they have regenerative properties and can form negative resistance, so they are not described in detail here.

[0089] The first buffer BUF1 may be used as appropriate and includes two inverters. The first buffer BUF1 is used to amplify the second clock V2 into a seventh clock V7 (which includes two voltages V 7+ and V 7- The second buffer BUF2 may also be used as appropriate and includes two inverters. The second buffer BUF2 is used to amplify the second clock V2 into an eighth clock V8 (which includes two voltages V 8+ and V 8-). When the first buffer BUF1 is not used (opted out), the seventh clock V7 will be the same as the second clock V2. When the second buffer BUF2 is not used, the eighth clock V8 will be the same as the second clock V2. The purpose of the first buffer BUF1 (the second buffer BUF2) is to provide isolation to prevent the first capacitive drive wire CDW1 (the second capacitive drive wire CDW2) from becoming a load of the resonant network 120.

[0090] The first capacitive driving wire CDW1 includes a first AC coupling capacitor AC1 and a first wire W1, and the first wire W1 is a local transmission line shorter than the main transmission line TL. The second capacitive driving wire CDW2 includes a second AC coupling capacitor AC2 and a second wire W2, and the second wire W2 is also a local transmission line shorter than the main transmission line TL. The first AC coupling capacitor AC1 (the second AC coupling capacitor AC2) has two purposes: the first purpose is to provide isolation of the DC voltage so that the subsequent circuit can establish the DC voltage by itself, and the subsequent circuit is the first self-biased inverter SBI1 (the second self-biased inverter SBI2); the second purpose is to reduce the capacitive load caused by the first wire W1 (the second wire W2) to the front circuit, wherein if the first buffer BUF1 (the second buffer BUF2) is adopted (opted in), the front circuit is the first buffer BUF1 (the second buffer BUF2), or if the first buffer BUF1 (the second buffer BUF2) is not adopted, the front circuit is the resonant network 120.

[0091] The first self-bias inverter SBI1 includes two inverters and two feedback resistors between their corresponding inputs and corresponding outputs. Similarly, the second self-bias inverter SBI2 includes two inverters and two feedback resistors between their corresponding inputs and corresponding outputs. The first self-bias inverter SBI1 and the second self-bias inverter SBI2 are both well known to those skilled in the art, and thus will not be described in detail herein.

[0092] The clock transmission circuit 100 has some advantages. The first advantage is that the transformer TXF presents a low impedance at the terminal of the main transmission line TL, so that the second current I2 can flow in more easily, thereby establishing current mode transmission, thereby reducing the insertion loss of the main transmission line TL, because the insertion loss of the main transmission line TL mainly produces a voltage drop rather than a current loss. In this way, the main transmission line TL transfers the first current I1 to the second current I2. However, unlike the clock transmission line circuit of the prior art recorded in the case of US Patent Publication No. 11269731, the clock transmission circuit 100 does not use a current buffer to achieve low impedance, so there is no need to consume a lot of power. The second advantage is that by making the number of turns of the secondary inductor L2 greater than the number of turns of the primary inductor L1, it will be easier for the second clock V2 to have a larger swing. The third advantage is that the transformer TXF itself provides DC isolation between the voltage-current converter 110 and the resonant network 120, so that the voltage-current converter 110 and the resonant network 120 can independently establish a DC level.

[0093] Reference Figure 3 , showing a flow chart of a clock transmission method according to an embodiment of the present invention. The clock transmission method includes: using a voltage-current converter to convert a first clock into a first current (step 310); using a main transmission line to transfer the first current into a second current (step 320); using a transformer including a primary inductor and a secondary inductor to convert the second current received through the primary inductor into a second clock output through the secondary inductor (step 330); using a tuning capacitor to resonate with the secondary inductor (step 340); and using a regenerative network to enhance resonance (step 350). In a further embodiment, the method further includes: using a first capacitive drive wire to transfer the second clock into a third clock (step 360); using a first self-biased inverter to amplify the third clock into a fourth clock (step 370); using a second capacitive drive wire to transfer the second clock into a fifth clock (step 380); and using a second self-biased inverter to amplify the fifth clock into a sixth clock (step 390).

[0094] Those skilled in the art will readily appreciate that many modifications and variations can be made to the apparatus and method while retaining the teachings of the present disclosure. Therefore, the above content should not be interpreted as being limited only by the description of the attached claims.

Claims

1. A clock transmission circuit, comprising: a voltage-to-current converter, used for converting a first clock into a first current; a main transmission line, used to transfer the first current into a second current; a transformer, comprising a primary inductor and a secondary inductor, and used for converting the second current received by the primary inductor into a second clock output by the secondary inductor; a tuning capacitor, used to form a resonant network with the secondary inductor; and A regenerative network is connected to the resonant network and is used to provide a negative resistance to enhance the resonance of the resonant network.

2. The clock transmission circuit as described in claim 1 is integrated and manufactured on a substrate using a multi-layer process technology, and the multi-layer process technology includes a first metal layer, a second metal layer and a via layer, and the via layer is used to provide an inter-metal layer connection between the first metal layer and the second metal layer. 3 . The clock transmission circuit as claimed in claim 2 , wherein the primary inductor and the secondary inductor are both spiral structures, and the number of turns of the secondary inductor is greater than the number of turns of the primary inductor. 4 . The clock transmission circuit as claimed in claim 3 , wherein the primary inductor is a single turn and the secondary inductor is a double turn. 5 . The clock transmission circuit as claimed in claim 3 , wherein the primary inductor and the secondary inductor are arranged in a staggered structure, and the staggered structure includes a metal routing combination arranged on the first metal layer and the second metal layer. 6 . The clock transmission circuit as claimed in claim 3 , wherein the primary inductor and the secondary inductor are arranged in a stacked structure, and the stacked structure includes a metal routing combination arranged on the first metal layer and the second metal layer.

7. The clock transmission circuit according to claim 3, further comprising: a first capacitive driving conductor, for directly or indirectly receiving the second clock through a first buffer and outputting a third clock; and A first self-biased inverter is used to receive the third clock and output a fourth clock, wherein the first capacitive driving wire includes a first AC coupling capacitor and a first wire, and the first wire is a first local transmission line shorter than the main transmission line.

8. The clock transmission circuit according to claim 7, further comprising: a second capacitive driving conductor, for directly or indirectly receiving the second clock through a second buffer, and outputting a fifth clock; and A second self-biased inverter is used to receive the fifth clock and output a sixth clock, wherein the second capacitive driving wire includes a second AC coupling capacitor and a second wire, and the second wire is a second local transmission line shorter than the main transmission line.

9. The clock transmission circuit of claim 1, wherein the regeneration network comprises two cross-coupled inverters.

10. A clock transmission method, comprising: Using a voltage-to-current converter to convert a first clock into a first current; Using a main transmission line, the first current is transferred into a second current; Using a transformer including a primary inductor and a secondary inductor, the second current received by the primary inductor is converted into a second clock outputted through the secondary inductor; utilizing a tuning capacitor to resonate with the secondary inductor; and A regenerative network is used to enhance resonance.

Images