A synchronous triggering method, system, terminal and storage medium based on microinstructions

Abstract

The present application relates to a microinstruction-based synchronous triggering method, system, terminal and storage medium, and relates to the field of chip testing technology. The method includes: setting a trigger instruction in the register of each chip to be tested in the chipset to be tested, and the trigger instruction is used to adjust the pin voltage of the chip to be tested; sending a test instruction to the chipset to be tested, the test instruction carries a microinstruction, and the microinstruction is associated with the trigger instruction; when it is detected that the pin voltages of each chip to be tested in the chipset to be tested are all preset voltages, sending a synchronous test signal to the chipset to be tested; monitoring the pin voltage changes of the chipset to be tested; and obtaining the test results of the chipset to be tested according to the pin voltage changes. The present application has the effect of improving the synchronization of chip testing and reducing the memory of test instructions.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a microinstruction-based synchronous triggering method, system, terminal and storage medium. Background Art

[0002] Chip test synchronization refers to the time coordination and consistency between test signals, control signals and data streams during chip testing. Especially in complex integrated circuit and system chip testing, test synchronization is crucial to ensure that each module of the chip can work as expected. Chip synchronization testing involves multiple aspects, mainly including timing synchronization, data synchronization, clock synchronization, etc.

[0003] When sending test instructions, the related technology will add voltage control instructions for the pins in the test instructions. The chip will adjust the corresponding pin voltage according to the voltage control instructions, and the host computer will monitor the pin voltage in real time. When the host computer monitors that the pin voltage of all chips has become the preset voltage, the host computer will send instructions to the chip to control all chips to start testing synchronously.

[0004] With respect to the above-mentioned related technologies, the inventors believe that if the voltage control instruction is too long, a large amount of memory of the test instruction will be consumed, resulting in a reduction in the effective content of the test instruction and affecting the synchronization of the chip test. Summary of the invention

[0005] In order to improve chip test synchronization and reduce test instruction memory, the present application provides a microinstruction-based synchronization trigger method, system, terminal and storage medium.

[0006] In a first aspect, the present application provides a microinstruction-based synchronous triggering method, which adopts the following technical solution:

[0007] A synchronous triggering method based on microinstructions, comprising:

[0008] Setting a trigger instruction in a register of each chip under test in the chip group under test, wherein the trigger instruction is used to adjust the pin voltage of the chip under test;

[0009] Sending a test instruction to the chipset to be tested, wherein the test instruction carries a microinstruction, and the microinstruction is associated with the trigger instruction;

[0010] When it is detected that the pin voltages of the chips under test in the chips under test are all preset voltages, sending a synchronous test signal to the chips under test;

[0011] Monitoring the pin voltage changes of the chipset to be tested;

[0012] The test result of the chipset to be tested is obtained according to the change of the pin voltage.

[0013] By adopting the above technical solution, a trigger instruction is set in the register of the chip to be tested. When the chip to be tested is tested, a microinstruction is added to the test instruction. The trigger instruction in the register is triggered by the microinstruction. The pin voltage of the chip to be tested is controlled by the trigger instruction. When it is detected that the pin voltage of each chip to be tested is a preset voltage, each chip to be tested is tested, thereby improving the synchronization of chip testing. There is no need to add microinstructions to the test instructions, which can reduce the memory of the test instructions.

[0014] Optionally, when it is detected that the current pin voltage of the target chip under test in the chipset under test has not changed to the preset voltage within a preset time period, a detection signal is sent to the target chip under test, wherein the detection signal is used to query the type of trigger instruction stored in the register of the target chip under test;

[0015] Receiving a reply signal returned by the target chip under test;

[0016] Determine an update trigger signal of the target chip to be tested according to the reply signal;

[0017] The update trigger signal is sent to the target signal to be tested.

[0018] By adopting the above technical solution, when the current pin voltage of the target chip to be tested does not become the preset voltage within the preset time period, the update trigger signal in the target chip to be tested can be determined by the detection signal, and the update trigger signal can be sent to the target chip to be tested to update the trigger signal in the target chip to be tested, thereby ensuring that the target signal to be tested can stably output the trigger signal and ensure the synchronization of the chip test.

[0019] Optionally, when the number of the update trigger signals is greater than a preset number, determining a trigger timing of the update trigger signals;

[0020] Arrange the update trigger signals according to the trigger timing;

[0021] According to the timing intervals between adjacent update trigger signals, counting the first update trigger signal whose timing interval is greater than the preset interval time, and the second update trigger signal whose timing interval is less than the preset interval time;

[0022] The update trigger signals are sent in sequence according to the trigger timing, wherein the first update trigger signal is sent individually and the adjacent second update trigger signals are sent in a package.

[0023] By adopting the above technical solution, the sending method of the update trigger signal is set according to the timing interval between adjacent update trigger signals, and individual sending or package sending is selected to ensure that the update trigger signal can reach the target chip to be tested in time without affecting the normal test of the chip.

[0024] Optionally, calculating the volume of a compressed package of the second update trigger signal;

[0025] In the case where the volume of the compressed package is larger than the preset volume, a third update trigger signal is selected according to the timing sequence of the update trigger signal in the second update trigger signal, the third update trigger signal is located at the end of the second update trigger signal, and the volume of the compressed package of the second update trigger signal after removing the third update trigger signal is smaller than the preset volume;

[0026] In a case where the next update trigger signal of the third update trigger signal belongs to the first update trigger signal, packaging the third update trigger signal and the next update trigger signal for transmission;

[0027] In the case where the next update trigger signal of the third update trigger signal belongs to the second update trigger signal, the third update trigger signal is sent alone.

[0028] By adopting the above technical solution, the sending method of the third update trigger signal is adjusted according to the type of the next update trigger signal of the third update trigger signal, and the sending efficiency of the update signal is improved as much as possible while ensuring that the target chip under test can receive the third update trigger signal in time.

[0029] Optionally, in the absence of the update trigger signal, detecting whether the current pin voltage belongs to a preset voltage interval, the preset voltage interval corresponding to the trigger instruction;

[0030] If not, stop testing the target chip to be tested;

[0031] If so, a mapping relationship is generated according to the current pin voltage, the trigger instruction and the microinstruction; the mapping relationship is transformed into a repair signal; and the repair signal is sent to the target chip to be tested.

[0032] By adopting the above technical solution, a mapping relationship is generated according to the current pin voltage, trigger instructions and microinstructions, and the mapping relationship is transformed into a repair signal, so that the target chip under test can repair the mapping error inside the repair signal repairer.

[0033] Optionally, an identification instruction is added to the microinstruction, and the identification instruction is used to control the output level of the target pin to become a target level;

[0034] Detecting the target pin of the target chip to be tested;

[0035] In the case where it is detected that the output level of the target pin becomes the target level, detecting whether the pin voltage of the target chip to be tested meets the preset voltage;

[0036] If yes, continue testing the target chip to be tested;

[0037] If not, the test of the target chip to be tested is stopped.

[0038] By adopting the above technical solution, an identification instruction is added to the microinstruction to control the output level of a specific target pin to become the target level, detect whether the target chip to be tested can accept and accurately read the microinstruction, and thereby determine whether the target chip to be tested can continue to participate in the chip test. Optionally, obtain historical test records;

[0039] According to the current pin voltage, searching the historical test records for a target historical test record corresponding to the current pin voltage;

[0040] Extracting a solution from the target historical test record;

[0041] Performing clustering operation on the solution to obtain the current solution of the target chip to be tested;

[0042] The current solution is implemented.

[0043] By adopting the above technical solution, the current repair method of the target chip to be tested is determined through historical test records, so that the target chip to be tested can participate in the test normally.

[0044] In a second aspect, the present application provides a microinstruction-based synchronous trigger system, which adopts the following technical solution:

[0045] A microinstruction-based synchronous trigger system, comprising:

[0046] An acquisition module is used to acquire test instructions, preset voltages, pin voltage changes, reply signals, preset quantities, preset intervals, preset voltage ranges, and historical test records;

[0047] A memory, used to store a program of any one of the above-mentioned microinstruction-based synchronous triggering methods;

[0048] The program in the processor memory can be loaded and executed by the processor and implement any of the above-mentioned microinstruction-based synchronous triggering methods.

[0049] By adopting the above technical solution, a trigger instruction is set in the register of the chip to be tested. When the chip to be tested is tested, a microinstruction is added to the test instruction. The trigger instruction in the register is triggered by the microinstruction. The pin voltage of the chip to be tested is controlled by the trigger instruction. When it is detected that the pin voltage of each chip to be tested is a preset voltage, each chip to be tested is tested, thereby improving the synchronization of chip testing. There is no need to add microinstructions to the test instructions, which can reduce the memory of the test instructions.

[0050] In a third aspect, the present application provides a smart terminal, which adopts the following technical solution:

[0051] An intelligent terminal comprises a memory and a processor, wherein the memory stores a computer program which can be loaded by the processor and execute any one of the above methods.

[0052] In a fourth aspect, the present application provides a computer storage medium capable of storing corresponding programs, which is convenient for improving chip test synchronization and reducing test instruction memory, and adopts the following technical solutions:

[0053] A computer-readable storage medium stores a computer program that can be loaded by a processor and execute any of the above-mentioned microinstruction-based synchronization triggering methods.

[0054] In summary, the present application includes at least one of the following beneficial technical effects:

[0055] A trigger instruction is set in the register of the chip to be tested. When the chip to be tested is tested, a microinstruction is added to the test instruction. The microinstruction triggers the trigger instruction in the register. The pin voltage of the chip to be tested is controlled by the trigger instruction. When it is detected that the pin voltages of each chip to be tested are all preset voltages, each chip to be tested is tested, thereby improving the synchronization of chip testing. It is not necessary to add microinstructions to the test instruction, and the memory of the test instruction can be reduced.

[0056] When the current pin voltage of the target chip under test does not change to the preset voltage within the preset time, the update trigger signal in the target chip under test can be determined by the detection signal, and the update trigger signal is sent to the target chip under test to update the trigger signal in the target chip under test, so as to ensure that the target chip under test can stably output the trigger signal and ensure the synchronization of the chip test;

[0057] According to the timing interval between adjacent update trigger signals, set the sending mode of the update trigger signal, and choose to send it individually or in a package to ensure that the update trigger signal can reach the target chip under test in time without affecting the normal test of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1It is a flowchart of a microinstruction-based synchronization triggering method provided in an embodiment of the present application.

[0059] Figure 2 It is a flowchart of a trigger signal updating method provided in an embodiment of the present application.

[0060] Figure 3 This is a flow diagram of a method for sending an update trigger instruction provided in an embodiment of the present application. Figure 1 .

[0061] Figure 4 This is a flow diagram of a method for sending an update trigger instruction provided in an embodiment of the present application. Figure 2 .

[0062] Figure 5 It is a flow chart of a method for repairing a trigger signal provided in an embodiment of the present application.

[0063] Figure 6 It is a flowchart of a method for sending microinstructions provided in an embodiment of the present application.

[0064] Figure 7 It is a flow chart of a method for repairing a chip under test provided in an embodiment of the present application.

[0065] Figure 8 It is a structural diagram of a microinstruction-based synchronous trigger system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solutions and advantages of this application more clear, the following Figures 1 to 8 It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0067] The present application embodiment discloses a flow chart of a synchronous triggering method based on microinstructions. Figure 1 , the method comprising:

[0068] Step S101: setting a trigger instruction in a register of each chip under test in the chip group under test, wherein the trigger instruction is used to adjust the pin voltage of the chip under test.

[0069] Exemplarily, the trigger instruction is a pin voltage control instruction, and the trigger instruction can control a specific pin on the chip to be tested to output a specific voltage.

[0070] The registers in the chip under test are used to store various control signals.

[0071] In some embodiments, each chip under test in the chip group under test needs to be connected to the same host computer, and the host computer sends a trigger instruction to each chip under test in the chip group under test. After receiving the trigger instruction, the chip under test stores the trigger instruction in a register.

[0072] Step S102: Send a test instruction to the chipset to be tested, the test instruction carries a microinstruction, and the microinstruction is associated with a trigger instruction.

[0073] Microinstructions are used to trigger instructions in trigger registers.

[0074] The test instruction is a control signal for the high and low levels of each pin on the chip to be tested. In chip testing, the test instruction will instruct the pin of the chip to be tested to output a specific level to determine whether the function of the chip to be tested is normal. Microinstructions are some special state instructions. In the embodiment of the present application, microinstructions are used to select and trigger the corresponding trigger instruction in the register.

[0075] Optionally, a plurality of different trigger instructions may be stored in the register, and different trigger instructions correspond to different microinstructions. Exemplarily, an identification bit is set on the trigger instruction, and the microinstruction consists of an instruction body and an identification bit. After receiving the microinstruction, the chip under test will determine that the function of the microinstruction is to trigger the trigger instruction in the register based on the instruction body, and will determine the trigger instruction corresponding to the microinstruction in the register based on the identification bit, and then output and execute the trigger instruction.

[0076] Step S103: When it is detected that the pin voltages of the chips under test in the chips under test are all preset voltages, a synchronous test signal is sent to the chips under test.

[0077] Exemplarily, a host computer connected to the chipset to be tested may monitor the pin voltage of each chip to be tested in real time.

[0078] When it is detected that the pin voltages of each chip under test in the chipset under test are all preset voltages, it means that each chip under test in the chipset under test is ready for synchronous testing and can start synchronous testing.

[0079] The synchronous test signal is used to instruct the chip under test to execute the test instruction.

[0080] In some embodiments, the synchronous test signal also includes a clock signal. After the signal to be tested receives the synchronous test signal, the clock signal is extracted therein and the clock signal is used to synchronize its own clock.

[0081] In some embodiments, the synchronous test signal also includes a test start time, which is used to set a time for the test chip to start testing. When the clock in the chip to be tested reaches the test start time, the chip to be tested starts executing the test instruction.

[0082] Step S104: monitoring the voltage change of the pins of the chipset to be tested.

[0083] The pin voltage change refers to the change of the pin voltage of each chip under test in the chipset under test over time. For example, the host computer connected to the chipset under test records the pin voltage of the chipset under test within a specific time period and organizes it into pin voltage change. It should be noted that the pin voltage change records the pin voltage of all chips under test.

[0084] Step S105: obtaining the test result of the chipset to be tested according to the change of the pin voltage.

[0085] Exemplarily, if the pin voltage change is consistent with the preset voltage change, the chipset under test is considered to have passed the test. Exemplarily, if the pin voltage change is inconsistent with the preset voltage change, the chipset under test is considered to have failed the test.

[0086] Furthermore, since this embodiment involves chip synchronization testing, the pin voltage of each chip to be tested needs to be synchronized, that is, when the pin voltage changes, the time difference of the pin voltage change of all chips to be tested needs to be smaller than the preset time difference.

[0087] To summarize, a trigger instruction is set in the register of the chip to be tested. When the chip to be tested is tested, a microinstruction is added to the test instruction. The trigger instruction in the register is triggered by the microinstruction. The pin voltage of the chip to be tested is controlled by the trigger instruction. When it is detected that the pin voltage of each chip to be tested is a preset voltage, each chip to be tested is tested, thereby improving the synchronization of chip testing. There is no need to add microinstructions to the test instruction, and the memory of the test instruction can be reduced.

[0088] In the following embodiments, when testing the signal to be tested, the pin voltage of some chips to be tested may not reach the preset voltage within the preset time. This may be because the chip to be tested did not write the trigger signal into the register, or the chip to be tested wrote an erroneous trigger instruction into the register. Therefore, the embodiment of the present application discloses a flow chart of a method for updating a trigger signal. Figure 2 , the method comprising:

[0089] Step S201: When it is detected that the current pin voltage of the target chip under test in the chipset under test does not become the preset voltage within the preset time, a detection signal is sent to the target chip under test, and the detection signal is used to query the trigger instruction type stored in the register of the target chip under test.

[0090] The preset duration is a preset empirical value. The embodiment of the present application does not specifically limit the value of the preset duration. For example, the preset time may be 1s or 2s.

[0091] Exemplarily, when an identification bit is set on the trigger signal, the detection signal will carry the identification bits of all trigger signals. The signal to be tested can be compared with each trigger instruction in the register using the identification bit in the detection signal to determine the trigger instruction missing in the register or the trigger instruction in which an error occurs. For example, the identification bits in the detection signal include 1, 2, 3, and 4, and the identification bits corresponding to the trigger signal in the register of the target chip to be tested include 1, 3, and 5. It can be determined that the target chip to be tested lacks the trigger signal corresponding to identification bits 2 and 4, and the trigger instruction corresponding to identifier 5 is a redundant trigger instruction.

[0092] Furthermore, when the target chip under test determines redundant trigger signals in the register through the detection signal, the redundant trigger signals can be deleted.

[0093] In some embodiments, after receiving the detection signal, the target signal to be tested can also use the detection signal to retrieve its own storage space to obtain all trigger signals stored in its storage space. If a trigger instruction missing from the register is retrieved in the storage space, the aforementioned trigger instruction is added to the register. The storage space includes at least one of a cache, a main memory, a system memory, a first-in first-out storage, and a flash memory.

[0094] Step S202: receiving a response signal returned by the target chip under test.

[0095] Optionally, the reply signal is used to indicate the missing trigger signal in the register of the target chip under test. Exemplarily, the reply signal includes an identification bit corresponding to the missing trigger signal.

[0096] In some embodiments, when the target chip under test reads and executes a trigger signal, an error signal is generated, causing the target chip under test to be unable to normally execute the trigger signal, and the identification bit corresponding to the trigger signal is also written into the reply signal.

[0097] Step S203: determining an update trigger signal of the target chip under test according to the reply signal.

[0098] The update trigger signal refers to a trigger signal that is missing from the target chip under test, or a trigger signal that reports an error in the target chip under test.

[0099] Step S204: sending an update trigger signal to the target signal to be tested.

[0100] Optionally, the host computer may send the update trigger signal to the target chip under test separately, or may package the update trigger signal and send it to the target chip under test.

[0101] To sum up, when the current pin voltage of the target chip to be tested does not change to the preset voltage within the preset time, the update trigger signal in the target chip to be tested can be determined by the detection signal, and the update trigger signal can be sent to the target chip to be tested to update the trigger signal in the target chip to be tested, thereby ensuring that the target signal to be tested can stably output the trigger signal and ensure the synchronization of the chip test.

[0102] In the following embodiments, the trigger signal itself is a voltage control instruction, so its length is long, which will affect the transmission efficiency. When the target chip under test requires too many update trigger signals, it will affect the transmission efficiency of the update trigger signal, extend the transmission time, and affect the normal test of the entire chip group under test. Therefore, the embodiment of the present application discloses a flow diagram of a method for sending an update trigger instruction. Figure 1 . Reference Figure 3 , the method comprising:

[0103] Step S301: when the number of update trigger signals is greater than a preset number, determining a triggering timing of the update trigger signal.

[0104] The preset number is a preset number value. This application does not specifically limit the value of the preset number.

[0105] The trigger timing refers to the order in which the trigger signals are executed, and the trigger timing is preset. In some embodiments, relevant personnel often need to perform various tests on the same set of chipsets to be tested. To ensure the accuracy of the test, each test must be resynchronized using different trigger signals to avoid the accidental nature of the test. For example, the first test is to test whether the function of the chipset to be tested can be performed normally, and trigger signal 1 is used for synchronization; the second test is to test whether the electrical performance of the chipset to be tested meets the standards, and trigger signal 2 is used for synchronization.

[0106] In another embodiment, when the total signal length of the update trigger signal is greater than a preset signal length, the trigger timing of the update trigger signal is determined.

[0107] Step S302: Update the trigger signal according to the trigger timing sequence.

[0108] Exemplarily, the update trigger signals are arranged from first to last according to the trigger timing, that is, the update trigger signal that is executed first is arranged in front.

[0109] Step S303: according to the timing intervals between adjacent update trigger signals, count the first update trigger signals whose timing intervals are greater than the preset interval time, and the second update trigger signals whose timing intervals are less than the preset interval time.

[0110] The preset interval time is a preset empirical value. The embodiment of the present application does not specifically limit the value of the preset interval time. Further, the preset interval time is positively correlated with the time required to send the update trigger signal.

[0111] The timing interval is determined based on the predicted duration of the test, and the timing interval is greater than the predicted duration of the test corresponding to the previous update trigger signal. For example, update trigger signal 1 and update trigger signal 2 are adjacent update trigger signals, update trigger signal 1 corresponds to the functional test of the chip, the duration of the functional test is predicted to be 20s, and update trigger signal 2 corresponds to the reliability test of the chip, then the timing interval between update trigger signal 1 and update trigger signal 2 needs to be greater than 20s.

[0112] Optionally, if the timing interval between a certain update trigger signal and an adjacent update trigger signal on one side is greater than a preset interval, and the timing interval between the update trigger signal and an adjacent update trigger signal on the other side is less than the preset interval, then the update trigger signal is a second update trigger signal.

[0113] Exemplarily, the update trigger signals include A, B, C, and D according to the trigger timing. The timing interval between A and B is greater than the preset interval time, the timing interval between B and C is less than the preset interval time, and the timing interval between C and D is greater than the preset interval time. Then A is the first update trigger signal, B is the second update trigger signal, C is the second update trigger signal, and D is the first update trigger signal.

[0114] Step S304: sending update trigger signals in sequence according to the triggering sequence, wherein the first update trigger signal is sent individually and the adjacent second update trigger signal is sent in a package.

[0115] Since the timing interval between the second update trigger signal and the adjacent update trigger signal is less than the preset interval time, if the adjacent second update trigger signal is sent separately, it may result in that the second update trigger signal has not yet entered the target chip under test, but the target test chip has completed the current test, resulting in the target test chip being unable to synchronize the next test in time, affecting the test of the entire chip group under test. However, sending the first update trigger signal separately will not cause this problem, and sending it separately can reduce the data processing amount of the target chip under test, ensuring that the target chip under test can process the test instructions normally.

[0116] Exemplarily, the update trigger signal includes A, B, C, and D according to the trigger timing, wherein A is the first update trigger signal, B is the second update trigger signal, C is the second update trigger signal, and D is the first update trigger signal. Then A and D are sent separately, and B and C need to be packaged together and sent.

[0117] In summary, according to the timing interval between adjacent update trigger signals, the sending mode of the update trigger signal is set, and individual sending or package sending is selected to ensure that the update trigger signal can reach the target chip under test in time without affecting the normal test of the chip.

[0118] In the following embodiment, if the size of the compressed package when sending the second update trigger instruction is too large, it will also affect the efficiency of sending the update signal. Figure 2 . Reference Figure 4 , the method comprising:

[0119] Step S401: Calculate the volume of the compressed package of the second update trigger signal.

[0120] The compressed package volume refers to the space occupied by the packaged second update trigger signal on the storage medium.

[0121] Step S402: When the compressed package volume is larger than the preset volume, the third update trigger signal is selected according to the timing sequence of the update trigger signal in the second update trigger signal. The third update trigger signal is located at the end of the second update trigger signal, and the compressed package volume of the second update trigger signal after removing the third update trigger signal is smaller than the preset volume.

[0122] The preset volume is a preset empirical value. The embodiment of the present application does not specifically limit the value of the preset volume.

[0123] Exemplarily, the second update trigger signal includes adjacent A, B, and C, and the compressed package volume of A, B, and C after packaging is larger than the preset volume, but the compressed package volume of A and B after packaging is smaller than the preset volume, then C is regarded as the third trigger signal.

[0124] In some other embodiments, the third update trigger signal is located at the head end of the second update trigger signal, and the volume of the compressed package of the second update trigger signal after removing the third update trigger signal is smaller than a preset volume.

[0125] Step S403: When the next update trigger signal of the third update trigger signal belongs to the first update trigger signal, the third update trigger signal and the next update trigger signal are packaged and sent.

[0126] The next update trigger signal of the third update trigger signal refers to an update trigger signal that is located after the third update trigger signal in terms of trigger timing.

[0127] Exemplarily, when the next update trigger signal of the third update trigger signal belongs to the first update trigger signal, the third update trigger signal is not suitable to be packaged and sent together with its adjacent update trigger signal, and the first update trigger signal itself is sent alone. Therefore, the third update trigger signal is packaged and sent with the next update trigger signal, and the impact on the sending efficiency of the update trigger signal is small.

[0128] Step S404: When the next update trigger signal of the third update trigger signal belongs to the second update trigger signal, send the third update trigger signal alone.

[0129] Exemplarily, when the next update trigger signal of the third update trigger signal belongs to the second update trigger signal, the third update trigger signal is not suitable to be packaged and sent together with its adjacent update trigger signal, while the second update trigger signal needs to be packaged and sent. Therefore, it is not suitable to package the third update trigger signal and the next update trigger signal to be sent, otherwise it will have a great impact on the sending efficiency of the update trigger signal. Therefore, the third update trigger signal is sent separately.

[0130] In summary, the sending mode of the third update trigger signal is adjusted according to the type of the next update trigger signal of the third update trigger signal, so as to improve the sending efficiency of the update signal as much as possible while ensuring that the target chip under test can receive the third update trigger signal in time.

[0131] In the following embodiment, when the reply signal returned by the target chip under test does not indicate any update trigger signal, the trigger instruction and microinstruction in the target chip under test are likely to be wrong, resulting in the target chip under test not outputting the correct pin voltage. Therefore, the embodiment of the present application discloses a flow chart of a method for repairing a trigger signal. Figure 5 , the method comprising:

[0132] Step S501: In the absence of an update trigger signal, detecting whether the current pin voltage belongs to a preset voltage range, the preset voltage range corresponding to the trigger instruction.

[0133] If the current pin voltage belongs to the preset voltage range, then execute step S503 to step S505;

[0134] If the current pin voltage belongs to the preset voltage range, step S502 is executed.

[0135] Exemplarily, after obtaining the reply signal, if the reply signal does not indicate any update trigger signal, it is considered that there is no update trigger signal.

[0136] The preset voltage range refers to the pin voltage after the chip under test executes the trigger instruction.

[0137] Exemplarily, a trigger signal A and a trigger signal B are set in the register of the target chip to be tested, and the preset voltage interval includes the pin voltage corresponding to the trigger signal A and the pin voltage corresponding to the trigger signal B.

[0138] Step S502: If not, stop testing the target chip to be tested.

[0139] If the current pin voltage does not belong to the preset voltage range, it means that the target test range does not execute any trigger instruction in the register. At this time, there is a problem with the target test chip itself, so the test of the target test chip is stopped.

[0140] Step S503: If yes, a mapping relationship is generated according to the current pin voltage, the trigger instruction and the microinstruction.

[0141] If the current pin voltage belongs to the preset voltage range, it means that the target chip under test executes a trigger instruction in the register, but the target chip under test does not execute the specified trigger instruction. In this case, the target chip under test executes the wrong trigger instruction according to the microinstruction in the test instruction. The reason for this is most likely that there is an error in the correspondence between the microinstruction and the trigger instruction.

[0142] The mapping relationship refers to the mapping from microinstructions to trigger instructions and current pin voltage.

[0143] Step S504: transform the mapping relationship into a repair signal.

[0144] Exemplarily, the mapping relationship is transformed into a repair signal through signal processing technology.

[0145] Step S505: Send a repair signal to the target chip under test.

[0146] Exemplarily, after the target chip under test receives the repair signal, it extracts the mapping relationship in the repair signal, and uses the mapping relationship to re-determine the trigger signal to obtain an updated trigger signal. The target chip under test executes the updated trigger signal and detects the pin voltage again within a preset time. If its pin voltage becomes the preset voltage, the target chip under test is used to continue testing; if its pin voltage does not become the preset voltage, the target chip under test is stopped from being used for testing.

[0147] In summary, a mapping relationship is generated according to the current pin voltage, trigger instruction and microinstruction, and the mapping relationship is transformed into a repair signal, so that the target chip under test can repair the mapping error inside the repair signal.

[0148] In the following embodiments, the microinstructions may be modified so that the target chip to be tested executes the modified microinstructions to determine whether the target chip to be tested has received and confirmed the microinstructions. Therefore, the present application embodiment discloses a flow chart of a method for sending microinstructions. Figure 6 , the method comprising:

[0149] Step S601: adding an identification instruction to the microinstruction, where the identification instruction is used to indicate that the output level of the target pin becomes a target level.

[0150] Optionally, the chip under test stores an operation instruction corresponding to the identification instruction. After the target chip under test obtains the identification instruction, it searches for the corresponding operation instruction according to the identification instruction, and executes the operation instruction to change the output level of the target pin to the target level.

[0151] The target pin is a specific pin on the chip to be tested. Exemplarily, the chip to be tested is provided with 8 pins, and the target pin is the second pin. After the instruction to be tested obtains the target pin, it will change the output level of the second pin to a high level. Exemplarily, the identification instruction can also be used to instruct the target pin to perform a specific action, for example, to control the output level of the target pin to flip a specified number of times within a specified time, or to control the output level of the target pin to output a voltage of a specified waveform within a specified time.

[0152] Step S602: Detect target pins of the target chip to be tested.

[0153] Exemplarily, a host computer connected to the chipset to be tested may monitor the pin voltage of a target pin of the target chip to be tested in real time.

[0154] Step S603: When it is detected that the output level of the target pin becomes the target level, it is detected whether the pin voltage of the target chip to be tested meets the preset voltage.

[0155] If the pin voltage of the target chip to be tested meets the preset voltage, step S604 is executed;

[0156] If the pin voltage of the target chip under test does not meet the preset voltage, step S605 is executed.

[0157] Step S604: If yes, continue testing the target chip to be tested.

[0158] If the pin voltage of the target chip under test meets the preset voltage, it means that the target test chip has received the microinstruction carrying the identification instruction and executed the action corresponding to the microinstruction. Therefore, there is no problem with the target chip under test itself and the test can continue.

[0159] Step S605: If not, stop testing the target chip to be tested.

[0160] If the pin voltage of the target chip under test does not meet the preset voltage, it means that the target test chip has not received the microinstruction carrying the identification instruction, or has not executed the action corresponding to the microinstruction. Therefore, there may be a problem with the target chip under test itself, so it is necessary to stop testing the target chip under test.

[0161] To summarize, an identification instruction is added to the microinstruction to control the output level of a specific target pin to become the target level, detect whether the target chip under test can accept and accurately read the microinstruction, and thereby determine whether the target chip under test can continue to participate in chip testing.

[0162] In the following embodiments, the target chip to be tested can also be modified through historical test records. The present application embodiment discloses a flow chart of a method for repairing a chip to be tested. Figure 7 , the method comprising:

[0163] Step S701: Obtain historical test records.

[0164] The historical test records include at least one of a test scenario, a test time, a chip model to be tested, and a chip type to be tested.

[0165] Furthermore, the historical test records will also record various problems that occurred during the test process of the chip under test and their solutions.

[0166] Step S702: according to the current pin voltage, searching the historical test records for a target historical test record corresponding to the current pin voltage.

[0167] Exemplarily, a target historical test record that is consistent with the change of the current pin voltage is searched in the historical test record. Exemplarily, if the current pin voltage has not changed within a preset time, a corresponding target historical test record is searched in the historical test record.

[0168] Step S703: extracting the solution from the target historical test record.

[0169] If the target historical test record does not record a solution, the process ends.

[0170] Step S704: performing clustering operation on the solutions to obtain the current solution of the target chip to be tested.

[0171] Optionally, the clustering operation includes but is not limited to any one of a K-Means clustering algorithm, a hierarchical clustering algorithm, a DBSCAN clustering algorithm, and a Gaussian mixture algorithm.

[0172] Step S705: Execute the current solution.

[0173] After the target chip to be tested executes the current solution, if the current pin voltage becomes the preset voltage, the test of the target chip to be tested continues. If the current pin voltage does not become the preset voltage, the test of the target chip to be tested is stopped.

[0174] In summary, the current repair method for the target chip under test is determined through historical test records, so that the target chip under test can participate in the test normally.

[0175] Based on the same inventive concept, the present application embodiment provides a structural diagram of a synchronous trigger system based on microinstructions, please refer to Figure 8 ,include:

[0176] The acquisition module 801 is used to acquire the test instruction, the preset voltage, the pin voltage change, the reply signal, the preset quantity, the preset interval time, the preset voltage range and the historical test record;

[0177] A memory 802, used to store a program of any one of the above microinstruction-based synchronization triggering methods;

[0178] Processor 803, the program in the memory can be loaded and executed by the processor and implement any of the above-mentioned microinstruction-based synchronization triggering methods.

[0179] To summarize, a trigger instruction is set in the register of the chip to be tested. When the chip to be tested is tested, a microinstruction is added to the test instruction. The trigger instruction in the register is triggered by the microinstruction. The pin voltage of the chip to be tested is controlled by the trigger instruction. When it is detected that the pin voltage of each chip to be tested is a preset voltage, each chip to be tested is tested, thereby improving the synchronization of chip testing. There is no need to add microinstructions to the test instruction, and the memory of the test instruction can be reduced.

[0180] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device and unit described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0181] An embodiment of the present application provides a computer-readable storage medium storing a computer program that can be loaded by a processor and execute a microinstruction-based synchronization triggering method.

[0182] Computer storage media include, for example, various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks or optical disks.

[0183] Based on the same inventive concept, an embodiment of the present application provides an intelligent terminal, including a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and execute a microinstruction-based synchronization triggering method.

[0184] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device and unit described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0185] The above are all preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. Any feature disclosed in this specification (including the abstract and drawings), unless otherwise stated, can be replaced by other equivalent or alternative features with similar purposes. That is, unless otherwise stated, each feature is only an example of a series of equivalent or similar features.

Claims

1. A synchronous triggering method based on microinstructions, characterized in that: The method comprises: Setting a trigger instruction in a register of each chip under test in the chip group under test, wherein the trigger instruction is used to adjust the pin voltage of the chip under test; Sending a test instruction to the chipset to be tested, wherein the test instruction carries a microinstruction, and the microinstruction is associated with the trigger instruction; When it is detected that the pin voltages of the chips under test in the chips under test are all preset voltages, sending a synchronous test signal to the chips under test; Monitoring the pin voltage changes of the chipset to be tested; Obtaining a test result of the chipset to be tested according to the pin voltage change; When it is detected that the current pin voltage of the target chip under test in the chipset under test does not change to the preset voltage within the preset time, a detection signal is sent to the target chip under test, wherein the detection signal is used to query the type of trigger instruction stored in the register of the target chip under test; Receiving a reply signal returned by the target chip under test; Determine an update trigger signal of the target chip to be tested according to the reply signal; Sending the update trigger signal to the target chip under test.

2. The microinstruction-based synchronous triggering method according to claim 1, characterized in that: The method further comprises: In the case where the number of the update trigger signals is greater than a preset number, determining a trigger timing of the update trigger signals; Arrange the update trigger signals according to the trigger timing; According to the timing intervals between adjacent update trigger signals, counting the first update trigger signal whose timing interval is greater than the preset interval time, and the second update trigger signal whose timing interval is less than the preset interval time; The update trigger signals are sent in sequence according to the trigger timing, wherein the first update trigger signal is sent individually and the adjacent second update trigger signals are sent in a package.

3. The microinstruction-based synchronous triggering method according to claim 2, characterized in that: The method further comprises: Calculating the volume of the compressed package of the second update trigger signal; In the case where the volume of the compressed package is larger than the preset volume, a third update trigger signal is selected according to the timing sequence of the update trigger signal in the second update trigger signal, the third update trigger signal is located at the end of the second update trigger signal, and the volume of the compressed package of the second update trigger signal after removing the third update trigger signal is smaller than the preset volume; In a case where the next update trigger signal of the third update trigger signal belongs to the first update trigger signal, the third update trigger signal is packaged and sent with the next update trigger signal; In the case where the next update trigger signal of the third update trigger signal belongs to the second update trigger signal, the third update trigger signal is sent alone.

4. The microinstruction-based synchronous triggering method according to claim 1, characterized in that: The method further comprises: In the absence of the update trigger signal, detecting whether the current pin voltage belongs to a preset voltage interval, the preset voltage interval corresponding to the trigger instruction; If not, stop testing the target chip to be tested; If so, a mapping relationship is generated according to the current pin voltage, the trigger instruction and the microinstruction; the mapping relationship is transformed into a repair signal; and the repair signal is sent to the target chip to be tested.

5. The microinstruction-based synchronous triggering method according to claim 4, characterized in that: The method further comprises: Adding an identification instruction to the microinstruction, wherein the identification instruction is used to control the output level of the target pin to become a target level; Detecting the target pin of the target chip to be tested; In the case where it is detected that the output level of the target pin becomes the target level, detecting whether the pin voltage of the target chip to be tested meets a preset voltage; If yes, continue testing the target chip to be tested; If not, the test of the target chip to be tested is stopped.

6. The microinstruction-based synchronous triggering method according to claim 1, characterized in that: The method further comprises: Get historical test records; According to the current pin voltage, searching the historical test records for a target historical test record corresponding to the current pin voltage; Extracting a solution from the target historical test record; Performing clustering operation on the solution to obtain the current solution of the target chip to be tested; The current solution is implemented.

7. A microinstruction-based synchronous trigger system, characterized in that: The system comprises: An acquisition module is used to obtain test instructions, preset voltages, and pin voltage changes; A memory for storing a program of a microinstruction-based synchronization triggering method according to any one of claims 1 to 6; The program in the memory can be loaded and executed by the processor and implement the microinstruction-based synchronization triggering method as described in any one of claims 1 to 6.

8. An intelligent terminal, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program which can be loaded by the processor and executes the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: A computer program is stored which can be loaded by a processor and execute the method according to any one of claims 1 to 6.

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