Address identification system and method for multi-card-slot system and multi-card-slot equipment

Abstract

The invention relates to an address identification system and method for a multi-card-slot system and multi-card-slot equipment, and the system comprises a signal generation module which is used for generating a fundamental wave signal according to a preset requirement of a user; the input end of the signal frequency division module is connected with the signal generation module, and the signal frequency division module is used for performing frequency division on the fundamental wave signal to obtain a plurality of frequency division signals with different frequencies and outputting the frequency division signals with different frequencies to different card slots; the input end of the signal detection module is connected with the card slot, and the signal detection module is used for receiving the frequency division signal transmitted to the card slot and identifying the physical address of the card slot according to the frequency division signal. According to the device address identification method, the fundamental wave signal with the fixed frequency is generated, and the frequency division signal is sequentially generated on each slot, so that the device on each slot can detect signals with different frequencies, and a traditional resistance voltage division method is replaced to carry out device address identification.

Description

Technical Field

[0001] The present application relates to the technical field of device address identification, and in particular to an address identification system and method for a multi-card slot system and a multi-card slot device. Background Art

[0002] In multi-card slot devices, such as communication equipment, computer servers, embedded systems, etc., it is crucial to accurately identify the location of the device in each slot. Existing address recognition schemes usually rely on address recognition technology. With the development of technology, the widely used address recognition methods include resistor voltage division method, DIP switch method, EEPROM address storage method and PCI bus method.

[0003] Among them, the resistor voltage division method is one of the traditional and common address identification methods. Although this method is easy to implement, the required resistor network becomes more complex as the number of slots increases. At the same time, this method is easily disturbed by the environment, affecting the accuracy of identification, and the expansion capability is limited. The DIP (Dual In-line Package) switch method is another common address identification method. The advantages of this method are simple implementation and low hardware cost; but it requires manual setting of switches, which is prone to misconfiguration, cumbersome maintenance process, and low efficiency. The EEPROM (Electrically Erasable Programmable Read-Only Memory) storage method determines its physical location by reading the address information in the EEPROM. This method is expensive and has the risk of damage or data loss in extreme environments. The PCI (Peripheral Component Interconnect) bus method is a device identification method widely used in modern computer systems. It identifies the existence and location of devices through bus scanning, but this method involves multi-level hardware and software interactions and requires dedicated bus interfaces and controllers. Therefore, it is complex, costly, and power-consuming, and is not suitable for low-power devices or embedded applications. It can be seen that the existing device address device solutions all have certain limitations. Summary of the invention

[0004] The embodiments of the present application provide an address recognition system, method and multi-card slot device for a multi-card slot system, so as to at least solve the problems of complex structure and high hardware cost of existing address recognition solutions in the related art.

[0005] In a first aspect, an embodiment of the present application provides an address recognition system for a multi-card slot system, including:

[0006] A signal generation module is used to generate a fundamental wave signal according to user preset requirements;

[0007] A signal frequency division module, the input end of which is connected to the signal generating module, for dividing the fundamental wave signal to obtain a plurality of frequency division signals with different frequencies, and outputting the frequency division signals with different frequencies to different card slots;

[0008] A signal detection module, wherein an input end of the signal detection module is connected to the card slot, and is used to receive the frequency-divided signal transmitted to the card slot, and identify the physical address of the card slot according to the frequency-divided signal.

[0009] In one embodiment, the signal detection module includes:

[0010] A signal acquisition unit, the input end of which is connected to the card slot, for acquiring a frequency-divided signal of the card slot, processing the frequency-divided signal, obtaining the frequency of the frequency-divided signal of the card slot, and sending the frequency to the address recognition unit;

[0011] An address identification unit, the input end of which is connected to the signal acquisition unit, is used to search in a preset address mapping table according to the frequency of the frequency-divided signal to obtain the physical address of the card slot.

[0012] In one embodiment, the signal acquisition unit includes:

[0013] A frequency measurement circuit is used to measure the frequency of the received frequency-divided signal to obtain the frequency of the frequency-divided signal.

[0014] The analog-to-digital conversion circuit is used to convert the frequency of the frequency-divided signal into a digital signal and then send it to the address recognition unit.

[0015] In one embodiment, the signal frequency division module includes multiple frequency dividers and multiple independent signal frequency division networks, each frequency divider is connected to the corresponding card slot through the signal frequency division network, the frequency divider is used to convert the fundamental wave signal into a frequency division signal of a preset frequency, and transmit the frequency division signal to the corresponding card slot through the signal frequency division network.

[0016] In one embodiment, the address identification device further includes a control logic module, and the output end of the control logic module is respectively connected to the signal generating module and the signal frequency dividing module for controlling the working states of the signal generating module and the signal frequency dividing module.

[0017] In one embodiment, the address recognition system further includes a main controller and an address storage module, and the input end of the main controller is connected to the signal detection module, wherein:

[0018] The address storage module is used to record the physical addresses and address mapping tables of all card slots;

[0019] The main controller is used to manage and schedule the slot device connected to the card slot according to the physical address to achieve data transmission and communication.

[0020] In one embodiment, the signal detection module is installed on a slot device, and when the slot device is inserted into a corresponding card slot, the signal detection module is electrically connected to the card slot.

[0021] In a second aspect, an embodiment of the present application provides a multi-card slot device, characterized in that it includes a slot interface module, a single board, a slot device, and an address recognition system for a multi-card slot system as described in any one of the above items, wherein the slot interface module is mounted on the single board, and the slot device is fixed on the single board through the slot interface module, wherein:

[0022] The signal generation module and the signal frequency division module are arranged on the single board, the signal detection module is arranged on the slot device, and the slot interface module includes a plurality of card slots.

[0023] In a third aspect, an embodiment of the present application provides an address recognition method for a multi-card slot system, characterized in that the address recognition method for a multi-card slot system applied in any of the above embodiments includes:

[0024] Generate fundamental wave signal according to user preset requirements;

[0025] Dividing the fundamental wave signal to obtain a plurality of divided frequency signals with different frequencies, and outputting the divided frequency signals with different frequencies to different card slots;

[0026] A frequency division signal transmitted to the card slot is received, and a physical address of the card slot is identified according to the frequency division signal.

[0027] In one embodiment, identifying the physical address of the card slot according to the frequency division signal includes:

[0028] The frequency division signal of the same card slot is sampled and measured multiple times to obtain multiple sampling frequencies;

[0029] Averaging multiple sampling frequencies to obtain a frequency average value, and converting the frequency average value into a digital signal;

[0030] An address mapping table is obtained, and the digital signal is matched with the address mapping table to obtain a physical address corresponding to the current card slot.

[0031] In one embodiment, the method further comprises: initializing the system; wherein,

[0032] After obtaining the physical address, the physical address is stored in a register inside the device, and the initialization configuration of the device is completed according to the physical address to obtain address information;

[0033] The address information is transmitted to the main controller, and the physical address of each slot device is checked twice by the main controller, and an initialization completion signal is output after the check passes;

[0034] After the initialization is completed, the main controller manages and schedules the slot devices according to the address information to achieve data transmission and communication.

[0035] In one embodiment, the method further comprises:

[0036] When the frequency division signal detected by the signal detection module is unstable or does not match the address mapping table, the backup identification mechanism is triggered and an abnormal signal is output to the main controller;

[0037] After the main controller receives the abnormal signal, it switches to the backup identification scheme, which is the resistor voltage division method, the DIP switch method, the EEPROM address storage method or the PCI bus method.

[0038] The address recognition system, method and multi-card slot device for a multi-card slot system provided by the embodiments of the present application have at least the following technical effects:

[0039] By generating a fundamental wave signal with a fixed frequency and generating a frequency division signal in each slot in turn, the device on each slot can detect signals of different frequencies, thereby replacing the traditional resistor voltage division method for device address recognition.

[0040] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0042] Figure 1 is a structural block diagram of an address recognition system for a multi-card slot system in an embodiment of the present application;

[0043] Figure 2 This is a circuit schematic diagram of an address recognition system for a multi-card slot system in an embodiment of the present application;

[0044] Figure 3 It is a flow chart of an address recognition method for a multi-card slot system in an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments provided in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0046] Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. In addition, it can also be understood that although the efforts made in this development process may be complicated and lengthy, for ordinary technicians in this field related to the content disclosed in this application, some changes in design, manufacturing or production based on the technical content disclosed in this application are just conventional technical means, and should not be understood as insufficient content disclosed in this application.

[0047] Reference to "embodiments" in this application means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0048] Unless otherwise defined, the technical terms or scientific terms involved in this application should be understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the" and the like involved in this application do not indicate a quantitative limitation, and may represent the singular or plural. The terms "include", "comprise", "have" and any of their variations involved in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0049] Among the existing address recognition methods, the resistor voltage division method generates a specific voltage signal by configuring a resistor network with different resistance values ​​at each slot (i.e., card slot) position. The slot device (referred to as the device) in the slot identifies its physical position by detecting these voltage signals. Although this method is easy to implement, it faces many problems: First, the hardware complexity. As the number of slots increases, the required resistor network becomes more complex, making it difficult to design and manage; second, environmental interference. The voltage signal is easily interfered by factors such as temperature and power supply noise, affecting the accuracy of recognition; third, poor scalability. Adding new slots requires redesigning the resistor network, which limits the scalability.

[0050] The DIP (Dual In-line Package) switch method is to configure a set of DIP switches on each device or slot, and define the address of the device by manually setting the switch position. The advantages of this method are simple implementation and low hardware cost, but the disadvantages are also significant: First, it is prone to human errors because the switches need to be set manually, so incorrect configuration is prone to occur, especially in multi-slot devices; second, maintenance complexity. Once the address is set incorrectly or needs to be changed, the maintenance process is cumbersome and inefficient; third, it is not suitable for automation needs. With the increase in system complexity and the improvement of automation needs, the DIP switch method is difficult to meet the requirements of modern systems.

[0051] The EEPROM (Electrically Erasable Programmable Read-Only Memory) storage method integrates an EEPROM module on each device or slot to store the unique address information of the device. When the device is powered on, its physical location is determined by reading the address information in the EEPROM. This method has certain advantages over the above two methods, such as high reliability. Through electronic storage technology, errors and interference caused by physical switches or resistor networks are avoided. It is also easy to manage. The address information is programmable and easy to update, which is convenient for system expansion and maintenance. However, the EEPROM method also has certain shortcomings: First, the cost is high. The integration of the EEPROM module increases the system cost, especially in large-scale production. The second is the risk of electrical failure. Although EEPROM is relatively stable, there is still a risk of damage or data loss in extreme environments.

[0052] The PCI (Peripheral Component Interconnect) bus method is a device identification method widely used in modern computer systems. Its principle is that on the PCI bus, each device has a unique device address, and the system identifies the existence and location of the device through bus scanning. When the system is powered on, the PCI bus can automatically scan and identify the devices in each slot without manual intervention; the PCI bus supports multi-device connection and has good scalability, which is suitable for large-scale, multi-slot devices; as an industrial standard, the PCI bus method has good versatility and compatibility, so this method has the advantages of automatic identification, high scalability and good compatibility. Although the PCI bus method is widely used in modern computer systems, it also has some shortcomings: first, it is highly complex. The PCI bus system design is complex, involving multi-level hardware and software interactions, and occupies a high amount of system resources; second, it is costly. The PCI bus method requires a dedicated bus interface and controller, which increases the hardware cost, especially in resource-constrained embedded systems. It is not economical; third, it has high power consumption. The PCI bus system usually has high power consumption and is not suitable for low-power devices or embedded applications.

[0053] Based on the above situation, the embodiments of the present application provide an address recognition system, method and multi-card slot device for a multi-card slot system, which realizes a new method of address recognition by performing signal frequency detection, aiming to replace the traditional resistance voltage division method, DIP switch method, EEPROM address storage method and PCI bus method, and is suitable for multi-slot application scenarios such as communication systems, computer systems, and embedded devices.

[0054] In a first aspect, an embodiment of the present application provides an address recognition system for a multi-card slot system. Figure 1 It is the structural diagram of the address recognition system, such as Figure 1As shown, the address identification system of the embodiment of the present application includes a signal generating module, a signal frequency dividing module and a signal detecting module. Among them, the signal generating module is used to generate a fundamental wave signal according to the preset requirements of the user; the input end of the signal frequency dividing module is connected to the signal generating module, which is used to divide the fundamental wave signal to obtain a plurality of frequency-divided signals with different frequencies, and output the frequency-divided signals with different frequencies to different card slots; the signal detecting module, the input end of the signal detecting module is connected to the card slot, which is used to receive the frequency-divided signal transmitted to the card slot, and identify the physical address of the card slot according to the frequency-divided signal. The embodiment of the present application generates a fundamental wave signal with a fixed frequency, and generates a frequency-divided signal on each slot in turn, so that the device on each card slot can detect signals of different frequencies, thereby replacing the traditional resistance voltage division method for device address identification, so as to ensure that the equipment in the multi-slot system can accurately and reliably identify its physical address.

[0055] In the embodiment of the present application, the signal generating module and the signal frequency dividing module can be designed on the same single board, and the signal generating module includes a signal generator, which can generate a fundamental wave signal of a fixed frequency to ensure that the frequency dividing signal of each slot has uniqueness and stability. The fundamental wave signal is processed by one or more frequency divider modules (signal frequency dividing modules) to generate a series of frequency dividing signals of different frequencies (that is, each frequency dividing signal has a unique frequency), and the frequency divider module sends the frequency dividing signal to each slot on the single board in sequence. In this embodiment, the device on each slot includes a signal detection module, which can detect and identify the specific frequency signal received in the slot. Through the detected frequency signal, the device can determine its position on the single board (that is, the slot address). In addition, the single board also includes the output end of the control logic module connected to the signal generating module and the signal frequency dividing module respectively, which is used to control the working state of the signal generating module and the signal frequency dividing module, that is, the control logic is responsible for managing the working state of the signal generator and the frequency divider module, and ensuring that the frequency dividing signal is sent to each slot in a predetermined order.

[0056] refer to Figure 1 The signal detection module of the embodiment of the present application includes a signal acquisition unit and an address recognition unit, wherein the input end of the signal acquisition unit is connected to the card slot, used to collect the frequency-divided signal of the card slot, process the frequency-divided signal, obtain the frequency of the frequency-divided signal of the card slot and send it to the address recognition unit; the input end of the address recognition unit is connected to the signal acquisition unit, used to search in a pre-set address mapping table according to the frequency of the frequency-divided signal, and obtain the physical address of the card slot.

[0057] More specifically, the signal acquisition unit may apply a frequency measurement circuit and an analog-to-digital conversion circuit, wherein the frequency measurement circuit is used to measure the frequency of the received divided frequency signal to obtain the divided frequency signal frequency, and the analog-to-digital conversion circuit is used to convert the divided frequency signal frequency into a digital signal and send it to the address recognition unit so that the address recognition unit performs address analysis based on the digital signal.

[0058] In one embodiment of the present application, refer to Figure 2 The signal frequency division module includes multiple frequency dividers and multiple independent signal frequency division networks. Each frequency divider is connected to the corresponding card slot through the signal frequency division network. The frequency divider is used to convert the fundamental wave signal into a frequency division signal of a preset frequency. The frequency of each frequency division signal can be set by the user, and the frequency division signal is transmitted to the corresponding card slot through the signal frequency division network.

[0059] exist Figure 2 In the embodiment, the card slot module includes a plurality of card slots 1-7 connected in series, and each card slot includes a frequency divider. The signal generating unit (i.e., frequency generating unit) includes a signal source, which is connected to the card slot module and can generate a signal of a fixed frequency and output it to the card slot. The frequency acquiring unit (i.e., signal acquiring unit) includes a card slot frequency detector and a basic frequency detector, which are respectively used to detect the card slot frequency (i.e., the frequency of the frequency-divided signal) and detect the basic frequency (i.e., the frequency of the fundamental signal) and output it to the address recognition unit. The address recognition unit analyzes the received frequency to generate an address.

[0060] In a preferred embodiment, reference Figure 1 The address recognition system further includes a main controller and an address storage module, and the input end of the main controller is connected to the signal detection module. The address storage module is used to record the physical addresses and address mapping tables of all card slots; the main controller is used to manage and schedule the slot devices connected to the card slots according to the physical addresses to achieve data transmission and communication.

[0061] In one embodiment, the signal detection module can be installed on the slot device, and when the slot device is inserted into the corresponding card slot, the signal detection module is electrically connected to the card slot, and the physical address detected at this time is also the physical address of the slot device. Alternatively, the signal detection module and the signal generation module can also be set on the same single board, and the physical address detected at this time is the address of the card slot, and the address detection can be achieved even if there is no connection between the card slot device.

[0062] In a preferred embodiment, the address identification system includes a signal generator, a frequency division circuit and slot devices in multiple slots. The frequency division circuit includes multiple frequency dividers connected to the signal generator, which are used to divide the fundamental wave signal and output it to multiple slots respectively. Each slot device includes a frequency detection module, which is used to detect the frequency of the frequency division signal assigned to the slot where it is located, so as to identify its physical address. In this embodiment, the signal detection module is set on the slot device.

[0063] In actual hardware design, the system of the present application can be composed of multiple integrated circuit modules (signal generation module, signal frequency division module, signal detection module), and each module is connected through a standardized interface to realize the programmability and maintainability of the system. The signal generator module, the frequency divider module and the frequency detection module can also be integrated in an ASIC or FPGA, or implemented in the form of a combination of multiple chips. In addition, a signal distribution network is configured between the signal frequency division module and the card slot, so that the signal frequency division module is connected to each slot to ensure low delay and high fidelity during signal transmission. And the system design reserves an external programming interface, allowing the user to adjust the frequency parameters and allocation strategy according to actual application requirements.

[0064] Through the above hardware design, the present invention realizes a multi-slot device address recognition method based on frequency signals on a single board, successfully replacing the traditional resistor voltage division method. The method has high accuracy, high reliability and flexibility, and is suitable for device management and configuration in a variety of multi-slot systems.

[0065] In summary, the address recognition system provided by the embodiment of the present application generates different frequency signals on each slot through frequency division technology, and identifies the physical location of different card slots or slot devices by detecting the frequency signal of each slot. Compared with the traditional resistor voltage division method, DIP switch method, EEPROM address storage method and PCI bus method, the address detection scheme of the present application has the following advantages:

[0066] The hardware is simplified, without the need for complex resistor networks, DIP switches or PCI bus interfaces, and the hardware design is more concise; the anti-interference ability is strong, and the frequency signal is more stable than the voltage signal and PCI bus signal, and is not easily affected by environmental interference or system noise; the scalability is good, and adding slots does not require significant changes to the circuit design, making it easy to expand; the maintenance is simple, through frequency signal identification, there is no need to maintain physical switches, EEPROM or PCI bus interfaces, reducing maintenance costs.

[0067] In the second aspect, an embodiment of the present application provides a multi-card slot device, including a slot interface module, a single board, a slot device, and an address identification system for a multi-card slot system as described in any of the above embodiments, wherein the slot interface module is installed on the single board, and the slot device is fixed on the single board through the slot interface module. Among them, the signal generation module and the signal frequency division module are arranged on the single board, the signal detection module is arranged on the slot device, the slot interface module includes a plurality of card slots, and the slot interface module of the present application includes a plurality of types of slot interfaces, including but not limited to PCI, PCIe, SATA, M.2 interfaces, etc. In summary, the multi-card slot device provided by the present application has the following advantages:

[0068] The hardware is simplified, no additional resistor network is required, and address recognition is achieved only through signal generators and dividers, which simplifies the hardware design; debugging is convenient, and the signal frequency can be adjusted through software or firmware configuration, making debugging more convenient; high reliability, signal transmission and detection are not affected by external factors such as resistance and temperature changes, and system reliability is significantly improved; strong scalability, the system can support a variety of different slot numbers and frequency ranges by adjusting the configuration of the signal generator and divider modules.

[0069] In a third aspect, the present application provides an address recognition method for a multi-card slot system, which is applied to the address recognition system for a multi-card slot system described in any of the above embodiments, with reference to Figure 3 , the method of this embodiment includes the following steps:

[0070] Step S1, generating a fundamental wave signal according to user preset requirements;

[0071] Step S2, dividing the fundamental wave signal to obtain a plurality of divided frequency signals with different frequencies, and outputting the divided frequency signals with different frequencies to different card slots;

[0072] Step S3, receiving the frequency division signal transmitted to the card slot, and identifying the physical address of the card slot according to the frequency division signal, sampling and measuring the frequency division signal of the same card slot multiple times to obtain multiple sampling frequencies; averaging the multiple sampling frequencies to obtain a frequency average value, and converting the frequency average value into a digital signal; obtaining an address mapping table, matching the digital signal with the address mapping table, and obtaining the physical address corresponding to the current card slot.

[0073] Specifically, the first step is to generate the fundamental signal. In this step, Figure 1The signal generator module integrated on the single-board system starts and generates a fixed-frequency fundamental signal. The frequency of this signal is predetermined by the system design, generally in the range of tens of kilohertz to hundreds of megahertz, and the specific frequency depends on the application requirements of the system and the performance requirements of the slot device. The signal generator module generates a stable fundamental signal through an internal oscillator. The fundamental signal is output to the input end of the frequency division circuit for subsequent frequency division processing.

[0074] The second step is the generation and distribution of the frequency division signal. In this step, the fundamental signal is processed by the frequency division circuit to generate multiple frequency division signals of different frequencies. These frequency division signals are distributed to each slot in the system in turn, so that each slot receives a unique frequency signal. The frequency division circuit is implemented by a programmable logic device (such as FPGA), which can generate multiple frequency division signals of predetermined frequencies according to the configuration. The generated frequency division signals are transmitted to each slot through the signal distribution network. Each slot has an independent signal transmission line to ensure that there is no crosstalk or attenuation during the transmission of the signal, thereby ensuring the integrity of the signal.

[0075] Finally, there is the frequency detection of the slot. In each slot, each slot device can be set to include a frequency detection module for receiving and detecting the frequency-divided signal transmitted to the slot. By detecting the frequency of the signal, the device can identify the slot location where it is located. The frequency detection module is implemented using common technologies such as PLL (phase-locked loop) circuit or frequency counter. After the device receives the frequency-divided signal, the frequency detection module starts and performs frequency analysis on the input signal. Through multiple sampling and averaging processing, the frequency detection module can obtain an accurate frequency value. The frequency detection module compares the detected frequency with the frequency and address mapping table preset inside the device to determine the physical address of the device.

[0076] In a preferred embodiment, the system needs to be initialized. After obtaining the physical address, the physical address is stored in a register inside the device, and the device initialization configuration is completed according to the physical address to obtain address information; the address information is transmitted to the main controller, and the physical address of each slot device is verified twice by the main controller, and an initialization completion signal is output after the verification passes; after the initialization is completed, the main controller manages and schedules the slot device according to the address information to realize data transmission and communication.

[0077] Specifically, after completing the frequency detection, the device stores the identified physical address in the internal register and completes the system initialization configuration based on the address. The device writes the compared physical address into its control register to complete the initial identification of the address. During the system initialization process, the device passes the address information to the main controller so that the main controller can correctly manage and schedule the devices in each slot. The main controller performs a secondary check on the physical address of each slot device to ensure the accuracy of address identification.

[0078] In another preferred embodiment, the method also includes: when the frequency division signal detected by the signal detection module is unstable or does not match the address mapping table, triggering a backup identification mechanism and outputting an abnormal signal to the main controller; after the main controller receives the abnormal signal, switching to a backup identification scheme, the backup identification scheme is a resistor voltage division method, a DIP switch method, an EEPROM address storage method or a PCI bus method.

[0079] Specifically, in order to enhance the fault tolerance of the system, this embodiment designs a set of backup identification mechanisms. When the frequency signal detection fails or is abnormal, the system automatically switches to other identification methods, such as the traditional resistor voltage division method or the PCI bus voltage address allocation method.

[0080] The device's frequency detection module triggers the backup identification mechanism when it detects that the frequency signal is unstable or cannot be matched. After the main controller receives the abnormal signal, it switches to the backup identification scheme, such as assigning physical addresses through voltage signals. After the backup identification is completed, the device continues to perform system initialization and subsequent operations to ensure the normal operation of the system

[0081] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. An address recognition system for a multi-card slot system, characterized in that: include: A signal generation module is used to generate a fundamental wave signal according to user preset requirements; A signal frequency division module, the input end of which is connected to the signal generating module, for dividing the fundamental wave signal to obtain a plurality of frequency division signals with different frequencies, and outputting the frequency division signals with different frequencies to different card slots; A signal detection module, wherein an input end of the signal detection module is connected to the card slot, and is used to receive the frequency-divided signal transmitted to the card slot, and identify the physical address of the card slot according to the frequency-divided signal.

2. The address recognition system according to claim 1, characterized in that: The signal detection module comprises: A signal acquisition unit, the input end of which is connected to the card slot, for acquiring a frequency-divided signal of the card slot, processing the frequency-divided signal, obtaining the frequency of the frequency-divided signal of the card slot, and sending the frequency to the address recognition unit; An address identification unit, the input end of which is connected to the signal acquisition unit, is used to search in a preset address mapping table according to the frequency of the frequency-divided signal to obtain the physical address of the card slot.

3. The address recognition system according to claim 2, characterized in that: The signal acquisition unit comprises: A frequency measurement circuit is used to measure the frequency of the received frequency-divided signal to obtain the frequency of the frequency-divided signal. The analog-to-digital conversion circuit is used to convert the frequency of the frequency-divided signal into a digital signal and then send it to the address recognition unit.

4. The address recognition system according to claim 1, characterized in that: The signal frequency division module includes multiple frequency dividers and multiple independent signal frequency division networks. Each frequency divider is connected to the corresponding card slot through the signal frequency division network. The frequency divider is used to convert the fundamental wave signal into a frequency division signal of a preset frequency, and transmit the frequency division signal to the corresponding card slot through the signal frequency division network.

5. The address recognition system according to claim 1, characterized in that: The address recognition device further comprises a control logic module, the output end of which is respectively connected to the signal generation module and the signal frequency division module, so as to control the working states of the signal generation module and the signal frequency division module.

6. The address recognition system according to claim 1, characterized in that: The address recognition system further comprises a main controller and an address storage module, wherein the input end of the main controller is connected to the signal detection module, wherein: The address storage module is used to record the physical addresses and address mapping tables of all card slots; The main controller is used to manage and schedule the slot device connected to the card slot according to the physical address to achieve data transmission and communication.

7. The address recognition system according to claim 1, characterized in that: The signal detection module is installed on the slot device. When the slot device is inserted into the corresponding card slot, the signal detection module is electrically connected to the card slot.

8. A multi-card slot device, characterized in that: The invention comprises a slot interface module, a single board, a slot device and an address recognition system for a multi-card slot system according to any one of claims 1 to 7, wherein the slot interface module is mounted on the single board, the slot device is fixed on the single board through the slot interface module, wherein: The signal generation module and the signal frequency division module are arranged on the single board, the signal detection module is arranged on the slot device, and the slot interface module includes a plurality of card slots.

9. An address recognition method for a multi-card slot system, characterized in that: The address recognition system for a multi-card slot system used in any one of claims 1 to 8 comprises: Generate fundamental wave signal according to user preset requirements; Dividing the fundamental wave signal to obtain a plurality of divided frequency signals with different frequencies, and outputting the divided frequency signals with different frequencies to different card slots; A frequency division signal transmitted to the card slot is received, and a physical address of the card slot is identified according to the frequency division signal.

10. The address recognition method according to claim 9, characterized in that: The step of identifying the physical address of the card slot according to the frequency division signal comprises: The frequency division signal of the same card slot is sampled and measured multiple times to obtain multiple sampling frequencies; Averaging multiple sampling frequencies to obtain a frequency average value, and converting the frequency average value into a digital signal; An address mapping table is obtained, and the digital signal is matched with the address mapping table to obtain a physical address corresponding to the current card slot.

11. The address recognition method according to claim 9, characterized in that: The method further comprises: initializing the system; wherein, After obtaining the physical address, the physical address is stored in a register inside the device, and the initialization configuration of the device is completed according to the physical address to obtain address information; The address information is transmitted to the main controller, and the physical address of each slot device is checked twice by the main controller, and an initialization completion signal is output after the check passes; After the initialization is completed, the main controller manages and schedules the slot device according to the address information to achieve data transmission and communication.

12. The address recognition method according to claim 9, characterized in that: The method further comprises: When the frequency division signal detected by the signal detection module is unstable or does not match the address mapping table, the backup identification mechanism is triggered and an abnormal signal is output to the main controller; After the main controller receives the abnormal signal, it switches to a backup identification scheme, which is a resistor voltage division method, a DIP switch method, an EEPROM address storage method or a PCI bus method.

Images