Shifting register and driving method thereof, gate driving circuit and display substrate

Abstract

The invention discloses a shift register and a driving method thereof, a gate driving circuit and a display substrate, and the shift register comprises a cascade sub-circuit which is configured to provide a signal of a second clock signal end for a first node under the control of signals of a signal input end, a first clock signal end and the second clock signal end, a signal of a signal input end is provided for the second node, and a signal of a first power supply end or a second power supply end is provided for a cascade output signal end under the control of the signals of the first node and the second node; and the gating sub-circuit is configured to provide a signal of the first power supply end or the second power supply end to the driving output signal end under the control of signals of the masking signal end, the first control signal end, the second control signal end, the third control signal end, the first node and the second node.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit and a display substrate. Background Art

[0002] With the rapid development of display technology, display devices are increasingly developing towards high integration and low cost. Among them, GOA (Gate Driver on Array) technology integrates TFT (Thin Film Transistor) gate drive circuits on the array substrate of the display device to form a scan drive for the display device. Among them, the gate drive circuit is usually composed of multiple cascaded shift registers. Summary of the invention

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0004] The present disclosure provides a shift register and a driving method thereof, a gate driving circuit and a display substrate.

[0005] In a first aspect, the present disclosure further provides a shift register, comprising: a cascade subcircuit and a gating subcircuit;

[0006] The cascade sub-circuit is respectively connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the first node, the second node and the cascade output signal terminal, and is configured to provide the signal of the second clock signal terminal to the first node and the signal of the signal input terminal to the second node under the control of the signals of the signal input terminal, the first clock signal terminal and the second clock signal terminal, and to provide the signal of the first power supply terminal or the second power supply terminal to the cascade output signal terminal under the control of the signals of the first node and the second node;

[0007] The gating subcircuit is respectively connected to the first node, the second node, the masking signal terminal, the first control signal terminal, the second control signal terminal, the third control signal terminal, the first power supply terminal, the second power supply terminal and the driving output signal terminal, and is configured to provide a signal from the first power supply terminal or the second power supply terminal to the driving output signal terminal under the control of the signals from the masking signal terminal, the first control signal terminal, the second control signal terminal, the third control signal terminal, the first node and the second node.

[0008] In an exemplary embodiment, the cascade subcircuit includes: a node control subcircuit, a cascade output subcircuit, and a voltage stabilization subcircuit;

[0009] The node control subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first node, and the second node, respectively, and is configured to provide the signal of the second clock signal terminal to the first node and provide the signal of the signal input terminal to the second node under the control of the signals of the signal input terminal, the first clock signal terminal, and the second clock signal terminal;

[0010] The cascade output subcircuit is electrically connected to the first node, the second node, the first power supply terminal, the second power supply terminal and the cascade output signal terminal respectively, and is configured to provide a signal from the first power supply terminal or the second power supply terminal to the cascade output signal terminal under the control of the signals from the first node and the second node;

[0011] The voltage stabilizing subcircuit is electrically connected to the cascade output signal terminal and the second power supply terminal, respectively, and is configured to store a voltage difference between the signals at the cascade output signal terminal and the second power supply terminal.

[0012] In an exemplary embodiment, the node control subcircuit includes: a first node control subcircuit, a second node control subcircuit, a third node control subcircuit, and a fourth node control subcircuit;

[0013] The first node control subcircuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the first node and the fourth node respectively, and is configured to provide the signal of the second power supply terminal to the fourth node, provide the signal of the second clock signal terminal to the first node, and store the voltage difference between the signal of the first node and the signal of the first power supply terminal under the control of the signal of the first clock signal terminal and the second clock signal terminal;

[0014] The second node control subcircuit is electrically connected to the first clock signal terminal, the signal input terminal and the second node respectively, and is configured to provide a signal from the signal input terminal to the second node under the control of a signal from the first clock signal terminal;

[0015] The third node control subcircuit is electrically connected to the first clock signal terminal, the second node and the fourth node respectively, and is configured to provide the signal of the first clock signal terminal to the fourth node under the control of the signal of the second node;

[0016] The fourth node control subcircuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first node and the second node, respectively, and is configured to provide the signal of the first clock signal terminal to the first node under the control of the signal of the second node, and store the voltage values ​​of the signals of the second node and the second clock signal terminal.

[0017] In an exemplary embodiment, the first node control subcircuit includes: a third transistor, a sixth transistor, a seventh transistor, a first capacitor and a second capacitor, the second node control subcircuit includes: a first transistor, and the third node control subcircuit includes: a second transistor;

[0018] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the second node;

[0019] The control electrode of the second transistor is electrically connected to the second node, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the first clock signal terminal;

[0020] A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the fourth node;

[0021] The control electrode of the sixth transistor is electrically connected to the fourth node, the first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the third node;

[0022] The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is electrically connected to the third node, and the second electrode of the seventh transistor is electrically connected to the first node;

[0023] The first end of the first capacitor is electrically connected to the fourth node, and the second end of the first capacitor is electrically connected to the third node;

[0024] A first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the first power supply end.

[0025] In an exemplary embodiment, the fourth node control subcircuit includes: a fourth transistor, a fifth transistor and a third capacitor;

[0026] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the fifth node, and the second electrode of the fourth transistor is electrically connected to the second clock signal terminal;

[0027] The control electrode of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the first clock signal terminal;

[0028] A first end of the third capacitor is electrically connected to the second node, and a second end of the third capacitor is electrically connected to the fifth node.

[0029] In an exemplary embodiment, the node control subcircuit includes: a first node control subcircuit, a second node control subcircuit, a third node control subcircuit, and a fourth node control subcircuit;

[0030] The first node control subcircuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the first node and the fourth node respectively, and is configured to provide the signal of the second power supply terminal to the fourth node, provide the signal of the second clock signal terminal to the first node, and store the voltage difference between the signal of the first node and the signal of the first power supply terminal under the control of the signal of the first clock signal terminal and the second clock signal terminal;

[0031] The second node control subcircuit is electrically connected to the first clock signal terminal, the signal input terminal and the second node respectively, and is configured to provide a signal from the signal input terminal to the second node under the control of a signal from the first clock signal terminal;

[0032] The third node control subcircuit is electrically connected to the first clock signal terminal, the signal input terminal and the fourth node respectively, and is configured to provide the signal of the first clock signal terminal to the fourth node under the control of the signal of the signal input terminal;

[0033] The fourth node control subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first node and the second node, respectively, and is configured to be under the control of the signal of the second node and store the voltage difference between the second clock signal terminal and the signal of the second node, and under the control of the signal of the signal input terminal, provide the signal of the first clock signal terminal to the first node.

[0034] In an exemplary embodiment, the first node control subcircuit includes: a third transistor, a sixth transistor, a seventh transistor, a first capacitor and a second capacitor, the second node control subcircuit includes: a first transistor, and the third node control subcircuit includes: a second transistor;

[0035] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the second node;

[0036] The control electrode of the second transistor is electrically connected to the signal input terminal, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the first clock signal terminal;

[0037] A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the fourth node;

[0038] The control electrode of the sixth transistor is electrically connected to the fourth node, the first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the third node;

[0039] The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is electrically connected to the third node, and the second electrode of the seventh transistor is electrically connected to the first node;

[0040] The first end of the first capacitor is electrically connected to the fourth node, and the second end of the first capacitor is electrically connected to the third node;

[0041] A first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the first power supply end.

[0042] In an exemplary embodiment, the fourth node control subcircuit includes: a fourth transistor, a fifth transistor and a third capacitor;

[0043] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the fifth node, and the second electrode of the fourth transistor is electrically connected to the second clock signal terminal;

[0044] The control electrode of the fifth transistor is electrically connected to the signal input terminal, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the first clock signal terminal;

[0045] A first end of the third capacitor is electrically connected to the second node, and a second end of the third capacitor is electrically connected to the fifth node.

[0046] In an exemplary embodiment, the node control subcircuit is also electrically connected to the third power supply terminal, and the node control subcircuit includes: a first node control subcircuit, a second node control subcircuit, a third node control subcircuit, and a fourth node control subcircuit;

[0047] The first node control subcircuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the first node and the fourth node respectively, and is configured to provide the signal of the second power supply terminal to the fourth node, provide the signal of the second clock signal terminal to the first node, and store the voltage difference between the signal of the first node and the signal of the first power supply terminal under the control of the signals of the first clock signal terminal, the second clock signal terminal and the second power supply terminal;

[0048] The second node control subcircuit is electrically connected to the first clock signal terminal, the signal input terminal, the second power terminal, the second node, the fifth node and the sixth node respectively, and is configured to provide the signal of the signal input terminal to the second node and the fifth node under the control of the signals of the first clock signal terminal, the second power terminal and the sixth node;

[0049] The third node control subcircuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the fourth node, the fifth node and the sixth node respectively, and is configured to provide the signal of the first clock signal terminal to the fourth node under the control of the signal of the fifth node, and to store the voltage difference between one of the first power supply terminal and the second clock signal terminal and the signal of the sixth node under the control of the signals of the fourth node and the sixth node;

[0050] The fourth node control subcircuit is electrically connected to the third power terminal, the first power terminal, the first node and the fifth node respectively, and is configured to provide a signal from the first power terminal to the first node under the control of signals from the fifth node and the third power terminal.

[0051] In an exemplary embodiment, the first node control subcircuit includes: a third transistor, a sixth transistor, a seventh transistor, an eleventh transistor, a first capacitor and a second capacitor, the second node control subcircuit includes: a first transistor, a twelfth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor, the third node control subcircuit includes: a second transistor, a fourth transistor, a fifth transistor and a third capacitor, and the fourth node control subcircuit includes: an eighth transistor and a thirteenth transistor;

[0052] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the fifth node;

[0053] The control electrode of the second transistor is electrically connected to the fifth node, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the first clock signal terminal;

[0054] A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the fourth node;

[0055] The control electrode of the fourth transistor is electrically connected to the sixth node, the first electrode of the fourth transistor is electrically connected to the seventh node, and the second electrode of the fourth transistor is electrically connected to the second clock signal terminal;

[0056] a control electrode of the fifth transistor is electrically connected to the fourth node, a first electrode of the fifth transistor is electrically connected to the first power supply terminal, and a second electrode of the fifth transistor is electrically connected to the seventh node;

[0057] The control electrode of the sixth transistor is electrically connected to the eighth node, the first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the third node;

[0058] The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is electrically connected to the third node, and the second electrode of the seventh transistor is electrically connected to the first node;

[0059] The control electrode of the eighth transistor is electrically connected to the fifth node, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the first power supply terminal;

[0060] The control electrode of the eleventh transistor is electrically connected to the second power supply terminal, the first electrode of the eleventh transistor is electrically connected to the fourth node, and the second electrode of the eleventh transistor is electrically connected to the eighth node;

[0061] The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the fifth node, and the second electrode of the twelfth transistor is electrically connected to the second node;

[0062] The control electrode of the thirteenth transistor is electrically connected to the third power supply terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the fifth node;

[0063] The control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourteenth transistor is electrically connected to the signal input terminal, and the second electrode of the fourteenth transistor is electrically connected to the ninth node;

[0064] The control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, the first electrode of the fifteenth transistor is electrically connected to the ninth node, and the second electrode of the fifteenth transistor is electrically connected to the sixth node;

[0065] The control electrode of the sixteenth transistor is electrically connected to the sixth node, the first electrode of the sixteenth transistor is electrically connected to the second node, and the second electrode of the sixteenth transistor is electrically connected to the sixth node;

[0066] A first end of the first capacitor is electrically connected to the eighth node, and a second end of the first capacitor is electrically connected to the third node;

[0067] A first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the first power supply terminal;

[0068] A first end of the third capacitor is electrically connected to the seventh node, and a second end of the third capacitor is electrically connected to the sixth node.

[0069] In an exemplary embodiment, the cascade output subcircuit includes: a ninth transistor and a tenth transistor, and the voltage stabilization subcircuit includes: a fourth capacitor;

[0070] The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the first power supply terminal, and the second electrode of the ninth transistor is electrically connected to the cascade output signal terminal;

[0071] The control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the cascade output signal terminal, and the second electrode of the tenth transistor is electrically connected to the second power supply terminal;

[0072] A first end of the fourth capacitor is electrically connected to the cascade output signal end, and a second end of the fourth capacitor is electrically connected to the second power supply end.

[0073] In an exemplary embodiment, the gating subcircuit includes: a first control subcircuit, a second control subcircuit, a third control subcircuit, a fourth control subcircuit, and a driving gating subcircuit;

[0074] The first control subcircuit is electrically connected to the masking signal terminal, the first control signal terminal, the first power supply terminal and the tenth node respectively, and is configured to provide a signal from the first power supply terminal to the tenth node under the control of the signals from the masking signal terminal and the first control signal terminal;

[0075] The second control subcircuit is electrically connected to the second control signal terminal, the third control signal terminal, the second power supply terminal and the tenth node respectively, and is configured to provide a signal from the second power supply terminal to the tenth node under the control of the signals from the second control signal terminal and the third control signal terminal;

[0076] The third control subcircuit is electrically connected to the first node, the tenth node, the eleventh node and the second power supply terminal respectively, and is configured to provide the signal of the first node to the eleventh node under the control of the signal of the tenth node, and store the voltage difference between the signal of the tenth node and the signal of the second power supply terminal;

[0077] The fourth control subcircuit is electrically connected to the driving output signal terminal, the masking signal terminal, the first power supply terminal and the eleventh node respectively, and is configured to provide a signal of the first power supply terminal to the eleventh node under the control of the signals of the driving output signal terminal and the masking signal terminal;

[0078] The drive selection subcircuit is electrically connected to the second node, the eleventh node, the first power supply terminal, the second power supply terminal and the drive output signal terminal, respectively, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the drive output signal terminal under the control of the signals of the second node and the eleventh node, and store a voltage difference between the signals of the eleventh node and the first power supply terminal.

[0079] In an exemplary embodiment, the first control subcircuit includes: a seventeenth transistor and an eighteenth transistor, the second control subcircuit includes: a nineteenth transistor and a twenty-third transistor, the third control subcircuit includes: a twenty-first transistor and a fifth capacitor, the fourth control subcircuit includes: a twenty-second transistor and a twenty-third transistor, and the drive gating subcircuit includes: a twenty-fourth transistor, a twenty-fifth transistor and a sixth capacitor;

[0080] The control electrode of the seventeenth transistor is electrically connected to the masked signal terminal, the first electrode of the seventeenth transistor is electrically connected to the tenth node, and the second electrode of the seventeenth transistor is electrically connected to the twelfth node;

[0081] The control electrode of the eighteenth transistor is electrically connected to the first control signal terminal, the first electrode of the eighteenth transistor is electrically connected to the twelfth node, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal;

[0082] The control electrode of the nineteenth transistor is electrically connected to the second control signal terminal, the first electrode of the nineteenth transistor is electrically connected to the tenth node, and the second electrode of the nineteenth transistor is electrically connected to the thirteenth node;

[0083] The control electrode of the twentieth transistor is electrically connected to the third control signal terminal, the first electrode of the twentieth transistor is electrically connected to the thirteenth node, and the second electrode of the twentieth transistor is electrically connected to the second power supply terminal;

[0084] a control electrode of the twenty-first transistor is electrically connected to the tenth node, a first electrode of the twenty-first transistor is electrically connected to the first node, and a second electrode of the twenty-first transistor is electrically connected to the eleventh node;

[0085] The control electrode of the twenty-second transistor is electrically connected to the driving output signal terminal, the first electrode of the twenty-second transistor is electrically connected to the eleventh node, and the second electrode of the twenty-second transistor is electrically connected to the fourteenth node;

[0086] The control electrode of the twenty-third transistor is electrically connected to the masking signal terminal, the first electrode of the twenty-third transistor is electrically connected to the fourteenth node, and the second electrode of the twenty-third transistor is electrically connected to the first power supply terminal;

[0087] A control electrode of the twenty-fourth transistor is electrically connected to the eleventh node, a first electrode of the twenty-fourth transistor is electrically connected to the first power supply terminal, and a second electrode of the twenty-fourth transistor is electrically connected to the drive output signal terminal;

[0088] The control electrode of the twenty-fifth transistor is electrically connected to the second node, the first electrode of the twenty-fifth transistor is electrically connected to the driving output signal terminal, and the second electrode of the twenty-fifth transistor is electrically connected to the second power supply terminal;

[0089] A first end of the fifth capacitor is electrically connected to the tenth node, and a second end of the fifth capacitor is electrically connected to the second power supply terminal;

[0090] A first end of the sixth capacitor is electrically connected to the eleventh node, and a second end of the sixth capacitor is electrically connected to the first power supply terminal.

[0091] In an exemplary embodiment, the cascade sub-circuit includes: a third node, the signal received by the first control signal terminal of at least one stage of the shift register is the same as the signal of the third node, or the signal received by the first control signal terminal of at least one stage of the shift register is the same as the signal of the third node of the first M stages of the shift register, and M is a positive integer greater than or equal to 1.

[0092] In an exemplary embodiment, the signal received by the second control signal terminal of at least one shift register is the same as the signal at the cascade output signal terminal, or the signal received by the second control signal terminal of at least one shift register is the same as the signal at the cascade output signal terminal of the first N shift registers, where N is a positive integer greater than or equal to 1.

[0093] In an exemplary embodiment, the signal received by the third control signal terminal of at least one stage of the shift register is the same as the signal of the second node.

[0094] In an exemplary embodiment, it includes: a plurality of cascaded shift registers as described above;

[0095] The cascade output signal terminal of at least one stage of shift register is connected to the signal input terminal of at least one stage of shift register other than the current stage of shift register.

[0096] In an exemplary embodiment, it further includes: an initial shift register, the initial shift register including: a cascade sub-circuit in at least one stage of the shift register, and the cascade output signal terminal of the initial shift register is electrically connected to the signal input terminal of the first stage of the shift register.

[0097] In a third aspect, the present disclosure further provides a display substrate having a display area and a non-display area located at least on one side of the display area, the non-display area being provided with the above-mentioned gate driving circuit, and the display area further comprising: sub-pixels arranged in an array;

[0098] The driving output signal terminal of at least one stage of shift register in the gate driving circuit is electrically connected to at least one row of sub-pixels.

[0099] In a fourth aspect, the present disclosure further provides a shift register driving method, which is configured to drive the above-mentioned shift register, and the method comprises:

[0100] The cascade subcircuit provides the signal of the second clock signal terminal to the first node and the signal of the signal input terminal to the second node under the control of the signals of the signal input terminal, the first clock signal terminal and the second clock signal terminal, and provides the signal of the first power supply terminal or the second power supply terminal to the cascade output signal terminal under the control of the signals of the first node and the second node;

[0101] The gating subcircuit provides a signal from the first power supply terminal or the second power supply terminal to the driving output signal terminal under the control of the signals from the masking signal terminal, the first control signal terminal, the second control signal terminal, the third control signal terminal, the first node and the second node.

[0102] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0103] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0104] Figure 1 is a structural schematic diagram of a display device;

[0105] Figure 2A A schematic diagram of a planar structure of a display substrate Figure 1 ;

[0106] Figure 2B FIG2 is a second schematic diagram of a planar structure of a display substrate;

[0107] Figure 2C A schematic diagram of a planar structure of a display substrate Figure 3 ;

[0108] Figure 3 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0109] Figure 4 for Figure 3 The working timing diagram of the pixel driving circuit provided;

[0110] Figure 5 A schematic diagram of the structure of a shift register provided in an embodiment of the present disclosure;

[0111] Figure 6 is a schematic diagram of the structure of the cascade sub-circuit;

[0112] Figure 7 A schematic diagram of a cascaded subcircuit structure provided for an exemplary embodiment Figure 1 ;

[0113] Figure 8 for Figure 7 Equivalent circuit diagram of the corresponding cascaded subcircuit;

[0114] Fig. 9 A second structural diagram of a cascade sub-circuit provided for an exemplary embodiment;

[0115] Fig.10 for Fig. 9 Equivalent circuit diagram of the corresponding cascaded subcircuit;

[0116] Fig.11 A schematic diagram of a cascaded subcircuit structure provided for an exemplary embodiment Figure 3 ;

[0117] Fig.12 for Fig.11 Equivalent circuit diagram of the corresponding cascaded subcircuit;

[0118] Fig.13 is a schematic diagram of the structure of the gating subcircuit;

[0119] Fig.14 is the equivalent circuit diagram of the gating subcircuit;

[0120] Fig.15 is an equivalent circuit diagram of a shift register;

[0121] Fig.16 is an equivalent circuit diagram of another shift register;

[0122] Fig.17 is an equivalent circuit diagram of another shift register;

[0123] Fig.18 for Figure 8 , Fig.10 and Fig.12 A timing diagram of the cascaded subcircuits in the shift register is provided;

[0124] Fig.19 for Figure 8 , Fig.10 and Fig.12 A timing diagram of the operation of a gating subcircuit in a shift register in a first display mode is provided;

[0125] Fig. 20 for Figure 8 , Fig.10 and Fig.12 A timing diagram of the operation of a gating subcircuit in a shift register in a second display mode is provided;

[0126] Fig.21 for Figure 8 , Fig.10 and Fig.12 Provided is the working timing diagram of the shift register in display mode switching. DETAILED DESCRIPTION

[0127] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings hereinafter. Note that the embodiments can be implemented in a number of different forms. A person of ordinary skill in the relevant technical field can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0128] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0129] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0130] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0131] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0132] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0133] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0134] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0135] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1 As shown, the display device may include a timing controller, a data driver, a gate driver and a pixel array, the timing controller is respectively connected to the data driver and the gate driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), and the gate driver is respectively connected to a plurality of gate lines (G1 to Gm). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively connected to the gate line and the data signal line.

[0136] In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver, and a clock signal, an emission stop signal, etc. suitable for the specifications of the light emitting driver to the light emitting driver. The data driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data driver may sample the grayscale value using the clock signal, and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.

[0137] In an exemplary embodiment, the gate driver may generate a scan signal to be provided to the gate line by receiving a clock signal, a gate start signal, etc. from a timing controller. For example, the scan driver may sequentially provide a scan signal having an on-level pulse to the gate line. For example, the gate driver may be configured in the form of a shift register, and may sequentially transmit a scan start signal provided in the form of an on-level pulse to a next-level circuit under the control of a clock signal to generate a scan signal.

[0138] Figure 2A A schematic diagram of a planar structure of a display substrate Figure 1 , Figure 2B FIG2 is a schematic diagram of a planar structure of a display substrate. Figure 2C A schematic diagram of a planar structure of a display substrate Figure 3 .like FIG. 2A to FIG. 2C As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, and the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the gate line and the data signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the gate line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which they are located.

[0139] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 may be a green subpixel (G) emitting green light.

[0140] In an exemplary embodiment, the shape of the sub-pixel may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged horizontally, vertically or in a herringbone pattern, which is not limited in the present disclosure.

[0141] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a herringbone pattern, which is not limited in the present disclosure. Figure 2A and Figure 2B The description is made by taking an example where a pixel unit includes three sub-pixels. Figure 2A The three sub-pixels in the image are arranged horizontally. Figure 2B The three sub-pixels are arranged in a herringbone pattern.

[0142] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure. Figure 2C The description is made by taking an example where a pixel unit includes four sub-pixels, and the four sub-pixels are arranged in a square.

[0143] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure, which is not limited in the present disclosure.

[0144] Figure 3 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 3As shown, the pixel driving circuit may include 7 transistors (first transistor M1 to seventh transistor M7) and 1 capacitor C. Among them, the gate electrode of the first transistor M1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor M1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor M1 is electrically connected to the first node N1 or the third node N3; the gate electrode of the second transistor M2 is electrically connected to the second scan signal line Gate2, the first electrode of the second transistor M2 is electrically connected to the first node N1, and the second electrode of the second transistor M2 is electrically connected to the third node N3; the gate electrode of the third transistor M3 is electrically connected to the first node N1, the first electrode of the third transistor M3 is electrically connected to the second node N2, and the second electrode of the third transistor M3 is electrically connected to the third node N3; the gate electrode of the fourth transistor M4 is electrically connected to the first scan signal line Gate1, and the first electrode of the fourth transistor M4 is electrically connected to the data signal line Data. , the second electrode of the fourth transistor M4 is electrically connected to the second node N2; the gate electrode of the fifth transistor M5 is electrically connected to the light emitting signal line EM, the first electrode of the fifth transistor M5 is electrically connected to the high-level power supply line VDD, and the second electrode of the fifth transistor M5 is electrically connected to the second node N2; the gate electrode of the sixth transistor M6 is electrically connected to the light emitting signal line EM, the first electrode of the sixth transistor M6 is electrically connected to the third node N3, and the second electrode of the sixth transistor M6 is electrically connected to the fourth node N4; the gate electrode of the seventh transistor M7 is electrically connected to the second reset signal line Reset2, the first electrode of the seventh transistor M7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor M7 is electrically connected to the fourth node N4; the first plate of the capacitor C is electrically connected to the first node N1, and the second plate of the capacitor C is electrically connected to the high-level power supply line VDD. Figure 3 The description is made by taking the example that the second electrode of the first transistor M1 is electrically connected to the first node N1.

[0145] In an exemplary embodiment, the signal of the second reset signal line Reset2 may be the same as the signal of the first scan signal line Gate1 , or may also be the same as the signal of the first reset signal line Reset1 .

[0146] In an exemplary embodiment, the first transistor M1 to the seventh transistor M7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active pattern of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (Low Temperature Poly-Silicon, referred to as LTPS), and the active pattern of the oxide thin film transistor adopts an oxide semiconductor (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current. The low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form an LTPO display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0147] In an exemplary embodiment, at least one of the first transistor M1 and the second transistor M2 is opposite to the transistor type of at least one of the third transistor M3 to the seventh transistor M7. Exemplarily, the first transistor M1 and the second transistor M2 may be N-type transistors, and the third transistor M3 to the seventh transistor M7 may be P-type transistors, or the second transistor M2 may be an N-type transistor, and the first transistor M1 and the third transistor M3 to the seventh transistor M7 may be P-type transistors.

[0148] In an exemplary embodiment, the N-type transistor may be an oxide transistor, and the P-type transistor may be a low temperature polysilicon transistor.

[0149] In an exemplary embodiment, the voltage value of the signal of the first initial signal line INIT1 is constant and is a DC signal. The voltage value of the signal of the first initial signal line INIT1 may be -3V.

[0150] In an exemplary embodiment, the voltage value of the signal of the second initial signal line INIT2 is constant and is a DC signal. The voltage value of the signal of the second initial signal line INIT2 may be 0V.

[0151] In an exemplary embodiment, the light emitting device L′ may be electrically connected to the fourth node N4 and the low-level power line VSS, respectively.

[0152] In an exemplary embodiment, the high-level power line VDD continuously provides a high-level signal, and the low-level power line VSS continuously provides a low-level signal.

[0153] Figure 4 for Figure 3 The working timing diagram of the pixel driving circuit provided is as follows. Figure 3 The operation process of the exemplary pixel driving circuit in the display phase is used to illustrate an exemplary embodiment of the present disclosure. Figure 4 The description is made by taking the second transistor M2 as an N-type transistor, the first transistor M1, the third transistor M3 to the seventh transistor M7 as P-type transistors, and the signal of the second reset signal line Reset2 being the same as the signal of the first reset signal line Reset1 as an example. Figure 3 The pixel driving circuit includes the first transistor M1 to the seventh transistor M7, a capacitor C and 9 signal lines (data signal line Data, a first scanning signal line Gate1, a second scanning signal line Gate2, a first reset signal line Reset1, a second reset signal line Reset2, a first initial signal line INIT1, a second initial signal line INIT2, a light emitting signal line EM and a high-level power line VDD).

[0154] Combination Figure 3 and Figure 4 As shown, the working process of the pixel driving circuit may include:

[0155] The first stage P1 is called the initialization stage. The signals of the first reset signal line Reset1 and the second reset signal line Reset2 are high-level signals. The first transistor M1 is turned on. The signal of the first initial signal line INIT1 is written into the first node N1 or the third node N3 through the turned-on first transistor M1, and the first node N1 or the third node N3 is initialized (reset), and the pre-stored voltage inside it is cleared to complete the initialization. The seventh transistor M7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4 through the turned-on seventh transistor M7, and the first electrode of the light-emitting device L is initialized (reset), and the pre-stored voltage inside it is cleared to complete the initialization.

[0156] The second stage P2 is called the data writing stage or the threshold compensation stage. The signal of the first scanning signal line Gate1 is a low level signal, the signal of the second scanning signal line Gate2 is a high level signal, and the data signal line Data outputs a data voltage. In this stage, since the first node N1 is a low level signal, the third transistor M3 is turned on. The signal of the first scanning signal line Gate1 is a low level signal, the fourth transistor M4 is turned on, the signal of the second scanning signal line Gate2 is a high level signal, the second transistor M2 is turned on, and the data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor M4, the second node N2, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage of the first node N1 is Vd-|Vth|, Vd is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the third transistor M3.

[0157] The third stage P3 is called the light-emitting stage. The signal of the light-emitting signal line EM is a low-level signal. The fifth transistor M5 and the sixth transistor M6 are turned on. The power supply voltage output by the high-level power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3 and the sixth transistor M6, thereby driving the light-emitting device L to emit light.

[0158] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor M3 is:

[0159] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0160] Among them, I is the driving current flowing through the third transistor M3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0161] In an exemplary embodiment, the light-emitting device L may include: any one of an organic light-emitting diode OLED, a quantum dot light-emitting diode, and an inorganic light-emitting diode. For example, the light-emitting device may be a micron-level light-emitting device, such as a micro light-emitting diode (Micro Light-Emitting Diode, referred to as Micro LED), a sub-millimeter light-emitting diode (Mini Light-Emitting Diode, referred to as Mini LED) or a micro organic light-emitting diode (Micro OLED), etc., and the embodiments of the present disclosure are not limited to this. For example, taking the light-emitting device L as an organic light-emitting diode (OLED) as an example, the light-emitting device may include: a stacked first electrode (for example, as an anode), an organic light-emitting layer, and a second electrode (for example, as a cathode).

[0162] In an exemplary embodiment, the organic light emitting layer may include a light emitting layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all sub-pixels may be a common layer connected together, and the light emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.

[0163] In an exemplary embodiment, the gate driver includes at least one gate driving circuit. The number of gate driving circuits depends on the gate signal line. Figure 3 Taking the display substrate of the provided pixel driving circuit as an example, the gate driving circuit includes: a first scanning driving circuit, a second scanning driving circuit and a light-emitting driving circuit. Among them, the first scanning driving circuit is electrically connected to the first scanning signal line, the first reset signal line and the second reset signal line. The second scanning driving circuit is electrically connected to the second scanning signal. The light-emitting driving circuit is electrically connected to the light-emitting signal line.

[0164] In an exemplary embodiment, any gate driving circuit in the gate driver may include: a plurality of cascaded shift registers.

[0165] The display product includes: a gate drive circuit and multiple sub-pixels. The sub-pixels include a pixel drive circuit. When the display product displays a picture, the gate drive circuit generates a drive signal, and the pixel drive circuit is initialized and data is written under the control of the drive signal to achieve display. When the display product displays, it will refresh the surface in each frame, that is, the pixel drive circuit needs to be initialized and data written in each display frame. For some special pictures (for example: off-screen display pictures, static pictures or less updated pictures, etc.), the pixel drive circuit does not need to be initialized and data written in at least some display frames, and the original brightness can be maintained by a low-leakage pixel drive circuit. The gate drive circuit of the display product will generate a drive signal in each frame regardless of the picture displayed, and repeatedly initialize and write data to the pixel drive circuit, so that the shift register cannot achieve different refresh rates in the same display area, resulting in high power consumption of the display product.

[0166] To this end, the present disclosure provides a shift register.

[0167] Figure 5 Schematic diagram of the structure of the shift register provided by the embodiment of the present disclosure. Figure 5 As shown, the shift register provided by the embodiment of the present disclosure includes: a cascade subcircuit and a gating subcircuit.

[0168] like Figure 5 As shown, the cascade sub-circuit is respectively connected to the signal input terminal IN, the first clock signal terminal CK, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL, the first node N1, the second node N2 and the cascade output signal terminal SOUT, and is configured to provide the signal of the second clock signal terminal CB to the first node N1 and the second node N2 under the control of the signals of the signal input terminal IN, the first clock signal terminal CK and the second clock signal terminal CB, and provide the signal of the signal input terminal IN to the second node N2, and provide the signal of the first power supply terminal VGH or the second power supply terminal VGL to the cascade output signal terminal SOUT under the control of the signals of the first node N1 and the second node N2.

[0169] like Figure 5 As shown, the gating sub-circuit is respectively connected to the first node N1, the second node N2, the masking signal terminal MS, the first control signal terminal G1, the second control signal terminal G2, the third control signal terminal G3, the first power supply terminal VGH, the second power supply terminal VGL and the driving output signal terminal NOUT, and is configured to provide a signal from the first power supply terminal VGH or the second power supply terminal VGL to the driving output signal terminal NOUT under the control of the signal from the masking signal terminal MS, the first control signal terminal G1, the second control signal terminal G2, the third control signal terminal G3, the first node N1 and the second node N2.

[0170] In an exemplary embodiment, the shift register provided by the present disclosure may be electrically connected to the second scanning signal line to which at least one row of pixel driving circuits is connected.

[0171] In an exemplary embodiment, the first power terminal VGH provides a first power signal, which is a high level signal, such as 5V to 10V. The second power terminal VGL provides a second power signal, which is a low level signal, such as -10V to -5V.

[0172] In an exemplary embodiment, the first power signal and the second power signal may be direct current signals.

[0173] In an exemplary embodiment, the signal of either the first clock signal terminal CK or the second clock signal terminal CB is a square wave signal that repeats high voltage and low voltage. Exemplarily, the signal of the first clock signal terminal CK and the second clock signal terminal CB may have the same period and may be configured as a phase-shifted signal. Here, the signal of the second clock signal terminal CB may be phase-shifted by half a period compared to the signal of the first clock signal terminal CK. The high voltage period of the signal of either the first clock signal terminal CK or the second clock signal terminal CB in each period may be set to be longer than the low voltage period.

[0174] In an exemplary embodiment, the signal at the masking signal terminal MS may be a low level signal or a high level signal. When the signal at the masking signal terminal MS is a low level signal, it may be -20V to -5V, and when the signal at the masking signal terminal MS is a high level signal, it may be 5V to 20V.

[0175] The present invention realizes that the cascade signal and the drive signal are output by different sub-circuits by setting a cascade sub-circuit to output a cascade signal provided by other shift registers to a cascade output signal terminal, and setting a selection sub-circuit to output a drive signal provided by a pixel drive circuit to a drive signal output terminal, thereby ensuring that the cascade signal and the drive signal are output by different sub-circuits. Whether to output the drive signal to the pixel drive circuit can be controlled while ensuring the normal output of the cascade signal.

[0176] The shift register provided by the present invention can control the enabling subcircuit according to the signal of the masking signal end according to the refresh rate requirement of the display area through the cooperation of the cascade subcircuit and the enabling subcircuit, so as to realize the control of the signal output by the driving signal output end, and realize different refresh rates in different display areas, that is, the coexistence of high and low refresh rates can be realized in the same frame image, and the embodiments of the present invention are not limited to realizing different refresh rates in a fixed area of ​​the display panel, and can realize dynamic refresh of any area, thereby reducing the power consumption of the display panel.

[0177] Figure 6 is a schematic diagram of the structure of the cascade subcircuit. Figure 6 As shown, in an exemplary embodiment, the cascade subcircuit includes: a node control subcircuit, a cascade output subcircuit and a voltage regulation subcircuit.

[0178] like Figure 6 As shown, the node control subcircuit is electrically connected to the signal input terminal IN, the first clock signal terminal CK, the second clock signal terminal CB and the first node N1 and the second node N2, respectively, and is configured to provide the signal of the second clock signal terminal CB to the first node N1 and provide the signal of the signal input terminal IN to the second node N2 under the control of the signals of the signal input terminal IN, the first clock signal terminal CK and the second clock signal terminal CB.

[0179] like Figure 6 As shown, the cascade output sub-circuit is electrically connected to the first node N1, the second node N2, the first power supply terminal VGH, the second power supply terminal VGL and the cascade output signal terminal SOUT, respectively, and is configured to provide a signal from the first power supply terminal VGH or the second power supply terminal VGL to the cascade output signal terminal SOUT under the control of the signals from the first node N1 and the second node N2.

[0180] like Figure 6As shown, the voltage stabilizing sub-circuit is electrically connected to the cascade output signal terminal SOUT and the second power supply terminal VGL, respectively, and is configured to store a voltage difference between the signals of the cascade output signal terminal SOUT and the second power supply terminal VGL.

[0181] Figure 7 A schematic diagram of a cascaded subcircuit structure provided for an exemplary embodiment Figure 1 .like Figure 7 As shown, the node control subcircuit includes: a first node control subcircuit, a second node control subcircuit, a third node control subcircuit and a fourth node control subcircuit. Figure 7 As shown, the first node control subcircuit is electrically connected to the first clock signal terminal CK, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL, the first node N1 and the fourth node N4, respectively, and is configured to provide the signal of the second power supply terminal VGL to the fourth node N4, provide the signal of the second clock signal terminal CB to the first node N1, and store the voltage difference between the signal of the first node N1 and the signal of the first power supply terminal VGH under the control of the signal of the first clock signal terminal CK and the second clock signal terminal CB. The second node control subcircuit is electrically connected to the first clock signal terminal CK, the signal input terminal IN and the second node N2, respectively, and is configured to provide the signal of the signal input terminal IN to the second node N2 under the control of the signal of the first clock signal terminal CK. The third node control subcircuit is electrically connected to the first clock signal terminal CK, the second node N2 and the fourth node N4, respectively, and is configured to provide the signal of the first clock signal terminal CK to the fourth node N4 under the control of the signal of the second node N2. The fourth node control sub-circuit is electrically connected to the first clock signal terminal CK, the second clock signal terminal CB, the first node N1 and the second node N2, respectively, and is configured to provide the signal of the first clock signal terminal CK to the first node N1 under the control of the signal of the second node N2, and store the voltage values ​​of the signals of the second node N2 and the second clock signal terminal CB.

[0182] Figure 8 for Figure 7 The equivalent circuit diagram of the corresponding cascade subcircuit. Figure 8 As shown, in Figure 7In the corresponding cascade subcircuit, the first node control subcircuit includes: a third transistor T3, a sixth transistor T6, a seventh transistor T7, a first capacitor C1 and a second capacitor C2. The control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third transistor T3 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the fourth node N4, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CB, and the second electrode of the sixth transistor T6 is electrically connected to the third node N3; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1; the first end of the first capacitor C1 is electrically connected to the fourth node N4, and the second end of the first capacitor C1 is electrically connected to the third node N3; the first end of the second capacitor C2 is electrically connected to the first node N1, and the second end of the second capacitor C2 is electrically connected to the first power supply terminal VGH.

[0183] like Figure 8 As shown, the second node control subcircuit includes: a first transistor T1, wherein the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the second node N2.

[0184] like Figure 8 As shown, the third node control subcircuit includes: a second transistor T2, wherein the control electrode of the second transistor T2 is electrically connected to the second node N2, the first electrode of the second transistor T2 is electrically connected to the fourth node N4, and the second electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK.

[0185] like Figure 8 As shown, the fourth node control subcircuit includes: a fourth transistor T4, a fifth transistor T5 and a third capacitor C3. Among them, the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the fifth node N5, and the second electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CB; the control electrode of the fifth transistor T5 is electrically connected to the second node N2, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the first clock signal terminal CK; the first end of the third capacitor C3 is electrically connected to the second node N2, and the second end of the third capacitor C3 is electrically connected to the fifth node N5.

[0186] Fig. 9 FIG2 is a structural schematic diagram of a cascade subcircuit provided in an exemplary embodiment. Fig. 9As shown, the node control subcircuit includes: a first node control subcircuit, a second node control subcircuit, a third node control subcircuit and a fourth node control subcircuit.

[0187] like Fig. 9 As shown, the first node control subcircuit is electrically connected to the first clock signal terminal CK, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL, the first node N1 and the fourth node N4, respectively, and is configured to provide the signal of the second power supply terminal VGL to the fourth node N4, provide the signal of the second clock signal terminal CB to the first node N1, and store the voltage difference between the signal of the first node N1 and the signal of the first power supply terminal VGH under the control of the signal of the first clock signal terminal CK and the second clock signal terminal CB. The second node control subcircuit is electrically connected to the first clock signal terminal CK, the signal input terminal IN and the second node N2, respectively, and is configured to provide the signal of the signal input terminal IN to the second node N2 under the control of the signal of the first clock signal terminal CK. The third node control subcircuit is electrically connected to the first clock signal terminal CK, the signal input terminal IN and the fourth node N4, respectively, and is configured to provide the signal of the first clock signal terminal CK to the fourth node N4 under the control of the signal of the signal input terminal IN. The fourth node control sub-circuit is electrically connected to the signal input terminal IN, the first clock signal terminal CK, the second clock signal terminal CB, the first node N1 and the second node N2, respectively, and is configured to be under the control of the signal of the second node N2 and store the voltage difference between the signal of the second clock signal terminal CB and the signal of the second node N2, and under the control of the signal of the signal input terminal IN, provide the signal of the first clock signal terminal CK to the first node N1.

[0188] Fig.10 for Fig. 9 The equivalent circuit diagram of the corresponding cascade subcircuit. Fig.10 As shown, in Fig. 9In the corresponding cascade subcircuit, the first node control subcircuit includes: a third transistor T3, a sixth transistor T6, a seventh transistor T7, a first capacitor C1 and a second capacitor C2. The control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third transistor T3 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the fourth node N4, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CB, and the second electrode of the sixth transistor T6 is electrically connected to the third node N3; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1; the first end of the first capacitor C1 is electrically connected to the fourth node N4, and the second end of the first capacitor C1 is electrically connected to the third node N3; the first end of the second capacitor C2 is electrically connected to the first node N1, and the second end of the second capacitor C2 is electrically connected to the first power supply terminal VGH.

[0189] like Fig.10 As shown, the second node control subcircuit includes: a first transistor T1, wherein the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the second node N2.

[0190] like Fig.10 As shown, the third node control subcircuit includes: a second transistor T2, wherein the control electrode of the second transistor T2 is electrically connected to the signal input terminal IN, the first electrode of the second transistor T2 is electrically connected to the fourth node N4, and the second electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK.

[0191] like Fig.10 As shown, the fourth node control subcircuit includes: a fourth transistor T4, a fifth transistor T5 and a third capacitor C3. Among them, the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the fifth node N5, and the second electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CB; the control electrode of the fifth transistor T5 is electrically connected to the signal input terminal IN, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the first clock signal terminal CK; the first end of the third capacitor C3 is electrically connected to the second node N2, and the second end of the third capacitor C3 is electrically connected to the fifth node N5.

[0192] Fig.11 A schematic diagram of a cascaded subcircuit structure provided for an exemplary embodiment Figure 3 .like Fig.11As shown, the node control subcircuit is also electrically connected to the third power supply terminal NCX, and the node control subcircuit includes: a first node control subcircuit, a second node control subcircuit, a third node control subcircuit and a fourth node control subcircuit.

[0193] like Fig.11 As shown, the first node control subcircuit is electrically connected to the first clock signal terminal CK, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL, the first node N1 and the fourth node N4, respectively, and is configured to provide the signal of the second power supply terminal VGL to the fourth node N4 and the signal of the second clock signal terminal CB to the first node N1 under the control of the signals of the first clock signal terminal CK, the second clock signal terminal CB and the second power supply terminal VGL, and store the voltage difference between the signals of the first node N1 and the first power supply terminal VGH; the second node control subcircuit is electrically connected to the first clock signal terminal CK, the signal input terminal IN, the second power supply terminal VGL, the second node N2, the fifth node N5 and the sixth node N6, respectively, and is configured to provide the signal of the second power supply terminal VGL to the fourth node N4 and the first node N1 under the control of the signals of the first clock signal terminal CK, the second clock signal terminal CB and the second power supply terminal VGL, and store the voltage difference between the signals of the first node N1 and the first power supply terminal VGH. 2 and the fifth node N5 provide the signal of the signal input terminal IN; the third node control sub-circuit is electrically connected to the first clock signal terminal CK, the second clock signal terminal CB, the first power supply terminal VGH, the fourth node N4, the fifth node N5 and the sixth node N6, respectively, and is configured to provide the signal of the first clock signal terminal CK to the fourth node N4 under the control of the signal of the fifth node N5, and under the control of the signals of the fourth node N4 and the sixth node N6, and store the voltage difference between the signal of one of the first power supply terminal VGH and the second clock signal terminal CB and the signal of the sixth node N6; the fourth node control sub-circuit is electrically connected to the third power supply terminal NCX, the first power supply terminal VGH, the first node N1 and the fifth node N5, respectively, and is configured to provide the signal of the first power supply terminal VGH to the first node N1 under the control of the signals of the fifth node N5 and the third power supply terminal NCX.

[0194] Fig.12 for Fig.11 The equivalent circuit diagram of the corresponding cascade subcircuit. Fig.12As shown, the first node control subcircuit includes: a third transistor T3, a sixth transistor T6, a seventh transistor T7, an eleventh transistor T11, a first capacitor C1 and a second capacitor C2. Among them, the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third transistor T3 is electrically connected to the fourth node N4; the control electrode of the sixth transistor T6 is electrically connected to the eighth node N8, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CB, and the second electrode of the sixth transistor T6 is electrically connected to the third node N3; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1; the control electrode of the eleventh transistor T11 is electrically connected to the second power supply terminal VGL, the first electrode of the eleventh transistor T11 is electrically connected to the fourth node N4, and the second electrode of the eleventh transistor T11 is electrically connected to the eighth node N8; the first end of the first capacitor C1 is electrically connected to the eighth node N8, and the second end of the first capacitor C1 is electrically connected to the third node N3; the first end of the second capacitor C2 is electrically connected to the first node N1, and the second end of the second capacitor C2 is electrically connected to the first power supply terminal VGH.

[0195] like Fig.12 As shown, the second node control subcircuit includes: a first transistor T1, a twelfth transistor T12, a fourteenth transistor T14, a fifteenth transistor T15 and a sixteenth transistor T16. Among them, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the fifth node N5; the control electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal VGL, the first electrode of the twelfth transistor T12 is electrically connected to the fifth node N5, and the second electrode of the twelfth transistor T12 is electrically connected to the second node N2; the control electrode of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CK, the first electrode of the fourteenth transistor T14 is electrically connected to the signal input terminal IN, and the second electrode of the fourteenth transistor T14 is electrically connected to the ninth node N9; the control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, the first electrode of the fifteenth transistor T15 is electrically connected to the ninth node N9, and the second electrode of the fifteenth transistor T15 is electrically connected to the sixth node N6; the control electrode of the sixteenth transistor T16 is electrically connected to the sixth node N6, the first electrode of the sixteenth transistor T16 is electrically connected to the second node N2, and the second electrode of the sixteenth transistor T16 is electrically connected to the sixth node N6.

[0196] like Fig.12As shown, the third node control subcircuit includes: a second transistor T2, a fourth transistor T4, a fifth transistor T5 and a third capacitor C3. Among them, the control electrode of the second transistor T2 is electrically connected to the fifth node N5, the first electrode of the second transistor T2 is electrically connected to the fourth node N4, and the second electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK; the control electrode of the fourth transistor T4 is electrically connected to the sixth node N6, the first electrode of the fourth transistor T4 is electrically connected to the seventh node N7, and the second electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CB; the control electrode of the fifth transistor T5 is electrically connected to the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VGH, and the second electrode of the fifth transistor T5 is electrically connected to the seventh node N7; the first end of the third capacitor C3 is electrically connected to the seventh node N7, and the second end of the third capacitor C3 is electrically connected to the sixth node N6.

[0197] like Fig.12 As shown, the fourth node control subcircuit includes: an eighth transistor T8 and a thirteenth transistor T13. Among them, the control electrode of the eighth transistor T8 is electrically connected to the fifth node N5, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the first power supply terminal VGH; the control electrode of the thirteenth transistor T13 is electrically connected to the third power supply terminal NCX, the first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal VGH, and the second electrode of the thirteenth transistor T13 is electrically connected to the fifth node N5.

[0198] In an exemplary embodiment, the third power supply terminal NCX is a low level signal in the power-on initialization stage to prevent the ninth transistor T9 and the tenth transistor T10 of the last stage control shift register from being turned on at the same time due to the delay of the output signal, or is a low level signal in the abnormal shutdown stage to prevent the ninth transistor T9 and the tenth transistor T10 from being turned on at the same time. The fifth power supply terminal NCX continuously provides a high level signal in the normal display stage, that is, in the normal display stage, the thirteenth transistor T13 is turned off.

[0199] Fig.13 Figure 1 is a schematic diagram of the structure of the gating subcircuit. Fig.13 As shown, in an exemplary embodiment, the gating subcircuit may include: a first control subcircuit, a second control subcircuit, a third control subcircuit, a fourth control subcircuit and a driving gating subcircuit.

[0200] like Fig.13 As shown, the first control sub-circuit is electrically connected to the masking signal terminal MS, the first control signal terminal G1, the first power supply terminal VGH and the tenth node N10, respectively, and is configured to provide a signal of the first power supply terminal VGH to the tenth node N10 under the control of the signals of the masking signal terminal MS and the first control signal terminal G1.

[0201] like Fig.13 As shown, the second control sub-circuit is electrically connected to the second control signal terminal G2, the third control signal terminal G3, the second power supply terminal VGL and the tenth node N10, respectively, and is configured to provide a signal from the second power supply terminal VGL to the tenth node N10 under the control of the signals from the second control signal terminal G2 and the third control signal terminal G3.

[0202] like Fig.13 As shown, the third control subcircuit is electrically connected to the first node N1, the tenth node N10, the eleventh node N11 and the second power supply terminal VGL, respectively, and is configured to provide the signal of the first node N1 to the eleventh node N11 under the control of the signal of the tenth node N10, and store the voltage difference between the signal of the tenth node N10 and the second power supply terminal VGL.

[0203] like Fig.13 As shown, the fourth control sub-circuit is electrically connected to the driving output signal terminal NOUT, the masking signal terminal MS, the first power supply terminal VGH and the eleventh node N11, respectively, and is configured to provide a signal of the first power supply terminal VGH to the eleventh node N11 under the control of the signals of the driving output signal terminal NOUT and the masking signal terminal MS.

[0204] like Fig.13 As shown, the driving selection sub-circuit is electrically connected to the second node N2, the eleventh node N11, the first power supply terminal VGH, the second power supply terminal VGL and the driving output signal terminal NOUT, respectively, and is configured to provide a signal of the first power supply terminal VGH or the second power supply terminal VGL to the driving output signal terminal NOUT under the control of the signals of the second node N2 and the eleventh node N11, and store the voltage difference between the signal of the eleventh node N11 and the first power supply terminal VGH.

[0205] Fig.14 is the equivalent circuit diagram of the gating subcircuit. Fig.14 As shown, the first control subcircuit in the gating subcircuit includes: a seventeenth transistor T17 and an eighteenth transistor T18. The control electrode of the seventeenth transistor T17 is electrically connected to the masking signal terminal MS, the first electrode of the seventeenth transistor T17 is electrically connected to the tenth node N10, and the second electrode of the seventeenth transistor T17 is electrically connected to the twelfth node N12; the control electrode of the eighteenth transistor T18 is electrically connected to the first control signal terminal G1, the first electrode of the eighteenth transistor T18 is electrically connected to the twelfth node N12, and the second electrode of the eighteenth transistor T18 is electrically connected to the first power supply terminal VGH.

[0206] like Fig.14As shown, the second control subcircuit in the gating subcircuit includes: a nineteenth transistor T19 and a twentieth transistor T20. The control electrode of the nineteenth transistor T19 is electrically connected to the second control signal terminal G2, the first electrode of the nineteenth transistor T19 is electrically connected to the tenth node N10, and the second electrode of the nineteenth transistor T19 is electrically connected to the thirteenth node N14; the control electrode of the twentieth transistor T20 is electrically connected to the third control signal terminal G3, the first electrode of the twentieth transistor T20 is electrically connected to the thirteenth node N14, and the second electrode of the twentieth transistor T20 is electrically connected to the second power supply terminal VGL.

[0207] like Fig.14 As shown, the third control subcircuit in the gating subcircuit includes: a twenty-first transistor T21 and a fifth capacitor C5. The control electrode of the twenty-first transistor T21 is electrically connected to the tenth node N10, the first electrode of the twenty-first transistor T21 is electrically connected to the first node N1, and the second electrode of the twenty-first transistor T21 is electrically connected to the eleventh node N11; the first end of the fifth capacitor C5 is electrically connected to the tenth node N10, and the second end of the fifth capacitor C5 is electrically connected to the second power supply terminal VGL.

[0208] The configuration of the fifth capacitor C5 in the present disclosure can ensure the stability of the signal of the tenth node N10 and improve the reliability of the shift register.

[0209] like Fig.14 As shown, the fourth control subcircuit in the gating subcircuit includes: a twenty-second transistor T22 and a twenty-third transistor T23. The control electrode of the twenty-second transistor T22 is electrically connected to the driving output signal terminal NOUT, the first electrode of the twenty-second transistor T22 is electrically connected to the eleventh node N11, and the second electrode of the twenty-second transistor T22 is electrically connected to the fourteenth node N14; the control electrode of the twenty-third transistor T23 is electrically connected to the masking signal terminal MS, the first electrode of the twenty-third transistor T23 is electrically connected to the fourteenth node N14, and the second electrode of the twenty-third transistor T23 is electrically connected to the first power supply terminal VGH.

[0210] like Fig.14As shown, the driving gating subcircuit in the gating subcircuit includes: a twenty-fourth transistor T24, a twenty-fifth transistor T25 and a sixth capacitor C6. Among them, the control electrode of the twenty-fourth transistor T24 is electrically connected to the eleventh node N11, the first electrode of the twenty-fourth transistor T24 is electrically connected to the first power supply terminal VGH, and the second electrode of the twenty-fourth transistor T24 is electrically connected to the driving output signal terminal NOUT; the control electrode of the twenty-fifth transistor T25 is electrically connected to the second node N2, the first electrode of the twenty-fifth transistor T25 is electrically connected to the driving output signal terminal NOUT, and the second electrode of the twenty-fifth transistor T25 is electrically connected to the second power supply terminal VGL; the first end of the sixth capacitor C6 is electrically connected to the eleventh node N11, and the second end of the sixth capacitor C6 is electrically connected to the first power supply terminal VGH.

[0211] The configuration of the sixth capacitor C6 in the present disclosure can ensure the stability of the signal at the eleventh node N11 and improve the reliability of the shift register.

[0212] In an exemplary embodiment, Figure 8 , Fig.10 and Fig.12 As shown, the cascade output subcircuit includes: a ninth transistor T9 and a tenth transistor T10. The control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth transistor T9 is electrically connected to the cascade output signal terminal SOUT; the control electrode of the tenth transistor T10 is electrically connected to the second node N2, the first electrode of the tenth transistor T10 is electrically connected to the cascade output signal terminal SOUT, and the second electrode of the tenth transistor T10 is electrically connected to the second power supply terminal VGL.

[0213] In an exemplary embodiment, Figure 8 , Fig.10 and Fig.12 As shown, the voltage stabilizing sub-circuit includes: a fourth capacitor C4. A first end of the fourth capacitor C4 is electrically connected to the cascade output signal terminal SOUT, and a second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VGL.

[0214] The setting of the fourth capacitor in the present disclosure can ensure the stability of the signal at the cascade output signal end, and is used to stabilize the input of the next-stage shift register, thereby preventing the input signal of the next-stage shift register from being unstable due to jitter during the transmission of the cascade signal output by the cascade output signal end, thereby improving the stability of the shift register.

[0215] Fig.15 is an equivalent circuit diagram of a shift register. Fig.15As shown, the cascade subcircuit in the shift register includes: the first transistor T1 to the sixteenth transistor T16 and the first capacitor C1 to the fourth capacitor C4, and the gating subcircuit in the shift register includes: the seventeenth transistor T17 to the twenty-fifth transistor T25, the fifth capacitor C5 and the sixth capacitor C6. Among them, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the fifth node N5; the control electrode of the second transistor T2 is electrically connected to the fifth node N5, the first electrode of the second transistor T2 is electrically connected to the fourth node N4, and the second electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third transistor T3 is electrically connected to the fourth node N4; The control electrode of the fourth transistor T4 is electrically connected to the sixth node N6, the first electrode of the fourth transistor T4 is electrically connected to the seventh node N7, and the second electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CB; the control electrode of the fifth transistor T5 is electrically connected to the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VGH, and the second electrode of the fifth transistor T5 is electrically connected to the seventh node N7; the control electrode of the sixth transistor T6 is electrically connected to the eighth node N8, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CB, and the second electrode of the sixth transistor T6 is electrically connected to the third node N3; the seventh transistor T7 is electrically connected to the fourth node N4, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VGH, and the second electrode of the fifth transistor T5 is electrically connected to the seventh node N7; The control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1; the control electrode of the eighth transistor T8 is electrically connected to the fifth node N5, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the first power supply terminal VGH; the control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth transistor T9 is electrically connected to the cascade output signal terminal SOUT; the control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the first power supply terminal VGH; a control electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal VGL, a first electrode of the twelfth transistor T12 is electrically connected to the fifth node N5, and a second electrode of the twelfth transistor T12 is electrically connected to the second node N2; a control electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal VGL, a first electrode of the twelfth transistor T12 is electrically connected to the fifth node N5, and a second electrode of the twelfth transistor T12 is electrically connected to the second node N2;The control electrode of the thirteenth transistor T13 is electrically connected to the third power supply terminal NCX, the first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal VGH, and the second electrode of the thirteenth transistor T13 is electrically connected to the fifth node N5; the control electrode of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CK, the first electrode of the fourteenth transistor T14 is electrically connected to the signal input terminal IN, and the second electrode of the fourteenth transistor T14 is electrically connected to the ninth node N9; the control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, the first electrode of the fifteenth transistor T15 is electrically connected to the ninth node N9, and the second electrode of the fifteenth transistor T15 is electrically connected to the sixth node N6; the control electrode of the sixteenth transistor T16 is electrically connected to the sixth node N6, the first electrode of the sixteenth transistor T16 is electrically connected to the second node N2, and the second electrode of the sixteenth transistor T16 is electrically connected to the sixth node N6; the control electrode of the seventeenth transistor T17 is electrically connected to the masking terminal VGL. The signal terminal MS is electrically connected, the first electrode of the seventeenth transistor T17 is electrically connected to the tenth node N10, and the second electrode of the seventeenth transistor T17 is electrically connected to the twelfth node N12; the control electrode of the eighteenth transistor T18 is electrically connected to the first control signal terminal G1, the first electrode of the eighteenth transistor T18 is electrically connected to the twelfth node N12, and the second electrode of the eighteenth transistor T18 is electrically connected to the first power supply terminal VGH; the control electrode of the nineteenth transistor T19 is electrically connected to the second control signal terminal G2, the first electrode of the nineteenth transistor T19 is electrically connected to the tenth node N10, and the second electrode of the nineteenth transistor T19 is electrically connected to the thirteenth node N13; the control electrode of the twentieth transistor T20 is electrically connected to the third control signal terminal G3, the first electrode of the twentieth transistor T20 is electrically connected to the thirteenth node N13, and the second electrode of the twentieth transistor T20 is electrically connected to the second power supply terminal VGL; the twenty-first transistor T21 and the fifth capacitor C5. wherein the control electrode of the twenty-first transistor T21 is electrically connected to the tenth node N10, the first electrode of the twenty-first transistor T21 is electrically connected to the first node N1, and the second electrode of the twenty-first transistor T21 is electrically connected to the eleventh node N11; the control electrode of the twenty-second transistor T22 is electrically connected to the drive output signal terminal NOUT, the first electrode of the twenty-second transistor T22 is electrically connected to the eleventh node N11, and the second electrode of the twenty-second transistor T22 is electrically connected to the fourteenth node N14; the control electrode of the twenty-third transistor T23 is electrically connected to the masking signal terminal MS, the first electrode of the twenty-third transistor T23 is electrically connected to the fourteenth node N14, and the second electrode of the twenty-third transistor T23 is electrically connected to the first power supply terminal VGH; the control electrode of the twenty-fourth transistor T24 is electrically connected to the eleventh node N11, the first electrode of the twenty-fourth transistor T24 is electrically connected to the first power supply terminal VGH, and the second electrode of the twenty-fourth transistor T24 is electrically connected to the drive output signal terminal NOUT;The control electrode of the twenty-fifth transistor T25 is electrically connected to the second node N2, the first electrode of the twenty-fifth transistor T25 is electrically connected to the driving output signal terminal NOUT, and the second electrode of the twenty-fifth transistor T25 is electrically connected to the second power supply terminal VGL; the first end of the first capacitor C1 is electrically connected to the eighth node N8, and the second end of the first capacitor C1 is electrically connected to the third node N3; the first end of the second capacitor C2 is electrically connected to the first node N1, and the second end of the second capacitor C2 is electrically connected to the first power supply terminal VGH; the first end of the third capacitor C3 is electrically connected to the seventh node N7, and the second end of the third capacitor C3 is electrically connected to the sixth node N6; the first end of the fourth capacitor C4 is electrically connected to the cascade output signal terminal SOUT, and the second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VGL; the first end of the fifth capacitor C5 is electrically connected to the tenth node N10, and the second end of the fifth capacitor C5 is electrically connected to the second power supply terminal VGL; the first end of the sixth capacitor C6 is electrically connected to the eleventh node N11, and the second end of the sixth capacitor C6 is electrically connected to the first power supply terminal VGH.;

[0216] In an exemplary embodiment, Fig.15 The cascade sub-circuit is described by taking 16T4C as an example. The cascade sub-circuit may also be a circuit structure of 10T3C, 10T4C, 12T3C, 12T4C, 13T3C, 13T4C, 16T3C or 16T4C, and the present disclosure does not make any limitation on this.

[0217] In an exemplary embodiment, when the cascade sub-circuit is a circuit structure of 10T3C, the cascade sub-circuit includes: first to tenth transistors T1 to T10 and first to third capacitors C1 to C3.

[0218] In an exemplary embodiment, when the cascade sub-circuit is a 10T4C circuit structure, the cascade sub-circuit includes: first to tenth transistors T1 to T10 and first to fourth capacitors C1 to C4.

[0219] In an exemplary embodiment, when the cascade sub-circuit is a 12T3C circuit structure, the cascade sub-circuit includes: first to twelfth transistors T1 to T12 and first to third capacitors C1 to C3.

[0220] In an exemplary embodiment, when the cascade sub-circuit is a 12T4C circuit structure, the cascade sub-circuit includes: first to twelfth transistors T1 to T12 and first to third capacitors C1 to C3 and a fourth capacitor C4.

[0221] In an exemplary embodiment, when the cascade sub-circuit is a circuit structure of 13T3C, the cascade sub-circuit includes: first to thirteenth transistors T1 to T13 and first to third capacitors C1 to C3.

[0222] In an exemplary embodiment, when the cascade sub-circuit is a circuit structure of 13T4C, the cascade sub-circuit includes: first to thirteenth transistors T1 to T13 and first to fourth capacitors C1 to C4.

[0223] In an exemplary embodiment, when the cascade sub-circuit is a 16T3C circuit structure, the cascade sub-circuit includes: first to sixteenth transistors T1 to T16 and first to third capacitors C1 to C3.

[0224] Fig.15 is the equivalent circuit diagram of another shift register. Fig.15As shown, the cascade subcircuit in the shift register includes: the first transistor T1 to the seventh transistor T7, the ninth transistor T9, the tenth transistor T10 and the first capacitor C1 to the fourth capacitor C4, and the selection subcircuit in the shift register includes: the seventeenth transistor T17 to the twenty-fifth transistor T25, the fifth capacitor C5 and the sixth capacitor C6.Among them, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the second node N2; the control electrode of the second transistor T2 is electrically connected to the second node N2, the first electrode of the second transistor T2 is electrically connected to the fourth node N4, and the second electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third transistor T3 is electrically connected to the fourth node N4; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, and the fourth transistor T4 is electrically connected to the fourth node N4. The first electrode of the fourth transistor T4 is electrically connected to the fifth node N5, and the second electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CB; the control electrode of the fifth transistor T5 is electrically connected to the second node N2, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the first clock signal terminal CK; the control electrode of the sixth transistor T6 is electrically connected to the fourth node N4, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CB, and the second electrode of the sixth transistor T6 is electrically connected to the third node N3; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the first node N 1; the control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth transistor T9 is electrically connected to the cascade output signal terminal SOUT; the control electrode of the tenth transistor T10 is electrically connected to the second node N2, the first electrode of the tenth transistor T10 is electrically connected to the cascade output signal terminal SOUT, and the second electrode of the tenth transistor T10 is electrically connected to the second power supply terminal VGL; the control electrode of the seventeenth transistor T17 is electrically connected to the masking signal terminal MS, the first electrode of the seventeenth transistor T17 is electrically connected to the tenth node N10, and the second electrode of the seventeenth transistor T17 is electrically connected to the twelfth node N12; the control electrode of the eighteenth transistor T18 is electrically connected to the second node N2, the first electrode of the tenth transistor T18 is electrically connected to the cascade output signal terminal SOUT, and the second electrode of the tenth transistor T18 is electrically connected to the second power supply terminal VGL; The control electrode of the twentieth transistor T20 is electrically connected to the third control signal terminal G3, the first electrode of the twentieth transistor T20 is electrically connected to the thirteenth node N13, and the second electrode of the twentieth transistor T20 is electrically connected to the second power supply terminal VGL; the twenty-first transistor T21 and the fifth capacitor C5.Among them, the control electrode of the twenty-first transistor T21 is electrically connected to the tenth node N10, the first electrode of the twenty-first transistor T21 is electrically connected to the first node N1, and the second electrode of the twenty-first transistor T21 is electrically connected to the eleventh node N11; the control electrode of the twenty-second transistor T22 is electrically connected to the drive output signal terminal NOUT, the first electrode of the twenty-second transistor T22 is electrically connected to the eleventh node N11, and the second electrode of the twenty-second transistor T22 is electrically connected to the fourteenth node N14; the control electrode of the twenty-third transistor T23 is electrically connected to the masking signal terminal MS, the first electrode of the twenty-third transistor T23 is electrically connected to the fourteenth node N14, and the second electrode of the twenty-third transistor T23 is electrically connected to the first power supply terminal VGH; the control electrode of the twenty-fourth transistor T24 is electrically connected to the eleventh node N11, the first electrode of the twenty-fourth transistor T24 is electrically connected to the first power supply terminal VGH, and the second electrode of the twenty-fourth transistor T24 is electrically connected to the drive output signal terminal NOUT; the twenty-fifth transistor T25 The control electrode of the twenty-fifth transistor T25 is electrically connected to the second node N2, the first electrode of the twenty-fifth transistor T25 is electrically connected to the drive output signal terminal NOUT, and the second electrode of the twenty-fifth transistor T25 is electrically connected to the second power supply terminal VGL; the first end of the first capacitor C1 is electrically connected to the fourth node N4, and the second end of the first capacitor C1 is electrically connected to the third node N3; the first end of the second capacitor C2 is electrically connected to the first node N1, and the second end of the second capacitor C2 is electrically connected to the first power supply terminal VGH; the first end of the third capacitor C3 is electrically connected to the second node N2, and the second end of the third capacitor C3 is electrically connected to the fifth node N5; the first end of the fourth capacitor C4 is electrically connected to the cascade output signal terminal SOUT, and the second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VGL; the first end of the fifth capacitor C5 is electrically connected to the tenth node N10, and the second end of the fifth capacitor C5 is electrically connected to the second power supply terminal VGL; the first end of the sixth capacitor C6 is electrically connected to the eleventh node N11, and the second end of the sixth capacitor C6 is electrically connected to the first power supply terminal VGH.

[0225] Fig.17 This is another equivalent circuit diagram of a shift register. Fig.17As shown, the cascade subcircuit in the shift register includes: the first transistor T1 to the seventh transistor T7, the ninth transistor T9, the tenth transistor T10 and the first capacitor C1 to the fourth capacitor C4, and the selection subcircuit in the shift register includes: the seventeenth transistor T17 to the twenty-fifth transistor T25, the fifth capacitor C5 and the sixth capacitor C6.The control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the second node N2; the control electrode of the second transistor T2 is electrically connected to the signal input terminal IN, the first electrode of the second transistor T2 is electrically connected to the fourth node N4, and the second electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third transistor T3 is electrically connected to the fourth node N4; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, and the fourth transistor T 4 is electrically connected to the fifth node N5, and the second electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CB; the control electrode of the fifth transistor T5 is electrically connected to the signal input terminal IN, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the first clock signal terminal CK; the control electrode of the sixth transistor T6 is electrically connected to the fourth node N4, the first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CB, and the second electrode of the sixth transistor T6 is electrically connected to the third node N3; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, the first electrode of the seventh transistor T7 is electrically connected to the third node N3, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1; the control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal VGH, and the second electrode of the ninth transistor T9 is electrically connected to the cascade output signal terminal SOUT; the control electrode of the tenth transistor T10 is electrically connected to the second node N2, the first electrode of the tenth transistor T10 is electrically connected to the cascade output signal terminal SOUT, and the second electrode of the tenth transistor T10 is electrically connected to the second power supply terminal VGL; the control electrode of the seventeenth transistor T17 is electrically connected to the masking signal terminal MS, the first electrode of the seventeenth transistor T17 is electrically connected to the tenth node N10, and the second electrode of the seventeenth transistor T17 is electrically connected to the twelfth node N12; the control electrode of the eighteenth transistor T18 is electrically connected to the second node N2, the first electrode of the tenth transistor T18 is electrically connected to the cascade output signal terminal SOUT, and the second electrode of the tenth transistor T18 is electrically connected to the second power supply terminal VGL; The control electrode of the twentieth transistor T20 is electrically connected to the third control signal terminal G3, the first electrode of the twentieth transistor T20 is electrically connected to the thirteenth node N13, and the second electrode of the twentieth transistor T20 is electrically connected to the second power supply terminal VGL; the twenty-first transistor T21 and the fifth capacitor C5.Among them, the control electrode of the twenty-first transistor T21 is electrically connected to the tenth node N10, the first electrode of the twenty-first transistor T21 is electrically connected to the first node N1, and the second electrode of the twenty-first transistor T21 is electrically connected to the eleventh node N11; the control electrode of the twenty-second transistor T22 is electrically connected to the drive output signal terminal NOUT, the first electrode of the twenty-second transistor T22 is electrically connected to the eleventh node N11, and the second electrode of the twenty-second transistor T22 is electrically connected to the fourteenth node N14; the control electrode of the twenty-third transistor T23 is electrically connected to the masking signal terminal MS, the first electrode of the twenty-third transistor T23 is electrically connected to the fourteenth node N14, and the second electrode of the twenty-third transistor T23 is electrically connected to the first power supply terminal VGH; the control electrode of the twenty-fourth transistor T24 is electrically connected to the eleventh node N11, the first electrode of the twenty-fourth transistor T24 is electrically connected to the first power supply terminal VGH, and the second electrode of the twenty-fourth transistor T24 is electrically connected to the drive output signal terminal NOUT; the twenty-fifth transistor T25 The control electrode of the twenty-fifth transistor T25 is electrically connected to the second node N2, the first electrode of the twenty-fifth transistor T25 is electrically connected to the drive output signal terminal NOUT, and the second electrode of the twenty-fifth transistor T25 is electrically connected to the second power supply terminal VGL; the first end of the first capacitor C1 is electrically connected to the fourth node N4, and the second end of the first capacitor C1 is electrically connected to the third node N3; the first end of the second capacitor C2 is electrically connected to the first node N1, and the second end of the second capacitor C2 is electrically connected to the first power supply terminal VGH; the first end of the third capacitor C3 is electrically connected to the second node N2, and the second end of the third capacitor C3 is electrically connected to the fifth node N5; the first end of the fourth capacitor C4 is electrically connected to the cascade output signal terminal SOUT, and the second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VGL; the first end of the fifth capacitor C5 is electrically connected to the tenth node N10, and the second end of the fifth capacitor C5 is electrically connected to the second power supply terminal VGL; the first end of the sixth capacitor C6 is electrically connected to the eleventh node N11, and the second end of the sixth capacitor C6 is electrically connected to the first power supply terminal VGH.

[0226] In an exemplary embodiment, Fig.10 and Fig.12 The number of transistors in the shift register provided is less than Figure 8 The number of transistors in the provided shift register can reduce the area occupied by the shift register, thereby achieving a narrow frame.

[0227] In an exemplary embodiment, Figure 8 , Fig.10 and Fig.12In the shift register provided, any capacitor among the first capacitor C1 to the sixth capacitor C6 can be a capacitor device made by a process, for example, the capacitor device can be realized by making a special capacitor electrode, and the multiple capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc. Alternatively, any capacitor among the first capacitor C1 to the sixth capacitor C6 can be a parasitic capacitor between multiple devices, which can be realized by the transistor itself and other devices and circuits. The connection method of any capacitor among the first capacitor C1 to the sixth capacitor C6 includes but is not limited to the method described above, and can be other applicable connection methods, and the level of the corresponding node can be stored. Here, the exemplary embodiment of the present disclosure is not limited to this.

[0228] In an exemplary embodiment, the transistors can be divided into N-type transistors and P-type transistors according to the characteristics of the transistors. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).

[0229] In an exemplary embodiment, Fig.15 In the provided shift register, at least one transistor among the first transistor T1 to the twenty-sixth transistor T26 is a P-type transistor.

[0230] In an exemplary embodiment, Fig.16 and Fig.17 In the provided shift register, at least one transistor among the first transistor T1 to the seventh transistor T7 , the ninth transistor T9 , the tenth transistor T10 , and the seventeenth transistor T17 to the twenty-sixth transistor T26 is a P-type transistor.

[0231] In an exemplary embodiment, the signal received by the first control signal terminal G1 of at least one shift register is the same as the signal of the third node N3, or the signal received by the first control signal terminal G1 of at least one shift register is the same as the signal of the third node N3 of the first M shift registers, where M is a positive integer greater than or equal to 1. Exemplarily, M=1 or 2.

[0232] In an exemplary embodiment, the signal received by the second control signal terminal G2 of at least one stage of the shift register is the same as the signal of the cascade output signal terminal SOUT, or the signal received by the second control signal terminal G2 of at least one stage of the shift register is the same as the signal of the cascade output signal terminal SOUT of the first N stages of the shift register, where N is a positive integer greater than or equal to 1. Exemplarily, N=1.

[0233] In an exemplary embodiment, the signal received by the third control signal terminal G3 of at least one stage of the shift register is the same as the signal of the second node N2.

[0234] The working process of the cascade subcircuit in the shift register provided by the present disclosure is independent of the working process of the gating subcircuit, while the working process of the gating subcircuit is related to some nodes in the cascade subcircuit.

[0235] Fig.18 for Figure 8 , Fig.10 and Fig.12 A timing diagram of the cascaded subcircuits in a shift register is provided. Fig.18 The description is made by taking the case where all transistors in the cascade subcircuit in the shift register are P-type transistors as an example.

[0236] for Fig.15 In the provided shift register cascade sub-circuit, during the operation of the shift register cascade sub-circuit, the eleventh transistor T11, the twelfth transistor T12 and the fifteenth transistor T15 are continuously turned on, and the thirteenth transistor T13 is continuously turned off.

[0237] Fig.15 The operation process of the cascaded subcircuit in the provided shift register may include the following stages:

[0238] In the first stage S1, i.e. the input stage, the signals at the signal input terminal IN and the second clock signal terminal CB are high level signals, and the signal at the first clock signal terminal CK is low level signal. The first transistor T1, the third transistor T3 and the fourteenth transistor T14 are turned on, and the seventh transistor T7 is turned off.

[0239] The turned-on first transistor T1 transmits the high-level signal of the signal input terminal IN to the fifth node N5, and the signal of the fifth node N5 is a high-level signal. The turned-on twelfth transistor T12 transmits the high-level signal of the fifth node N5 to the second node N2, and the turned-on fourteenth transistor T14 and fifteenth transistor T15 transmit the high-level signal of the signal input terminal IN to the sixth node N6. The second transistor T2, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10, and the sixteenth transistor T16 are turned off. In addition, the turned-on third transistor T3 and the eleventh transistor T11 transmit the low-level signal of the second power supply terminal VGL to the fourth node N4 and the eighth node N8, the fifth transistor T5 and the sixth transistor T6 are turned on, and the signal of the seventh node N7 is a high-level signal. Since the seventh transistor T7 is turned off, the signal of the first node N1 remains a high-level signal, the ninth transistor T9 is turned off, and the signal of the cascade output signal terminal SOUT remains the previous low-level signal.

[0240] In this stage, the signals at the first node N1, the second node N2 and the third node N3 are high level signals, and the signal at the cascade output signal terminal SOUT is a low level signal.

[0241] In the second stage S2, i.e. the output stage, the signal at the second clock signal terminal CB is a low level signal, and the signals at the signal input terminal IN and the first clock signal terminal CK are high level signals. The first transistor T1, the third transistor T3 and the fourteenth transistor T14 are turned off, and the seventh transistor T7 is turned on.

[0242] Under the action of the first capacitor C1, the signals of the fourth node N4 and the eighth node N8 maintain low-level signals, and the fifth transistor T5 and the sixth transistor T6 are turned on. The low-level signal of the second clock signal terminal CB is transmitted to the third node N3 and the first node N1 through the turned-on sixth transistor T6 and the seventh transistor T7, the ninth transistor T9 is turned on, and the high-level signal of the first power supply terminal VGH is transmitted to the cascade output signal terminal SOUT through the turned-on ninth transistor T9. Under the action of the third capacitor C3, the sixth node N6 maintains the high-level signal of the previous stage, the second node N2 and the fifth node N5 maintain the high-level signal of the previous stage, and the second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are turned off.

[0243] In this stage, the signals at the first node N1 and the third node N3 are low level signals, the signal at the second node N2 is a high level signal, and the signal at the cascade output signal terminal SOUT is a high level signal.

[0244] In the third stage S3, the signal at the first clock signal terminal CK is a low level signal, the signals at the signal input terminal IN and the second clock signal terminal CB are high level signals, the first transistor T1, the third transistor T3 and the fourteenth transistor T14 are turned on, and the seventh transistor T7 is turned off.

[0245] Under the action of the second capacitor C2, the first node N1 maintains the low level signal of the previous stage, the ninth transistor T9 is continuously turned on, and the high level signal of the first power supply terminal VGH is transmitted to the cascade output signal terminal SOUT through the ninth transistor T9 that is turned on. The first transistor T1 and the twelfth transistor T12 that are turned on transmit the high level signal of the signal input terminal IN to the second node N2 and the fifth node N5, the fourteenth transistor T14 and the fifteenth transistor T15 that are turned on transmit the high level signal of the signal input terminal IN to the sixth node N6, and the second transistor T2, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10 and the sixteenth transistor T16 are turned off. In addition, the third transistor T3 and the eleventh transistor T11 that are turned on transmit the low level signal of the second power supply terminal VGL to the fourth node N4 and the eighth node N8, the fifth transistor T5 and the sixth transistor T6 are turned on, the high level signal of the signal of the second clock signal terminal CB is written into the third node N3, and the high level signal of the first power supply terminal VGH is written into the seventh node N7.

[0246] In this stage, the signal of the first node N1 is a low level signal, the signals of the second node N2 and the third node N3 are high level signals, and the signal of the cascade output signal terminal SOUT is a high level signal.

[0247] In the fourth stage S4, the signals at the signal input terminal IN and the second clock signal terminal CB are low level signals, and the signal at the first clock signal terminal CK is high level signal. The first transistor T1, the third transistor T3 and the fourteenth transistor T14 are turned off, and the seventh transistor T7 is turned on.

[0248] Under the action of the first capacitor C1, the signals of the fourth node N4 and the eighth node N8 maintain low-level signals, and the fifth transistor T5 and the sixth transistor T6 are turned on. The low-level signal of the second clock signal terminal CB is transmitted to the third node N3 and the first node N1 through the turned-on sixth transistor T6 and the seventh transistor T7, the ninth transistor T9 is turned on, and the high-level signal of the first power supply terminal VGH is transmitted to the cascade output signal terminal SOUT through the turned-on ninth transistor T9. Under the action of the third capacitor C3, the sixth node N6 maintains the high-level signal of the previous stage, the fifth node N5 and the second node N2 maintain the high-level signal of the previous stage, and the second transistor T2, the fourth transistor T4, the eighth transistor T8 and the tenth transistor T10 are turned off.

[0249] Therefore, in this stage, the signals at the first node N1 and the third node N3 are low level signals, the signal at the second node N2 is a high level signal, and the signal at the cascade output signal terminal SOUT is a high level signal.

[0250] In the fifth stage S5, the signal of the second clock signal terminal CB is a high level signal, the signals of the signal input terminal IN and the first clock signal terminal CK are low level signals, the first transistor T1, the third transistor T3 and the fourteenth transistor T14 are turned on, and the seventh transistor T7 is turned off.

[0251] The turned-on first transistor T1 and the twelfth transistor T12 transmit the low-level signal of the signal input terminal IN to the fifth node N5 and the second node N2, the turned-on fourteenth transistor T14 and the fifteenth transistor T15 transmit the low-level signal of the signal input terminal IN to the sixth node N6, the second transistor T2, the fourth transistor T4, the eighth transistor T8, the tenth transistor T10 and the sixteenth transistor T16 are turned on. The turned-on sixth transistor T6 transmits the high-level signal of the second clock signal terminal CB to the third node N3, the turned-on fourth transistor T4 transmits the high-level signal of the second clock signal terminal CB to the seventh node N7, the turned-on sixteenth transistor T16 continuously transmits the low-level signal of the sixth node N6 to the second node N2, the turned-on second transistor T2 transmits the low-level signal of the first clock signal terminal CK to the fourth node N4, the signal of the fourth node N4 is a low-level signal, the fourth node N4 and the eighth node N8 continue to maintain the low-level signal of the previous stage, and the fifth transistor T5 and the sixth transistor T6 are turned on. The signal of the second clock signal terminal CB is a high level signal, and the seventh transistor T7 is turned off. In addition, the high level signal of the first power supply terminal VGH is transmitted to the first node N1 through the turned-on eighth transistor T8, and the ninth transistor T9 is turned off. The low level signal of the second power supply terminal VGL is transmitted to the cascade output signal terminal SOUT through the turned-on tenth transistor T10.

[0252] In this stage, the signals at the first node N1 and the third node N3 are high level signals, the signal at the second node N2 is a low level signal, and the signal at the cascade output signal terminal SOUT is a low level signal.

[0253] The second stage S2 and the third stage S3 in the shift register are alternately arranged until the signal at the signal input terminal IN changes from a high level signal to a low level signal.

[0254] Fig.16 The operation process of the cascaded subcircuit in the provided shift register may include the following stages:

[0255] In the first stage S1, ie, the input stage, the signals at the signal input terminal IN and the second clock signal terminal CB are high level signals, and the signal at the first clock signal terminal CK is low level signal. The first transistor T1 and the third transistor T3 are turned on, and the seventh transistor T7 is turned off.

[0256] The turned-on first transistor T1 transmits the high-level signal of the signal input terminal IN to the second node N2, and the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the tenth transistor T10 are turned off. In addition, the turned-on third transistor T3 transmits the low-level signal of the second power supply terminal VGL to the fourth node N4, the sixth transistor T6 is turned on, and since the seventh transistor T7 is turned off, the signal of the first node N1 remains as a high-level signal, the ninth transistor T9 is turned off, and the signal of the cascade output signal terminal SOUT remains as the previous low-level signal.

[0257] In this stage, the signals at the first node N1, the second node N2 and the third node N3 are high level signals, and the signal at the cascade output signal terminal SOUT is a low level signal.

[0258] In the second stage S2, ie, the output stage, the signal at the second clock signal terminal CB is a low level signal, and the signals at the signal input terminal IN and the first clock signal terminal CK are high level signals. The first transistor T1 and the third transistor T3 are turned off, and the seventh transistor T7 is turned on.

[0259] Under the action of the first capacitor C1, the signal of the fourth node N4 maintains a low level signal, and the sixth transistor T6 is turned on. The low level signal of the second clock signal terminal CB is transmitted to the third node N3 and the first node N1 through the turned-on sixth transistor T6 and the seventh transistor T7, the ninth transistor T9 is turned on, and the high level signal of the first power supply terminal VGH is transmitted to the cascade output signal terminal SOUT. Under the action of the third capacitor C3, the second node N2 maintains a high level signal in the previous stage, and the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the tenth transistor T10 are turned off.

[0260] In this stage, the signals at the first node N1 and the third node N3 are low level signals, the signal at the second node N2 is a high level signal, and the signal at the cascade output signal terminal SOUT is a high level signal.

[0261] In the third stage S3, the signal at the first clock signal terminal CK is a low level signal, the signals at the signal input terminal IN and the second clock signal terminal CB are high level signals, the first transistor T1 and the third transistor T3 are turned on, and the seventh transistor T7 is turned off.

[0262] Under the action of the second capacitor C2, the first node N1 maintains the low level signal of the previous stage, the ninth transistor T9 is continuously turned on, and the high level signal of the first power supply terminal VGH is transmitted to the cascade output signal terminal SOUT. The turned-on first transistor T1 transmits the high level signal of the signal input terminal IN to the second node N2, and the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the tenth transistor T10 are turned off. In addition, the turned-on third transistor T3 transmits the low level signal of the second power supply terminal VGL to the fourth node N4, the sixth transistor T6 is turned on, and the high level signal of the signal of the second clock signal terminal CB is written into the third node N3.

[0263] In this stage, the signal of the first node N1 is a low level signal, the signals of the second node N2 and the third node N3 are high level signals, and the signal of the cascade output signal terminal SOUT is a high level signal.

[0264] In the fourth stage S4, the signals at the signal input terminal IN and the second clock signal terminal CB are low level signals, the signal at the first clock signal terminal CK is high level signal, the first transistor T1 and the third transistor T3 are turned off, and the seventh transistor T7 is turned on.

[0265] Under the action of the first capacitor C1, the signal of the fourth node N4 maintains a low level signal, and the sixth transistor T6 is turned on. The low level signal of the second clock signal terminal CB is transmitted to the third node N3 and the first node N1 through the turned-on sixth transistor T6 and the seventh transistor T7, the ninth transistor T9 is turned on, and the high level signal of the first power supply terminal VGH is transmitted to the cascade output signal terminal SOUT through the turned-on ninth transistor T9. Under the action of the third capacitor C3, the second node N2 maintains the high level signal of the previous stage, and the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the tenth transistor T10 are turned off.

[0266] Therefore, in this stage, the signals at the first node N1 and the third node N3 are low level signals, the signal at the second node N2 is a high level signal, and the signal at the cascade output signal terminal SOUT is a high level signal.

[0267] In the fifth stage S5, the signal at the second clock signal terminal CB is a high level signal, the signals at the signal input terminal IN and the first clock signal terminal CK are low level signals, the first transistor T1 and the third transistor T3 are turned on, and the seventh transistor T7 is turned off.

[0268] The turned-on first transistor T1 transmits the low level signal of the signal input terminal IN to the second node N2 , and the second transistor T2 , the fourth transistor T4 , the fifth transistor T5 , and the tenth transistor T10 are turned on. The turned-on second transistor T2 transmits the low-level signal of the first clock signal terminal CK to the fourth node N4, and the signal of the fourth node N4 is a low-level signal. The turned-on third transistor T3 continuously transmits the low-level signal of the second power supply terminal VGL to the fourth node N4. The sixth transistor T6 is turned on, and the turned-on sixth transistor T6 transmits the high-level signal of the second clock signal terminal CB to the third node N3. The turned-on fourth transistor T4 writes the high-level signal of the second clock signal terminal CB to the fifth node N5. The turned-on fifth transistor T5 transmits the low-level signal of the first clock signal terminal CK to the first node N1. The ninth transistor T9 is turned on, and the turned-on ninth transistor T9 transmits the high-level signal of the first power supply terminal VGH to the cascade signal output terminal SOUT. However, since the turned-on tenth transistor T10 transmits the low-level signal of the second power supply terminal VGL to the cascade output signal terminal SOUT, the cascade output signal terminal SOUT is a low-level signal.

[0269] In this stage, the signal of the third node N3 is a high level signal, the signals of the first node N1 and the second node N2 are low level signals, and the signal of the cascade output signal terminal SOUT is a low level signal.

[0270] The second stage S2 and the third stage S3 in the shift register are alternately arranged until the signal at the signal input terminal IN changes from a high level signal to a low level signal.

[0271] Fig.17 The operation process of the cascaded subcircuit in the provided shift register may include the following stages:

[0272] In the first stage S1, i.e., the input stage, the signals at the signal input terminal IN and the second clock signal terminal CB are high level signals, and the signal at the first clock signal terminal CK is low level signal. The first transistor T1 and the third transistor T3 are turned on, and the second transistor T2, the fifth transistor T5 and the seventh transistor T7 are turned off.

[0273] The turned-on first transistor T1 transmits the high-level signal of the signal input terminal IN to the second node N2, and the fourth transistor T4 and the tenth transistor T10 are turned off. In addition, the turned-on third transistor T3 transmits the low-level signal of the second power supply terminal VGL to the fourth node N4, the sixth transistor T6 is turned on, and since the seventh transistor T7 is turned off, the signal of the first node N1 remains as a high-level signal, the ninth transistor T9 is turned off, and the signal of the cascade output signal terminal SOUT remains as the previous low-level signal.

[0274] In this stage, the signals at the first node N1, the second node N2 and the third node N3 are high level signals, and the signal at the cascade output signal terminal SOUT is a low level signal.

[0275] In the second stage S2, i.e., the output stage, the signal at the second clock signal terminal CB is a low level signal, and the signals at the signal input terminal IN and the first clock signal terminal CK are high level signals. The first transistor T1, the second transistor T2, the third transistor T3 and the fifth transistor T5 are turned off, and the seventh transistor T7 is turned on.

[0276] Under the action of the first capacitor C1, the signal of the fourth node N4 maintains a low level signal, and the sixth transistor T6 is turned on. The low level signal of the second clock signal terminal CB is transmitted to the third node N3 and the first node N1 through the turned-on sixth transistor T6 and the seventh transistor T7, the ninth transistor T9 is turned on, and the high level signal of the first power supply terminal VGH is transmitted to the cascade output signal terminal SOUT. Under the action of the third capacitor C3, the second node N2 maintains a high level signal in the previous stage, and the fourth transistor T4 and the tenth transistor T10 are turned off.

[0277] In this stage, the signals at the first node N1 and the third node N3 are low level signals, the signal at the second node N2 is a high level signal, and the signal at the cascade output signal terminal SOUT is a high level signal.

[0278] In the third stage S3, the signal at the first clock signal terminal CK is a low level signal, the signals at the signal input terminal IN and the second clock signal terminal CB are high level signals, the first transistor T1 and the third transistor T3 are turned on, and the second transistor T2, the fifth transistor T5 and the seventh transistor T7 are turned off.

[0279] Under the action of the second capacitor C2, the first node N1 maintains the low level signal of the previous stage, the ninth transistor T9 is continuously turned on, and the high level signal of the first power supply terminal VGH is transmitted to the cascade output signal terminal SOUT. The turned-on first transistor T1 transmits the high level signal of the signal input terminal IN to the second node N2, and the fourth transistor T4 and the tenth transistor T10 are disconnected. In addition, the turned-on third transistor T3 transmits the low level signal of the second power supply terminal VGL to the fourth node N4, the sixth transistor T6 is turned on, and the high level signal of the signal of the second clock signal terminal CB is written into the third node N3.

[0280] In this stage, the signal of the first node N1 is a low level signal, the signals of the second node N2 and the third node N3 are high level signals, and the signal of the cascade output signal terminal SOUT is a high level signal.

[0281] In the fourth stage S4, the signals at the signal input terminal IN and the second clock signal terminal CB are low level signals, and the signal at the first clock signal terminal CK is high level signal. The first transistor T1 and the third transistor T3 are turned off, and the second transistor T2, the fifth transistor T5 and the seventh transistor T7 are turned on.

[0282] The second transistor T2 is turned on, the high level signal of the first clock signal terminal CK is written into the fourth node N4, the sixth transistor T6 is turned off, the third node N3 is a high level signal under the action of the first capacitor C1, the fifth transistor T5 is turned on, the high level signal of the first clock signal terminal CK is written into the first node N1, and the ninth transistor T9 is turned off. The second node N2 maintains the high level signal of the previous stage under the action of the third capacitor C3, the tenth transistor T10 is turned off, and the cascade output signal terminal SOUT maintains the high level signal of the previous stage.

[0283] In this stage, the signals at the first node N1, the second node N2 and the third node N3 are high level signals, and the signal at the cascade output signal terminal SOUT is a high level signal.

[0284] In the fifth stage S5, the signal at the second clock signal terminal CB is a high level signal, and the signals at the signal input terminal IN and the first clock signal terminal CK are low level signals. The first transistor T1, the second transistor T2, the third transistor T3 and the fifth transistor T5 are turned on, and the seventh transistor T7 is turned off.

[0285] The turned-on first transistor T1 transmits the low level signal of the signal input terminal IN to the second node N2 , and the fourth transistor T4 and the tenth transistor T10 are turned on. The turned-on second transistor T2 transmits the low-level signal of the first clock signal terminal CK to the fourth node N4, and the signal of the fourth node N4 is a low-level signal. The turned-on third transistor T3 continuously transmits the low-level signal of the second power supply terminal VGL to the fourth node N4. The sixth transistor T6 is turned on, and the turned-on sixth transistor T6 transmits the high-level signal of the second clock signal terminal CB to the third node N3. The turned-on fourth transistor T4 writes the high-level signal of the second clock signal terminal CB to the fifth node N5. The turned-on fifth transistor T5 transmits the low-level signal of the first clock signal terminal CK to the first node N1. The ninth transistor T9 is turned on, and the turned-on ninth transistor T9 transmits the high-level signal of the first power supply terminal VGH to the cascade signal output terminal SOUT. However, since the turned-on tenth transistor T10 transmits the low-level signal of the second power supply terminal VGL to the cascade output signal terminal SOUT, the cascade output signal terminal SOUT is a low-level signal.

[0286] In this stage, the signal of the third node N3 is a high level signal, the signals of the first node N1 and the second node N2 are low level signals, and the signal of the cascade output signal terminal SOUT is a low level signal.

[0287] The second stage S2 and the third stage S3 in the shift register are alternately arranged until the signal at the signal input terminal IN changes from a high level signal to a low level signal.

[0288] In an exemplary embodiment, when the signal of the cascade signal output terminal SOUT in the shift register is a low level signal, the signal of the second node N2 is a low level signal.

[0289] In an exemplary embodiment, the signal of the first control signal terminal G1 connected to at least one shift register (also the signal of the third node N3 in the cascade subcircuit of the current shift register or the first M shift registers) can be regarded as a periodically changing clock signal.

[0290] In an exemplary embodiment, the shift register is arranged in a display device, the content displayed by the display device includes multiple display frames, and the display mode of the display device includes: a first display mode and a second display mode, and the refresh rate of the first display mode is greater than the refresh rate of the second display mode.

[0291] In the first display mode, the signal at the cascade output signal terminal and the signal at the drive output signal terminal of the shift register are the same.

[0292] In the second display mode, the signal at the cascade output signal terminal and the signal at the drive output signal terminal of the shift register are inverted signals at least part of the time.

[0293] In the first display mode, the signal at the mask signal terminal MS is an invalid level signal. When the seventeenth transistor T17 and the twenty-third transistor T23 are P-type transistors, the signal at the mask signal terminal MS is a high level signal.

[0294] In the second display mode, the signal at the mask signal terminal MS is a valid level signal. When the seventeenth transistor T17 and the twenty-third transistor T23 are P-type transistors, the signal at the mask signal terminal MS is a low level signal.

[0295] In an exemplary embodiment, Fig.19 for Figure 8 , Fig.10 and Fig.12 Provided is a working timing diagram of a gating subcircuit in a shift register in a first display mode.

[0296] When the signal at the masking signal terminal MS is an invalid level signal, the seventeenth transistor T17 and the twenty-third transistor T23 are disconnected, and the high level signal of the first power supply terminal VGH cannot be written into the twenty-first transistor T21, and only the low level signal of the second power supply terminal VGL can be written into the twenty-first transistor T21. When the low level signal of the second power supply terminal VGL is written into the twenty-first transistor T21, the first node N1 and the eleventh node N11 are connected, the signals of the driving output signal terminal and the cascade output signal terminal of the shift register are the same, and the display device where the shift register is located is in the first display mode.

[0297] When the signal at the masking signal terminal MS is a valid level signal, the seventeenth transistor T17 and the twenty-third transistor T23 are turned off, the high level signal at the first power supply terminal VGH can be written into the twenty-first transistor T21, and the twenty-first transistor T21 is turned off. The first node N1 and the eleventh node N11 cannot be connected, the drive output signal terminal of the shift register is different from the signal at the cascade output signal terminal, the drive output signal terminal of the shift register outputs a low level signal, and the display device where the shift register is located is in the second display mode.

[0298] When the signal at the masking signal terminal MS is an invalid level signal, the cascade subcircuit in the shift register outputs normally. The operation process of the gating subcircuit in the shift register in the first time period t1 includes: the signal at the cascade output signal terminal in the shift register is a low level signal, the signal at the first node is a high level signal, the signal at the second node is a low level signal, that is, the signal at the third control signal terminal G3 is a low level signal, the twentieth transistor T20 and the twenty-fifth transistor T25 are turned on, the cascade output signal terminal of at least one level of shift register before the current level shift register is a low level signal in part of the time period, the nineteenth transistor T19 is turned on, the low level signal of the second power supply terminal VGL is written into the tenth node N10 through the turned-on nineteenth transistor T19 and the twenty-tenth transistor T20, the twenty-first transistor T21 is turned on, the high level signal of the first node N1 is written into the eleventh node N11, the twenty-fourth transistor T24 is turned off, and the high level signal of the first power supply terminal VGH cannot be written into the drive output signal terminal NOUT. The low level signal of the second power supply terminal VGL is written into the drive output signal terminal NOUT through the turned-on twenty-fifth transistor T25.

[0299] When the signal at the masking signal terminal MS is an invalid level signal, the cascade subcircuit in the shift register outputs normally. The operation process of the gating subcircuit in the shift register in the second time period t2 includes: the signal at the cascade output signal terminal in the shift register is a high level signal, the signal at the first node is a low level signal, the signal at the second node is a high level signal, that is, the signal at the third control signal terminal G3 is a high level signal, the twentieth transistor T20 and the twenty-fifth transistor T25 are turned off, the cascade output signal terminal of at least one shift register before the current shift register is a high level signal, the nineteenth transistor T19 is turned off, under the action of the fifth capacitor C5, the tenth node N10 maintains the low level signal of the previous time period, the twenty-first transistor T21 is turned on, the low level signal of the first node N1 is written into the eleventh node N11, the twenty-fourth transistor T24 is turned on, and the high level signal of the first power supply terminal VGH is written into the driving output signal terminal NOUT.

[0300] When the signal of the masking signal terminal MS is an invalid level signal, the cascade subcircuit in the shift register outputs normally. The operation process of the gating subcircuit in the shift register in the third time period t3 includes: the signal of the cascade output signal terminal in the shift register is a low level signal, the signal of the first node is a high level signal, and the signal of the second node is a low level signal, that is, the signal of the third control signal terminal G3 is a low level signal, the twentieth transistor T20 and the twenty-fifth transistor T25 are turned on, and the signal of the cascade output signal terminal of at least one level of shift register before the current level shift register is a low level signal in part of the time period, the nineteenth transistor T19 is turned on, and the low level signal of the second power supply terminal VGL is written into the tenth node N10 through the turned-on nineteenth transistor T19 and the twenty-tenth transistor T20, the twenty-first transistor T21 is turned on, and the high level signal of the first node N1 is written into the eleventh node N11, the twenty-fourth transistor T24 is turned off, and the high level signal of the first power supply terminal VGH cannot be written into the drive output signal terminal NOUT. The low level signal of the second power supply terminal VGL is written into the drive output signal terminal NOUT through the turned-on twenty-fifth transistor T25.

[0301] In an exemplary embodiment, Fig. 20 for Figure 8 , Fig.10 and Fig.12 Provided is a working timing diagram of a gating subcircuit in a shift register in a second display mode.

[0302] When the signal at the masking signal terminal MS is a valid level signal, the cascade subcircuit in the shift register outputs normally. The operation process of the gating subcircuit in the shift register in the first time period t1 includes: the signal at the cascade output signal terminal in the shift register is a low level signal, the signal at the first node is a high level signal, the signal at the second node is a low level signal, that is, the signal at the third control signal terminal G3 is a low level signal, the twentieth transistor T20 and the twenty-fifth transistor T25 are turned on, the cascade output signal terminal of at least one shift register before the current shift register is a low level signal in part of the time period, the nineteenth transistor T19 is turned on, the low level signal of the second power supply terminal VGL is written into the tenth node N10 through the turned-on nineteenth transistor T19 and the twenty-tenth transistor T20, the twenty-first transistor T21 is turned on, the high level signal of the first node N1 is written into the eleventh node N11, the twenty-fourth transistor T24 is turned off, and the high level signal of the first power supply terminal VGH cannot be written into the drive output signal terminal NOUT. The low level signal of the second power supply terminal VGL is written into the drive output signal terminal NOUT through the turned-on twenty-fifth transistor T25.

[0303] When the signal at the masking signal terminal MS is a valid level signal, the cascade subcircuit in the shift register outputs normally. The operation process of the gating subcircuit in the shift register in the second time period t2 includes: the signal at the cascade output signal terminal in the shift register is a high level signal, the signal at the first node is a low level signal, and the signal at the second node is a high level signal, that is, the signal at the third control signal terminal G3 is a high level signal, the twentieth transistor T20 and the twenty-fifth transistor T25 are turned off, the cascade output signal terminal of at least one shift register before the current shift register is a high level signal, and the nineteenth transistor T19 is turned off. The seventeenth transistor T17 is turned on, and since the signal at the first control signal terminal G1 is a clock signal, when the seventeenth transistor T17 and the eighteenth transistor T18 are both turned on, the signal at the first clock signal terminal VGH is written into the tenth node N10, the twenty-first transistor T21 is turned off, the signal at the driving output signal terminal NOUT maintains the previous low level signal, the twenty-second transistor T22 and the twenty-third transistor T23 are turned on, the high level signal at the first power supply terminal VGH is written into the eleventh node N11, and the twenty-fourth transistor T24 is turned off.

[0304] When the signal at the masking signal terminal MS is a valid level signal, the cascade subcircuit in the shift register outputs normally. The operation process of the gating subcircuit in the shift register in the third time period t3 includes: the signal at the cascade output signal terminal in the shift register is a low level signal, the signal at the first node is a high level signal, and the signal at the second node is a low level signal, that is, the signal at the third control signal terminal G3 is a low level signal, the twentieth transistor T20 and the twenty-fifth transistor T25 are turned on, the signal at the cascade output signal terminal of at least one shift register before the current shift register is a low level signal in part of the time period, the nineteenth transistor T19 is turned on, the low level signal at the second power supply terminal VGL is written into the tenth node N10 through the turned-on nineteenth transistor T19 and the twenty-tenth transistor T20, the twenty-first transistor T21 is turned on, the high level signal at the first node N1 is written into the eleventh node N11, the twenty-fourth transistor T24 is turned off, and the high level signal at the first power supply terminal VGH cannot be written into the drive output signal terminal NOUT. The low level signal at the second power supply terminal VGL is written into the drive output signal terminal NOUT through the turned-on twenty-fifth transistor T25.

[0305] In an exemplary embodiment, Fig.21 for Figure 8 , Fig.10 and Fig.12 The shift register provided is switched in the display mode. When the signal at the masking signal terminal MS is a low level signal at some time, the signal at the drive output signal terminal of some shift registers is a low level signal, and the signal at the drive output signal terminal of some shift registers is the same as the signal at the cascade output signal terminal. Fig.21 As shown, the signal NOUT(n+4) at the driving output signal end of the n+4th shift register, the signal NOUT(n+5) at the driving output signal end of the n+5th shift register, and the signal NOUT(n+6) at the driving output signal end of the n+4th shift register are low level signals, the signal NOUT(n+7) at the driving output signal end after the n+7th shift register is the same as the signal at the cascade output signal end, and the start time of the driving signal output by the signal NOUT(n+7) at the driving output signal end after the n+7th shift register is equal to the end time of the time period when the signal at the masking signal end MS is a valid level signal. The number of shift registers whose driving output signal end is a low level signal depends on the duration of the time period when the signal at the masking signal end MS is a valid level signal and the signals received by the first control signal end and the second control signal end connected to at least one shift register, and the present disclosure does not make any limitation on this.

[0306] The shift register driving method provided in the embodiment of the present disclosure is configured to drive the shift register provided in any of the aforementioned embodiments, and the shift register driving method includes:

[0307] Step 100, the cascade subcircuit provides a signal from the second clock signal terminal to the first node, provides a signal from the signal input terminal to the second node, and provides a signal from the first power supply terminal or the second power supply terminal to the cascade output signal terminal under the control of the signals from the signal input terminal, the first clock signal terminal and the second clock signal terminal.

[0308] Step 200, the selection subcircuit provides a signal from the first power supply terminal or the second power supply terminal to the driving output signal terminal under the control of the signals from the masking signal terminal, the first control signal terminal, the second control signal terminal, the third control signal terminal, the first node and the second node.

[0309] An embodiment of the present disclosure further provides a gate driving circuit, comprising: a plurality of cascaded shift registers provided by any of the aforementioned embodiments.

[0310] In an exemplary embodiment, the cascade output signal terminal of at least one stage of the shift register is connected to the signal input terminal of at least one stage of the shift register other than the current stage of the shift register.

[0311] In an exemplary embodiment, the gate driving circuit further includes: an initial shift register, the initial shift register including: a cascade sub-circuit in at least one stage of the shift register, the cascade output signal terminal of the initial shift register being electrically connected to the signal input terminal of the first stage of the shift register.

[0312] The embodiment of the present disclosure also provides a display substrate, comprising a display area and a non-display area located at least on one side of the display area, wherein the non-display area is provided with a gate drive circuit provided by any of the aforementioned embodiments, and the display area further comprises: sub-pixels arranged in an array, wherein the drive output signal terminal of at least one stage of the shift register in the gate drive circuit is electrically connected to at least one row of sub-pixels.

[0313] In an exemplary embodiment, the display device may be any product or component having a display function, such as a wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0314] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0315] For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of the layer or microstructure are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intermediate elements.

[0316] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims

1. A shift register, characterized in that: include: Cascade subcircuits and gating subcircuits; The cascade sub-circuit is respectively connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the first node, the second node and the cascade output signal terminal, and is configured to provide the signal of the second clock signal terminal to the first node and the signal of the signal input terminal to the second node under the control of the signals of the signal input terminal, the first clock signal terminal and the second clock signal terminal, and to provide the signal of the first power supply terminal or the second power supply terminal to the cascade output signal terminal under the control of the signals of the first node and the second node; The gating subcircuit is respectively connected to the first node, the second node, the masking signal terminal, the first control signal terminal, the second control signal terminal, the third control signal terminal, the first power supply terminal, the second power supply terminal and the driving output signal terminal, and is configured to provide a signal from the first power supply terminal or the second power supply terminal to the driving output signal terminal under the control of the signals from the masking signal terminal, the first control signal terminal, the second control signal terminal, the third control signal terminal, the first node and the second node.

2. The shift register according to claim 1, characterized in that: The cascade subcircuit comprises: a node control subcircuit, a cascade output subcircuit and a voltage stabilization subcircuit; The node control subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first node, and the second node, respectively, and is configured to provide the signal of the second clock signal terminal to the first node and provide the signal of the signal input terminal to the second node under the control of the signals of the signal input terminal, the first clock signal terminal, and the second clock signal terminal; The cascade output subcircuit is electrically connected to the first node, the second node, the first power supply terminal, the second power supply terminal and the cascade output signal terminal respectively, and is configured to provide a signal from the first power supply terminal or the second power supply terminal to the cascade output signal terminal under the control of the signals from the first node and the second node; The voltage stabilizing subcircuit is electrically connected to the cascade output signal terminal and the second power supply terminal, respectively, and is configured to store a voltage difference between signals at the cascade output signal terminal and the second power supply terminal.

3. The shift register according to claim 2, characterized in that: The node control subcircuit includes: a first node control subcircuit, a second node control subcircuit, a third node control subcircuit and a fourth node control subcircuit; The first node control subcircuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the first node and the fourth node respectively, and is configured to provide the signal of the second power supply terminal to the fourth node, provide the signal of the second clock signal terminal to the first node, and store the voltage difference between the signal of the first node and the signal of the first power supply terminal under the control of the signal of the first clock signal terminal and the second clock signal terminal; The second node control subcircuit is electrically connected to the first clock signal terminal, the signal input terminal and the second node respectively, and is configured to provide a signal from the signal input terminal to the second node under the control of a signal from the first clock signal terminal; The third node control subcircuit is electrically connected to the first clock signal terminal, the second node and the fourth node respectively, and is configured to provide the signal of the first clock signal terminal to the fourth node under the control of the signal of the second node; The fourth node control subcircuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first node and the second node, respectively, and is configured to provide the signal of the first clock signal terminal to the first node under the control of the signal of the second node, and store the voltage values ​​of the signals of the second node and the second clock signal terminal.

4. The shift register according to claim 3, characterized in that: The first node control subcircuit includes: a third transistor, a sixth transistor, a seventh transistor, a first capacitor and a second capacitor, the second node control subcircuit includes: a first transistor, and the third node control subcircuit includes: a second transistor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the second node; The control electrode of the second transistor is electrically connected to the second node, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the first clock signal terminal; A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the fourth node; The control electrode of the sixth transistor is electrically connected to the fourth node, the first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the third node; The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is electrically connected to the third node, and the second electrode of the seventh transistor is electrically connected to the first node; The first end of the first capacitor is electrically connected to the fourth node, and the second end of the first capacitor is electrically connected to the third node; A first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the first power supply end.

5. The shift register according to claim 3, characterized in that: The fourth node control subcircuit includes: a fourth transistor, a fifth transistor and a third capacitor; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the fifth node, and the second electrode of the fourth transistor is electrically connected to the second clock signal terminal; A control electrode of the fifth transistor is electrically connected to the second node, a first electrode of the fifth transistor is electrically connected to the first node, and a second electrode of the fifth transistor is electrically connected to the first clock signal terminal; A first end of the third capacitor is electrically connected to the second node, and a second end of the third capacitor is electrically connected to the fifth node.

6. The shift register according to claim 2, characterized in that: The node control subcircuit includes: a first node control subcircuit, a second node control subcircuit, a third node control subcircuit and a fourth node control subcircuit; The first node control subcircuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the first node and the fourth node respectively, and is configured to provide the signal of the second power supply terminal to the fourth node, provide the signal of the second clock signal terminal to the first node, and store the voltage difference between the signal of the first node and the signal of the first power supply terminal under the control of the signal of the first clock signal terminal and the second clock signal terminal; The second node control subcircuit is electrically connected to the first clock signal terminal, the signal input terminal and the second node respectively, and is configured to provide a signal from the signal input terminal to the second node under the control of a signal from the first clock signal terminal; The third node control subcircuit is electrically connected to the first clock signal terminal, the signal input terminal and the fourth node respectively, and is configured to provide the signal of the first clock signal terminal to the fourth node under the control of the signal of the signal input terminal; The fourth node control subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first node and the second node, respectively, and is configured to be under the control of the signal of the second node and store the voltage difference between the second clock signal terminal and the signal of the second node, and under the control of the signal of the signal input terminal, provide the signal of the first clock signal terminal to the first node.

7. The shift register according to claim 6, characterized in that: The first node control subcircuit includes: a third transistor, a sixth transistor, a seventh transistor, a first capacitor and a second capacitor, the second node control subcircuit includes: a first transistor, and the third node control subcircuit includes: a second transistor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the second node; The control electrode of the second transistor is electrically connected to the signal input terminal, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the first clock signal terminal; A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the fourth node; The control electrode of the sixth transistor is electrically connected to the fourth node, the first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the third node; The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is electrically connected to the third node, and the second electrode of the seventh transistor is electrically connected to the first node; The first end of the first capacitor is electrically connected to the fourth node, and the second end of the first capacitor is electrically connected to the third node; A first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the first power supply end.

8. The shift register according to claim 6, characterized in that: The fourth node control subcircuit includes: a fourth transistor, a fifth transistor and a third capacitor; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the fifth node, and the second electrode of the fourth transistor is electrically connected to the second clock signal terminal; The control electrode of the fifth transistor is electrically connected to the signal input terminal, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the first clock signal terminal; A first end of the third capacitor is electrically connected to the second node, and a second end of the third capacitor is electrically connected to the fifth node.

9. The shift register according to claim 2, characterized in that: The node control subcircuit is also electrically connected to the third power supply terminal, and the node control subcircuit includes: a first node control subcircuit, a second node control subcircuit, a third node control subcircuit and a fourth node control subcircuit; The first node control subcircuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the first node and the fourth node respectively, and is configured to provide the signal of the second power supply terminal to the fourth node, provide the signal of the second clock signal terminal to the first node, and store the voltage difference between the signal of the first node and the signal of the first power supply terminal under the control of the signals of the first clock signal terminal, the second clock signal terminal and the second power supply terminal; The second node control subcircuit is electrically connected to the first clock signal terminal, the signal input terminal, the second power terminal, the second node, the fifth node and the sixth node respectively, and is configured to provide the signal of the signal input terminal to the second node and the fifth node under the control of the signals of the first clock signal terminal, the second power terminal and the sixth node; The third node control subcircuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the fourth node, the fifth node and the sixth node respectively, and is configured to provide the signal of the first clock signal terminal to the fourth node under the control of the signal of the fifth node, and to store the voltage difference between one of the first power supply terminal and the second clock signal terminal and the signal of the sixth node under the control of the signals of the fourth node and the sixth node; The fourth node control subcircuit is electrically connected to the third power terminal, the first power terminal, the first node and the fifth node respectively, and is configured to provide a signal from the first power terminal to the first node under the control of signals from the fifth node and the third power terminal.

10. The shift register according to claim 9, characterized in that: The first node control subcircuit includes: a third transistor, a sixth transistor, a seventh transistor, an eleventh transistor, a first capacitor and a second capacitor, the second node control subcircuit includes: a first transistor, a twelfth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor, the third node control subcircuit includes: a second transistor, a fourth transistor, a fifth transistor and a third capacitor, and the fourth node control subcircuit includes: an eighth transistor and a thirteenth transistor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the fifth node; The control electrode of the second transistor is electrically connected to the fifth node, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the first clock signal terminal; A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the fourth node; The control electrode of the fourth transistor is electrically connected to the sixth node, the first electrode of the fourth transistor is electrically connected to the seventh node, and the second electrode of the fourth transistor is electrically connected to the second clock signal terminal; a control electrode of the fifth transistor is electrically connected to the fourth node, a first electrode of the fifth transistor is electrically connected to the first power supply terminal, and a second electrode of the fifth transistor is electrically connected to the seventh node; The control electrode of the sixth transistor is electrically connected to the eighth node, the first electrode of the sixth transistor is electrically connected to the second clock signal terminal, and the second electrode of the sixth transistor is electrically connected to the third node; The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is electrically connected to the third node, and the second electrode of the seventh transistor is electrically connected to the first node; The control electrode of the eighth transistor is electrically connected to the fifth node, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the first power supply terminal; The control electrode of the eleventh transistor is electrically connected to the second power supply terminal, the first electrode of the eleventh transistor is electrically connected to the fourth node, and the second electrode of the eleventh transistor is electrically connected to the eighth node; The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the fifth node, and the second electrode of the twelfth transistor is electrically connected to the second node; The control electrode of the thirteenth transistor is electrically connected to the third power supply terminal, the first electrode of the thirteenth transistor is electrically connected to the first power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the fifth node; The control electrode of the fourteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the fourteenth transistor is electrically connected to the signal input terminal, and the second electrode of the fourteenth transistor is electrically connected to the ninth node; The control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, the first electrode of the fifteenth transistor is electrically connected to the ninth node, and the second electrode of the fifteenth transistor is electrically connected to the sixth node; The control electrode of the sixteenth transistor is electrically connected to the sixth node, the first electrode of the sixteenth transistor is electrically connected to the second node, and the second electrode of the sixteenth transistor is electrically connected to the sixth node; A first end of the first capacitor is electrically connected to the eighth node, and a second end of the first capacitor is electrically connected to the third node; A first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to the first power supply terminal; A first end of the third capacitor is electrically connected to the seventh node, and a second end of the third capacitor is electrically connected to the sixth node.

11. The shift register according to claim 2, characterized in that: The cascade output subcircuit includes: a ninth transistor and a tenth transistor, and the voltage stabilization subcircuit includes: a fourth capacitor; The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the first power supply terminal, and the second electrode of the ninth transistor is electrically connected to the cascade output signal terminal; The control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the cascade output signal terminal, and the second electrode of the tenth transistor is electrically connected to the second power supply terminal; A first end of the fourth capacitor is electrically connected to the cascade output signal end, and a second end of the fourth capacitor is electrically connected to the second power supply end.

12. The shift register according to claim 1, characterized in that: The gating subcircuit comprises: a first control subcircuit, a second control subcircuit, a third control subcircuit, a fourth control subcircuit and a driving gating subcircuit; The first control subcircuit is electrically connected to the masking signal terminal, the first control signal terminal, the first power supply terminal and the tenth node respectively, and is configured to provide a signal from the first power supply terminal to the tenth node under the control of the signals from the masking signal terminal and the first control signal terminal; The second control subcircuit is electrically connected to the second control signal terminal, the third control signal terminal, the second power supply terminal and the tenth node respectively, and is configured to provide a signal from the second power supply terminal to the tenth node under the control of the signals from the second control signal terminal and the third control signal terminal; The third control subcircuit is electrically connected to the first node, the tenth node, the eleventh node and the second power supply terminal respectively, and is configured to provide the signal of the first node to the eleventh node under the control of the signal of the tenth node, and store the voltage difference between the signal of the tenth node and the signal of the second power supply terminal; The fourth control subcircuit is electrically connected to the driving output signal terminal, the masking signal terminal, the first power supply terminal and the eleventh node respectively, and is configured to provide a signal of the first power supply terminal to the eleventh node under the control of the signals of the driving output signal terminal and the masking signal terminal; The drive selection subcircuit is electrically connected to the second node, the eleventh node, the first power supply terminal, the second power supply terminal and the drive output signal terminal, respectively, and is configured to provide a signal of the first power supply terminal or the second power supply terminal to the drive output signal terminal under the control of the signals of the second node and the eleventh node, and store a voltage difference between the signals of the eleventh node and the first power supply terminal.

13. The shift register according to claim 12, characterized in that: The first control subcircuit includes: a seventeenth transistor and an eighteenth transistor, the second control subcircuit includes: a nineteenth transistor and a twenty-third transistor, the third control subcircuit includes: a twenty-first transistor and a fifth capacitor, the fourth control subcircuit includes: a twenty-second transistor and a twenty-third transistor, and the drive gating subcircuit includes: a twenty-fourth transistor, a twenty-fifth transistor and a sixth capacitor; The control electrode of the seventeenth transistor is electrically connected to the masked signal terminal, the first electrode of the seventeenth transistor is electrically connected to the tenth node, and the second electrode of the seventeenth transistor is electrically connected to the twelfth node; The control electrode of the eighteenth transistor is electrically connected to the first control signal terminal, the first electrode of the eighteenth transistor is electrically connected to the twelfth node, and the second electrode of the eighteenth transistor is electrically connected to the first power supply terminal; The control electrode of the nineteenth transistor is electrically connected to the second control signal terminal, the first electrode of the nineteenth transistor is electrically connected to the tenth node, and the second electrode of the nineteenth transistor is electrically connected to the thirteenth node; The control electrode of the twentieth transistor is electrically connected to the third control signal terminal, the first electrode of the twentieth transistor is electrically connected to the thirteenth node, and the second electrode of the twentieth transistor is electrically connected to the second power supply terminal; a control electrode of the twenty-first transistor is electrically connected to the tenth node, a first electrode of the twenty-first transistor is electrically connected to the first node, and a second electrode of the twenty-first transistor is electrically connected to the eleventh node; The control electrode of the twenty-second transistor is electrically connected to the driving output signal terminal, the first electrode of the twenty-second transistor is electrically connected to the eleventh node, and the second electrode of the twenty-second transistor is electrically connected to the fourteenth node; The control electrode of the twenty-third transistor is electrically connected to the masking signal terminal, the first electrode of the twenty-third transistor is electrically connected to the fourteenth node, and the second electrode of the twenty-third transistor is electrically connected to the first power supply terminal; A control electrode of the twenty-fourth transistor is electrically connected to the eleventh node, a first electrode of the twenty-fourth transistor is electrically connected to the first power supply terminal, and a second electrode of the twenty-fourth transistor is electrically connected to the drive output signal terminal; The control electrode of the twenty-fifth transistor is electrically connected to the second node, the first electrode of the twenty-fifth transistor is electrically connected to the driving output signal terminal, and the second electrode of the twenty-fifth transistor is electrically connected to the second power supply terminal; A first end of the fifth capacitor is electrically connected to the tenth node, and a second end of the fifth capacitor is electrically connected to the second power supply terminal; A first end of the sixth capacitor is electrically connected to the eleventh node, and a second end of the sixth capacitor is electrically connected to the first power supply terminal.

14. The shift register according to claim 1, characterized in that: The cascade sub-circuit includes: a third node, a signal received by the first control signal end of at least one shift register is the same as a signal of the third node, or a signal received by the first control signal end of at least one shift register is the same as a signal of the third node of the first M shift registers, where M is a positive integer greater than or equal to 1.

15. The shift register according to claim 1, characterized in that: The signal received by the second control signal terminal of at least one shift register is the same as the signal at the cascade output signal terminal, or the signal received by the second control signal terminal of at least one shift register is the same as the signal at the cascade output signal terminal of the first N shift registers, where N is a positive integer greater than or equal to 1.

16. The shift register according to claim 1, characterized in that: The signal received by the third control signal terminal of at least one stage of the shift register is the same as the signal of the second node.

17. A gate drive circuit, characterized in that: include: A plurality of cascaded shift registers as claimed in any one of claims 1 to 16; The cascade output signal terminal of at least one stage of shift register is connected to the signal input terminal of at least one stage of shift register other than the current stage of shift register.

18. The gate driving circuit according to claim 17, characterized in that: It also includes: an initial shift register, which includes: a cascade subcircuit in at least one stage of shift register, and the cascade output signal end of the initial shift register is electrically connected to the signal input end of the first stage shift register.

19. A display substrate, characterized in that: A device having a display area and a non-display area located at least on one side of the display area, wherein the non-display area is provided with a gate driving circuit as claimed in claim 17 or 18, and the display area further comprises: sub-pixels arranged in an array; The driving output signal terminal of at least one stage of shift register in the gate driving circuit is electrically connected to at least one row of sub-pixels.

20. A shift register driving method, characterized in that: is configured to drive the shift register according to any one of claims 1 to 16, the method comprising: The cascade subcircuit provides the signal of the second clock signal terminal to the first node and the signal of the signal input terminal to the second node under the control of the signals of the signal input terminal, the first clock signal terminal and the second clock signal terminal, and provides the signal of the first power supply terminal or the second power supply terminal to the cascade output signal terminal under the control of the signals of the first node and the second node; The gating subcircuit provides a signal from the first power supply terminal or the second power supply terminal to the driving output signal terminal under the control of the signals from the masking signal terminal, the first control signal terminal, the second control signal terminal, the third control signal terminal, the first node and the second node.

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