Non-volatile memory, related integrated circuit, electronic system and method

Abstract

The invention relates to a non-volatile memory, a related integrated circuit, an electronic system and a method. The non-volatile memory includes a row decoder including, for each word line, a respective pull-up connected to a first supply voltage and a switching circuit for selectively connecting one of the word lines to ground. The row decoder includes a demultiplexer connected to a second supply voltage less than the first supply voltage and configured to assert the enable signal according to the address signal. The switching circuit includes two n-channel FETs connected in series between a word line and ground, where a gate terminal of one FET is connected to a first signal and a gate terminal of the other FET is connected to a second voltage. The bias circuit is configured to set a voltage between the two FETs to a second voltage when the FETs are off. The switching circuit includes a p-channel FET connected between the word line and a second voltage, and a gate terminal connected to a second signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Application No. 102023000017769, filed on August 29, 2023, which is incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to memories, and in particular, row decoders of memories, such as non-volatile memories, such as phase change memories. Background Art

[0004] Figure 1 A block diagram of a typical memory 20 is shown including a memory region 200, which in turn includes a plurality of memory cells CELL. For example, the memory cells CELL are often arranged in multiple columns and rows.

[0005] For example, in a phase change memory (PCM), each memory cell CELL is based on an alloy, such as a chalcogenide alloy, such as GexSbyTz (more simply referred to as a GST alloy), which, after appropriate heat treatment, reversibly transforms from an amorphous state with low conductivity to a polycrystalline state with high conductivity. For example, in this context, U.S. patent application numbers US2019 / 0096480A1, US2019 / 0140175A1, US2019 / 0140176A1 and US2021 / 0012836A1 can be cited, the contents of which are incorporated herein by reference.

[0006] Typically, the memory 20 receives an address signal ADR at an input, wherein the address signal ADR is used to select a given memory sub-region within the memory region 200. For example, the address signal ADR may be supplied to a row decoder 202 (configured to select a word line WL) and an optional column decoder 204 (configured to select a bit line signal BL) in order to select a given memory sub-region in the memory region 200.

[0007] The memory 20 further includes one or more input terminals and / or output terminals for exchanging data signals DATA with the memory 20, wherein the data signals DATA may include data DATA_IN to be written and / or data DATA_OUT that has been read. Typically, the selected sub-area of ​​the memory cell CELL has n bits corresponding to the number of bits of each of the signals DATA_IN and DATA_OUT. Therefore, in the case where each row of the memory 20 has n bits, the column decoder 204 may be omitted, and the row decoder 202 is sufficient to select a given sub-area in the memory area 200.

[0008] The address signal ADR is usually not directly supplied to the row decoder 202 and the optional column decoder 204, but is stored in the address buffer 208. Similarly, the data signal DATA may also be stored in the data buffer 214.

[0009] Specifically, in the example considered, the memory 20 supports both read and write operations, which can be selected by the control signal W / R. To this end, the memory area 200 has an associated write and read interface 206. For example, the interface 206 may include a write circuit 212 for writing data DATA_IN to a selected memory sub-area (i.e., a selected memory cell CELL), and a read circuit 210 (e.g., including a plurality of sense amplifiers) for reading data DATA_OUT from the selected memory cell CELL.

[0010] For example, with respect to phase change memory, the (considerable) difference in conductivity between the amorphous state and the polycrystalline state enables binary data to be associated with the material state of the cell CELL. For example, the state can be detected by measuring a parameter indicative of the resistance of the material of the cell CELL via the measurement / reading circuit 210. Conversely, in order to write information in the memory cell CELL, the write circuit 212 is configured to selectively write / program the state of the memory cell (whether amorphous or polycrystalline).

[0011] For example, Figure 2A As shown, in order to make the memory cell CELL of the phase change memory 20 enter the first low conductivity state (also called reset state), the write circuit 212 applies a current I to the cell within a (short) time interval ΔT1. cell =I reset , after which the current I cell drops sharply to zero. In particular, the current I cell It should be high enough to make the material of the cell reach the melting point T of the cell. melt , which causes the material of the cell to melt. The subsequent rapid cooling makes the material amorphous.

[0012] On the contrary, Figure 2B As shown, in order to change the memory cell CELL from the first (reset) state to the second high conductivity state (also called the set state), the write circuit 212 applies a current I to the cell within a (short) time interval ΔT2. cell =I set , where I set Reset , wherein the current then decreases in a ramp or in steps during the time interval ΔT3. In particular, the current I cell =I set It should be enough to reach the crystallization temperature T of the cell​x , where T x <T melt In this case, gradual cooling leads to the formation of crystals and thus to high conductivity conditions.

[0013] For example, Figure 3 A possible implementation of a memory 20 is shown. In particular, in the example considered, a single memory cell CELL connected between a universal bit line BLr and a universal word line WLq is shown. In particular, as previously described, the cell CELL of the PCM 20 comprises a memory element GST, such as, for example, a chalcogenide alloy, connected between a bit line BL and a word line WL. As previously described, in the memory 20, the address signal ADR is usually used to select a given row of a memory area 200 via a row decoder 202, and optionally a given subset of columns of the memory area 200 via a column decoder 204. As previously described, the column decoder 204 is purely optional.

[0014] like Figure 2A and Figure 2B As shown, in order to program a given memory cell CELL of the PCM, the write circuit 212 should be configured to apply a given current I to the cell CELL. cell In the example considered, for this purpose, the write circuit 212 comprises n driver circuits 2126 , so-called programming drivers, each driver circuit 2126 generating a respective current I cell Therefore, the current I generated by the driving circuit 2126 cell can be applied to a given bit line BL, or the demultiplexer 204 (implementing a column decoder) can be used to select the applied current I according to the change of the address signal ADR cell The given positioning line BL.

[0015] In contrast, in order to generate a current flowing through a specific cell CELL, the row decoder 202 drives the word line WL according to the address signal ADR. For example, in order to enable a current to flow through Figure 3 The cell CELL shown in FIG. 1 is driven by the driving circuit 2126 (eg, via the column decoder 204) to drive the current I cellis applied to the bit line BLr, and the row decoder 202 is configured to selectively connect the word line WLq to ground. For example, in order to connect a given word line WLq to ground, the row decoder 202 may include, for each word line WL, a corresponding electronic switch MN1, such as a field effect transistor (FET) MN1, such as a metal oxide semiconductor field effect transistor (MOSFET), for example of an n-channel type, such as an NMOS transistor, wherein (the conduction path of) the electronic switch MN1 is connected between the corresponding word line WL and ground, and wherein the control terminal (e.g., the gate terminal of the FET) is driven via the demultiplexer 2020. Therefore, the electronic switch MN1 and the demultiplexer 2020 implement the row decoder 202.

[0016] Thus, in the example considered, the row decoder 202 and the optional column decoder 204 select a given subset of n memory cells CELL, and the driver circuit 2126 provides a corresponding current I to each of the selected cells CELL. cell Specifically, by using a corresponding driving circuit 2126 for each selected cell (or alternatively by sequentially providing one or more driving circuits 2126 to the selected cells), the corresponding current I cell Each selected cell CELL is supplied with power. In the example considered, the driver circuit 2126 can therefore receive one or more control signals CTRL which set the current I supplied by the driver circuit 2126. cell For example, using digital control signals, the driver circuit 2126 essentially implements a current digital-to-analog converter (IDAC). In the example considered, the control signal CTRL is generated by the control circuit 2124 according to the (write / read) signal W / R and the corresponding data bit DATA_In to be written into the cell CELL. <n>For example, in this way, the driver circuit 2126 can provide the current I cell Set to current I reset (For example, W / R = "1" and DATA_IN <n>= "0") or current I set (For example, W / R = "1" and DATA-IN <n>= "1"). In addition, the driving circuit 2126 can also be used by the reading circuit 210 to convert the current I cell A different current is set to be suitable for performing a read operation (eg, W / R=“0”). For a more detailed description of such PCM, reference may be made to document US 2021 / 012836 A1.

[0017] Similar memory interface circuit 212 is also used in other non-volatile memories 20, where a given current distribution I is applied to the memory cell CELL. cell To program the memory cell CELL. For example, other types of such memories include spin transfer torque magnetic random access memory (STT-MRAM, also called STT-RAM or sometimes ST-MRAM and ST-RAM) and resistive random access memory.

[0018] The power supply voltage V used to power the combinational and sequential logic circuits of the memory interface (such as the demultiplexer 2020 of the word line WL) LV In comparison, the drive circuit 2126 of the memory 20 is usually supplied with a higher power supply voltage V HV For example, generally, this means that the demultiplexer 2020 cannot directly drive the FET MN1, but requires an additional level conversion (specifically, a level lifter) circuit 2022 to convert the logic level of the control signal generated by the demultiplexer 2020 from the low voltage domain V LV Convert to high voltage domain V HV For example, in modern memory, the voltage V LV can be between 1V and 3V, and the voltage V HV Can be greater than 4V. Summary of the invention

[0019] Various embodiments of the present disclosure provide improved solutions for such memories, in particular for implementing row decoders of such memories. According to one or more embodiments, the above objects are achieved by memories having unique elements specifically set forth in the following claims. In addition, embodiments relate to related integrated circuits.

[0020] The claims are an integral part of the technical teaching of the description provided herein.

[0021] As previously mentioned, various embodiments of the present disclosure relate to a non-volatile memory. Specifically, the non-volatile memory includes a memory area having a plurality of bit lines and a plurality of word lines. In various embodiments, in order to program the memory, the memory includes a current source and a row decoder. Specifically, the current source is configured to provide a programming current to one or more of the bit lines, wherein the current source is powered via a first power supply voltage. The row decoder is configured to connect one of the word lines to ground according to an address signal. To this end, the row decoder includes a demultiplexer configured to provide a corresponding enable signal for each word line, wherein the demultiplexer is configured to assert one of the enable signals according to the address signal.

[0022] Specifically, in various embodiments, the demultiplexer is powered by a second power supply voltage, whereby each enable signal is connected to the second power supply voltage or ground. Specifically, in various embodiments, the second power supply voltage is less than the first power supply voltage. For example, this allows the demultiplexer and other digital circuits to use small FETs that only need to support the second power supply voltage. For example, in various embodiments, the first power supply voltage is greater than 4V, preferably between 5V and 6V, and the second power supply voltage is less than 3V, preferably between 1V and 3V.

[0023] However, this also means that the row decoder should be able to support the first power supply voltage, because the row decoder must be able to connect the word line to ground. Specifically, in various embodiments, the row decoder includes various FETs for this purpose. However, as will be described in more detail below, the solution disclosed herein allows the first power supply voltage to be greater than the gate-source and / or drain-source breakdown voltage of such FETs of the row decoder. For example, this allows all FETs of the row decoder to be implemented using the same production technology.

[0024] In particular, in various embodiments, for this purpose, the non-volatile memory comprises a power supply circuit configured to generate an auxiliary voltage, in particular a first voltage and a second voltage, wherein the second voltage is less than the first voltage, wherein the first voltage corresponds to or is less than the first power supply voltage, and wherein the second voltage corresponds to or is greater than the second power supply voltage. For example, the second voltage can be selected between 40% and 60% of the value of the first power supply voltage, preferably between 45% and 55%, preferably about 50%. Conversely, the first voltage can be selected between the first power supply voltage and the value of the first power supply voltage minus the gate-source threshold voltage of the FET of the row decoder.

[0025] For example, in various embodiments, the power supply circuit may include three resistors connected in series between a first power supply voltage and ground, wherein the second voltage corresponds to a voltage at an intermediate node between the second resistor and the third resistor, and the first voltage corresponds to a voltage at an intermediate node between the first resistor and the second resistor.

[0026] Furthermore, in various embodiments, the row decoder includes a charging circuit and a discharging circuit for each word line, the charging circuit being implemented via a pull-up connected between the corresponding word line and the first power supply voltage. The pull-up may be an active pull-up or a passive pull-up.

[0027] In various embodiments, the discharge circuit includes a first n-channel FET and a second n-channel FET connected in series. Specifically, a source terminal of the first n-channel FET is connected to ground, and a gate terminal of the first n-channel FET is connected to a first signal. In addition, a drain terminal of the second n-channel FET is connected to a corresponding word line, a source terminal of the second n-channel FET is connected to a drain terminal of the first n-channel FET, and a gate terminal of the second n-channel FET is connected to a second voltage.

[0028] Furthermore, in various embodiments, the discharge circuit includes a first p-channel FET, wherein a drain terminal of the first p-channel FET is connected to a second voltage, a source terminal of the first p-channel FET is connected to a corresponding word line, and a gate terminal of the first p-channel FET is connected to a second signal. In essence, the p-channel FET is used to pre-discharge the word line.

[0029] Finally, in various embodiments, the discharge circuit includes a bias circuit configured to set a voltage at a drain terminal of the first n-channel FET to a second voltage when the first n-channel FET and the second n-channel FET are disconnected. For example, in various embodiments, the bias circuit includes a third n-channel FET, wherein a source terminal of the third n-channel FET is connected to a drain terminal of the first n-channel FET, a drain terminal of the third n-channel FET is connected to the second voltage, and a gate terminal of the third n-channel FET is connected to a corresponding word line.

[0030] Furthermore, the row decoder comprises a circuit for driving the first n-channel FET via the first signal and the first p-channel FET via the second signal. Specifically, in various embodiments, for this purpose, the row decoder comprises a first delay circuit and a second delay circuit.

[0031] Specifically, the first delay circuit is configured to detect a change in the enable signal. In response to detecting a change in the enable signal from an asserted logic level to a de-asserted logic level, the first delay circuit connects the first signal to ground. Conversely, in response to detecting a change in the enable signal from a de-asserted logic level to an asserted logic level, the first delay circuit sets the first signal after the first delay to a voltage to close the first FET. For example, in various embodiments, the first delay circuit is configured to close the first FET by setting the first signal to a second voltage. In various embodiments, the enable signal is asserted when the enable signal is connected to the first power supply voltage.

[0032] For example, to achieve such asymmetric delay, the first delay circuit includes a first capacitor and a fourth n-channel FET, the first capacitor having a first terminal connected to the ground and a second terminal connected to the second voltage via a fourth resistor, and the fourth n-channel FET is configured to selectively short-circuit the capacitor according to an enable signal.

[0033] In contrast, the second delay circuit is configured to detect a change in the enable signal. In response to detecting a change in the enable signal from a de-asserted logic level to an asserted logic level, the second delay circuit sets the second signal to a second voltage. In contrast, in response to detecting a change in the enable signal from an asserted logic level to a de-asserted logic level, the second delay circuit sets the second signal after the second delay to a first voltage. For example, the second delay circuit may include a second capacitor and a fifth n-channel FET, the second capacitor having a first terminal connected to the second voltage and a second terminal connected to the first voltage via a fifth resistor, the fifth n-channel FET being configured to selectively short-circuit the capacitor according to the enable signal.

[0034] In various embodiments, the second delay circuit further includes a level shifter circuit configured to generate a level-shifted version of the enable signal, wherein the level-shifted version is set to the first voltage or the second voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, which are provided by way of non-limiting example only, in which:

[0036] Figure 1 An example of a memory including a plurality of memory cells is shown;

[0037] Figure 2A and Figure 2B An example of performing a reset and a set of a memory cell is shown;

[0038] Figure 3 Shows Figure 1 An example of a memory write interface;

[0039] Figure 4 An embodiment of a row decoder according to the present disclosure is shown;

[0040] Figure 5 Shows Figure 4 An embodiment of the operation of a row decoder;

[0041] Figure 6 Shows Figure 4 An embodiment of a voltage supply circuit for a row decoder;

[0042] Figure 7 Shows Figure 4 An embodiment of a first delay circuit of a row decoder;

[0043] Fig. 8A and Figure 8B Shows Figure 4 An embodiment of a first level conversion circuit of a row decoder;

[0044] Fig. 9 Shows Figure 4 An embodiment of a second delay circuit of a row decoder;

[0045] Fig.10 Shows Figure 4 An embodiment of a second level conversion circuit of a row decoder; and

[0046] Fig.11 An embodiment of a system including a memory according to the present disclosure is shown. DETAILED DESCRIPTION

[0047] In the following description, various specific details are shown to provide a deeper understanding of the embodiments. The embodiments can be obtained without one or more of the specific details, or using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments are not obscured.

[0048] References to "an embodiment" or "one embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in various places in this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or characteristics may be combined in any appropriate manner.

[0049] The reference signs used herein are provided for convenience only and therefore do not define the scope of protection or the scope of the embodiments.

[0050] Described below Figures 4 to 11 In, reference has been made Figures 1 to 3 The parts, elements or components described are indicated by the same reference numerals used previously in these figures. In order not to overload this detailed description, the previous description of these elements will not be repeated below.

[0051] like Figure 3 As shown, generally, a row decoder of a nonvolatile memory (especially when using a programming current I cell In the case of a non-volatile memory such as PCM, STT-MRAM or ReRAM, the row decoder 202 includes a corresponding FET MN1 and a demultiplexer 2020 for each word line WL, the demultiplexer being configured to drive the FET MN1 so as to close one of the FET MN1 according to the (e.g., buffered) address signal ADR, thereby connecting one of the word lines WL to ground. In addition, the power supply voltage V of the demultiplexer 2020 for the word line WL is connected to the ground. LV In comparison, the (multiple) driving circuits 2126 are typically supplied with a higher power supply voltage V HV .

[0052] Therefore, although the demultiplexer 2020 can use the maximum supported voltage V LV The first type of FET, but the level conversion circuit 2022 and the FET MN1 must use a maximum voltage V HV However, it may be complicated to implement such different FETs supporting different maximum voltages within the same integrated circuit. For example, in order to support a higher gate-source voltage, the gate oxide of the second type of FET must be thicker than the gate oxide of the first type of FET. However, this means that the gate oxides of both types of FETs cannot be implemented in the same process steps, but rather additional steps are required to implement the thicker gate oxide of the second type of FET.

[0053] Therefore, in order to reduce the cost, the FETs of the combinational and logic circuits (such as the demultiplexer 2020) can also be implemented using the second type of FETs, also using the power supply voltage V HV However, this will generate additional power losses.

[0054] Figure 4 An embodiment of the row decoder 202a is shown, in which each FET MN1 is replaced with a corresponding switch circuit, wherein each switch circuit may include only low-power FETs. Specifically, in various embodiments, these low-power FETs are configured to support a maximum gate-source voltage and a maximum drain-source voltage V LV , but does not support V HV For example, this means that when the gate-source voltage of the drain-source voltage reaches the voltage V HV The low power FET will be damaged.

[0055] Specifically, the row decoder 202a also includes a demultiplexer 2020a configured to generate a plurality of enable signals EN, wherein each enable signal EN is associated with a corresponding word line WL. According to the foregoing description, the demultiplexer 2020a is configured to assert one of the enable signals EN according to the address signal ADR. For example, in various embodiments, the enable signal EN is asserted by setting the enable signal EN to high. However, in other embodiments, the enable signal EN is asserted by setting the enable signal EN to low.

[0056] Therefore, in the embodiment under consideration, when the enable signal EN is asserted / set to the first logic level, the corresponding word line WL should be connected to the ground GND, and when the enable signal EN is de-asserted / set to the second logic level, the corresponding word line WL should be connected to the voltage V HV , which is used to power the drive circuit / current generator 2126 (see also Figure 3 description).

[0057] Specifically, in the embodiment considered, the word line WL is connected via a pull-up 30 to a voltage V HV Typically, the pull-up may be a passive pull-up, such as a pull-up resistor, for example a resistor, or an active pull-up, which may be controlled, for example, by an enable signal. For example, the active pull-up may be enabled when the corresponding enable signal EN is de-asserted / set to the second logic level.

[0058] In contrast, in order to connect the word line WL to the ground GND, the row decoder 202a includes an n-channel FET MN2 such as an NMOS and an additional switch circuit 32. Specifically, the source terminal of the FET MN2 is connected (e.g., directly) to the ground GND, and the drain terminal of the FET MN2 represents a node A connected to the word line WL via the switch circuit 32.

[0059] As mentioned above, the FET of row decoder 202a may not be able to support the voltage V HV Therefore, in various embodiments, to enable the word line WL, i.e., to connect the word line to the ground GND, the circuit 32 is configured to first discharge the word line to a voltage lower than the maximum drain-source voltage supported by the FET MN2. Next, the FET MN2 is closed to connect (short-circuit) the word line WL to the ground GND.

[0060] In particular, in the embodiment considered, the circuit 32 comprises:

[0061] a p-channel FET MP1, such as a PMOS, wherein a source terminal of the FET MP1 is connected (e.g., directly) to the word line WL, a drain terminal of the FET MP1 is connected (e.g., directly) to a voltage V2, and a gate terminal of the FET MP1 is driven via a signal EN2;

[0062] An n-channel FET MN3, such as an NMOS, wherein a drain terminal of FET MN3 is connected (e.g., directly) to word line WL, a source terminal of FET MN3 is connected (e.g., directly) to a drain terminal of FET MN2 (node ​​A), and a gate terminal of FET MN3 is connected (e.g., directly) to voltage V2.

[0063] Thus, in the embodiment under consideration, when FET MP1 is closed, word line WL is connected to voltage V2. For example, in various embodiments, voltage V2 is between V HV Therefore, in order to properly drive FET MP1, signal EN2 should be set to:

[0064] In order to disconnect FET MP1 to a voltage V1, where the value of V1 is V HV To V HV minus the gate-source threshold voltage of FET MP1;

[0065] In order to close FET MP1 and allow word line WL to discharge to voltage V2.

[0066] For example, in various embodiments, the voltage V HV is greater than 4 V and is selected, for example, in the range between 5 V and 6 V, for example, about 5 V, and the voltage V2 corresponds to V HV 50% of, for example, about 2.5 V. In this case, the voltage V1 may be selected in the range between 5 V and about 4.4 V, and may correspond to, for example, 4.5 V.

[0067] For example, Figure 6 shows a voltage V HV One embodiment of a power supply circuit 50 that generates voltages V1 and V2.

[0068] Specifically, in the embodiment considered, the voltage V2 is generated via a voltage divider and a voltage buffer 502 (such as a voltage follower). In contrast, the voltage V1 may correspond to the voltage V HV , or it may be generated via a voltage divider and a voltage buffer 500 (such as a voltage follower). Figure 6 The voltage generator 50 includes a series connection between the voltage V HV and ground, wherein voltage V2 (via buffer 502 ) corresponds to the voltage at the middle node between resistors R2 and R3 , and voltage V1 (via buffer 500 ) corresponds to the voltage at the middle node between resistors R1 and R2 .

[0069] In the embodiment under consideration, the circuit 32 also includes a bias circuit 300 configured to prevent the node A from remaining floating when the FETs MN2 and MN3 are turned off. Specifically, in various embodiments, the bias circuit is configured to couple the node A to the voltage V2 when the FETs MN2 and MN3 are turned off, thereby also limiting the drain-source voltage of the FETs MN2 and MN3. In general, the bias circuit 300 can be a passive bias circuit or an active bias circuit.

[0070] Specifically, with respect to the active bias circuit, when the gate-source voltage of the FET MN3 (i.e., the voltage difference between the voltage V2 and the voltage at the node A) is greater than the threshold voltage of the FET MN3, the FET MN3 is closed. In this regard, when the FET MN2 is turned off (the signal EN1 is low), when the voltage at the node A exceeds the voltage V2 minus the threshold voltage of the FET MN3, the FET MN3 is automatically turned off.

[0071] Therefore, in various embodiments, the active bias circuit 300 can be configured to provide a bias voltage V WL The bias circuit 300 implicitly detects whether the FETs MN2 and MN3 are disconnected by exceeding the voltage V2. For example, in the embodiment considered, the bias circuit 300 includes an n-channel FET MN4, such as an NMOS, wherein the source terminal of the FET MN4 is (e.g., directly) connected to the drain terminal (node ​​A) of the FET MN2, the drain terminal of the FET MN4 is (e.g., directly) connected to the voltage V2, and the gate terminal of the FET MN4 is (e.g., directly) connected to the word line WL.

[0072] In contrast, a passive bias circuit may be implemented by replacing the FET MN4 with a resistor (such as a resistor) connected between the node A and the voltage V2, wherein the resistor preferably has a larger resistance value.

[0073] Therefore, if Figure 5 As shown, in various embodiments, the enable signal EN is initially de-asserted, for example, set to low. In this case, the row decoder 202a is configured as:

[0074] setting signal EN2 to voltage V1, whereby p-channel FET MP1 is turned off; and

[0075] The signal EN1 is set to ground GND, so that the n-channel FET MN2 is turned off.

[0076] In this case, as will be described below, FET MN3 is turned off and node A is set to voltage V2 via bias circuit 300. For example, in the embodiment considered, FET MN4 is closed because the voltage V WL is greater than voltage V2, so node A is connected to voltage V2. Therefore, in the embodiment considered, the drain-source voltage of FETs MP1 and MN3 is V WL -V2, and the drain-source voltage of FET MN2 is V2.

[0077] At time t1, the demultiplexer 2020a asserts the enable signal EN, for example, in response to a write request to the corresponding address ADR. Once the enable signal EN is asserted at time t1, the row decoder 202a is configured as follows:

[0078] Setting signal EN2 to voltage V2, thereby closing p-channel FET MP1; and

[0079] The signal EN1 is set to ground GND, thereby keeping the n-channel FET MN2 off.

[0080] Therefore, in this way, the word line WL is discharged to the voltage V2 until the voltage V WL The voltage V2 plus the gate-source threshold voltage of FET MP1 is reached. For example, when a voltage V2 of 2.5V is used, the word line WL is discharged to about 3.2V (assuming a gate-source threshold voltage of 0.7V).

[0081] In this case, the active bias circuit 300 may also be disabled. For example, in the embodiment considered, when the voltage V WL When it drops below voltage V2 plus the threshold voltage of FET MN4, FET MN4 turns off.

[0082] Therefore, in the embodiment considered, the pre-discharged word line WL can now be fully discharged and it is sufficient that the FET can support the remaining voltage (i.e., the voltage V2 plus the gate-source threshold voltage of the FET MP1). For example, in the embodiment considered, after a time Δt1 relative to the instant t1, the row decoder 202a is configured as follows:

[0083] Setting signal EN2 to voltage V2; and

[0084] Signal EN1 is set to a voltage, such as voltage V2, to close n-channel FET MN2.

[0085] In this case, the FET MP1 remains turned off. In contrast, the FET MN3 remains turned on because the gate-source voltage of the FET MN3 is higher than the threshold voltage of the FET MN3 (ie, the gate-source voltage of the FET MN3 is about V2). Therefore, in this way, the word line WL is connected to the ground GND via the FETs MN2 and MN3.

[0086] In this case, the active bias circuit 300 may remain disabled. For example, the FET MN4 remains off because the gate-source voltage of the FET MN4 is lower than the threshold voltage of the FET MN4.

[0087] FETs MN2, MN3 and MP1 can also be used to gradually increase the voltage V of the word line WL Specifically, once the demultiplexer 2020a de-asserts the enable signal EN at time t3, the row decoder 202a is configured as:

[0088] Setting signal EN2 to voltage V2; and

[0089] The signal EN1 is set to ground GND, thereby turning off the n-channel FET MN2.

[0090] Therefore, at time t5, the voltage V WL Increased due to the pull-up 30. Specifically, due to the increased voltage V WL , when the voltage at node A reaches voltage V2 minus the gate-source threshold voltage of FET MN3, FET MN3 is turned off. In addition, since the gate terminal of FET MP1 is connected to voltage V2, FET MP1 turns voltage V WL The limit is the voltage V2 plus the gate-source threshold voltage of FET MP1.

[0091] Typically, time t5 may correspond to time t3, or time t5 may start after a delay of Δt3. For example, when a passive pull-up 30 is used, once FET MN2 is turned off (ie, t5=t3), the voltage V WL Increase immediately.

[0092] In contrast, when using active pull-ups 30, the row decoder 202a may be configured to deactivate the pull-ups at a time t1 when the enable signal EN is asserted or after a given delay relative to the time t1 when the enable signal EN is asserted. In a complementary manner, the row decoder 202a may be configured to activate the pull-ups 30 at a time t3 when the enable signal EN is deasserted or after a given delay Δt3 relative to the time when the enable signal EN is deasserted. In general, the delay Δt3 may also simply result from the propagation delay of activating the pull-ups at time t3.

[0093] Thus, in the embodiment considered, after a delay Δt2 relative to the instant t3 (where Δt2>Δt3), the row decoder 202a is configured as:

[0094] Setting signal EN2 to voltage V1; and

[0095] Set the signal EN1 to ground GND.

[0096] Therefore, in this case, FET MP1 is off and word line WL is charged to a maximum voltage via pull-up 30. Basically, the maximum voltage at the word line is defined via pull-up 30.

[0097] As previously mentioned, when FETs MN2 and MN3 are turned off, bias circuit 300 should apply a bias voltage to node A. For example, in the embodiment under consideration, once voltage V WL When voltage V2 plus the gate-source threshold voltage of FET MN4 is reached, FET MN4 connects node A to voltage V2.

[0098] Therefore, if Figure 4 As shown, in order to generate delayed signals EN1 and EN2 for driving FETs MN2 and MP1, respectively, the row decoder 202a may include corresponding delay circuits 36 and 40 for each signal. In addition, the enable signal EN2 is associated with a level conversion circuit 38 (particularly a level shifter). Optionally, the enable signal EN1 may also have an associated level conversion circuit 34. In general, the level conversion may be performed before the delay operation (e.g., Figure 4 In various embodiments, the level conversion circuit may be integrated in the corresponding delay circuit.

[0099] For example, Figure 7 FIG. 3 shows an embodiment of the delay circuit 36. Specifically, Figure 5 As shown, the delay circuit 36 ​​is configured as follows:

[0100] In response to detecting that the enable signal EN changes from de-asserted to asserted, for example, in response to a rising edge of the signal EN, setting the signal EN1 after a delay Δt1 to high;

[0101] In response to detecting that the enable signal EN changes from asserted to de-asserted, for example, in response to a falling edge of the signal EN, the signal EN1 is immediately (or after a short delay that is an order of magnitude less than the delay Δt1 ) set low.

[0102] For example, in the embodiment considered, different delays are introduced via a delay circuit 36, which includes: a capacitor 364, with a first terminal connected to the supply voltage via a resistor 368 and a second terminal connected to ground; and an n-channel FET 362, such as an NMOS, with a drain terminal connected to the first terminal of the capacitor (an intermediate node between the capacitor 364 and the resistor 368) and a source terminal connected to ground.

[0103] Thus, when FET 362 is off, capacitor 364 is gradually charged via resistor 368, and when FET 362 is closed, capacitor 364 is (almost instantly) discharged.

[0104] Therefore, in the embodiment considered, the circuit 36 ​​includes a comparator 366, such as a comparator with hysteresis, for example implemented with an even number of inverters (not gates), which is configured to set the signal EN1 high when the voltage at the capacitor 364 is greater than a first threshold, and to set the signal EN1 low when the voltage at the capacitor 364 is less than a second threshold, and the second threshold can also correspond to the first threshold.

[0105] Therefore, when the enable signal EN (or its level-shifted version EN V2 ), the level of the gate voltage of the FET 362 is inverted. Therefore, in the considered embodiment, the delay circuit 36 ​​includes an inverter 360 configured to drive the gate terminal of the FET 362 with an inverted version of the signal EN. Generally, the inverter 360 can also be omitted or implemented in the level conversion circuit 34, depending on the logic level of the signal EN.

[0106] In the case where the delay circuit 36 ​​directly drives the FET MN2, the comparator circuit 366 is powered by the voltage V2, whereby the comparator 366 generates a signal that is set to V2 or ground. In various embodiments, the resistor 368 and the optional inverter 360 are also powered by the voltage V2.

[0107] Fig. 8A The first embodiment of the level conversion circuit 34a is shown. For example, when the voltage V LV This circuit can be used when (for signal EN) is less than voltage V2.

[0108] For example, in Fig. 8A In the embodiment, the level shifting circuit 34a includes an n-channel FET 340, wherein the drain terminal is connected to the power supply voltage V2 via a pull-up resistor 342, and the source terminal is connected to ground. Therefore, by driving the gate terminal of the FET 340 with the inverted version of the signal EN, the drain terminal of the FET 340 provides the level shifted version EN of the signal EN. V2 , the version is set to V2 or ground.

[0109] Figure 8B A second embodiment of a level shifting circuit 34 b is shown in which resistor 342 has been replaced with a p-channel FET 348 .

[0110] In particular, in the considered embodiment, the source terminal of the FET 340 is connected to the ground, the drain terminal of the FET 340 is connected to the drain terminal of the FET 348, and the source terminal of the FET 348 is connected to the power supply voltage V2. Furthermore, the source terminal of the further n-channel FET 344 is connected to the ground GND, the drain terminal of the further FET 344 is connected to the drain terminal of the further p-channel FET 346, and the source terminal of the further p-channel FET 346 is connected to the power supply voltage V2. Finally, the gate terminal of the FET 348 is connected to the drain terminal of the FET 344 (an intermediate node between the FETs 344 and 346), and the gate terminal of the FET 346 is connected to the drain terminal of the FET 340 (an intermediate node between the FETs 340 and 348). Thus, by driving the gate terminal of FET 344 with signal EN and driving the gate terminal of FET 340 with an inverted version of signal EN, the drain terminal of FET 340 again provides a level shifted version of signal EN. V2 , the version is set to V2 or ground GND.

[0111] Therefore, the delay circuit 36 ​​is supplied with a voltage V LV In the case of FIG. 1 , a similar level conversion circuit 34 a or 34 b may also be provided at the output of the delay circuit 36 ​​.

[0112] Fig. 9 FIG. 4 shows an embodiment of the delay circuit 40. Specifically, Figure 5 As shown, the delay circuit 36 ​​is configured as follows:

[0113] In response to detecting that the enable signal EN changes from assertion to de-assertion, for example, in response to a falling edge of the signal EN, setting the signal EN2 after a delay Δt2 to high;

[0114] In response to detecting that the enable signal EN changes from de-asserted to asserted, for example, in response to a rising edge of the signal EN, the signal EN2 is immediately (or after a short delay that is an order of magnitude less than the delay Δt2 ) set low.

[0115] For example, in the embodiment considered, the circuit 40 has received a signal EN corresponding to a level-shifted and inverted version of the signal EN V1 Thus, similar to delay circuit 36, delay circuit 40 may include:

[0116] a capacitor 404 with a first terminal connected to a voltage V1 via a resistor 408 and a second terminal connected to a voltage V2, thus representing a shifted ground; and an n-channel FET 402, such as an NMOS, with a drain terminal connected to a first terminal of the capacitor 404 (an intermediate node between the capacitor 404 and the resistor 408) and a source terminal connected to a voltage V2;

[0117] a comparator 406, such as a comparator with hysteresis (e.g., implemented with an even number of inverters (not gates)), configured to set the signal EN2 to V1 (high) when the voltage at the capacitor 404 is greater than a first threshold, and to set the signal EN2 to V2 (low) when the voltage at the capacitor 404 is less than a second threshold, which may also correspond to the first threshold, wherein the comparator 406 is powered by the voltage V1 and referenced to the voltage V2;

[0118] Another inverter 400, which is based on the signal EN V1 The gate terminal of the drive FET 402.

[0119] Normally, when the signal EN V1 When only corresponding to the level-shifted version of the signal EN, the inverter 400 may be omitted, or the inverter 400 may be implemented in the level conversion circuit 38 .

[0120] Fig.10 One embodiment of a level shifter 38 is shown. Specifically, since the level shifter 38 operates at a voltage V2, the level shifter should ensure that the voltage at the FET does not exceed the maximum allowed voltage.

[0121] Specifically, to this end, the level shifter 38 includes an even number of inverter stages, such as two inverters 380 and 382, ​​which are connected to form a ring, wherein these inverters are powered by a voltage V1 and referenced to a voltage V2. Therefore, by setting the input of the inverter 380 or the even-numbered inverters to low, the output of the last inverter (e.g., inverter 380) can be set to V1 (high). Conversely, by setting the input of the odd-numbered inverter (e.g., inverter 382) to low, the output of the last inverter (e.g., inverter 380) can be set to V2 (low).

[0122] Specifically, in the embodiment under consideration, the input of the inverter 382 is connected to a low voltage via an n-channel FET 384 and a first voltage limiter circuit. Specifically, in the embodiment under consideration, the source terminal of the FET 384 is connected to ground, the drain terminal is connected to the input of the inverter 382 via the first voltage limiter circuit, and the gate terminal of the FET 384 is connected to the enable signal EN. In this regard, the first voltage limiter circuit is configured to limit the voltage at the input of the inverter 382 and the drain-source voltage of the FET 384 (when the FET 384 is turned off).

[0123] For example, in the embodiment considered, the first voltage limiter circuit comprises a p-channel FET 393 and two n-channel FETs 392 and 391, where:

[0124] The source terminal of FET 393 is connected to the input of inverter 382, ​​the drain terminal of FET 393 is connected to the drain terminal of FET 392, and the gate terminal of FET 393 is connected to voltage V2;

[0125] The gate terminal of FET 392 is connected to the drain terminal of FET 392; and

[0126] The source terminal of the FET 391 is connected to the drain terminal of the FET 384 , the drain terminal of the FET 391 is connected to the source terminal of the FET 392 , and the gate terminal of the FET 391 is connected to the voltage V2 .

[0127] Essentially, p-channel FET 393 implements a cascode that limits the voltage at the input of inverter 382 to a minimum value corresponding to voltage V2 plus the gate-source threshold voltage of FET 393. Conversely, n-channel FET 391 implements a cascode that limits the voltage at the drain terminal of FET 384. Finally, FET 392 essentially implements a diode for reducing voltage. Typically, based on the specific voltage level, FET 392 is purely optional and can be omitted or replaced with a plurality of FETs connected in series, each FET being configured as a diode.

[0128] Similarly, in the embodiment under consideration, the input of the inverter 380 is connected to a low voltage via an n-channel FET 386 and a second voltage limiter circuit. Specifically, in the embodiment under consideration, the source terminal of the FET 386 is connected to ground, the drain terminal is connected to the input of the inverter 380 via the second voltage limiter circuit, and the gate terminal of the FET 386 is connected to an inverted version of the enable signal EN. In this regard, the second voltage limiter circuit is configured to limit the voltage at the input of the inverter 380 and the drain-source voltage of the FET 386 (when the FET 386 is turned off).

[0129] For example, in the embodiment considered, the second voltage limiter circuit comprises a p-channel FET 396 and two n-channel FETs 394 and 395, where:

[0130] The source terminal of FET 396 is connected to the input of inverter 380, the drain terminal of FET 396 is connected to the drain terminal of FET 395, and the gate terminal of FET 396 is connected to voltage V2;

[0131] The gate terminal of FET 395 is connected to the drain terminal of FET 395; and

[0132] The source terminal of FET 394 is connected to the drain terminal of FET 386 , the drain terminal of FET 394 is connected to the source terminal of FET 395 , and the gate terminal of FET 394 is connected to voltage V2 .

[0133] Thus, in this case, p-channel FET 396 implements a cascode that limits the voltage at the input of inverter 380 to a minimum value. Conversely, n-channel FET 394 implements a cascode that limits the voltage at the drain terminal of FET 386. Finally, FET 395 essentially implements a diode for reducing voltage. Furthermore, FET 395 can be omitted or replaced with a plurality of FETs connected in series, each FET being configured as a diode.

[0134] Thus, when FET 384 is driven with the enable signal EN and FET 386 is driven with an inverted version of the enable signal EN, the output of the last inverter of the loop (e.g., inverter 380) has provided an inverted and level-shifted version of the signal EN. V1 Optionally, the signal EN V1 It may also be generated via comparator 388, such as a comparator with hysteresis, for example, implemented with an even number of inverters (not gates), which is configured to assert signal EN when the voltage at the output of inverter 380 is greater than a first threshold. V1 is set to V1 (high), and when the voltage at the output of the inverter 380 is less than the second threshold, the signal EN V1 Set to V2 (low), the second threshold may also correspond to the first threshold.

[0135] Therefore, the solution disclosed herein ensures that the gate-source and drain-source voltages of the various FETs of the row decoder 202a do not exceed a maximum voltage, which is at most the voltage V2 plus the gate-source threshold voltage of the p-channel FET MP1, so that the maximum allowed voltage can be less than the voltage V HV .

[0136] Fig.11 A portion of an electronic system 130 according to the present disclosure is shown. The electronic system 130 may be used for an electronic device such as: a PDA (personal digital assistant); a portable or fixed computer that may have wireless data transmission capabilities; a mobile phone; a digital audio player; a camera or video camera; or other devices capable of processing, storing, sending and receiving information.

[0137] In particular, the electronic system 130 comprises the above-mentioned (non-volatile) memory 20 and a processor or processing unit 131 (for example, equipped with a microprocessor, DSP or microcontroller), which are both coupled to a bus 136 designed to exchange data with the memory 20. Therefore, the processor or processing unit 131 can generate the signals ADR and DATA_IN described above.

[0138] Additionally, the electronic system 130 may optionally include one or more of the following elements coupled to the bus 136:

[0139] Input / output device 132 (e.g., equipped with a keypad and a display) for inputting and displaying data;

[0140] A wireless interface 134, such as an antenna, for sending and receiving data via a radio frequency wireless communication network;

[0141] RAM 135;

[0142] The battery 137 can be used as a power source in the electronic system 130; that is, the battery 137 can be used to generate a power supply voltage V LV and / or V HV ;as well as

[0143] Camera 138.

[0144] In various embodiments, processor or processing unit 131 may be connected to memory 20 via a dedicated connection that is distinct from and possibly in addition to bus 136 (which may or may not be present).

[0145] Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what is described and illustrated herein purely by way of example, without departing from the scope of the invention as defined in the appended claims.< / n> < / n> < / n>

Claims

1. A non-volatile memory, comprising: a memory region having a plurality of bit lines and a plurality of word lines; a current source configured to provide a programming current to one or more of the bit lines, wherein the current source is powered via a first supply voltage; a power supply circuit configured to generate a first voltage and a second voltage, wherein the second voltage is less than the first voltage, wherein the first voltage corresponds to or is less than the first power supply voltage, and wherein the second voltage corresponds to or is greater than a second power supply voltage; as well as a row decoder configured to connect one of the word lines to ground according to a first change of an address signal, and comprising a demultiplexer, the demultiplexer being configured to provide a corresponding enable signal for each word line, and assert one of the enable signals according to a second change of the address signal, wherein the demultiplexer is powered by the second power supply voltage, wherein each enable signal is connected to the second power supply voltage or the ground, wherein the second power supply voltage is less than the first power supply voltage, and wherein the row decoder comprises, for each word line: A pull-up connected between the corresponding word line and the first power supply voltage; a first n-channel field effect transistor FET, wherein a source terminal of the first n-channel FET is connected to the ground and a gate terminal of the first n-channel FET is connected to a first signal; a second n-channel FET, wherein a drain terminal of the second n-channel FET is connected to the corresponding word line, a source terminal of the second n-channel FET is connected to the drain terminal of the first n-channel FET, and a gate terminal of the second n-channel FET is connected to the second voltage; a first p-channel FET, wherein a drain terminal of the first p-channel FET is connected to the second voltage, a source terminal of the first p-channel FET is connected to the corresponding word line, and a gate terminal of the first p-channel FET is connected to a second signal; a bias circuit configured to set a drain voltage at the drain terminal of the first n-channel FET to the second voltage when the first n-channel FET and the second n-channel FET are disconnected; The first delay circuit is configured as follows: detecting a change in the enable signal; connecting the first signal to the ground in response to detecting a change in the enable signal from an asserted logic level to a de-asserted logic level; and In response to detecting a change in the enable signal from the de-asserted logic level to the asserted logic level, setting the first signal after a first delay to a voltage to close the first FET; and The second delay circuit is configured as follows: detecting the change of the enable signal; in response to detecting the change of the enable signal from the de-asserted logic level to the asserted logic level, setting the second signal to the second voltage; and In response to detecting the change of the enable signal from the asserted logic level to the de-asserted logic level, the second signal after a second delay is set to the first voltage. 2 . The memory according to claim 1 , wherein the first power supply voltage is greater than a gate-source and / or drain-source breakdown voltage of the FET.

3. The memory of claim 1, wherein the second voltage is selected between 40% and 60% of the first power supply voltage.

4. The memory of claim 1, wherein the first voltage is selected between the first power supply voltage and the first power supply voltage minus a gate-source threshold voltage of the first p-channel FET.

5. The memory of claim 1, wherein the first power supply voltage is greater than 4V, and wherein the second power supply voltage is less than 3V.

6. The memory according to claim 1, wherein the bias circuit comprises: a third n-channel FET, wherein a source terminal of the third n-channel FET is connected to the drain terminal of the first n-channel FET, a drain terminal of the third n-channel FET is connected to the second voltage, and a gate terminal of the third n-channel FET is connected to a corresponding word line.

7. A memory according to claim 1, wherein the power supply circuit includes a first resistor, a second resistor and a third resistor connected in series between the first power supply voltage and the ground, wherein the second voltage corresponds to a first node voltage at a first intermediate node between the second resistor and the third resistor, and the first voltage corresponds to a second node voltage at a second intermediate node between the first resistor and the second resistor.

8. The memory of claim 1, wherein the enable signal is asserted when the enable signal is connected to the first power supply voltage. 9 . The memory of claim 1 , wherein the first delay circuit is configured to close the first FET by setting the first signal to the second voltage.

10. The memory according to claim 9, wherein the first delay circuit comprises: a first capacitor having a first terminal connected to the ground and a second terminal connected to the second voltage via a fourth resistor; as well as A fourth n-channel FET is configured to selectively short-circuit the first capacitor according to the enable signal.

11. The memory according to claim 10, wherein the second delay circuit comprises: a second capacitor having a first terminal connected to the second voltage and a second terminal connected to the first voltage via a fifth resistor; as well as A fifth n-channel FET is configured to selectively short-circuit the second capacitor according to the enable signal.

12. The memory according to claim 1, wherein the second delay circuit comprises: A level shifter circuit is configured to generate a level-shifted version of the enable signal, wherein the level-shifted version of the enable signal is set to the first voltage or the second voltage.

13. The memory of claim 1, wherein the memory is disposed on an integrated circuit.

14. An electronic system comprising: a processor configured to generate an address signal; as well as a non-volatile memory operatively coupled to the processor and comprising: a memory region having a plurality of bit lines and a plurality of word lines; a current source configured to provide a programming current to one or more of the bit lines, wherein the current source is powered via a first supply voltage; a power supply circuit configured to generate a first voltage and a second voltage, wherein the second voltage is less than the first voltage, wherein the first voltage corresponds to or is less than the first power supply voltage, and wherein the second voltage corresponds to or is greater than a second power supply voltage; and a row decoder configured to connect one of the word lines to ground according to a first change of the address signal, and comprising a demultiplexer, the demultiplexer being configured to provide a corresponding enable signal for each word line, and assert one of the enable signals according to a second change of the address signal, wherein the demultiplexer is powered by the second power supply voltage, wherein each enable signal is connected to the second power supply voltage or the ground, wherein the second power supply voltage is less than the first power supply voltage, and wherein the row decoder comprises, for each word line: A pull-up connected between the corresponding word line and the first power supply voltage; a first n-channel field effect transistor FET, wherein a source terminal of the first n-channel FET is connected to the ground and a gate terminal of the first n-channel FET is connected to a first signal; a second n-channel FET, wherein a drain terminal of the second n-channel FET is connected to the corresponding word line, a source terminal of the second n-channel FET is connected to the drain terminal of the first n-channel FET, and a gate terminal of the second n-channel FET is connected to the second voltage; a first p-channel FET, wherein a drain terminal of the first p-channel FET is connected to the second voltage, a source terminal of the first p-channel FET is connected to the corresponding word line, and a gate terminal of the first p-channel FET is connected to a second signal; a bias circuit configured to set a drain voltage at the drain terminal of the first n-channel FET to the second voltage when the first n-channel FET and the second n-channel FET are disconnected; The first delay circuit is configured as follows: detecting a change in the enable signal; connecting the first signal to the ground in response to detecting a change in the enable signal from an asserted logic level to a de-asserted logic level; and In response to detecting a change in the enable signal from the de-asserted logic level to the asserted logic level, setting the first signal after a first delay to a voltage to close the first FET; and The second delay circuit is configured as follows: detecting the change of the enable signal; in response to detecting the change of the enable signal from the de-asserted logic level to the asserted logic level, setting the second signal to the second voltage; and In response to detecting the change of the enable signal from the asserted logic level to the de-asserted logic level, the second signal after a second delay is set to the first voltage.

15. A method of operating a non-volatile memory, the non-volatile memory comprising: A memory region having a plurality of bit lines and a plurality of word lines, a current source powered via a first supply voltage, a power supply circuit configured to generate a first voltage and a second voltage, the second voltage being less than the first voltage, the first voltage corresponding to or less than the first power supply voltage, and the second voltage corresponding to or greater than the second power supply voltage, and A row decoder, comprising a demultiplexer, the demultiplexer being configured to provide a corresponding enable signal for each word line, and asserting one of the enable signals according to a first change of an address signal, the demultiplexer being powered by the second power supply voltage, each enable signal being connected to the second power supply voltage or ground, and for each word line, the row decoder comprising: a pull-up connected between the corresponding word line and the first supply voltage, a first n-channel field effect transistor FET, a source terminal of the first n-channel FET being connected to the ground and a gate terminal of the first n-channel FET being connected to a first signal, a second n-channel FET having a drain terminal connected to the corresponding word line, a source terminal connected to the drain terminal of the first n-channel FET, and a gate terminal connected to the second voltage, a first p-channel FET having a drain terminal connected to the second voltage, a source terminal connected to the corresponding word line, and a gate terminal connected to a second signal, Bias circuit, a first delay circuit, and The second delay circuit, The method comprises: providing the first power supply voltage and the second power supply voltage to the nonvolatile memory, the second power supply voltage being lower than the first power supply voltage; and The address signal is provided to the row decoder.

16. The method of claim 15 , further comprising, in response to detecting a change in the enable signal from an asserted logic level to a de-asserted logic level: connecting the first signal to the ground by the first delay circuit; and The second signal after the second delay is set to the first voltage by the second delay circuit.

17. The method of claim 15 , further comprising, in response to detecting a change in the enable signal from a de-asserted logic level to an asserted logic level: setting the first signal after the first delay to the first voltage by the first delay circuit to close the first FET; and The second signal is set to the second voltage by the second delay circuit.

18. The method of claim 15, further comprising setting, by the bias circuit, a drain voltage at the drain terminal of the first n-channel FET to the second voltage in response to the first n-channel FET and the second n-channel FET being turned off.

19. The method according to claim 15, further comprising: connecting one of the word lines to the ground by the row decoder according to a second change of the address signal; providing, by the demultiplexer, the enable signal to the one of the word lines; as well as A programming current is provided by the current source to one or more of the bit lines.

20. The method of claim 15, further comprising: closing the first FET by setting the first signal to the second voltage by the first delay circuit; selectively short-circuiting a first capacitor of the first delay circuit according to a first change of the enable signal by a fourth n-channel FET of the first delay circuit, wherein a first terminal of the first capacitor is connected to the ground, and a second terminal of the first capacitor is connected to the second voltage via a fourth resistor; as well as A second capacitor of the second delay circuit is selectively short-circuited by a fifth n-channel FET of the second delay circuit according to a second change of the enable signal, a first terminal of the second capacitor is connected to the second voltage, and a second terminal of the second capacitor is connected to the first voltage via a fifth resistor.

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