A packaging method of a double-sided bump package chip and a corresponding structure thereof

Abstract

The application discloses a packaging method of a double-face bump packaging chip, which solves the defects of easy oxidation and electric leakage of the double-face bump chip, and ensures the quality and working stability of the double-face bump packaging chip. The method is characterized in that: after the wafer front surface operation is completed, the wafer front surface is reversely arranged after being bonded with glass, then the Si surface of the wafer back surface is ground and stress is released, then a SiO2 layer is formed on the surface of the Si layer, then a Ti / Cu layer is sputtered on the surface of the SiO2 layer, then the Cu is electroplated on the surface of the Ti / Cu layer to form an electroplated Cu layer, then the RDL corresponding to the pattern is formed on the wafer back surface through photoetching, then the Ti / Cu layer etching and the adhesive removing operation are carried out through photoetching, the back surface Cu manufacturing is completed, after the back surface Cu operation is completed, the wafer back surface is treated by plasma, then the RDL surface is protected by electroplating, after being reversely arranged again, the glass and the wafer are separated by UV light, and the complete single chip is formed by mechanical cutting.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor chip packaging, specifically to a packaging method for a double-bump packaged chip, and also provides a packaging structure for the double-bump packaged chip. Background Technology

[0002] Figure 1 This paper illustrates a conventional double-sided Cu chip packaging structure. The existing packaging method for this chip is as follows: A PI layer 40' is deposited on the die side 2' of wafer 1', exposing the pad 30' area. Then, a Ti / Cu seed layer 50' is sputtered onto the pad 30' area. Next, a bump 60' is generated through photolithography, electroplating, resist removal, and Ti / Cu etching. This completes the front-side bump 60' process. After the front-side bump of wafer 1' is completed, a bonding adhesive is applied, and the wafer is temporarily bonded to glass for the back-side processing of wafer 1'. After the back side of wafer 1' is thinned by grinding, the Si surface is simultaneously etched to release stress. Then, a Ti / Cu layer 20' is sputtered on the back side of wafer 1', followed by Cu electroplating. After Cu electroplating, photolithography is performed on the Cu surface. Through Ti / Cu etching and resist removal, the RDL10' of the back Cu is formed. The packaging structure of the double-sided Cu chip produced by this method is prone to oxidation and leakage problems on both sides. Therefore, it is urgent to develop a new packaging method suitable for double-sided Cu chip packaging to solve the oxidation and leakage problems that double-sided Cu chips are prone to. Summary of the Invention

[0003] To address the aforementioned problems, this invention provides a packaging method for a double-bump packaged chip, which solves the defects of double-bump chips being prone to oxidation and leakage, ensuring the quality and operational stability of the double-bump packaged chip.

[0004] A packaging method for a double-sided bump packaged chip, characterized in that:

[0005] After the front side of the wafer is completed, the wafer is bonded to the glass and then inverted. The Si side of the back side of the wafer is then ground and stress-relieving is performed. A SiO2 layer is then deposited on the surface of the Si layer, followed by a Ti / Cu layer sputtered onto the SiO2 layer. Cu is then electroplated onto the Ti / Cu layer to form an electroplated Cu layer. The corresponding RDL pattern is then formed on the back side of the wafer through photolithography. The Ti / Cu layer is then etched and the resist is removed through photolithography to complete the fabrication of the back Cu layer. After the back Cu layer is completed, the back side of the wafer is subjected to plasma treatment, followed by chemical plating to protect the RDL surface. After inverting the wafer again, UV light is used to debond the glass and separate the wafer. Finally, the wafer is mechanically diced to form a complete single chip.

[0006] Its further features are:

[0007] The SiO2 layer was obtained through chemical vapor deposition.

[0008] In the Ti / Cu layer sputtered on the SiO2 layer, Ti serves as a barrier layer and Cu serves as a conductive seed layer. The thickness of the electroplated Cu layer is less than 15 μm, and photolithography is performed on the surface of the electroplated Cu layer.

[0009] Its further characteristic lies in the following specific operating steps:

[0010] S1, wafer material, the wafer includes the bottom Si layer and the upper Pad and functional layers;

[0011] S2. The wafer is cleaned and baked, and the wafer surface is subjected to plasma treatment. Then, a PI layer is covered on the upper surface of the wafer, exposing the Pad.

[0012] S3. After completing the PI layer, perform a bumping operation on the wafer to form several upward bumps on the upper surface of the wafer.

[0013] S4. After applying a layer of bonding adhesive to the surface of the wafer, press the glass and the wafer together to make them a single unit.

[0014] S5. Invert the wafer and perform operations on the back side of the wafer. First, thin the back side of the wafer by grinding to reduce the Si layer. To reduce grinding stress damage, etch the Si layer on the back side of the wafer to release its stress.

[0015] S6. After the Si layer is thinned by grinding, in order to prevent leakage, a SiO2 layer is deposited on the surface of the Si layer by chemical vapor deposition.

[0016] S7. Sputter a Ti / Cu layer on the SiO2 layer as a seed layer, then electroplate Cu on the seed layer surface. The thickness of the electroplated Cu layer is less than 15um. Then perform photolithography on the Cu layer surface to form a pattern distribution. Form the required RDL by TiCu etching. Then perform a resist removal operation to completely expose the RDL.

[0017] S8. Plasma treatment is performed on the back surface of the wafer, and then a metal protective layer is formed on the RDL surface by chemical plating.

[0018] S9. Apply a scribe film to the back of the wafer;

[0019] S10. Invert the wafer, then irradiate it with UV light to debond it and separate the wafer from the glass.

[0020] S11. The wafer is cut, the dicing film is removed, making it into a single chip, and then it is shipped.

[0021] Its further characteristic is:

[0022] In step S5, the thickness of the thinned Si layer is 10 to 150 μm, and the specific thickness requirement is determined according to the overall chip thickness.

[0023] In step S8, a NiAu metal protective layer is formed by electroless plating.

[0024] The packaging structure of a double-bump packaged chip is characterized by comprising:

[0025] The substrate includes a lower Si layer, an upper pad layer, and a functional layer.

[0026] Several upward-convex bumps;

[0027] And several downward-convex RDLs;

[0028] A Pi layer is disposed on the functional layer of the substrate. A first Ti / Cu seed layer is disposed on the upper surface of the PAD and the outer periphery of the PAD. A corresponding bump is disposed on the first Ti / Cu seed layer and arranged upwardly. A SiO2 layer, a second Ti / Cu layer and a Cu layer are disposed sequentially on the lower surface of the Si layer of the substrate. A plurality of downwardly protruding RDLs are disposed on the lower surface of the Cu layer. A metal protective layer is covered on the outer periphery of the RDLs.

[0029] A further feature is that the metal protective layer is a NiAu metal protective layer.

[0030] After adopting the above technical solution, a SiO2 layer is applied to the surface of the Si layer, and then a Ti / Cu layer is sputtered on the surface of the SiO2 layer, which can effectively prevent leakage. In addition, after the RDL is formed and the Cu application on the back side is completed, the back side of the wafer is subjected to plasma treatment, and then chemical plating is used to protect the RDL surface. The metal protective film formed by plasma treatment and chemical plating effectively prevents RDL oxidation. In summary, it solves the defects of easy oxidation and leakage of double-bump chips, and ensures the quality and operational stability of double-bump packaged chips. Attached Figure Description

[0031] Figure 1 The packaging structure for existing double-sided Cu chips;

[0032] Figure 2 This is a schematic diagram of step S1 of the packaging method of the present invention.

[0033] Figure 3 This is a schematic diagram of step S2 in the process flow of the packaging method of the present invention;

[0034] Figure 4This is a schematic diagram of step S3 in the process flow of the packaging method of the present invention;

[0035] Figure 5 This is a schematic diagram of step S4 in the process flow of the packaging method of the present invention;

[0036] Figure 6 This is a schematic diagram of step S5 in the process flow of the packaging method of the present invention;

[0037] Figure 7 This is a schematic diagram of step S6 in the process flow of the packaging method of the present invention;

[0038] Figure 8 This is a schematic diagram of step S7 in the process flow of the packaging method of the present invention;

[0039] Figure 9 This is a schematic diagram of step S8 in the process flow of the packaging method of the present invention;

[0040] Figure 10 This is a schematic diagram of step S9 in the process flow of the packaging method of the present invention;

[0041] Figure 11 This is a schematic diagram of step S10 of the packaging method of the present invention.

[0042] Figure 12 This is a schematic diagram of step S11 of the packaging method of the present invention, and also a schematic diagram of the corresponding packaging structure of the present invention.

[0043] The names corresponding to the serial numbers in the diagram are as follows:

[0044] Wafer 1', Die face 2', RDL 10', Ti / Cu layer 20', pad 30', PI layer 40', Ti / Cu seed layer 50', bump 60';

[0045] Wafer 1, Si layer 10, Pad 20, functional layer 30, PI layer 40, first Ti / Cu seed layer 50, bump 60, bonding adhesive 70, glass 80, SiO2 layer 90, second Ti / Cu seed layer 100, RDL 110, surface metal protective layer 120, outer ring region metal protective layer 130, dicing film 140. Detailed Implementation

[0046] A packaging method for a double-sided bump packaged chip, see Figures 2-12After the front side of wafer 1 is completed, the front side of wafer 1 is bonded to glass 80 and then inverted. The Si layer 10 on the back side of wafer 1 is then ground and stress-relieving is performed. A SiO2 layer 90 is then deposited on the surface of the Si layer 10. A Ti / Cu layer is then sputtered on the surface of the SiO2 layer 90. Cu is then electroplated on the surface of the Ti / Cu layer to form an electroplated Cu layer. Then, the corresponding pattern RDL110 is formed on the back side of the wafer through photolithography. The back Cu layer is then fabricated through photolithography, Ti / Cu layer etching, and resist removal. After the back Cu layer is completed, the back side of wafer 1 is subjected to plasma treatment. Then, the surface of RDL110 is protected by chemical plating. After inverting again, UV light is used to debond the wafer 80 and separate it from the wafer 1. Finally, the wafer is mechanically diced to form a complete single chip.

[0047] In practice, Ti is used as a barrier layer and Cu is used as a conductive seed layer in the sputtered Ti / Cu layer of SiO2 layer 90. The thickness of the electroplated Cu layer is less than 15um, and photolithography is performed on the surface of the electroplated Cu layer.

[0048] The specific operating steps are as follows:

[0049] S1, Wafer 1 arrived. Wafer 1 includes the bottom Si layer 10 and the upper Pad 20 and functional layer 30 (see...). Figure 2 );

[0050] S2. Wafer 1 is cleaned and baked, and its surface is subjected to plasma treatment. Then, a PI layer 40 is applied to the upper surface of wafer 1, exposing Pad 20 (see...). Figure 3 );

[0051] S3. After completing the PI layer 40, perform a bump operation on wafer 1 to form several upward bumps 60 on the upper surface of the wafer (see...). Figure 4 The process involves first sputtering a first Ti / Cu seed layer 50 onto the PI layer, performing photolithography on the first Ti / Cu seed layer 50 to arrange the pattern, and then electroplating Cu and SnAg to generate bump 60. After completing bump 60, the resist is removed to completely expose bump 60. Then, Ti / Cu etching is performed to remove the seed layer in other areas except bump, forming several raised bumps 60 on the wafer surface.

[0052] S4. After applying a layer of bonding adhesive 70 to the upper surface of wafer 1, press the glass 80 onto wafer 1 to make them a single unit (see...). Figure 5 );

[0053] S5. Invert wafer 1 and perform operations on the back side of wafer 1. First, thin the back side of the wafer by grinding, thinning the Si layer 10. The thinning thickness of the Si layer is 10 to 150 μm, and the specific thickness requirement is determined according to the overall chip thickness. To reduce grinding stress damage, etch the Si layer 10 on the back side of the wafer to release its stress (see...). Figure 6 );

[0054] S6. After the Si layer 10 is thinned by grinding, to prevent leakage current, a SiO2 layer 90 is deposited on the surface of the Si layer by chemical vapor deposition (see...). Figure 7 );

[0055] S7. A Ti / Cu layer is sputtered onto the SiO2 layer 90 as a second Ti / Cu seed layer 100. Then, Cu is electroplated onto the seed layer surface, with a Cu layer thickness of less than 15 μm. Next, photolithography is performed on the Cu layer surface to form a pattern distribution. The desired RDL110 is formed using TiCu etching. Afterwards, a resist stripping process is performed to completely expose the RDL110 (see...). Figure 8 );

[0056] S8. Plasma treatment is performed on the back surface of wafer 1, followed by chemical plating to form a metal protective layer on the RDL surface. The metal protective layer includes a surface metal protective layer 120 and an outer ring region metal protective layer 130 (see...). Figure 9 );

[0057] S9. Then, a scribe line 140 is applied to the back of the wafer (see...). Figure 10 );

[0058] S10. Invert wafer 1, then irradiate with UV light to debond it and separate wafer 1 from glass 80 (see...). Figure 11 );

[0059] S11. Divide wafer 1, remove the dicing film 140 to make it a single chip, and then ship it (see...). Figure 12 ).

[0060] In step S8 of the specific embodiment, a NiAu metal protective layer is formed by electroless plating.

[0061] For the packaging structure of a double-bump packaged chip, see... Figure 12 It includes a substrate, several upwardly convex bumps, and several downwardly convex RDLs, wherein the substrate is the area of ​​unit area formed after wafer 1 is cut.

[0062] The substrate includes a lower Si layer 10, an upper pad 20, and a functional layer 30. A Pi layer 40 is disposed on the functional layer 30 of the substrate. A first Ti / Cu seed layer 50 is disposed on the upper surface and the outer periphery of the PAD 20. A corresponding bump 60 is disposed on the first Ti / Cu seed layer 50 and is arranged upwardly. A SiO2 layer 90, a second Ti / Cu seed layer 100, and a Cu layer are sequentially disposed on the lower surface of the Si layer 10. A plurality of downwardly protruding RDL110s are disposed on the lower surface of the Cu layer. A metal protective layer is covered around the outer periphery of the RDL110.

[0063] In specific implementation, the metal protective layer is a NiAu metal protective layer, which includes a surface metal protective layer 120 and an outer ring area metal protective layer 130 to ensure reliable protection for RDL110.

[0064] The principle is as follows: a SiO2 layer is applied to the surface of the Si layer, and then a Ti / Cu layer is sputtered on the surface of the SiO2 layer, which can effectively prevent leakage current; in addition, after the RDL is formed and the Cu on the back side is completed, the back side of the wafer is subjected to plasma treatment, and then the RDL surface is protected by chemical plating. The metal protective film formed by plasma treatment and chemical plating effectively prevents RDL oxidation.

[0065] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0066] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A packaging method for a double-sided bump-packaged chip, characterized in that: After the front side of the wafer is completed, the front side of the wafer is bonded to the glass and then inverted. The Si side of the back side of the wafer is then ground and stress is released. A SiO2 layer is then deposited on the surface of the Si layer. A Ti / Cu layer is then sputtered onto the surface of the SiO2 layer. Cu is then electroplated onto the surface of the Ti / Cu layer to form an electroplated Cu layer. Then, the corresponding RDL pattern is formed on the back side of the wafer through photolithography. The Ti / Cu layer is then etched and the resist is removed through photolithography to complete the fabrication of the back Cu. After the back Cu is completed, the back side of the wafer is subjected to plasma treatment. Then, the RDL surface is protected by chemical plating. After being inverted again, the wafer is debonded by UV light to separate the glass from the wafer. Finally, it is mechanically diced to form a complete single chip. The specific operating steps are as follows: S1, wafer material, the wafer includes the bottom Si layer and the upper Pad and functional layers; S2. The wafer is cleaned and baked, and the wafer surface is subjected to plasma treatment. Then, a PI layer is covered on the upper surface of the wafer, exposing the Pad. S3. After completing the PI layer, perform a bumping operation on the wafer to form several upward bumps on the upper surface of the wafer. S4. After applying a layer of bonding adhesive to the surface of the wafer, press the glass and the wafer together to make them a single unit. S5. Invert the wafer and perform operations on the back side of the wafer. First, thin the back side of the wafer by grinding to reduce the Si layer. To reduce grinding stress damage, etch the Si layer on the back side of the wafer to release its stress. S6. After the Si layer is thinned by grinding, in order to prevent leakage, a SiO2 layer is deposited on the surface of the Si layer by chemical vapor deposition. S7. Sputter a Ti / Cu layer on the SiO2 layer as a seed layer, then electroplate Cu on the seed layer surface. The thickness of the electroplated Cu layer is less than 15um. Then perform photolithography on the Cu layer surface to form a pattern distribution. Form the required RDL by TiCu etching. Then perform a resist removal operation to completely expose the RDL. S8. Plasma treatment is performed on the back surface of the wafer, and then a metal protective layer is formed on the RDL surface by chemical plating. S9. Apply a scribe film to the back of the wafer; S10. Invert the wafer, then irradiate it with UV light to debond it and separate the wafer from the glass. S11. The wafer is cut, the dicing film is removed, making it into a single chip, and then it is shipped.

2. The packaging method for a double-sided bump packaged chip according to claim 1, characterized in that: The SiO2 layer was obtained through chemical vapor deposition.

3. The packaging method for a double-sided bump packaged chip according to claim 1, characterized in that: In the Ti / Cu layer sputtered on the SiO2 layer, Ti serves as a barrier layer and Cu serves as a conductive seed layer. The thickness of the electroplated Cu layer is less than 15 μm, and photolithography is performed on the surface of the electroplated Cu layer.

4. The packaging method for a double-sided bump packaged chip according to claim 1, characterized in that: In step S5, the thickness of the thinned Si layer is 10 to 150 μm, and the specific thickness requirement is determined according to the overall chip thickness.

5. The packaging method for a double-sided bump packaged chip according to claim 1, characterized in that: In step S8, a NiAu metal protective layer is formed by electroless plating.

6. A packaging structure for a double-sided bump packaged chip, which is obtained by the packaging method for a double-sided bump packaged chip as described in any one of claims 1-5, characterized in that, It includes: The substrate includes a lower Si layer, an upper pad layer, and a functional layer. Several upward-convex bumps; And several downward-convex RDLs; A Pi layer is disposed on the functional layer of the substrate. A first Ti / Cu seed layer is disposed on the upper surface of the PAD and the outer periphery of the PAD. A corresponding bump is disposed on the first Ti / Cu seed layer and arranged upwardly. A SiO2 layer, a second Ti / Cu layer and a Cu layer are disposed sequentially on the lower surface of the Si layer of the substrate. A plurality of downwardly protruding RDLs are disposed on the lower surface of the Cu layer. A metal protective layer is covered on the outer periphery of the RDLs.

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