A semiconductor device, a manufacturing method thereof, and a storage system
By employing a first gate line gap structure with alternating stacked insulating and gate layers in 3D NAND memory to form a capacitor structure, the problem of low utilization of gate line gap structures is solved, achieving higher storage capacity and lower storage cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2023-08-29
- Publication Date
- 2026-07-10
AI Technical Summary
The gate slot structure of existing 3D NAND memory has too low a utilization rate, making it difficult to further increase storage capacity and reduce the cost per bit of storage.
The first gate line gap structure in the stacked structure includes alternating stacked insulating layers and gate layers. The first gate line gap structure penetrates the stacked structure along the stacking direction and extends along the first direction. The capacitor structure is formed by two mutually insulating conductive layers, which increases functionality and saves circuit area.
It improves the utilization rate of the first gate line slot structure, increases the capacitance function, reduces circuit area waste, and enhances the overall performance of the memory device.
Smart Images
Figure CN119545801B_ABST
Abstract
Description
Technical Field
[0001] This application generally relates to the field of electronic devices, and more specifically, to a semiconductor device and its fabrication method and a storage system. Background Technology
[0002] NAND flash memory devices are non-volatile memory products with low power consumption, light weight, and high performance, and are widely used in electronic products. Planar NAND devices have reached their practical expansion limits. To further increase storage capacity and reduce the cost per bit, 3D NAND flash memory was proposed. In the 3D NAND flash memory structure, multiple layers of data storage cells are vertically stacked to achieve a stacked memory structure.
[0003] 3D NAND memory includes a gate-slot structure, but the utilization rate of the gate-slot structure is currently too low.
[0004] Application content
[0005] The purpose of this application is to provide a semiconductor device and its fabrication method, as well as a memory system, which aims to improve the utilization rate of the first gate gap structure.
[0006] In a first aspect, this application provides a semiconductor device, the semiconductor device comprising:
[0007] A stacked structure, comprising alternating stacked insulating layers and gate layers;
[0008] The first gate line slot structure penetrates the stacked structure along the stacking direction and extends along a first direction, which intersects the stacking direction.
[0009] The first gate gap structure includes a first conductive layer, a second conductive layer, and a first dielectric layer. The first conductive layer surrounds the sidewall of the second conductive layer, and the first dielectric layer is located between the second conductive layer and the first conductive layer.
[0010] In some embodiments, the first gate wire gap structure further includes:
[0011] A second dielectric layer extends along the first direction, and a second conductive layer surrounds the sidewall of the second dielectric layer.
[0012] In some embodiments, the first gate wire gap structure further includes:
[0013] A first isolation layer is located between the stacked structure and the first conductive layer.
[0014] In some embodiments, the semiconductor device further includes:
[0015] The first partition structure extends along the stacking direction and is located at both ends of the first conductive layer along the first direction;
[0016] The first partition structure divides the first conductive layer into a first electrode and a second electrode. The first electrode and the second electrode are located on both sides of the first dielectric layer along the second direction, and the first direction, the second direction and the stacking direction intersect each other.
[0017] In some embodiments, the semiconductor device further includes:
[0018] The second partition structure extends along the stacking direction and is located at both ends of the second conductive layer along the first direction;
[0019] The second isolation structure isolates the second conductive layer into a third electrode and a fourth electrode. The third electrode and the fourth electrode are located on both sides of the second dielectric layer along the second direction, and the first direction, the second direction and the stacking direction intersect each other.
[0020] In some embodiments, the semiconductor device includes a body region and an edge region located around the body region. The edge region includes a first edge region and a second edge region located on both sides of the body region in a second direction. The first direction, the second direction, and the stacking direction intersect each other.
[0021] The first grid line slot structure is located in the first edge region and the second edge region.
[0022] In some embodiments, the first edge region has two first gate line slot structures arranged along the first direction and parallel to each other, and the second edge region has two first gate line slot structures arranged along the first direction and parallel to each other.
[0023] In some embodiments, the semiconductor device includes a core region and a non-core region adjacent to the core region in the first direction, wherein the first gate gap structure is located in the non-core region and disposed along the first direction.
[0024] In some embodiments, the semiconductor device further includes:
[0025] The second gate line slot structure penetrates the stacked structure of the core region along the stacking direction and is disposed along the first direction. One end of the second gate line slot structure along the first direction is connected to the first gate line slot structure.
[0026] In some embodiments, the second gate wire gap structure includes:
[0027] A third conductive layer is disposed along the first direction and connected to the first conductive layer;
[0028] The second isolation layer surrounds the sidewall of the third conductive layer and is connected to the first isolation layer.
[0029] In some embodiments, the width of the second gate slot structure along the second direction is smaller than the width of the first gate slot structure along the second direction, and the first direction, the second direction, and the stacking direction intersect each other.
[0030] In some embodiments, the semiconductor device further includes:
[0031] The peripheral circuit is located on one side of the stacked structure. The peripheral circuit includes a charge pump circuit, and a plurality of first gate line slot structures are connected to the charge pump circuit through connecting contact points.
[0032] In some embodiments, the plurality of first conductive layers in the plurality of first gate wire slot structures are connected in parallel, and the plurality of second conductive layers in the plurality of first gate wire slot structures are connected in parallel.
[0033] Secondly, this application provides a method for fabricating a semiconductor device, the method comprising:
[0034] A stacked structure is formed, the stacked structure comprising alternately stacked insulating layers and gate layers;
[0035] A first gate line slot structure is formed that extends through the stacking structure along the stacking direction of the stacking structure. The first gate line slot structure extends along a first direction that intersects the stacking direction. The first gate line slot structure includes a first conductive layer, a second conductive layer, and a first dielectric layer. The first conductive layer surrounds the sidewall of the second conductive layer, and the first dielectric layer is located between the second conductive layer and the first conductive layer.
[0036] In some embodiments, the semiconductor device includes a body region and an edge region located around the body region. The edge region includes a first edge region and a second edge region located on both sides of the body region in a second direction. The first direction, the second direction, and the stacking direction intersect each other.
[0037] The step of forming a first gate wire slot structure that penetrates the stack structure along the stacking direction includes:
[0038] A first gate line slot is formed that extends through the stacking structure along the stacking direction of the stacking structure. The first gate line slot is located in the first edge region and the second edge region and extends along the first direction.
[0039] A first isolation layer, a first conductive layer, a first dielectric layer, a second conductive layer, and a second dielectric layer are sequentially formed in the first gate line gap.
[0040] In some embodiments, the semiconductor device includes a body region and an edge region located around the body region. The body region includes a core region and a non-core region adjacent to the core region in the first direction. The first gate line gap structure is located in the non-core region.
[0041] The method for fabricating the semiconductor device further includes:
[0042] A second gate slot structure is formed in the stacked structure that extends through the core region along the stacking direction.
[0043] In some embodiments, the steps of forming the first gate wire slot structure and forming the second gate wire slot structure include:
[0044] A trench is formed that penetrates the stacking structure along the stacking direction. The trench includes a first gate line slot located in the non-core region and a second gate line slot located in the core region. The width of the first gate line slot in the second direction is greater than the width of the second gate line slot in the second direction. The first direction, the second direction, and the stacking direction intersect each other.
[0045] An isolation layer, a conductive layer, a first dielectric layer, a second conductive layer, and a second dielectric layer are sequentially formed in the trench. The isolation layer includes a first isolation layer located in the first gate line gap and a second isolation layer located in the second gate line gap. The conductive layer includes a first conductive layer located in the first gate line gap and a third conductive layer located in the second gate line gap. The second isolation layer and the third conductive layer fill the second gate line gap.
[0046] In some embodiments, the method for fabricating the semiconductor device further includes:
[0047] An external circuit is formed on one side of the stacked structure. The external circuit includes a charge pump circuit, and a plurality of first gate line slot structures are connected to the charge pump circuit through connecting contact points.
[0048] Thirdly, this application provides a storage system, comprising:
[0049] Semiconductor devices in any of the above embodiments;
[0050] A controller, electrically connected to the semiconductor device, is used to control the semiconductor device to store data.
[0051] This application provides a semiconductor device and its fabrication method, as well as a memory system. The semiconductor device includes a stacked structure and a first gate line gap structure. The stacked structure includes alternately stacked insulating layers and gate layers. The first gate line gap structure penetrates the stacked structure along its stacking direction and extends along a first direction, which intersects the stacking direction. The first gate line gap structure includes a first conductive layer, a second conductive layer, and a first dielectric layer. The first conductive layer surrounds the sidewall of the second conductive layer, and the first dielectric layer is located between the second conductive layer and the first conductive layer. Because the first gate line gap structure includes two mutually insulating conductive layers, the first and second conductive layers can form a capacitor structure as part of some circuits. Therefore, this application fully utilizes the first gate line gap structure, increases its functionality, and improves its utilization rate. Attached Figure Description
[0052] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.
[0053] Figure 1 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application;
[0054] Figure 2 This is a schematic diagram of the operation of a charge pump circuit provided in some embodiments of this application;
[0055] Figure 3 This is a schematic diagram of the capacitor structure in a charge pump circuit provided in some embodiments of this application;
[0056] Figure 4 This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application;
[0057] Figure 5a This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application;
[0058] Figure 5b Some embodiments provided in this application Figure 5a A schematic diagram of the cross-sectional structure of the first grid line slot structure along B-B1;
[0059] Figure 6 This is a partial cross-sectional structural schematic diagram of the first grid line slot structure and the second grid line slot structure provided in some embodiments of this application;
[0060] Figure 7 This is a schematic cross-sectional view of a semiconductor device along the YZ plane provided in some embodiments of this application;
[0061] Figure 8This is a schematic flowchart of a method for fabricating a semiconductor device provided in some embodiments of this application;
[0062] Figures 9a-9d These are schematic diagrams illustrating the fabrication process of semiconductor devices provided in some embodiments of this application;
[0063] Figures 10a-10c These are schematic diagrams illustrating the fabrication process of semiconductor devices provided in some embodiments of this application;
[0064] Figure 11 This is a schematic diagram of the structure of a storage system provided in some embodiments of this application. Detailed Implementation
[0065] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0066] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of this application.
[0067] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.
[0068] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entirety of a lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.
[0069] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.
[0070] This paper uses Cartesian coordinates to represent directions, where "X" represents the first direction, "Y" represents the second direction, and "Z" represents the stacking direction. The first direction, the second direction, and the stacking direction intersect each other, that is, X, Y, and Z intersect each other, for example, they can be perpendicular to each other or form a certain angle.
[0071] The semiconductor device in this application embodiment can be a wafer, or a three-dimensional memory or a portion thereof. Three-dimensional memory can be applied to communication products, consumer electronics, automotive products, aerospace products, artificial intelligence products, or big data, etc. Consumer electronics include, but are not limited to, mobile phones, computers, tablets, cameras, smart glasses, or gaming products, etc.
[0072] Please see Figure 1 , Figure 1 This is a cross-sectional structural schematic diagram of a semiconductor device provided in some embodiments of this application.
[0073] Semiconductor device 100 includes a stacked structure 10 and a first gate line gap structure 11. The stacked structure 10 includes alternately stacked insulating layers 101 and gate layers 102. The first gate line gap structure 11 penetrates the stacked structure 10 along the stacking direction (Z) and extends along a first direction (X). The first gate line gap structure 11 includes a first conductive layer 111, a second conductive layer 112, and a first dielectric layer 113. The first conductive layer 111 surrounds the sidewall of the second conductive layer 112, and the first dielectric layer 113 is located between the second conductive layer 112 and the first conductive layer 111.
[0074] The number of layers in the stacking structure 10 determines the number of storage cells it contains in the stacking direction (Z). For example, the number of layers in the stacking structure 10 can be 32, 64, 96, 128, etc., and the more layers the stacking structure 10 has, the higher the integration of the corresponding three-dimensional memory.
[0075] The material of the insulating layer 101 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The gate layer 102 may include a conductive layer, such as tungsten. In some embodiments, the gate layer 102 may include a dielectric layer (e.g., a high-k dielectric layer) and a conductive layer, wherein the conductive layer may include a first conductive layer (e.g., titanium carbide) and a second conductive layer (e.g., tungsten) formed sequentially.
[0076] The materials of the first conductive layer 111 and the second conductive layer 112 may include at least one of polycrystalline silicon and metal. The material of the first dielectric layer 113 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The first dielectric layer 113 is used to isolate the first conductive layer 111 and the second conductive layer 112. In some embodiments, the first conductive layer 111 and the second conductive layer 112 may also include some semiconductor conductive materials, such as silicon (Si) and germanium (Ge).
[0077] like Figure 1 As shown, the first dielectric layer 113 surrounds the sidewalls and bottom of the second conductive layer 112, and the second conductive layer 112 surrounds the sidewalls and bottom of the first dielectric layer 113. Since the first gate line slot structure 11 includes two mutually insulating conductive layers, the first conductive layer 111 and the second conductive layer 112 can form a capacitor structure as part of some circuits. Therefore, this application can fully utilize the first gate line slot structure 11, not only increasing the functionality of the first gate line slot structure 11 but also saving some circuit area.
[0078] For example, the semiconductor device 100 may include peripheral circuitry 12, which may include charge pump circuitry, analog circuitry, etc., and these circuits include at least one capacitor. Peripheral circuitry 12 may be located on one side of the stacked structure 10 along the stacking direction (Z) and connected to the first gate line slot structure 11. Specifically, peripheral circuitry 12 may be connected to the first conductive layer 111 and the second conductive layer 112 via contact points (not shown). Specifically, the stacked structure 10 has a side near the bottom of the first gate line slot structure 11 and a side away from the bottom of the first gate line slot structure 11. Peripheral circuitry 12 may be connected to the side of the stacked structure 10 near the bottom of the first gate line slot structure 11 by bonding (e.g., ...). Figure 1 (As shown), it can also be connected to the side of the stacked structure 10 away from the bottom of the first gate line slot structure 11. Therefore, the capacitor in the peripheral circuit 12 can be transferred to the first gate line slot structure 11, saving the area of the peripheral circuit 12, while making full use of the first gate line slot structure 11 to realize its capacitor function.
[0079] Please see Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of the operation of a charge pump circuit provided in some embodiments of this application. Figure 3 This is a schematic diagram of the capacitor structure in a charge pump circuit provided in some embodiments of this application.
[0080] The charge pump circuit includes switches S1, S2, S3, and S4, and capacitors C1 and C2 connected in parallel. During the operation of semiconductor device 100, the charge pump circuit converts a low voltage V... DD Pull to operating voltage Vout Capacitor C1 can be formed by multiple capacitor structures connected in parallel, and capacitor C2 can also be formed by multiple capacitor structures connected in parallel. Since C1 and C2 are connected in parallel, all capacitor structures can be connected in parallel through a charge pump circuit.
[0081] The structure of a capacitor is as follows Figure 3 As shown, multiple capacitor structures C0 connected in parallel can form Figure 2 One of the capacitors C1 / C2 is a capacitor, and each capacitor structure C0 includes a first plate C01 and a second plate C02. One plate from each capacitor structure C0 is connected together, and the other plate from each capacitor structure C0 is connected together. For example, the first plates C01 of each capacitor structure C0 are all connected in parallel, and the second plates C02 of each capacitor structure C0 are all connected in parallel. The first plate C01 can be the first conductive layer 111 in the above embodiment, and the second plate C02 can be the second conductive layer 112 in the above embodiment; that is, multiple first conductive layers 111 in the multiple first gate line slot structures 11 are all connected in parallel, and multiple second conductive layers 112 in the multiple first gate line slot structures 11 are all connected in parallel.
[0082] Please see Figure 4 , Figure 4 This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application.
[0083] The semiconductor device 100 includes multiple memory planes, each memory plane including a main region P1 and an edge region P2 located around the main region P1, that is, the edge region P2 surrounds the main region P1. Figure 4 The main purpose is to show the position of the first grid line slot structure 11. Figure 1 It can be Figure 4 A schematic diagram of the cross-sectional structure of the first grid line slot structure 11 along A-A1.
[0084] In some embodiments, the first grid line slot structure 11 may be located in the edge region P2 around the main body region P1. For example, the first grid line slot structure 11 may be a square shape, i.e., two rectangles of different sizes.
[0085] In some embodiments, the first grid line slot structure 11 may be located only in the edge regions P2 on both sides of the main body region P1 along the first direction (X), that is, the first grid line slot structure 11 may extend along the second direction (Y), and the first grid line slot structure 11 is the long side of two rectangles.
[0086] In some embodiments, the edge region P2 includes a first edge region P21 and a second edge region P22 located on both sides of the main body region P1 in the second direction (Y). The first gate line slot structure 11 may be located only in the first edge region P21 and the second edge region P22, that is, the first gate line slot structure 11 extends along the first direction (X), and the first gate line slot structure 11 is the shorter side of two rectangles. Specifically, the first edge region P21 has two first gate line slot structures 11 arranged along the first direction (X) and parallel to each other, and the second edge region P22 has two first gate line slot structures 11 arranged along the first direction (X) and parallel to each other.
[0087] In some embodiments, the first gate gap structure 11 further includes a second dielectric layer 114 extending along the first direction (X), and the second conductive layer 112 surrounding the sidewalls and bottom of the second dielectric layer 114. The second dielectric layer 114 may be made of the same material as the first dielectric layer 113.
[0088] In some embodiments, the first gate gap structure 11 further includes a first isolation layer 115, which is located between the stacked structure 10 and the first conductive layer 111, isolating the gate layer 102 and the first conductive layer 111. The material of the first isolation layer 115 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.
[0089] like Figure 4 As shown, the semiconductor device 100 may include a plurality of memory blocks G arranged along a first direction (X), and the first gate gap structure 11 near the main body region P1 can isolate adjacent memory blocks G.
[0090] Please see Figure 5a and Figure 5b , Figure 5a This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this application. Figure 5b Some embodiments provided in this application Figure 5a A schematic cross-sectional view of the first grid line slot structure along line B-B1. For ease of understanding and concise explanation, the same structures in this embodiment use the same reference numerals as those in the above embodiments. This embodiment only provides detailed descriptions of structures that differ from those in the above embodiments.
[0091] The first gate gap structure 11' in the semiconductor device 100' includes a first conductive layer 111', a second conductive layer 112', a first dielectric layer 113', a second dielectric layer 114', and a first isolation layer 115'. The bottom of the first conductive layer 111' is interrupted by the first dielectric layer 113', and the bottom of the second conductive layer 112' is interrupted by the second dielectric layer 114'. The first gate gap structure 11' also includes a first isolation structure 1110 and a second isolation structure 1120. The first isolation structure 1110 extends along the stacking direction (Z) and is located at both ends of the first conductive layer 111' along a first direction (X).
[0092] The first partition structure 1110 and the first dielectric layer 113' divide the first conductive layer 111' into a first electrode 111a and a second electrode 111b, with the first electrode 111a and the second electrode 111b located on both sides of the first dielectric layer 113' along the second direction (Y).
[0093] The second partition structure 1120 extends along the stacking direction (Z) and is located at both ends of the second conductive layer 112' along the first direction (X). The second partition structure 1120 and the second dielectric layer 114' partition the second conductive layer 112' into a third electrode 112a and a fourth electrode 112b, which are respectively located on both sides of the second dielectric layer 114' along the second direction (Y). Therefore, the first electrode 111a and the third electrode 112a can form... Figure 3 In the capacitor structure C0, the second electrode 111b and the fourth electrode 112b can form a capacitor structure C0 in 3.
[0094] Please see Figure 6 and Figure 7 , Figure 6 This is a partial cross-sectional schematic diagram of the first and second gate wire slot structures provided in some embodiments of this application. Figure 7 This is a schematic cross-sectional view of a semiconductor device along the YZ plane provided in some embodiments of this application. Figure 7 The left-middle figure is a schematic cross-sectional view of the semiconductor device along the YZ plane at the second gate gap. Figure 7 The figure on the right is a schematic cross-sectional view of the semiconductor device along the YZ plane at the first gate gap.
[0095] Semiconductor device 200 includes a core region S1 and a non-core region S2 adjacent to the core region S1 in the first direction (X). The first gate line slot structure 21 is located in the non-core region S2 and is disposed along the first direction (X). The first gate line slot structure 21 includes a first conductive layer 211, a second conductive layer 212, a first dielectric layer 213, a second dielectric layer 214, and a first isolation layer 215.
[0096] In some embodiments, the core region S1 may be located on both sides of the non-core region S2 along the first direction (X), that is, the non-core region S2 is located in the middle of the core region S1.
[0097] In some embodiments, the semiconductor device 200 may include a main region and an edge region located around the main region. The main region may include the core region S1 and the non-core region S2.
[0098] In some embodiments, the semiconductor device 200 further includes a second gate line gap structure 22 located in the core region S1. The second gate line gap structure 22 penetrates the stacked structure 20 of the core region S1 along the stacking direction (Z) and is disposed along the first direction (X). The stacked structure 20 includes alternately stacked insulating layers 201 and gate layers 202.
[0099] like Figure 6 As shown, one end of the second gate line slot structure 22 along the first direction (X) is connected to the first gate line slot structure 21. The first gate line slot structure 21 and the second gate line slot structure 22 form a continuous gate line slot structure, dividing different storage blocks.
[0100] It should be noted that, Figure 6 Only a portion of the structure at the connection between the first gate line slot structure 21 and the second gate line slot structure 22 is shown. Specifically, the second gate line slot structure 22 includes a third conductive layer 221 and a second insulating layer 225. The third conductive layer 221 is disposed along the first direction (X) and connected to the first conductive layer 211. The second insulating layer 225 surrounds the sidewall of the third conductive layer 221 and is connected to the first insulating layer 215. The first insulating layer 215 and the second insulating layer 225 together surround the sidewalls and bottom of the third conductive layer 221 and the first conductive layer 211.
[0101] In some embodiments, the width W1 of the second gate line slot structure 22 along the second direction (Y) is smaller than the width W2 of the first gate line slot structure 21 along the second direction (Y). Therefore, the first gate line slot structure 21 has more space to accommodate two conductive layers.
[0102] In some embodiments, such as Figure 7As shown, the junction of the first isolation layer 215 and the gate layer 202 has a protruding structure, and the junction of the second isolation layer 225 and the gate layer 202 has a protruding structure.
[0103] In some embodiments, referring to FIG5, a first partition structure may be provided at the connection between the first conductive layer 211 and the third conductive layer 221 to partition the first conductive layer 211 into a first electrode and a second electrode. Second partition structures may be provided at both ends of the second conductive layer 212 along the first direction (X) to partition the second conductive layer 212 into a third electrode and a fourth electrode.
[0104] The semiconductor device provided in this application includes a stacked structure and a first gate line gap structure. The stacked structure includes alternately stacked insulating layers and gate layers. The first gate line gap structure penetrates the stacked structure along its stacking direction (Z) and extends along a first direction (X), which intersects the stacking direction (Z). The first gate line gap structure includes a first conductive layer, a second conductive layer, and a first dielectric layer. The first conductive layer surrounds the sidewall of the second conductive layer, and the first dielectric layer is located between the second conductive layer and the first conductive layer. Since the first gate line gap structure includes two mutually insulating conductive layers, the first and second conductive layers can form a capacitor structure as part of some circuitry. Therefore, this application can fully utilize the first gate line gap structure 21, improving its utilization rate and reducing wasted area. The first gate line gap structure can not only separate memory blocks but also form a capacitor structure, and further save area for corresponding peripheral circuitry.
[0105] Please see Figure 8 , Figure 8 This is a schematic flowchart illustrating the fabrication method of a semiconductor device provided in some embodiments of this application. Please also refer to... Figures 9a-9d , Figures 9a-9d This is a schematic diagram of the structure of the semiconductor device provided in some embodiments of this application during the fabrication process. This embodiment uses the fabrication of the above-mentioned semiconductor device 100 as an example to illustrate the fabrication method of the semiconductor device 100. Therefore, please refer to... Figure 1 , Figure 4 As shown in Figure 5, the method for fabricating this semiconductor device includes the following steps S1-S2.
[0106] Step S1: Form a stacked structure 10, the stacked structure 10 including an insulating layer 101 and a gate layer 102 stacked alternately.
[0107] Step S2: Form a first gate line slot structure 11 that extends through the stacking structure 10 along the stacking direction (Z). The first gate line slot structure 11 extends along a first direction (X) that intersects the stacking direction (Z). The first gate line slot structure 11 includes a first conductive layer 111, a second conductive layer 112, and a first dielectric layer 113. The first conductive layer 111 surrounds the sidewall of the second conductive layer 112, and the first dielectric layer 113 is located between the second conductive layer 112 and the first conductive layer 111.
[0108] For details, see Figure 9a A first gate line slot 116 is formed that runs through the stacking structure 10 along the stacking direction (Z). The first gate line slot 116 is located in the first edge region P21 and the second edge region P22 and extends along the first direction (X).
[0109] See Figures 9a-9d and Figure 1 A first isolation layer 115, a first conductive layer 111, a first dielectric layer 113, a second conductive layer 112, and a second dielectric layer 114 are sequentially formed in the first gate line gap 116.
[0110] You can refer to this. Figure 1 The method for fabricating a semiconductor device may further include forming a peripheral circuit 12 on one side of the stacked structure 10. The peripheral circuit 12 includes a charge pump circuit, and a plurality of the first gate line gap structures 11 are connected to the charge pump circuit through connecting contacts.
[0111] Please see Figures 10a-10c , Figures 10a-10c This is a schematic diagram of the semiconductor device provided in some embodiments of this application during the fabrication process. This embodiment uses the fabrication of the above-mentioned semiconductor device 200 as an example to illustrate the fabrication method of the semiconductor device 200. Therefore, please refer to... Figure 6 and Figure 7 The method for fabricating this semiconductor device includes steps S1-S2.
[0112] Step S1: Form a stacked structure 20, which includes an insulating layer 201 and a gate layer 202 stacked alternately.
[0113] Step S2: Form a first gate line slot structure 21 that extends through the stacking structure 20 along the stacking direction (Z). The first gate line slot structure 21 extends along a first direction (X) that intersects the stacking direction (Z). The first gate line slot structure 21 includes a first conductive layer 211, a second conductive layer 212, and a first dielectric layer 213. The first conductive layer 211 surrounds the sidewall of the second conductive layer 212, and the first dielectric layer 213 is located between the second conductive layer 212 and the first conductive layer 211.
[0114] The method for fabricating the semiconductor device further includes forming a second gate gap structure 22 of the stacked structure 20 that extends through the core region S1 along the stacking direction (Z).
[0115] In some embodiments, the second gate line slot structure 22 may be formed together with the first gate line slot structure 21. The steps of forming the first gate line slot structure 21 and forming the second gate line slot structure 22 include the following steps.
[0116] 1) See Figure 10a and Figure 6 A trench is formed that runs through the stack structure 20 along the stacking direction (Z). The trench includes a first gate line slot T1 located in the non-core region S2 and a second gate line slot T2 located in the core region S1. The width of the first gate line slot T1 in the second direction (Y) is greater than the width of the second gate line slot T2 in the second direction (Y).
[0117] in, Figure 10a The left-middle figure is a schematic diagram of the cross-sectional structure of the second grid line gap T2 along the YZ plane. Figure 10a The figure on the right is a schematic diagram of the cross-sectional structure of the first grid line gap T1 along the YZ plane.
[0118] The method for fabricating this semiconductor device further includes forming a first memory channel structure CH1 and a second memory channel structure CH2 in the stacked structure 20 of the non-core region S2 and the core region S1, respectively. The first memory channel structure CH1 is adjacent to the first gate line gap T1, and the second memory channel structure CH2 is adjacent to the second gate line gap T2. Unlike the second memory channel structure CH2, a lead-out contact CHC is also formed on the top of the first memory channel structure CH1.
[0119] 2) See Figures 10a-10cAn isolation layer, a conductive layer, a first dielectric layer 213, a second conductive layer 212, and a second dielectric layer 114 are sequentially formed in the trench. The isolation layer includes a first isolation layer 115 located in the first gate line gap T1 and a second isolation layer 225 located in the second gate line gap T2. The conductive layer includes a first conductive layer 211 located in the first gate line gap T1 and a third conductive layer 221 located in the second gate line gap T2, and the second isolation layer 225 and the third conductive layer 221 fill the second gate line gap T2.
[0120] An isolation layer, a conductive layer, a first dielectric layer 213, a second conductive layer 212, and a second dielectric layer 114 can be sequentially deposited in the first gate gap T1 and the second gate gap T2 using a deposition process. Since the width of the first gate gap T1 is greater than the width of the second gate gap T2, even after the isolation layer and the conductive layer fill the second gate gap T2, there is still space in the first gate gap T1 to continue depositing the first dielectric layer 213, the second conductive layer 212, and the second dielectric layer 114.
[0121] like Figure 10b As shown, an isolation layer and a conductive layer are also deposited on the stacked structure 20 of the core region S1 and the non-core region S2. Figure 10c As shown, the first dielectric layer 213 and the second conductive layer 212 are also deposited on the stacked structure 20 of the core region S1. Figure 7 As shown, the method for fabricating the semiconductor device 00 may further include: removing the isolation layer, conductive layer, first dielectric layer 213 and second conductive layer 212 located on the stacked structure 20 by chemical mechanical polishing.
[0122] The semiconductor device fabrication method provided in this application forms two mutually insulating conductive layers in the first gate gap T1. The first conductive layer 211 and the second conductive layer 212 can form a capacitor structure as part of some circuit structures. Therefore, this application can make full use of the first gate gap structure 21, improve the utilization rate of the first gate gap structure 21, reduce area waste, and also save some circuit area.
[0123] Please see Figure 11 , Figure 11 This is a schematic diagram of the structure of a storage system provided in some embodiments of this application. The storage system 300 includes a semiconductor device 301 and a controller 302. The semiconductor device 301 can be any of the semiconductor devices described in the above embodiments, and can be fabricated using the methods described in the above embodiments. The controller 302 is electrically connected to the semiconductor device 301 and is used to control the semiconductor device 301 to store data. The semiconductor device 301 can perform data storage operations based on the control of the controller 302.
[0124] In some implementations, the storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.
[0125] The semiconductor device 301 may include a stacked structure and a first gate line gap structure. The stacked structure includes alternately stacked insulating layers and gate layers. The first gate line gap structure extends through the stacked structure along its stacking direction and extends along a first direction that intersects the stacking direction. The first gate line gap structure includes a first conductive layer, a second conductive layer, and a first dielectric layer. The first conductive layer surrounds the sidewall of the second conductive layer, and the first dielectric layer is located between the second conductive layer and the first conductive layer.
[0126] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A semiconductor device, characterized in that, The semiconductor device includes: A stacked structure, comprising alternating stacked insulating layers and gate layers; The first gate line slot structure penetrates the stacked structure along the stacking direction and extends along a first direction, which intersects the stacking direction. The first gate gap structure includes a first conductive layer, a second conductive layer, and a first dielectric layer. The first conductive layer surrounds the sidewall of the second conductive layer, and the first dielectric layer is located between the second conductive layer and the first conductive layer.
2. The semiconductor device according to claim 1, characterized in that, The first gate wire slot structure further includes: A second dielectric layer extends along the first direction, and a second conductive layer surrounds the sidewall of the second dielectric layer.
3. The semiconductor device according to claim 2, characterized in that, The first gate wire slot structure further includes: A first isolation layer is located between the stacked structure and the first conductive layer.
4. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: The first partition structure extends along the stacking direction and is located at both ends of the first conductive layer along the first direction; The first partition structure divides the first conductive layer into a first electrode and a second electrode. The first electrode and the second electrode are located on both sides of the first dielectric layer along the second direction, and the first direction, the second direction and the stacking direction intersect each other.
5. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes: The second partition structure extends along the stacking direction and is located at both ends of the second conductive layer along the first direction; The second isolation structure isolates the second conductive layer into a third electrode and a fourth electrode. The third electrode and the fourth electrode are located on both sides of the second dielectric layer along the second direction, and the first direction, the second direction and the stacking direction intersect each other.
6. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a body region and an edge region located around the body region. The edge region includes a first edge region and a second edge region located on both sides of the body region in a second direction. The first direction, the second direction, and the stacking direction intersect each other. The first grid line slot structure is located in the first edge region and the second edge region.
7. The semiconductor device according to claim 6, characterized in that, The first edge region has two first grid line slot structures arranged along the first direction and parallel to each other, and the second edge region has two first grid line slot structures arranged along the first direction and parallel to each other.
8. The semiconductor device according to claim 3, characterized in that, The semiconductor device includes a core region and a non-core region adjacent to the core region in the first direction, and the first gate line gap structure is located in the non-core region and is disposed along the first direction.
9. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes: The second gate line slot structure penetrates the stacked structure of the core region along the stacking direction and is disposed along the first direction. One end of the second gate line slot structure along the first direction is connected to the first gate line slot structure.
10. The semiconductor device according to claim 9, characterized in that, The second gate line slot structure includes: A third conductive layer is disposed along the first direction and connected to the first conductive layer; The second isolation layer surrounds the sidewall of the third conductive layer and is connected to the first isolation layer.
11. The semiconductor device according to claim 9, characterized in that, The width of the second gate line slot structure along the second direction is smaller than the width of the first gate line slot structure along the second direction, and the first direction, the second direction and the stacking direction intersect each other.
12. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: The peripheral circuit is located on one side of the stacked structure. The peripheral circuit includes a charge pump circuit, and a plurality of first gate line slot structures are connected to the charge pump circuit through connecting contact points.
13. The semiconductor device according to claim 12, characterized in that, The multiple first conductive layers in the multiple first gate wire slot structures are connected in parallel, and the multiple second conductive layers in the multiple first gate wire slot structures are connected in parallel.
14. A method for fabricating a semiconductor device, characterized in that, The method for fabricating the semiconductor device includes: A stacked structure is formed, the stacked structure comprising alternately stacked insulating layers and gate layers; A first gate line slot structure is formed that extends through the stacking structure along the stacking direction of the stacking structure. The first gate line slot structure extends along a first direction that intersects the stacking direction. The first gate line slot structure includes a first conductive layer, a second conductive layer, and a first dielectric layer. The first conductive layer surrounds the sidewall of the second conductive layer, and the first dielectric layer is located between the second conductive layer and the first conductive layer.
15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The semiconductor device includes a body region and an edge region located around the body region. The edge region includes a first edge region and a second edge region located on both sides of the body region in a second direction. The first direction, the second direction, and the stacking direction intersect each other. The step of forming a first gate wire slot structure that penetrates the stack structure along the stacking direction includes: A first gate line slot is formed that extends through the stacking structure along the stacking direction of the stacking structure. The first gate line slot is located in the first edge region and the second edge region and extends along the first direction. A first isolation layer, a first conductive layer, a first dielectric layer, a second conductive layer, and a second dielectric layer are sequentially formed in the first gate line gap.
16. The method for fabricating a semiconductor device according to claim 14, characterized in that, The semiconductor device includes a main region and an edge region located around the main region. The main region includes a core region and a non-core region adjacent to the core region in the first direction. The first gate line gap structure is located in the non-core region. The method for fabricating the semiconductor device further includes: A second gate slot structure is formed in the stacked structure that extends through the core region along the stacking direction.
17. The method for fabricating a semiconductor device according to claim 16, characterized in that, The steps of forming the first gate wire slot structure and forming the second gate wire slot structure include: A trench is formed that penetrates the stacking structure along the stacking direction. The trench includes a first gate line slot located in the non-core region and a second gate line slot located in the core region. The width of the first gate line slot in the second direction is greater than the width of the second gate line slot in the second direction. The first direction, the second direction, and the stacking direction intersect each other. An isolation layer, a conductive layer, a first dielectric layer, a second conductive layer, and a second dielectric layer are sequentially formed in the trench. The isolation layer includes a first isolation layer located in the first gate line gap and a second isolation layer located in the second gate line gap. The conductive layer includes a first conductive layer located in the first gate line gap and a third conductive layer located in the second gate line gap. The second isolation layer and the third conductive layer fill the second gate line gap.
18. The method for fabricating a semiconductor device according to claim 14, characterized in that, The method for fabricating the semiconductor device further includes: An external circuit is formed on one side of the stacked structure. The external circuit includes a charge pump circuit, and a plurality of first gate line slot structures are connected to the charge pump circuit through connecting contact points.
19. A storage system, characterized in that, include: The semiconductor device according to any one of claims 1-13; A controller, electrically connected to the semiconductor device, is used to control the semiconductor device to store data.