Semiconductor device and method of manufacturing the same
By alternately filling the gaps with silicon oxide and silicon nitride materials, the problem of the gap dielectric affecting the capacitance value in the prior art is solved, thus improving the device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUAHONG INTEGRATED CIRCUIT (CHENGDU) CO LTD
- Filing Date
- 2026-03-30
- Publication Date
- 2026-06-23
AI Technical Summary
In existing embedded silicon-germanium processes, the filling medium in the gaps affects the gate-contact capacitance, thus impacting device performance.
The gap between the fill layer and the gate sidewall is filled with a sidewall material with a low dielectric constant. By using silicon oxide and silicon nitride materials to fill the gap alternately during the fabrication process, the capacitance of the gate-contact hole is reduced.
This effectively reduces the capacitance of the gate-contact hole, thus improving device performance.
Smart Images
Figure CN122269744A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit manufacturing technology, and in particular to a semiconductor device and its fabrication method. Background Technology
[0002] Maximizing transistor performance is a persistent goal in the field of semiconductor technology. Since stress can change the bandgap and carrier mobility (electrons in NMOS transistors and holes in PMOS transistors) of silicon materials, applying stress to the channel region of transistors to improve transistor performance has become an increasingly common approach.
[0003] For PMOS transistors, embedded silicon-germanium technology can be used to generate compressive stress in the channel region of the transistor, thereby improving carrier mobility. Embedded silicon-germanium technology refers to embedding silicon-germanium material in a semiconductor substrate adjacent to the channel region of the PMOS transistor. By utilizing the lattice difference between silicon and silicon-germanium (SiGe), compressive stress is generated in the channel region.
[0004] In an existing embedded silicon-germanium process, such as Figure 1 As shown, after forming a hard mask layer covering the semiconductor substrate 10 and the gate structure 11, the hard mask layer is patterned to form a hard mask pattern. Then, using the hard mask pattern as a mask, the semiconductor substrate 10 is etched to form trenches, and dielectric material is filled into the trenches to form silicon-germanium source / drain regions 12. The hard mask pattern is then removed. When the dielectric material filling the trench is higher than the semiconductor substrate 10, after removing the hard mask pattern, the protruding portion will form a gap B between itself and the gate structure 11. Studies have found that the dielectric material filling gap B affects the capacitance value between the gate and contact hole (CGC), thereby affecting device performance. Summary of the Invention
[0005] This application provides a semiconductor device and its fabrication method. By filling the gap between the fill layer and the gate sidewall with a sidewall material with a small dielectric constant, the capacitance value of the gate-contact hole (CGC) is reduced, thereby improving device performance.
[0006] According to some embodiments of this application, one aspect of this application provides a method for fabricating a semiconductor device, including:
[0007] A semiconductor substrate is provided, the semiconductor substrate including an N-type well region, and a first gate structure is formed above the N-type well region; a hard mask layer is formed, the hard mask layer covering the semiconductor substrate and the top surface and sidewalls of the first gate structure; the hard mask layer on the surface of the semiconductor substrate and the top surface of the first gate structure in the N-type well region is removed, and the hard mask layer on the sidewalls of the first gate structure is thinned to form a first sidewall layer, and grooves are formed in the N-type well regions on both sides of the first gate structure; a fill layer is formed in the grooves, and the hard mask layer outside the N-type well region is removed, wherein the fill layer protrudes above the semiconductor substrate and there is a gap between the protruding portion and the first sidewall layer; a second sidewall layer is formed. The second sidewall material covers the semiconductor substrate, the top surface of the first gate structure, the first sidewall layer, and the top surface of the fill layer, and fills the gaps. The material of the second sidewall material is silicon oxide. The second sidewall material is etched back to remove a portion of its thickness. A third sidewall material is formed, which covers the second sidewall material and is made of silicon nitride. The second sidewall material on the surface of the semiconductor substrate and the top surface of the first gate structure is removed to form a second sidewall layer, and the third sidewall material on the surface of the semiconductor substrate and the top surface of the first gate structure is removed to form a third sidewall layer.
[0008] Furthermore, before the second sidewall material is etched back, the thickness of the second sidewall material is between 50 and 60 angstroms; after the second sidewall material is etched back, the remaining thickness of the second sidewall material is between 15 and 25 angstroms.
[0009] Furthermore, the filler layer is made of silicon-germanium alloy.
[0010] Furthermore, the groove is sigma-shaped.
[0011] Furthermore, the trench formation step includes: using the hard mask layer as a mask, performing dry etching on the N-type well region of the semiconductor substrate to form a trench in the semiconductor substrate; and using a TMAH aqueous solution to perform wet etching on the sidewalls of the trench to form the trench.
[0012] Furthermore, the semiconductor substrate also includes a P-type well region, on which a second gate structure is formed.
[0013] Furthermore, the hard mask layer also covers the top surface and sidewalls of the second gate structure on the P-type well region;
[0014] The step of removing the hard mask layer on the surface of the semiconductor substrate and the top surface of the first gate structure in the N-type well region includes: performing a photolithography process to form a photoresist layer on the hard mask layer in the P-type well region; and using the photoresist layer as a mask, etching the hard mask layer on the surface of the semiconductor substrate and the top surface of the first gate structure in the N-type well region.
[0015] Furthermore, the second sidewall material is formed using a thermal oxidation process.
[0016] Furthermore, a wet etching process is used to etch the second sidewall material back.
[0017] According to some embodiments of this application, another aspect of this application provides a semiconductor device, which is prepared using the semiconductor device preparation method described in any one of the above-mentioned methods.
[0018] The technical solution provided in this application has at least the following advantages:
[0019] The semiconductor device and its fabrication method provided in this application include providing a semiconductor substrate, the semiconductor substrate including an N-type well region, and a first gate structure formed above the N-type well region; forming a hard mask layer covering the top surface and sidewalls of the semiconductor substrate and the first gate structure; removing the hard mask layer on the surface of the semiconductor substrate and the top surface of the first gate structure in the N-type well region, and thinning the hard mask layer on the sidewalls of the first gate structure to form a first sidewall layer; forming grooves in the N-type well regions on both sides of the first gate structure; forming a filling layer in the grooves; and removing the hard mask layer outside the N-type well region, wherein the filling layer protrudes above the semiconductor substrate and the protruding portion is adjacent to the first sidewall layer. A gap exists between the two layers. A second sidewall material is formed, covering the semiconductor substrate, the top surface of the first gate structure, the first sidewall layer, and the top surface of the fill layer, and filling the gap. The material of the second sidewall material is silicon oxide. The second sidewall material is etched back to remove a portion of its thickness. A third sidewall material is formed, covering the second sidewall material. The material of the third sidewall material is silicon nitride. The second sidewall material on the surface of the semiconductor substrate and the top surface of the first gate structure is removed to form a second sidewall layer, and the third sidewall material on the surface of the semiconductor substrate and the top surface of the first gate structure is also removed to form a third sidewall layer. In this way, a sidewall material with a smaller dielectric constant is filled into the gap between the fill layer and the gate sidewall to reduce the capacitance of the gate-contact hole (CGC) and improve device performance. Attached Figure Description
[0020] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 A schematic cross-sectional view of a semiconductor substrate provided in a prior art embodiment;
[0022] Figure 2 A schematic flowchart illustrating the fabrication method of the semiconductor device provided in the embodiments of this application;
[0023] Figure 3 This is a cross-sectional schematic diagram of step S11 in the method for fabricating the semiconductor device provided in this embodiment;
[0024] Figure 4 This is a cross-sectional schematic diagram of step S12 in the method for fabricating the semiconductor device provided in this embodiment;
[0025] Figures 5A to 5B This is a cross-sectional schematic diagram of step S13 in the method for fabricating the semiconductor device provided in this embodiment;
[0026] Figures 6A to 6B This is a cross-sectional schematic diagram of step S14 in the method for fabricating the semiconductor device provided in this embodiment;
[0027] Figure 7 This is a cross-sectional schematic diagram of step S15 in the method for fabricating the semiconductor device provided in this embodiment;
[0028] Figure 8 This is a cross-sectional schematic diagram of step S16 in the method for fabricating the semiconductor device provided in this embodiment;
[0029] Figure 9 This is a cross-sectional schematic diagram of step S17 in the method for fabricating the semiconductor device provided in this embodiment;
[0030] Figure 10 This is a cross-sectional schematic diagram of step S18 in the method for fabricating the semiconductor device provided in this embodiment.
[0031] Explanation of icon numbers:
[0032] 100 - Semiconductor substrate, 101 - N-type well region, 1011A - First source region, 1011B - First drain region, 102 - P-type well region, 1021A - Second source region, 1021B - Second drain region, 103 - STI isolation region, 111 - First gate structure, 111A - First polysilicon layer, 111B - First gate oxide layer, 111C - N-region sub-sidewall, 112 - Second Gate structure, 112A - second polysilicon layer, 112B - second gate oxide layer, 112C - P-region sub-sidewall, 120 - hard mask layer, 121 - first sidewall layer, 1012 - trench, 1012A - trench, A - gap, 130 - photoresist layer, 140 - fill layer, 150 - second sidewall material, 151 - second sidewall layer, 160 - third sidewall material, 161 - third sidewall layer. Detailed Implementation
[0033] In related technologies, Figure 1 The filling medium in the gap shown is one of the subsequent multilayer sidewall materials, and a sidewall material with a relatively large dielectric constant is used. The study found that after gap filling, the actual value of the gate-channel (CGC) capacitance differed significantly from the target value.
[0034] Based on this, this application provides a semiconductor device and a method for fabricating the same. In the fabrication method, a second sidewall material, made of silicon oxide, fills the gaps. Then, the second sidewall material is etched back to remove a portion of its thickness before forming a third sidewall material, made of silicon nitride. Finally, the second and third sidewall materials are etched to form a second sidewall layer and a third sidewall layer. In this way, a second sidewall material with a relatively low dielectric constant is filled into the gap between the fill layer and the first sidewall layer, thereby reducing the capacitance of the gate-contact (CGC) and improving device performance.
[0035] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0036] refer to Figure 2 , Figure 2 This is a schematic flowchart illustrating the fabrication method of the semiconductor device provided in this embodiment. The fabrication method of the semiconductor device provided in this application embodiment includes:
[0037] S11: A semiconductor substrate is provided, the semiconductor substrate including an N-type well region, and a first gate structure is formed above the N-type well region;
[0038] S12: Form a hard mask layer, which covers the top surface and sidewalls of the semiconductor substrate and the first gate structure;
[0039] S13: Remove the hard mask layer on the surface of the semiconductor substrate and the top surface of the first gate structure in the N-type well region, and thin the hard mask layer on the sidewall of the first gate structure to form the first sidewall layer, and form grooves in the N-type well regions on both sides of the first gate structure.
[0040] S14: Form a filling layer in the groove and remove the hard mask layer other than the N-type well region, wherein the filling layer protrudes above the semiconductor substrate and there is a gap between the protruding portion and the first sidewall layer;
[0041] S15: Form a second sidewall material. The second sidewall material covers the semiconductor substrate, the top surface of the first gate structure, the first sidewall layer, and the top surface of the filling layer. The second sidewall material also fills the gaps. The material of the second sidewall material is silicon oxide.
[0042] S16: Etch back the second sidewall material to remove a portion of the second sidewall material thickness;
[0043] S17: Form a third sidewall material, which covers the second sidewall layer. The material of the third sidewall material is silicon nitride.
[0044] S18: Remove the second sidewall material from the surface of the semiconductor substrate and the top surface of the first gate structure to form a second sidewall layer, and remove the third sidewall material from the surface of the semiconductor substrate and the top surface of the first gate structure to form a third sidewall layer.
[0045] The embodiments of this application will be described in more detail below with reference to the accompanying drawings.
[0046] First, execute step S11, as follows: Figure 3 As shown, a semiconductor substrate 100 is provided. The material of the semiconductor substrate 100 may include undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. As an example, the semiconductor substrate 100 is made of single-crystal silicon.
[0047] The semiconductor substrate 100 includes an N-type well region 101, and a first gate structure 111 is formed above the N-type well region 101. First source / drain regions are formed in the N-type well regions 101 on both sides of the first gate structure 111. The first gate structure 111 includes a first polysilicon layer 111A, a first gate oxide layer 111B, and an N-region sub-sidewall 111C. The first gate oxide layer 111B is located below the first polysilicon layer, and the N-region sub-sidewall 111C is located on the sidewall of the first polysilicon layer. The first source / drain regions include a first source region 1011A (S) and a first drain region 1011B (D). The material of the N-region sub-sidewall 111C can be silicon nitride.
[0048] The semiconductor substrate 100 also includes a P-type well region 102, and a second gate structure 112 is formed above the P-type well region 102. Second source / drain regions are formed in the P-type well regions 102 on both sides of the second gate structure 112. The second gate structure 112 includes a second polysilicon layer 112A, a second gate oxide layer 112B, and a P-region sub-sidewall 112C. The second source / drain regions include a second source region 1021A and a second drain region 1021B. The material of the P-region sub-sidewall 112C may be silicon nitride.
[0049] The semiconductor substrate 100 also includes an STI isolation region 103, which divides the semiconductor substrate 100 into an N-type well region 101 and a P-type well region 102. A first gate structure 111 can be used to form a PMOS transistor in the N-type well region 101. A second gate structure 112 can be used to form an NMOS transistor in the P-type well region 102.
[0050] Next, proceed to step S12, as follows: Figure 4 As shown, a hard mask layer 120 is formed, which covers the top surface and sidewalls of the semiconductor substrate and the first gate structure 111.
[0051] In this embodiment, the hard mask layer 120 also covers the top surface and sidewalls of the second gate structure 112. Typically, the hard mask layer 120 is formed using chemical vapor deposition. The material of the hard mask layer 120 is silicon oxide.
[0052] Next, proceed to step S13, as follows: Figure 5A and Figure 5B As shown, the hard mask layer 120 on the surface of the semiconductor substrate 100 and the top surface of the first gate structure 111 in the N-type well region 101 is removed, and the hard mask layer 120 on the sidewall of the first gate structure 111 is thinned to form the first sidewall layer 121, and the groove 1012 is formed in the N-type well region 101 on both sides of the first gate structure 111.
[0053] As an example, such as Figure 5AAs shown, the step of removing the hard mask layer 120 from the surface of the semiconductor substrate 100 and the top surface of the first gate structure 111 in the N-type well region 101 includes: performing a photolithography process to form a photoresist layer 130 on the hard mask layer 120 of the P-type well region 102; and using the photoresist layer 130 as a mask, etching the hard mask layer 120 from the surface of the semiconductor substrate 100 and the top surface of the first gate structure 111 on the N-type well region 101. Specifically, an anisotropic dry etching process is used to etch the hard mask layer 120 from the surface of the semiconductor substrate 100 and the top surface of the first gate structure 111.
[0054] Next, the semiconductor substrates 100 on both sides of the first gate structure 111 are etched using a dry etching process. When the etching gas etches the semiconductor substrate 100, the hard mask layer 120 on the sidewall of the first gate structure 111 is thinned by the bombardment of the plasma, thus forming the first sidewall layer 121.
[0055] As an example, the groove 1012 is sigma-shaped. The groove 1012 covers at least a portion of the first source-drain region. Of course, the groove 1012 can also be other shapes, such as square, U-shaped, etc. When the groove 1012 is sigma-shaped, the distance between the first source-drain regions can be reduced, effectively increasing the stress applied to the channel region, thereby improving the performance of the PMOS transistor above the channel region.
[0056] As an example, such as Figure 5B As shown, when the groove 1012 is sigma-shaped, during the formation of the groove 1012, the N-type well region 101 of the semiconductor substrate 100 is dry-etched to form the trench 1012A within the semiconductor substrate 100. The trench 1012A at this time has a conventional shape, such as a bowl shape. Then, the sidewalls of the trench 1012A are wet-etched using a TMAH (Tetramethyl Ammonium Hydroxide) aqueous solution to form the groove 1012.
[0057] TMAH solution has a high etching rate, is non-toxic and non-polluting, and is easy to operate. TMAH also has good crystal orientation selectivity, with a faster etching rate in some crystal orientations and a very slow etching rate in others. Therefore, by taking advantage of the different etching rates of TMAH aqueous solution in different crystal orientations of semiconductor substrate 100, trenches can be etched to form sigma-shaped grooves.
[0058] Next, proceed to step S14, as follows: Figure 6A and 6B As shown, a filling layer 140 is formed in the groove 1012, and a hard mask layer 120 is removed from the N-type well region. The filling layer 140 extends above the semiconductor substrate 100 and there is a gap A between the extended portion and the first sidewall layer 121.
[0059] As an example, such as Figure 6B As shown, removing the hard mask layer 120 outside the N-type well region specifically includes: removing the photoresist layer 130 on the P-type well region using an ashing process, and then removing the hard mask layer 120 on the P-type well region using a dry etching process, a wet etching process, or a combination thereof. Dry etching processes include, for example, fluorine-based plasma etching, and wet etching processes include, for example, thermal phosphoric acid etching.
[0060] As an example, the material of the filling layer 140 can be a silicon-germanium alloy. The filling layer 140 is formed by an epitaxial growth process. Because the lattice difference between the filling layer 140 and the silicon in the semiconductor substrate 100 is different, it can generate compressive stress in the channel region between the first source and drain regions 1011, which is beneficial to improving the carrier mobility.
[0061] In this embodiment, the filler layer 140 protrudes from the groove 1012, such that the top surface of the filler layer 140 is higher than the semiconductor substrate 100. In another embodiment, the top surface of the filler layer 140 may be lower than the semiconductor substrate 100, or it may be nearly flush with the semiconductor substrate 100. This embodiment mainly considers the case where the filler layer 140 protrudes from the groove 1012.
[0062] Next, proceed to step S15, as follows: Figure 7 As shown, a second sidewall material 150 is formed, which covers the top surface of the semiconductor substrate 100, the first gate structure 111, the first sidewall layer 121, and the top surface of the filling layer 140. The second sidewall material 150 fills the gap A, and the material of the second sidewall material 150 is silicon oxide.
[0063] In this embodiment, a thermal oxidation process is used to form the second sidewall material 150. The second sidewall material 150 also covers the second gate structure 112. After the thermal oxidation process, the semiconductor substrate 100, the top surface of the first gate structure 111, the first sidewall layer 121, the top surface and sidewalls of the second gate structure 112 form the second sidewall material 150. As another example, the material of the second sidewall material 150 is not limited to silicon oxide, but can also be other oxygen-containing materials.
[0064] In this embodiment, the thickness of the second sidewall material 150 is at least greater than the gap width, so that when the filling layer in the groove is higher than the semiconductor substrate, there is a gap between the protruding part and the first sidewall layer 121, and the second sidewall material 150 can fill the gap.
[0065] Next, proceed to step S16, as follows: Figure 8 As shown, the second sidewall material 150 is etched back to remove a portion of the thickness of the second sidewall material 150.
[0066] Furthermore, a portion of the second sidewall material 150 can be removed using either dry etching or wet etching processes. The etchant used in the wet etching process can be a hydrofluoric acid solution.
[0067] Before the second sidewall material 150 is etched back, its thickness is between 50 and 60 angstroms; after the second sidewall material 150 is etched back, its remaining thickness is between 15 and 25 angstroms. As an example, the width of gap A is 16 angstroms, and the thickness of the second sidewall material before the etch-back is 55 angstroms. Thus, the second sidewall material 150 fills gap A, and its thickness after the etch-back is 20 angstroms, thereby satisfying the preset sidewall thickness requirement for the second sidewall material.
[0068] Next, proceed to step S17, as follows: Figure 9 As shown, a third sidewall material 160 is formed, which covers the second sidewall material 150. The material of the third sidewall material 160 is silicon nitride.
[0069] As an example, the thickness of the third sidewall material 160 is between 85 and 95 angstroms.
[0070] To further explain, this embodiment selects the sidewall material for filling the gap from the perspective of the dielectric constant of the filling medium. Specifically, the dielectric constant of the third sidewall material 160 is greater than that of the second sidewall material 150. The second sidewall material 150 is made of silicon oxide, which has a dielectric constant of 3.9, while the third sidewall material 160 is made of silicon nitride, which has a dielectric constant of 7.
[0071] In one embodiment, when the filling medium in gap A is the third sidewall material 160 silicon nitride, the gate-channel capacitance is 0.33F, and when the filling medium in gap A is the second sidewall material 150 silicon oxide, the gate-channel capacitance is 0.285F. Thus, in this embodiment, gap A is filled with the second sidewall material 150, which increases the gate-channel capacitance by about 13.5% and narrows the gap between the measured value and the target value.
[0072] Next, proceed to step S18, as follows: Figure 10 As shown, the second sidewall material 150 on the surface of the semiconductor substrate 100 and the top surface of the first gate structure 111 is removed to form a second sidewall layer 151, and the third sidewall material 160 on the surface of the semiconductor substrate 100 and the top surface of the first gate structure 111 is removed to form a third sidewall layer 161.
[0073] Furthermore, step S18 also includes removing the second sidewall material 150 from the top surface of the second gate structure 112 and removing the third sidewall material 160 from the top surface of the second gate structure 112, thereby forming a second sidewall layer 151 and a third sidewall layer 161 on the sidewall of the second gate structure 112.
[0074] This embodiment also provides a semiconductor device, which is prepared using the above-described preparation method.
[0075] In summary, the technical solution provided in this application includes providing a semiconductor substrate, the semiconductor substrate including an N-type well region, and a first gate structure formed above the N-type well region; forming a hard mask layer, the hard mask layer covering the top surface and sidewalls of the semiconductor substrate and the first gate structure; removing the hard mask layer on the surface of the semiconductor substrate and the top surface of the first gate structure in the N-type well region, and thinning the hard mask layer on the sidewalls of the first gate structure to form a first sidewall layer; forming grooves in the N-type well regions on both sides of the first gate structure; forming a filling layer in the grooves; and removing the hard mask layer outside the N-type well region, wherein the filling layer protrudes above the semiconductor substrate and the protruding portion is between the first sidewall layer and the semiconductor substrate. A gap exists; a second sidewall material is formed, covering the semiconductor substrate, the top surface of the first gate structure, the first sidewall layer, and the top surface of the fill layer, and filling the gap. The material of the second sidewall material is silicon oxide. The second sidewall material is etched back to remove a portion of its thickness. A third sidewall material is formed, covering the second sidewall material. The material of the third sidewall material is silicon nitride. The second sidewall material on the surface of the semiconductor substrate and the top surface of the first gate structure is removed to form a second sidewall layer, and the third sidewall material on the surface of the semiconductor substrate and the top surface of the first gate structure is also removed to form a third sidewall layer. In this way, a sidewall material with a smaller dielectric constant is filled into the gap between the fill layer and the gate sidewall to reduce the capacitance of the gate-contact via (CGC) and improve device performance.
[0076] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including an N-type well region, and a first gate structure is formed above the N-type well region; A hard mask layer is formed, which covers the semiconductor substrate and the top surface and sidewalls of the first gate structure; Remove the hard mask layer on the surface of the semiconductor substrate and the top surface of the first gate structure in the N-type well region, and thin the hard mask layer on the sidewall of the first gate structure to form a first sidewall layer, and form grooves in the N-type well regions on both sides of the first gate structure. A fill layer is formed in the groove, and the hard mask layer other than the N-type well region is removed, wherein the fill layer protrudes above the semiconductor substrate and there is a gap between the protruding portion and the first sidewall layer; A second sidewall material is formed, which covers the semiconductor substrate, the top surface of the first gate structure, the first sidewall layer, and the top surface of the filling layer, and fills the gap. The material of the second sidewall material is silicon oxide. The second sidewall material is etched back to remove a portion of its thickness. A third sidewall material is formed, which covers the second sidewall material, and the material of the third sidewall material is silicon nitride; The second sidewall material on the surface of the semiconductor substrate and the top surface of the first gate structure is removed to form a second sidewall layer, and the third sidewall material on the surface of the semiconductor substrate and the top surface of the first gate structure is removed to form a third sidewall layer.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, Before the second sidewall material is etched back, the thickness of the second sidewall material is between 50 and 60 angstroms; after the second sidewall material is etched back, the remaining thickness of the second sidewall material is between 15 and 25 angstroms.
3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The filling layer is made of silicon-germanium alloy.
4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The groove is sigma shaped.
5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The steps for forming the groove include: Using the hard mask layer as a mask, dry etching is performed on the N-type well region of the semiconductor substrate to form trenches within the semiconductor substrate; The sidewalls of the trench are wet-etched using a TMAH aqueous solution to form a groove.
6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The semiconductor substrate further includes a P-type well region, and a second gate structure is formed above the P-type well region.
7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The hard mask layer also covers the top surface and sidewalls of the second gate structure on the P-type well region; The step of removing the hard mask layer from the semiconductor substrate surface of the N-type well region and the top surface of the first gate structure includes: A photolithography process is performed to form a photoresist layer on the hard mask layer of the P-type well region; Using the photoresist layer as a mask, the hard mask layer on the surface of the semiconductor substrate and the top surface of the first gate structure on the N-type well region is etched.
8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The second sidewall material is formed using a thermal oxidation process.
9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The second sidewall material was etched back using a wet etching process.
10. A semiconductor device, characterized in that, It is prepared by the method of any one of claims 1 to 9.