Semiconductor structure, method for forming semiconductor structure, and electronic device

Abstract

The application relates to the technical field of semiconductors, in particular to a semiconductor structure, a forming method of the semiconductor structure and an electronic device, the semiconductor structure comprising: a substrate; a shallow trench isolation structure formed from a first surface of the substrate, and a deep trench isolation structure formed from a second surface of the substrate; at least two active regions in the substrate; a polysilicon resistance layer formed at an end of the shallow trench isolation structure close to the first surface; a first contact hole formed on a surface of the active region, and a second contact hole formed on a surface of the polysilicon resistance layer away from the shallow trench isolation structure; wherein a height difference between the first contact hole and the second contact hole is less than a preset height threshold. The semiconductor structure provided by the embodiment of the application has the polysilicon resistance layer directly formed at the end of the shallow trench isolation structure close to the first surface, the step height difference between CT-AA and CT-Poly is reduced, and the CT etch has a sufficient process window.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure, a method for forming a semiconductor structure, and an electronic device. Background Technology

[0002] Automotive 3D distance imaging systems typically require high gain, high sensitivity, and high temporal resolution. A common optical sensor for 3D distance imaging systems is the silicon photomultiplier tube (SiPM). A SiPM consists of multiple single-photon avalanche diodes (SPADs) connected in parallel. Each SPAD unit is usually connected in series with a quenching resistor, and the cathode and anode are connected in parallel. One array outputs a signal as a pixel, and multiple arrays can achieve 3D imaging. The high gain requirement of 3D distance imaging systems for SPAD sensors necessitates higher overvoltages to achieve higher photon detection efficiency. However, excessively high operating voltages pose greater challenges to the device's electrical isolation and DC resistance (DCR) reduction requirements.

[0003] To meet design requirements, a high voltage is typically applied between the polysilicon resistive (Poly) layer and the deep trench isolation (DTI) structure. To achieve electrical isolation between the Poly and DTI under high voltage, related technologies usually involve depositing silicon carbide and an isolation layer (Dep SIN and OX) on the substrate, and then forming the polysilicon resistive (Poly) layer on the isolation layer. However, in these technologies, there is a step height difference of nearly 2000 angstroms between the contact vias (CT-AA) formed on the active region (AA) and the contact vias (CT-Poly) formed on the Poly. This excessive step height difference results in insufficient process windows for the contact via etching (CT etch) process, thus affecting the wafer acceptance test (WAT) performance of the semiconductor device. Summary of the Invention

[0004] This application provides a semiconductor structure, a method for forming a semiconductor structure, and an electronic device to at least solve the problem in the related art where the step height difference between CT-AA and CT-Poly is too large, resulting in insufficient process windows in the CT etch process, thereby affecting the WAT performance of the semiconductor device.

[0005] To solve the above-mentioned technical problems, the technical solution of this application is as follows:

[0006] According to a first aspect of the embodiments of this application, a semiconductor structure is provided, comprising:

[0007] The substrate includes opposing first and second surfaces;

[0008] A shallow trench isolation structure is formed from a first surface of the substrate and a deep trench isolation structure is formed from a second surface of the substrate.

[0009] At least two active regions are located in the substrate, and adjacent active regions are separated by the shallow trench isolation structure and the deep trench isolation structure;

[0010] A polysilicon resistive layer is formed at the end of the shallow trench isolation structure near the first surface; the polysilicon resistive layer is electrically connected to the active region;

[0011] A first contact hole is formed on the surface of the active region, and a second contact hole is formed on the surface of the polysilicon resistive layer away from the shallow trench isolation structure;

[0012] Wherein, the height difference between the height of the first contact hole and the height of the second contact hole is less than a preset height threshold, the preset height threshold being a threshold that ensures the formation process of the first contact hole and the second contact hole meets a preset process window.

[0013] In an optional embodiment, the preset height threshold is proportional to the thickness of the polysilicon resistive layer.

[0014] In an optional embodiment, the preset height threshold is 500 angstroms to 1000 angstroms.

[0015] In an optional embodiment, there are at least two shallow trench isolation structures, and the polysilicon resistive layer is formed on the ends of two adjacent shallow trench isolation structures near the first surface.

[0016] In an optional embodiment, the distance between the end of the deep trench isolation structure away from the second surface and the first surface is greater than 0.

[0017] In an optional embodiment, the distance between the end of the deep trench isolation structure away from the second surface and the first surface is 0.5 μm to 2 μm.

[0018] In an optional embodiment, the deep trench isolation structure extends to the shallow trench isolation structure, and the end of the deep trench isolation structure away from the second surface contacts the end of the shallow trench isolation structure away from the polysilicon resistive layer.

[0019] In one optional embodiment, there are at least two shallow trench isolation structures distributed around the perimeter of the deep trench isolation structure.

[0020] In an optional embodiment, the deep trench isolation structure is located between two adjacent shallow trench isolation structures, the end of the deep trench isolation structure away from the second surface is in contact with the ends of the two adjacent shallow trench isolation structures away from the polysilicon resistive layer, and the distance between the two adjacent shallow trench isolation structures is less than or equal to the width of the deep trench isolation structure.

[0021] In an optional embodiment, the semiconductor structure further includes a light-limiting groove located on the second surface, the light-limiting groove being used to adjust the amount of light irradiated onto the second surface.

[0022] In an optional embodiment, the light-limiting groove has an inverted triangular structure.

[0023] According to a second aspect of the embodiments of this application, a method for forming a semiconductor structure is provided, comprising:

[0024] A substrate is provided; the substrate includes opposing first and second surfaces;

[0025] A shallow trench isolation structure is formed within the substrate from the first surface of the substrate;

[0026] At least two active regions are formed in the substrate;

[0027] A polysilicon resistive layer is formed at the end of the shallow trench isolation structure near the first surface; the polysilicon resistive layer is electrically connected to the active region;

[0028] A first contact hole is formed on the active region, and a second contact hole is formed on the surface of the polysilicon resistive layer away from the shallow trench isolation structure; wherein the height difference between the height of the first contact hole and the height of the second contact hole is less than a preset height threshold, the preset height threshold being a threshold that allows the formation process of the first contact hole and the second contact hole to meet a preset process window.

[0029] A deep trench isolation structure is formed within the substrate from the second surface of the substrate; the deep trench isolation structure and the shallow trench isolation structure are used to isolate adjacent active regions.

[0030] In an optional embodiment, forming a shallow trench isolation structure located within the substrate from a first surface of the substrate includes:

[0031] An isolation layer is formed on the first surface of the substrate, and a zero-layer photomask layer is formed on the isolation layer; a zero-layer marking pattern and a first-layer main chip region pattern are reconstructed in the zero-layer photomask layer; the first-layer main chip region pattern defines the dimensions of the shallow trench isolation structure and the positional relationship between the shallow trench isolation structure and the deep trench isolation structure.

[0032] Using the zero-layer photomask as a mask, the isolation layer and a portion of the substrate are etched sequentially to form the shallow trench isolation structure in the substrate and to form a zero-layer mark in the dicing area; the end of the deep trench isolation structure away from the second surface is in contact with the end of the shallow trench isolation structure away from the polysilicon resistor layer.

[0033] In an optional embodiment, there are at least two shallow trench isolation structures, and the deep trench isolation structure is located between two adjacent shallow trench isolation structures. The end of the deep trench isolation structure away from the second surface contacts the ends of the two adjacent shallow trench isolation structures away from the polysilicon resistor layer, and the distance between two adjacent shallow trench isolation structures is less than or equal to the width of the deep trench isolation structure.

[0034] In an optional embodiment, after forming the shallow trench isolation structure located within the substrate from the first surface of the substrate, the method further includes:

[0035] The shallow trench isolation structure is filled with an insulating material using a high-density plasma method to obtain the filled shallow trench isolation structure.

[0036] The filled shallow trench isolation structure is subjected to chemical mechanical polishing, stopping at the surface of the isolation layer away from the first surface, to obtain the polished shallow trench isolation structure.

[0037] In an optional embodiment, the shallow trench isolation structure comprises at least two structures, wherein a polysilicon resistive layer is formed at the end of the shallow trench isolation structure near the first surface, including:

[0038] The polysilicon resistive layer is deposited on the end of the target shallow trench isolation structure near the first surface; the target shallow trench isolation structure is two adjacent shallow trench isolation structures after polishing.

[0039] In an optional embodiment, after forming a first contact hole on the active region and a second contact hole on the surface of the polysilicon resistive layer away from the shallow trench isolation structure, the method further includes:

[0040] A metal stack is formed at the end of the first contact hole away from the active region and at the end of the second contact hole away from the polysilicon resistive layer;

[0041] The structure forming the metal stack is fused and bonded to the carrier wafer, and the bonded structure is then flipped.

[0042] The formation of a deep trench isolation structure within the substrate from the second surface of the substrate includes:

[0043] The deep trench isolation structure is formed from the upper surface of the flipped structure; wherein the upper surface of the flipped semiconductor structure is the second surface.

[0044] In an optional embodiment, forming the deep trench isolation structure from the upper surface of the flipped structure includes:

[0045] A photoresist layer with a deep trench isolation structure pattern is formed on the upper surface of the flipped semiconductor structure; the dimensions of the deep trench isolation structure are defined in the photoresist layer.

[0046] Using the deep trench isolation structure pattern as a mask, the substrate is etched in the direction of the shallow trench isolation structure. The etching stops when the shallow trench isolation structure is etched to the end away from the polysilicon resistor layer, thus forming the deep trench isolation structure.

[0047] In an optional embodiment, the distance between the end of the deep trench isolation structure away from the second surface and the first surface is greater than 0.

[0048] In an optional embodiment, the distance between the end of the deep trench isolation structure away from the second surface and the first surface is 0.5 μm to 2 μm.

[0049] In an optional embodiment, the preset height threshold is proportional to the thickness of the polysilicon resistive layer.

[0050] In an optional embodiment, the preset height threshold is 500 angstroms to 1000 angstroms.

[0051] In an optional embodiment, the method further includes:

[0052] A light-limiting groove is formed on the second surface; wherein the light-limiting groove is used to adjust the amount of light irradiated onto the second surface.

[0053] According to a third aspect of the embodiments of this application, an electronic device is provided, the electronic device comprising the semiconductor structure as described above.

[0054] The technical solutions provided by the embodiments of this application bring at least the following beneficial effects: The semiconductor structure fabrication method provided by the embodiments of this application, by forming a shallow trench isolation structure located in the substrate from the first surface of the substrate, directly forming a polysilicon resistive layer at the end of the shallow trench isolation structure near the first surface, forming a first contact hole on the active region, and forming a second contact hole on the surface of the polysilicon resistive layer away from the shallow trench isolation structure, eliminates the Dep SIN and OX processes in the original FSI loop process, simplifies the FSI loop process flow, reduces the step height difference between CT-AA and CT-Poly, and makes CT etch have sufficient process window, thereby reducing the impact on the WAT performance of semiconductor devices.

[0055] The semiconductor structure provided in this application includes: a substrate, including a first surface and a second surface opposite to each other; a shallow trench isolation structure formed from the first surface of the substrate and a deep trench isolation structure formed from the second surface of the substrate; at least two active regions located in the substrate, adjacent active regions being separated by the shallow trench isolation structure and the deep trench isolation structure; a polysilicon resistive layer formed at an end of the shallow trench isolation structure near the first surface; the polysilicon resistive layer being electrically connected to the active regions; a first contact hole formed on the surface of the active regions, and a second contact hole formed on the surface of the polysilicon resistive layer away from the shallow trench isolation structure; wherein the height difference between the height of the first contact hole and the height of the second contact hole is less than a preset height threshold, the preset height threshold being a threshold for the formation process of the first contact hole and the second contact hole to meet a preset process window. As can be seen, the semiconductor structure provided in this application directly forms a polysilicon resistive layer at the end of the shallow trench isolation structure near the first surface, removing the SIN and OX layers deposited in the original process. This reduces the step height difference between CT-AA and CT-Poly, ensuring that CT etch has sufficient process window, thereby reducing the impact on the WAT performance of the semiconductor device.

[0056] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0057] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application, and do not constitute an undue limitation of this application.

[0058] Figure 1 This is a schematic flowchart illustrating a method for forming a semi-semiconductor structure according to an exemplary embodiment.

[0059] Figure 2 This is a schematic cross-sectional view of a substrate according to an exemplary embodiment.

[0060] Figure 3 This is a top view of a zero-layer photomask layer according to an exemplary embodiment.

[0061] Figure 4 This is a top view of a reconstructed zero-layer photomask layer according to an exemplary embodiment.

[0062] Figure 5 This is a cross-sectional schematic diagram of a shallow trench isolation structure according to an exemplary embodiment.

[0063] Figure 6 This is a schematic cross-sectional structure diagram illustrating a high-density plasma deposition process and a chemical mechanical polishing process according to an exemplary embodiment.

[0064] Figure 7 This is a schematic cross-sectional structure diagram of an FSIloop process according to an exemplary embodiment.

[0065] Figure 8 This is a schematic diagram of a flipped cross-sectional structure according to an exemplary embodiment.

[0066] Figure 9 This is a cross-sectional structural schematic diagram illustrating a deep trench isolation structure according to an exemplary embodiment.

[0067] Figure 10 This is a schematic cross-sectional view of a deposition dock and a chemical mechanical polishing (CMP) completed dock grinding process, according to an exemplary embodiment.

[0068] Figure 11 This is a schematic cross-sectional view of a deposition dock and a chemical mechanical polishing (CMP) completed dock grinding process, according to an exemplary embodiment.

[0069] The following is a supplementary explanation of the reference numerals in the accompanying drawings:

[0070] 11-Substrate; 1101-First surface; 1102-Second surface; 12-Shallow trench isolation structure; 13-Isolation layer; 14-Zero layer marking pattern; 15-Main chip area; 16-First layer main chip area pattern; 17-Deep trench isolation structure pattern; 18-Cut-out area; 19-Active area; 111-Polysilicon resistor layer; 112-Nitride shielding layer; 113-Dielectric layer; 114-First contact hole; 115-Second contact hole; 116-First metal layer; 117-Second metal layer; 118-Carrier wafer; 119-Deep trench isolation structure; 120-Optical isolation material; 121-Aluminum layer. Detailed Implementation

[0071] The following provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and configurations are described below in a simplified manner. Of course, these elements and configurations are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances throughout this application. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0072] Additionally, spatial relative terms, such as “below,” “under,” “lower part,” “above,” “upper part,” “front,” “back,” “above,” and similar terms, may be used in this application for ease of description to describe the relationship between one element or feature as illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures.

[0073] As described in the background section, the step height difference between CT-AA and CT-Poly formed using related technologies is too large, and their performance urgently needs improvement. This paper will now illustrate and analyze a method for forming a semiconductor structure.

[0074] Figure 1 This is a schematic flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment. Please refer to... Figure 1 The method for forming the semiconductor structure may include:

[0075] S101. Provide a substrate; the substrate includes opposing first and second surfaces.

[0076] Figure 2This is a schematic cross-sectional view of a substrate according to an exemplary embodiment, such as... Figure 2 As shown, the substrate 11 has a first surface 1101 and a second surface 1102 opposite to the first surface 1101. The first surface 1101 can be considered as the front side, and the second surface 1102 can be considered as the back side. In one embodiment, in a front side illumination (FSI) loop, the first surface 1101 is the surface that receives light, i.e., the light-receiving surface. In another embodiment, in a BSI (Browser-Induced Illumination) process, the second surface 1102 is the surface that receives light, i.e., the light-receiving surface.

[0077] Optionally, the material of the substrate 11 may include, but is not limited to: silicon, materials comprising silicon, III-V compound semiconductor materials such as gallium arsenide (GaAs), silicon on insulator (SOI), germanium on insulator (GOI), or another type of semiconductor material capable of generating charge from photons of incident light. Among these, the multi-element semiconductor materials composed of III-V elements include indium phosphide (InP), gallium arsenide (GaAs), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), indium gallium arsenide (InGaAs), or indium gallium arsenide phosphide (InGaAsP).

[0078] Optionally, at least two photodiodes (not shown) are formed in the substrate 11. In the BSI process, these at least two photodiodes are adapted for light irradiation at the second surface, i.e., for converting photons incident from the second surface 1102 onto the substrate into electrical signals. For example, the photodiode can be a single-photon avalanche diode.

[0079] Optionally, at least two photodiodes can be arranged in an array within the substrate 11. Specifically, forming a single-photon avalanche diode can be achieved by ion implantation into a region of the substrate 11 where the single-photon avalanche diode is intended to be formed, creating a doped region with a doping type opposite to that of the substrate 11. This doped region, together with the substrate 11, constitutes a single-photon avalanche diode. For example, an N-type doped region can be formed in a P-type semiconductor substrate, and this N-type doped region, together with the P-type substrate, constitutes a single-photon avalanche diode.

[0080] S103. A shallow trench isolation structure is formed from the first surface of the substrate and located within the substrate.

[0081] In this embodiment, at least two shallow trench isolation (STI) structures can be formed from the first surface 1101 of the substrate 11, i.e., from the front side of the substrate 11, within the substrate 11. Specifically, the shallow trench isolation structure 12 is formed on the side of the pixel region of the substrate 11, and it is used to provide an isolation structure for SPADs, for example, reducing optical crosstalk between adjacent SPADs forming semiconductor structures. Furthermore, the shallow trench isolation structure 12 can be formed between adjacent pixel regions of the substrate 11.

[0082] In some embodiments, the STI structure may include a reflective material such that the STI structure blocks light from adjacent pixel areas of the semiconductor structure and / or directs light in the pixel areas back to the SPAD. In some implementations, the reflective material may be a stack of reflective metals or a multilayer oxide structure with different refractive indices (e.g., to form a total internal reflection structure).

[0083] It should be noted that the embodiments of this application do not limit the shape of the shallow trench isolation structure, and the shape of its cross-sectional structure may include, but is not limited to, rectangle, trapezoid, etc.

[0084] Optionally, the shallow trench isolation structure 12 can be formed in various ways in the embodiments of this application, and no specific limitation is made thereto.

[0085] In one embodiment, in step S103 above, forming a shallow trench isolation structure located within the substrate from the first surface of the substrate may include:

[0086] An isolation layer 13 is formed on the first surface 1101 of the substrate 11, and a zero-layer photomask layer is formed on the isolation layer 13. The zero-layer photomask layer contains a zero-layer marking pattern and a first-layer main chip region pattern. The first-layer main chip region pattern defines the dimensions of the shallow trench isolation structure and the positional relationship between the shallow trench isolation structure and the deep trench isolation structure.

[0087] Using the zero-layer photomask as a mask, the isolation layer 13 and a portion of the substrate 11 are etched sequentially to form the shallow trench isolation structure in the substrate 11 and to form a zero-layer mark in the dicing area.

[0088] The aforementioned process of "forming a shallow trench isolation structure located within the substrate from the first surface of the substrate" can be simply referred to as "Zero PH and ET" in the FSI loop. Here, Zero refers to the zero-layer photomask, PH is short for Photo-lithography, and ET is short for Etch.

[0089] Figure 3 This is a top view of a zero-layer photomask layer according to an exemplary embodiment. Figure 4 This is a top view illustrating a reconstructed zero-layer photomask layer according to an exemplary embodiment. (e.g.) Figure 4 As shown, the FSI loop in this embodiment of the application... Figure 3 The zero-layer photomask layer shown is retooled, except... Figure 3 In addition to the existing zero-layer marking pattern 14, a first-layer main chip area pattern 16 (zero pattern) is added to the main chip area 15. This zero pattern can be distributed around the deep trench isolation structure pattern 17 (DTI pattern) of the BSI loop. The deep trench isolation structure pattern 17 is located between the corresponding areas of two adjacent SPADs. It can be seen that this zero pattern not only defines the size of the shallow trench isolation structure 12, but also defines the positional relationship between the shallow trench isolation structure and the deep trench isolation structure: that is, two adjacent shallow trench isolation structures are distributed around the deep trench isolation structure, and the spacing between two adjacent shallow trench isolation structures is less than or equal to the width of the deep trench isolation structure.

[0090] This zero pattern ensures perfect contact between the high-density plasma (HDP) subsequently deposited in the shallow trench isolation structure (Dep) and the deep trench isolation structure (DTI) of the BSI. The zero-mark pattern exposes a zero mark for alignment on the substrate 11. This zero mark is used to ensure that each layer is aligned with the zero mark during layer stacking on the substrate 11, thereby guaranteeing that the overlay error between layers meets the requirements.

[0091] Using the zero-layer photomask as a mask, the isolation layer and a portion of the substrate 11 are etched sequentially to form the shallow trench isolation structure in the substrate 11 and a zero-layer mark in the dicing area 18. In this embodiment, in addition to the original zero-layer mark pattern 14, a zero pattern is added to the main chip area. This zero pattern can be distributed around the DTI pattern of the BSI loop. This zero pattern ensures that the HDP subsequently deposited in the shallow trench isolation structure can perfectly contact the DTI of the BSI, thereby allowing the end of the final deep trench isolation structure away from the second surface to perfectly contact the end of the shallow trench isolation structure away from the polysilicon resistor layer. This effectively isolates devices through the combined action of the deep trench isolation structure and the shallow trench isolation structure, effectively solving the problem of electrical crosstalk between devices.

[0092] The following explains the "Zero PH and ET" process:

[0093] Figure 5 This is a cross-sectional structural schematic diagram of a shallow trench isolation structure according to an exemplary embodiment, such as... Figure 5 As shown, the isolation layer 13 can be deposited on the first surface 1101 of the substrate 11 using a semiconductor processing tool (e.g., a deposition tool). Exemplarily, the isolation layer can be an oxide layer formed using a local oxidation of silicon (LOCOS) process, a thermal oxidation process, or a chemical vapor deposition process.

[0094] The embodiments of this application do not limit the formation process of the isolation layer. For example, the isolation layer 13 can be formed on the first surface 1101 by plasma-enhanced atomic layer deposition, or the isolation layer 13 can be formed on the first surface 1101 in an oxygen vapor environment. Optionally, the material of the isolation layer may include, but is not limited to, silicon oxide, oxynitride, composite oxide, etc.

[0095] In this embodiment, one or more semiconductor tools can form a shallow trench isolation structure from the first surface 1101 of the substrate 11. For example, a deposition tool can form a zero-layer photomask layer on the first surface 1101 of the substrate 11, an exposure tool can expose the zero-layer photomask layer to a radiation source to pattern the zero-layer mark pattern and the first-layer main chip area pattern in the zero-layer photomask layer, a developer tool can partially develop and remove the zero-layer photomask layer to expose the pattern, and an etching tool can sequentially etch the isolation layer 13 and a portion of the substrate 11 to form the shallow trench isolation structure 12 in the substrate 11 and form the zero-layer mark in the dicing area 18. After obtaining the shallow trench isolation structure, the inner wall of the shallow trench isolation structure 12 can be surface-oxidized, for example, by introducing oxygen into the reaction chamber, where the oxygen reacts with the single-crystal silicon on the exposed silicon substrate surface to generate a silicon oxide layer. The substrate 11, which has formed the STI structure, is then subjected to chemical mechanical polishing (CMP) to planarize the upper surface of the substrate 11.

[0096] It should be noted that the etching depth of substrate 11 is set according to actual production requirements and is not specifically limited. For example... Figure 5 The illustration shows only one shallow trench isolation structure. In actual applications, multiple shallow trench isolation structures may be distributed at certain intervals on the first surface 1101 of the substrate 11. The embodiments of this application do not limit the number and distribution of shallow trench isolation structures.

[0097] In an optional embodiment, the method for forming the above-described semiconductor structure may further include:

[0098] A reflective layer (not shown) may also be formed on the first surface 1101 of the substrate 11. This reflective layer is used to reflect light toward the SPAD during the operation of the semiconductor structure. For example, the reflective layer can reflect any incident light back toward the SPAD (e.g., acting as a mirror), thereby enhancing light absorption by the SPAD and improving the photosensitivity of the semiconductor structure. In some embodiments, the reflective layer comprises a metallic material, such as copper or another type of metallic material with reflective properties.

[0099] In some embodiments, one or more semiconductor processing tools may be used to form the reflective layer. For example, a deposition tool may form the reflective layer over a first surface 1101 of the substrate 11. Next, the deposition tool may form a photoresist layer over the reflective layer, an exposure tool may expose the photoresist layer to a radiation source to pattern the photoresist layer, a developer tool may develop and remove portions of the photoresist layer to expose the pattern, and an etching tool may etch one or more portions of the reflective layer to remove portions of the reflective layer, leaving the portion over the SPAD intact. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer after the etching tool has etched the reflective layer.

[0100] S105. At least two active regions are formed in the substrate.

[0101] In this embodiment, after obtaining multiple shallow trench isolation structures, an active area 19 (AA) can be defined based on the multiple shallow trench isolation structures. Adjacent active areas 19 are separated from each other by the formed multiple shallow isolation trenches. The aforementioned photodiode can be formed in this active area.

[0102] In some embodiments, after forming a shallow trench isolation structure located within the substrate 11 from the first surface 1101 of the substrate 11, the above method may further include:

[0103] The shallow trench isolation structure is filled with an insulating material using a high-density plasma method to obtain the filled shallow trench isolation structure.

[0104] The filled shallow trench isolation structure is subjected to chemical mechanical polishing treatment, stopping at the surface of the isolation layer away from the first surface 1101, to obtain the polished shallow trench isolation structure.

[0105] The aforementioned "high-density plasma deposition and chemical mechanical polishing" process can be simply referred to as "HD P Fill + HDP CMP Stop on OX" in FSIloop. Here, HDP stands for High Density Plasma, and Fill means to fill. The "OX" in "Stop on OX" can be the isolation layer 13, and the material of this isolation layer 13 can be, but is not limited to, silicon oxide, oxide nitride, and composite oxides.

[0106] The following explains the "HDP Fill + HDP CMP Stop on OX" process:

[0107] Figure 6 This is a schematic cross-sectional view of a structure after high-density plasma deposition and chemical mechanical polishing, according to an exemplary embodiment. Figure 6 As shown, semiconductor processing tools can form a substrate isolation layer on the surface of a shallow trench isolation structure using the HDP method, and then fill the insulating layer using the same HDP method. This application embodiment can employ various methods for HDP filling, without specific limitations. In one embodiment, the insulating material can first be filled to half the height of the shallow trench isolation structure using the HDP method, completing the first step of the HDP filling process. Then, the HDP reactive gas flow rate ratio is adjusted according to the surface roughness of the substrate 11, while the substrate 11 is rotated at a specific angle, and the insulating material is then filled to the top of the shallow trench isolation structure, completing the second step of the HDP filling process. This two-step HDP filling process significantly reduces the surface roughness after the HDP process, facilitating the smooth progress of subsequent processes.

[0108] In some implementations, to reduce damage to the active region caused by the HDP method, the active region can be divided into sparse and dense areas. The HDP method has different filling capabilities for these two areas. For sparse areas, protective strips can be added to both sides of the active region, adjusting the distance between adjacent protective strips and their respective protected active regions. This ensures that the spacing between adjacent protective strips meets the HDP method's filling capability for the shallow trench isolation structure between active regions in the dense areas. Specifically, sparse areas are regions with larger distances between active regions, while dense areas are regions with smaller distances between active regions.

[0109] After the HDP Fill process is completed, the filled insulation can be planarized by CMP until the isolation layer 13 is exposed. In some embodiments, to avoid damage to the isolation layer 13 and the substrate 11 by CMP, a protective layer (not shown) can be deposited on the isolation layer 13 in advance. This protective layer can be a double-layer structure with a hard upper layer and a soft lower layer. When CMP is performed on the HDP structure, CMP stops when it encounters the harder upper protective layer, while the softer lower protective layer can protect the isolation layer 13 and the substrate 11. Then, the barrier layer is removed by etching, thereby avoiding the adverse effects of CMP on the isolation layer 13 and the substrate 11, and ensuring the flatness of the ends of the shallow trench isolation structure.

[0110] This embodiment utilizes an HDP Fill + HDP CMP Stop on OX process. On one hand, HDP Fill forms a uniform insulator within the trench isolation structure, effectively isolating devices and thus effectively solving the problem of electrical crosstalk between devices. On the other hand, the HDP CMP Stop on OX process ensures the flatness of the ends of the shallow trench isolation structure and the isolation layer 13, thereby enabling the fabrication of a high-quality semiconductor structure. Figure 6 As shown, the shallow trench isolation structure prepared by the HDP Fill+HDP CMP Stopon OX process is uniformly filled with insulating material, and the ends of the shallow trench isolation structure and the OX layer have high flatness.

[0111] S107. A polysilicon resistive layer is formed at the end of the shallow trench isolation structure near the first surface; the polysilicon resistive layer is electrically connected to the active region.

[0112] In this embodiment, the FSI loop process can be simplified by removing the Dep SIN and OX processes from the original FSI loop process, and directly forming a polysilicon resistive layer 111 at the end of the shallow trench isolation structure 12 near the first surface 1101. In the FSI loop process, the "end of the shallow trench isolation structure near the first surface 1101" can refer to the top of the shallow trench isolation structure.

[0113] For example, the polysilicon resistive layer 111 may refer to a poly resistive layer, which can be used as a quenching resistor, a type of resistor unique to CMOS. The polysilicon resistive layer 111 may be electrically connected to the active region, specifically to the photodiode in the active region.

[0114] Optionally, the top view shape of the polycrystalline silicon resistive layer can be a conventional shape such as a strip, an S-shape, or a spiral. In this embodiment, the top view shape of the polycrystalline silicon resistive layer is a strip.

[0115] The process for forming the polysilicon resistive layer described above can be simply referred to as "Poly Dep". In this application embodiment, the polysilicon resistive layer 111 can be formed in various ways at the end of the shallow trench isolation structure 12 near the first surface 1101, and no specific limitation is made here.

[0116] In one implementation, the above Poly Dep can be:

[0117] Figure 7 This is a schematic cross-sectional structure diagram obtained by an FSI loop process according to an exemplary embodiment, such as... Figure 7 As shown, an isolation layer 13 can be formed on the first surface 1101 of the substrate 11 using semiconductor tools. A polysilicon thin film is formed on the surface of the isolation layer 13 away from the first surface 1101 (including the end of the shallow trench isolation structure near the first surface 1101), and the polysilicon thin film is ion-doped. The polysilicon thin film is etched to form a strip-shaped polysilicon resistor layer 111. A nitride shielding layer 112 (e.g., the nitride shielding layer is one or more of silicon oxide, silicon nitride, and silicon oxynitride) is formed on the surface of the polysilicon resistor layer 111 away from the isolation layer 13 and on the surface of the isolation layer 13 away from the first surface 1101. The nitride shielding layer is used to protect the surface of the polysilicon resistor layer 111 so that undesirable metal silicides do not form on the surface of the covered polysilicon resistor layer 111. A dielectric layer 113 (e.g., an OX layer) is formed on the surface of the nitride shielding layer away from the polysilicon resistor layer 111. A conductive plug is formed within the dielectric layer 113, and the polysilicon resistor layer 111 is connected to other circuits, such as electrically connected to a single-photon avalanche diode, using the conductive plug.

[0118] For example, the process of forming the polycrystalline silicon thin film may include: forming a polycrystalline silicon thin film on the surface of the isolation layer 13 away from the first surface 1101 (including the end of the shallow trench isolation structure near the first surface 1101) using a low-pressure chemical vapor deposition (LPCVD) process, wherein the polycrystalline silicon thin film is doped with N-type or P-type impurity ions, wherein the N-type impurity ions are one or more of boron, gallium, and indium, and the P-type impurity ions are one or more of phosphorus, arsenic, and antimony.

[0119] Exemplarily, the specific process for forming the polysilicon resistor may include: forming a photoresist layer (not shown) on the surface of the polysilicon thin film, and exposing and developing the photoresist layer to form a patterned photoresist layer; using the patterned photoresist layer as a mask, etching the polysilicon thin film to form a polysilicon resistor layer 111 at the end of the shallow trench isolation structure 12 near the first surface 1101. In this embodiment, the polysilicon resistor layer 111 is completely located on the surface of the isolation layer 13, so that the polysilicon resistor layer is electrically isolated from the substrate 11 and a short circuit will not occur.

[0120] In another embodiment, if there are at least two shallow trench isolation structures, then the above Poly Dep can be: depositing the polysilicon resistive layer on the end of the target shallow trench isolation structure near the first surface; the target shallow trench isolation structure is two adjacent shallow trench isolation structures after polishing.

[0121] like Figure 7 As shown, the polysilicon resistive layer 111 is directly deposited on the top of two adjacent polished shallow trench isolation structures 12 (i.e., the end near the first surface 1101), eliminating the Dep SIN and OX processes in the original FSI loop process, simplifying the FSI loop process flow, reducing the step height difference h between CT-AA and CT-Poly, and ensuring that CT etch has sufficient process window, thereby reducing the impact on the WAT performance of semiconductor devices.

[0122] This application does not limit the relationship between the size of the polysilicon resistive layer and the distance between two adjacent shallow trench isolation structures. In some embodiments, the length of the polysilicon resistive layer is greater than or equal to the distance between two adjacent shallow trench isolation structures. In other embodiments, the length of the polysilicon resistive layer may be less than the distance between two adjacent shallow trench isolation structures.

[0123] S109. A first contact hole is formed on the active region, and a second contact hole is formed on the surface of the polysilicon resistive layer away from the shallow trench isolation structure; wherein the height difference between the height of the first contact hole and the height of the second contact hole is less than a preset height threshold, the preset height threshold being a threshold that allows the formation process of the first contact hole and the second contact hole to meet a preset process window.

[0124] In this embodiment, after obtaining the polycrystalline silicon resistor layer, other front-illuminated processes (FSI process), fused bonding processes (FB loop), flipping processes, etc., can be performed.

[0125] Optionally, the other FSI process may include, but is not limited to: a process of forming a nitride shielding layer 112 on the surface of the polysilicon resistive layer 111 away from the isolation layer 13 and on the surface of the isolation layer 13 away from the first surface 1101; a process of forming a dielectric layer 113 on the surface of the nitride shielding layer 112 away from the polysilicon resistive layer 111; a process of forming a first contact hole 114 on the active region 19, and a process of forming a second contact hole 115 on the surface of the polysilicon resistive layer 111 away from the shallow trench isolation structure 12; and a process of forming a metal stack, etc.

[0126] The embodiments of this application can employ various methods to form the first contact hole 114 and the second contact hole 115, without specific limitations. In one embodiment, the process of forming the first contact hole 114 on the active region 19 may include: depositing a photoresist layer on the surface of the dielectric layer 113 away from the nitride masking layer 112 using a semiconductor tool; exposing and developing the photoresist layer to define the position of the first contact hole 114; and then using the photoresist layer as a mask, sequentially etching the underlying dielectric layer 113, nitride masking layer 112, and isolation layer 13 until etching stops at the upper surface of the active region 19, thus obtaining the first contact hole 114. For example, the cross-sectional shape of the first contact hole 114 may be rectangular or inverted trapezoidal, without specific limitations. In one embodiment, the process of forming a second contact hole 115 on the surface of the polysilicon resistive layer 111 away from the shallow trench isolation structure 12 may include: depositing a photoresist layer on the surface of the dielectric layer 113 away from the nitride masking layer 112 using a semiconductor tool; exposing and developing the photoresist layer to define the position of the second contact hole 115; and then using the photoresist layer as a mask to etch the underlying dielectric layer 113 and nitride masking layer 112 repeatedly until etching reaches the upper surface of the polysilicon resistive layer 111 (i.e., the surface away from the shallow trench isolation structure 12), thereby obtaining the second contact hole 115. For example, the cross-sectional shape of the second contact hole 115 may be rectangular or inverted trapezoidal, without specific limitation.

[0127] The height difference between the first contact hole 114 and the second contact hole 115 is less than a preset height threshold, which is a threshold value that ensures the formation process of the first contact hole 114 and the second contact hole 115 meets a preset process window. The height difference between the first contact hole 114 and the second contact hole 115 can be understood as the height between the upper surface of the polysilicon resistive layer 111 (i.e., the surface away from the shallow trench isolation structure 12) and the upper surface of the active region 19 (i.e., the surface close to the first surface 1101).

[0128] In the photolithography process, the process window refers to a window used to control the size of a semiconductor wafer, limiting the range of dimensions that can be controlled during the process. To ensure the quality and performance of semiconductor wafers, a suitable process window needs to be maintained. When the process window becomes too small, the controllability of the photolithography process will be limited, potentially leading to dimensional deviations and semiconductor wafer quality problems.

[0129] To ensure wafer quality and performance, CT etching needs to control the loss of the polysilicon resistive layer 111 and AA within a certain range. If the height difference between the first contact hole 114 and the second contact hole 115 is large, the AA will not be etched when the CT etching reaches the polysilicon resistive layer 111. This will result in significant poly loss before the AA begins to be etched. This places high demands on the CT etching process and limits the possibility of CT etching, thus eliminating the need for a preset process window in the CT etching process. In this embodiment, the polysilicon resistive layer is deposited directly on the top of two adjacent polished shallow trench isolation structures (i.e., the end near the first surface 1101), eliminating the Dep SIN and OX processes in the original FSI loop process, simplifying the FSI loop process flow, reducing the step height difference between CT-AA and CT-Poly, and enabling CT-AA etching to be performed in a shorter time when CT etches onto the polysilicon resistive layer 111, reducing the loss of the polysilicon resistive layer 111 and AA during the CT etching process, so that the loss of the polysilicon resistive layer 111 and AA is controlled within a certain range, thereby making the CT etching process controllable, and thus ensuring that CT etch has a sufficient process window, reducing the impact on the WAT performance of semiconductor devices.

[0130] In some embodiments, the preset height threshold is proportional to the thickness of the polysilicon resistive layer 111. In an exemplary embodiment, the preset height threshold is 500 angstroms to 1000 angstroms. Since the height difference between the height of the first contact hole and the height of the second contact hole can be understood as the height between the upper surface of the polysilicon resistive layer (i.e., the surface away from the shallow trench isolation structure 12) and the upper surface of the active region (i.e., the surface near the first surface 1101), the preset height threshold is proportional to the thickness of the polysilicon resistive layer; the thicker the polysilicon resistive layer, the greater the height difference, and vice versa. Since the polysilicon resistive layer is deposited directly at the end of the shallow trench near the first surface 1101, and the second contact hole is formed on the polysilicon resistive layer, the height difference is mainly related to the thickness of the polysilicon resistive layer. Therefore, setting the height threshold is proportional to the thickness of the polysilicon resistive layer, and specifically setting the preset height threshold to 500 angstroms to 1000 angstroms can improve the accuracy of determining the height threshold, so that the formation process of the first and second contact holes can well meet the preset process window, thereby reducing the impact on the WAT performance of the semiconductor device.

[0131] The processes for forming metal stacks, fused bonding (FB loop), and flipping processes in the embodiments of this application can be implemented in various ways, and no specific limitations are made here.

[0132] In one embodiment, after forming a first contact hole on the active region and a second contact hole on the surface of the polysilicon resistive layer away from the shallow trench isolation structure, the method further includes:

[0133] Metal stacks are formed at the ends of the first contact hole away from the active region and the ends of the second contact hole away from the polysilicon resistive layer.

[0134] The structure forming the metal stack is fused and bonded to the carrier wafer, and the bonded structure is then flipped.

[0135] Exemplarily, the metal stack may include a first metal layer, at least one low-k layer (i.e., a layer formed of a material having a low dielectric constant (K), such as SiOx or SixNx), a second metal layer, etc. Forming the metal stack at the ends of the first contact hole away from the active region and the second contact hole away from the polysilicon resistive layer may include: continuing as... Figure 7As shown, a semiconductor processing tool (e.g., a deposition tool) can deposit a metal material (e.g., copper) over the dielectric layer 113, the first contact hole 114, and the second contact hole 115 to form a first metal layer 116. Next, the semiconductor processing tool (deposition tool) can deposit a low-k material onto the first metal layer to form a low-k layer. Then, the semiconductor processing tool (e.g., a deposition tool) can deposit another metal material layer over the substrate (e.g., on the low-k layer) to form a second metal layer 117.

[0136] For example, fusion bonding the semiconductor structure forming a metal stack to the carrier wafer 118 may include: continuing as follows Figure 7 As shown, semiconductor processing tools can achieve bonding effects by utilizing the Si-O-Si bonds on the surface of the carrier wafer. Besides fusion bonding, a temporary bonding process can also be used to bond the semiconductor structure forming a metal stack to the carrier wafer using adhesive. The temporary bonding temperature is less than 200 degrees Celsius. Using adhesive to temporarily bond the semiconductor structure forming a metal stack to the carrier wafer avoids deformation of the semiconductor structure caused by the high temperatures during fusion bonding and annealing, thus reducing the thermal load on the semiconductor structure.

[0137] After bonding, the bonded structure can be flipped over, and the upper surface of the flipped structure becomes the second surface 1102 of the substrate 11, so that the second surface 1102 of the substrate 11 can be processed in the future. Figure 8 This is a schematic diagram of a flipped cross-sectional structure according to an exemplary embodiment, such as... Figure 8 As shown, the upper surface of the flipped structure is the second surface 1102.

[0138] Therefore, after the FSI loop and FB loop are completed, the obtained structure can be flipped to perform BSI loop, so that the photodiode can be adapted for light irradiation at the second surface 1102 without passing through the metal wiring layer, thereby reducing photon loss and improving quantum efficiency (QE).

[0139] S111. A deep trench isolation structure is formed from a second surface of the substrate within the substrate; wherein the second surface is opposite to the first surface, and the deep trench isolation structure and the shallow trench isolation structure are used to isolate adjacent active regions.

[0140] In this embodiment, a deep trench isolation structure 119 (DTI) can be formed within the substrate 11 from a second surface 1102, which is a surface on the substrate 11 opposite to the first surface 1101. This deep trench isolation structure 119 provides isolation for SPADs in the active region (e.g., reducing optical crosstalk from adjacent SPADs in the semiconductor structure). The DTI structure can be formed between a pixel region of the substrate and adjacent pixel regions (not shown). In some implementations, the DTI structure may include a reflective material such that the DTI component blocks light from adjacent pixel regions of the semiconductor structure and / or directs light from the pixel region back toward the SPAD. In some implementations, the reflective material may be a reflective metal or a multilayer oxide structure with different refractive indices (e.g., to form a total internal reflection structure).

[0141] In one embodiment, the deep trench isolation structure 119 can be formed from the upper surface of the flipped structure; wherein the upper surface of the flipped semiconductor structure is the second surface 1102. In other embodiments, the semiconductor processing tool can also form the deep trench isolation structure located within the substrate 11 from the second surface 1102 of the substrate 11 through an appropriate process without flipping, and then flip the structure after forming the deep trench isolation structure.

[0142] The process of forming the deep trench isolation structure from the upper surface of the flipped structure can be simply referred to as "DTIPH and ET", which can include:

[0143] Figure 9 This is a cross-sectional structural schematic diagram illustrating a deep trench isolation structure according to an exemplary embodiment, such as... Figure 9As shown, a photoresist layer with a deep trench isolation structure pattern is formed on the upper surface (i.e., the second surface 1102) of the flipped semiconductor structure; the dimensions of the deep trench isolation structure 119 are defined in the photoresist layer; the substrate 11 is etched in the direction of the shallow trench isolation structure using the deep trench isolation structure pattern as a mask, and etching stops when the shallow trench isolation structure 12 is etched away from the end of the polysilicon resistive layer 111, thus forming the deep trench isolation structure 119. That is, the end of the deep trench isolation structure 119 away from the second surface 1101 is in contact with the end of the shallow trench isolation structure 12 away from the polysilicon resistive layer 111. Optionally, "in contact" can mean that the deep trench isolation structure is located between two adjacent shallow trench isolation structures, and the end of the deep trench isolation structure away from the second surface is in contact with the ends of the two adjacent shallow trench isolation structures away from the polysilicon resistive layer. As one example, the end of the deep trench isolation structure 119 away from the second surface 1101 intersects with the ends of two adjacent shallow trench isolation structures 12 away from the polysilicon resistive layer 111 in the substrate 11. Alternatively, as another example, the sidewall of the end of the deep trench isolation structure 119 away from the second surface 1101 contacts the sidewall of the ends of two adjacent shallow trench isolation structures 12 away from the polysilicon resistive layer 111 in the substrate 11.

[0144] In some embodiments, a deposition tool can form a photoresist layer on a second surface 1102 of a substrate 11, the photoresist layer defining the dimensions of the deep trench isolation structure. An exposure tool can expose the photoresist layer to a radiation source to pattern the photoresist layer. A developer tool can develop and remove several portions of the photoresist layer to expose the pattern, and an etching tool can etch the substrate 11 from the second surface 1102 toward the direction of the shallow trench isolation structure to a predetermined depth, stopping when etching reaches the end of the shallow trench isolation structure 12 away from the polysilicon resistive layer 111, such that the end of the deep trench isolation structure 119 away from the second surface 1102 contacts the end of the shallow trench isolation structure 12 away from the polysilicon resistive layer 111, obtaining one or more portions to form one or more DTIs. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer after the etching tool etches the substrate 11.

[0145] Therefore, DTI can be obtained by performing DTIPH and ET on the flipped structure to provide isolation for SPADs, reducing optical crosstalk from adjacent SPADs in the semiconductor structure, thereby reducing electrical crosstalk between devices; in addition, the deep trench isolation structure and the shallow trench isolation structure have end contacts away from the polysilicon resistive layer, which can effectively isolate devices through the combined action of the deep trench isolation structure and the shallow trench isolation structure, effectively solving the problem of electrical crosstalk between devices.

[0146] In practical applications, BSI SIPM sensors typically apply a high voltage between the poly and the DTI to meet design requirements. To ensure the poly and DTI can withstand this high voltage, the substrate 11 can be prevented from being etched through during the DTIPH and ET processes, meaning a certain thickness of Si is retained at the bottom of the DTI. Furthermore, retaining a certain thickness of Si at the bottom of the DTI also ensures electrical isolation between the poly and DTI at high potentials. In some embodiments, continuing as... Figure 9 As shown, the distance between the end of the deep trench isolation structure 119 away from the second surface 1102 and the first surface 1101 (e.g.) Figure 9 (As indicated by the middle arrow) is greater than 0. The end of the deep trench isolation structure away from the second surface 1102 can be understood as the bottom of the DTI.

[0147] It should be noted that the embodiments of this application do not limit the distance between the end of the deep trench isolation structure 119 away from the second surface 1102 and the first surface 1101, which can be set according to actual business needs. Taking Si as an example, the intrinsic Si thickness of about 100nm can withstand 3V voltage. Based on this characteristic and combined with the actual high voltage resistance requirements, the thickness of Si retained at the bottom of the DTI can be set. In some embodiments, the distance between the end of the deep trench isolation structure 119 away from the second surface 1102 and the first surface 1101 is 0.5um to 2um. That is, a silicon thickness of 0.5um to 2um is retained at the bottom of the DTI. This 0.5um to 2um silicon allows the poly and the DTI to withstand high voltage and can better achieve electrical isolation between the poly and the DTI at high potentials. Therefore, when an operating voltage is applied between Poly and DTI, the voltage can be blocked by a certain thickness of silicon retained between the deep trench isolation structure and the first surface of the substrate, thereby improving the electrical isolation between Poly and DTI. This ensures that the thin film between Poly and DTI will not be broken down under high voltage, solving the leakage problem of the semiconductor device at high operating voltage (e.g., operating voltage exceeding 40V). This enables the semiconductor device to meet the higher gain performance requirements of automotive 3D distance imaging systems for image sensors.

[0148] In some embodiments, in order to ensure that the HDP deposited in the shallow trench isolation structure can make perfect contact with the DTI of the BSI, so that the end of the final deep trench isolation structure away from the second surface can make perfect contact with the end of the shallow trench isolation structure away from the polysilicon resistive layer, thereby effectively isolating the device through the combined action of the deep trench isolation structure and the shallow trench isolation structure and effectively solving the problem of electrical crosstalk between devices, at least two deep trench isolation structures can be set. The at least two deep trench isolation structures are set in the surrounding area of ​​the DTI, and the distance between two adjacent deep trench isolation structures is less than or equal to the width of the deep trench isolation structure.

[0149] In an optional embodiment, after DTIPH and ET, W dep and W CMP processes can also be performed. Here, W refers to the metal dock, W dep refers to the deposited dock, and W CMP refers to dock grinding using chemical mechanical polishing. The W dep and W CMP processes are described below: Figure 10 This is a schematic cross-sectional view of a deposition dock and a chemical mechanical polishing (CMP) completed dock grinding process, according to an exemplary embodiment. Figure 10 As shown, the deposition tool can use chemical vapor deposition to fill one or more DTIs with optical isolation material 120 (e.g., W), and the planarization tool can use W CMP technology to remove excess material. Depositing W in the DTI can shield the photomask and prevent optical crosstalk problems between adjacent SPADs. In other embodiments, the optical isolation material can also be an oxide material such as silicon oxide (SiOx) or another type of dielectric material.

[0150] In another alternative embodiment, AL dep and other BSI processes may be performed after the W dep and W CMP processes. Exemplarily, AL dep may include: Figure 11 This is a schematic cross-sectional view of a deposition dock and a chemical mechanical polishing (CMP) completed dock grinding process, according to an exemplary embodiment. Figure 11 As shown, aluminum is filled onto the metal W deposited in the isolation trench to form an aluminum layer 121; the aluminum layer 121 is exposed and patterned to form an aluminum pad; a through-silicon via is formed on the second surface 1102 to expose the tungsten metal layer; and the metal W is connected to the aluminum pad.

[0151] Exemplary examples show that other BSI processes may include forming a metal grid structure on the second surface 1102, forming a high-k dielectric layer (HK layer), forming a filter on the second surface 1102, etc. It should be noted that the embodiments of this application do not limit the specific process of other BSI processes. In some implementations, the filter (e.g., a film or thin film) filters out incident light, thereby allowing incident light of a specific wavelength to pass through to the SPAD (and blocking other wavelengths). In some implementations, the thickness of the filter may be designed to control (e.g., extend) the integration time of the SPAD (e.g., total integration time). In some implementations, the filter may contain, for example, titanium or titanium nitride. In some implementations, the thickness of the filter may vary between SPADs in a semiconductor structure. In some implementations, semiconductor processing tools (e.g., deposition tools) may use chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another type of deposition technique to deposit the filter.

[0152] In other embodiments, to increase the light intake of the semiconductor structure and thus improve the photodetector efficiency (PDE), the method for forming the semiconductor structure may further include: forming a light-limiting groove (not shown) on the second surface 1102; wherein the light-limiting groove is used to adjust the amount of light irradiating the second surface 1102. The specific forming process of the light-limiting groove may be as follows: a deposition tool can form a photoresist layer on the second surface 1102 of the substrate 11, the photoresist layer defining the size of the light-limiting groove. An exposure tool can expose the photoresist layer to a radiation source to pattern the photoresist layer; a developer tool can develop and remove several portions of the photoresist layer to expose the pattern; and an etching tool can etch the substrate 11 from the second surface 1102 to obtain the light-limiting groove. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer after the etching tool etches the substrate 11.

[0153] It should be noted that, in order to prevent W from filling into the light-limiting groove and affecting PDE, the forming process of the light-limiting groove can be carried out before forming the DFI, when depositing W into the DTI. An oxide layer can be pre-attached to the bottom and sidewalls of the light-limiting groove and the DTI.

[0154] The embodiments of this application do not limit the shape and size of the light-limiting groove. The cross-sectional shape of the light-limiting groove can be an inverted triangle, an ellipse, an inverted trapezoid, etc.

[0155] The following is a general description of the method for forming the above semiconductor structure:

[0156] 1) Provide substrate 11.

[0157] 2) Retooling Zero Mask: In addition to the original zero mark, a zero pattern is added to the main chip area. These patterns are distributed around the BSI loop DTI pattern.

[0158] 3) Zero PH&ET: An isolation layer 13 is formed on the first surface 1101 of the substrate 11, and a zero-layer photomask layer is formed on the isolation layer; the isolation layer and a portion of the substrate 11 are sequentially etched using the zero-layer photomask layer as a mask to form the shallow trench isolation structure 12 in the substrate 11 and to form a zero-layer mark in the dicing area. An active region 19 is defined according to the shallow trench isolation structure. A single-photon avalanche diode is formed in the active region.

[0159] 4) HDP Fill + HDP CMP Stop on OX: The shallow trench isolation structure is filled with an insulating material by a high-density plasma method to obtain a filled shallow trench isolation structure; the filled shallow trench isolation structure is subjected to chemical mechanical polishing treatment, stopping at the surface of the isolation layer away from the first surface 1101, to obtain a polished shallow trench isolation structure.

[0160] 5) Poly Dep + other FSI process + FB loop: Remove the original FSI loop Dep SIN + OX and directly use Dep Poly to simplify the FSI loop process; form a first contact hole 114 on the active region 19 and a second contact hole 115 on the surface of the polysilicon resistive layer 111 away from the shallow trench isolation structure 12; form a metal stack at the end of the first contact hole 114 away from the active region 19 and the end of the second contact hole 115 away from the polysilicon resistive layer 111; fused and bond the structure forming the metal stack to the carrier wafer 118.

[0161] 6) Flip: Flip the bonded structure.

[0162] 7) DTIPH and ET: The deep trench isolation structure 119 is formed from the upper surface of the flipped structure; wherein the upper surface of the flipped semiconductor structure is the second surface 1102.

[0163] 8) W dep and W CMP: One or more DTIs are filled with optically isolated material (e.g., W) using chemical vapor deposition, and excess material can be removed using W CMP technology.

[0164] 9) AL dep and other BSI process: Aluminum is filled onto the deposited metal W in the isolation trench to form an aluminum layer; the aluminum layer is exposed and patterned to form aluminum pads; through-silicon vias are formed on the second surface 1102 to expose the tungsten metal layer; the metal W is connected to the aluminum pads. A metal grid structure and a high-k dielectric layer (HK layer) are formed on the first surface 1101, and a filter is formed on the second surface 1102, etc.

[0165] This application embodiment also provides a semiconductor structure, which may include:

[0166] A substrate includes opposing first and second surfaces; a shallow trench isolation structure is formed from the first surface of the substrate and a deep trench isolation structure is formed from the second surface of the substrate.

[0167] At least two active regions are located in the substrate, and adjacent active regions are separated by the shallow trench isolation structure and the deep trench isolation structure.

[0168] A polysilicon resistive layer is formed at the end of the shallow trench isolation structure near the first surface; the polysilicon resistive layer is electrically connected to the active region.

[0169] A first contact hole is formed on the surface of the active region, and a second contact hole is formed on the surface of the polysilicon resistive layer away from the shallow trench isolation structure; wherein the height difference between the height of the first contact hole and the height of the second contact hole is less than a preset height threshold, the preset height threshold being a threshold that allows the formation process of the first contact hole and the second contact hole to meet a preset process window.

[0170] like Figure 11 As shown, after flipping, the second surface 1102 of the substrate 11 is on top, while the first surface 1101 is on the bottom. In the BSI process, the second surface 1102 is the light-receiving surface.

[0171] Optionally, the end of the shallow trench isolation structure 12 near the first surface 1101 can be the bottom of the shallow trench isolation structure 12 after flipping, that is, the polysilicon resistor layer 111 is located at the bottom of the shallow trench isolation structure after flipping.

[0172] Optionally, the surface of the active region 19 can be below the active region after flipping, that is, the first contact hole 114 is located below the active region 19 after flipping.

[0173] Optionally, the polysilicon resistive layer 111 is located away from the surface of the shallow trench isolation structure 12. After flipping, it can be the lower surface of the polysilicon resistive layer 111, that is, after flipping, the second contact hole 115 is located on the lower surface of the polysilicon resistive layer 111.

[0174] The semiconductor structure provided in this application provides a shallow trench isolation structure formed from the first surface of the substrate, a polysilicon resistive layer formed directly at the end of the shallow trench isolation structure near the first surface, a first contact hole formed on the active region, and a second contact hole formed on the surface of the polysilicon resistive layer away from the shallow trench isolation structure. This simplifies the FSI loop process, removes the original silicon carbide and oxide layers deposited on the polysilicon in the formed semiconductor structure, reduces the step height difference between CT-AA and CT-Poly, and ensures that CT etch has sufficient process window, thereby reducing the impact on the WAT performance of the semiconductor device.

[0175] In some embodiments, the preset height threshold is proportional to the thickness of the polysilicon resistive layer 111. In some embodiments, the preset height threshold is 500 angstroms to 1000 angstroms. Since the height difference between the height of the first contact hole and the height of the second contact hole can be understood as the height between the upper surface of the polysilicon resistor near the second contact hole and the upper surface of the active region near the first contact hole, the preset height threshold is proportional to the thickness of the polysilicon resistive layer. The thicker the polysilicon resistive layer, the greater the height difference, and vice versa. Since the polysilicon resistive layer is deposited directly at the end of the shallow trench near the first surface, and the second contact hole is formed on the polysilicon resistive layer, the height difference is mainly related to the thickness of the polysilicon resistive layer. Therefore, setting the height threshold to be proportional to the thickness of the polysilicon resistive layer, and specifically setting the preset height threshold to 500 angstroms to 1000 angstroms, can improve the accuracy of determining the height threshold, thereby ensuring that the formation process of the first and second contact holes can well meet the preset process window, and thus reduce the impact on the WAT performance of the semiconductor device.

[0176] In some embodiments, there are at least two shallow trench isolation structures, and the polysilicon resistive layer 111 is formed on the ends of two adjacent shallow trench isolation structures 12 near the first surface 1101.

[0177] In some embodiments, the distance between the end of the deep trench isolation structure 119 away from the second surface 1102 and the first surface 1101 is greater than 0. Because a certain thickness of Si can be retained at the bottom of the DTI, the poly and DTI can withstand high voltage, preventing the substrate 11 from being etched through during DTIPH and ET processes. Furthermore, retaining a certain thickness of Si at the bottom of the DTI also ensures electrical isolation between the poly and DTI at high potentials.

[0178] In some embodiments, the distance between the end of the deep trench isolation structure 119 away from the second surface 1102 and the first surface 1101 is 0.5µm to 2µm. That is, a silicon layer with a thickness of 0.5µm to 2µm is retained at the bottom of the DTI. This 0.5µm to 2µm silicon layer enables the poly and DTI to withstand high voltage and can better achieve electrical isolation between the poly and DTI at high potentials.

[0179] In some embodiments, the deep trench isolation structure 119 extends to the shallow trench isolation structure 12, and the end of the deep trench isolation structure 119 away from the second surface 1102 contacts the end of the shallow trench isolation structure 12 away from the polysilicon resistive layer 111. After flipping, the "end of the deep trench isolation structure away from the second surface" is the bottom of the DTI, and the "end of the shallow trench isolation structure away from the polysilicon resistive layer" is the top of the shallow trench isolation structure, that is, the bottom of the DTI extends to the shallow trench isolation structure, and the bottom of the DTI contacts the top of the shallow trench isolation structure. Thus, the devices can be effectively isolated through the combined action of the deep trench isolation structure and the shallow trench isolation structure, effectively solving the problem of electrical crosstalk between devices.

[0180] In some embodiments, at least two shallow trench isolation structures 12 are distributed around the periphery of the deep trench isolation structure 119. In some embodiments, the deep trench isolation structure is located between two adjacent shallow trench isolation structures, with the end of the deep trench isolation structure away from the second surface contacting the ends of the two adjacent shallow trench isolation structures away from the polysilicon resistive layer, and the distance between two adjacent shallow trench isolation structures is less than or equal to the width of the deep trench isolation structure. This allows the HDP deposited in the shallow trench isolation structure to make perfect contact with the DTI of the BSI, resulting in the end of the final deep trench isolation structure away from the second surface making perfect contact with the end of the shallow trench isolation structure away from the polysilicon resistive layer. This effectively isolates devices through the combined action of the deep trench isolation structure and the shallow trench isolation structure, effectively solving the problem of electrical crosstalk between devices.

[0181] In some embodiments, the semiconductor structure further includes a light-limiting groove located on the second surface 1102, the light-limiting groove being used to adjust the amount of light irradiating the second surface 1102. In some embodiments, the light-limiting groove has an inverted triangular structure. By providing a light-limiting groove, the amount of light entering the semiconductor structure can be increased, thereby improving the photodetectivity (PDE).

[0182] In some embodiments, the semiconductor structure may further include: a nitride shielding layer 112 (e.g., the nitride shielding layer is one or more of silicon oxide, silicon nitride, and silicon oxynitride) located on the surface of the polysilicon resistive layer and the surface of the insulating layer away from the first surface, the nitride shielding layer protecting the surface of the polysilicon resistive layer so that undesirable metal silicides do not form on the covered polysilicon resistive surface; and a dielectric layer 113 (e.g., an OX layer) located on the surface of the nitride shielding layer away from the polysilicon resistive layer.

[0183] In some embodiments, the semiconductor structure may further include a metal stack layer located on the surface of the dielectric layer (e.g., an OX layer) away from the nitride shielding layer. The metal stack may include a first metal layer, at least one low-k layer (i.e., a material having a low dielectric constant (K), such as SiO₂). x or Si x N x The formed layer), the second metal layer, etc.

[0184] In some embodiments, the semiconductor structure may further include a carrier wafer 118 located on the surface of the metal stack layer away from the dielectric layer (e.g., the OX layer).

[0185] In some embodiments, the semiconductor structure may further include: a metal grid structure located on the second surface 1102, a high-k dielectric layer (HK layer), a filter, etc.

[0186] It should be noted that the embodiments of this semiconductor structure have the same inventive concept as the embodiments of the above-described method for forming the semiconductor structure.

[0187] In an exemplary embodiment, an electronic device is also provided, the electronic device including the semiconductor structure described above, the electronic device may include any electronic component such as MOS device, non-MOS device, other integrated circuit, electronic device, etc.

[0188] The electronic device in this embodiment can be selected from any electronic product or device such as mobile phone, PDA, tablet computer, laptop computer, game console, television, video compact disc (VCD), digital video disc (DVD), navigator, camera, camcorder, voice recorder, MP3, MP4, PlayStation Portable (PSP), etc., or any intermediate product including the above-mentioned semiconductor devices.

[0189] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0190] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes opposing first and second surfaces; A shallow trench isolation structure is formed from a first surface of the substrate and a deep trench isolation structure is formed from a second surface of the substrate. At least two active regions are located in the substrate, and adjacent active regions are separated by the shallow trench isolation structure and the deep trench isolation structure; A polysilicon resistive layer is formed at the end of the shallow trench isolation structure near the first surface; the polysilicon resistive layer is electrically connected to the active region; A first contact hole is formed on the surface of the active region, and a second contact hole is formed on the surface of the polysilicon resistive layer away from the shallow trench isolation structure; wherein, the height between the surface of the polysilicon resistive layer away from the shallow trench isolation structure and the surface of the active region near the first surface is less than a preset height threshold, the preset height threshold being a threshold that allows the formation process of the first contact hole and the second contact hole to meet a preset process window.

2. The semiconductor structure according to claim 1, characterized in that, The preset height threshold is proportional to the thickness of the polycrystalline silicon resistive layer.

3. The semiconductor structure according to claim 1, characterized in that, The preset height threshold is 500 angstroms to 1000 angstroms.

4. The semiconductor structure according to claim 1, characterized in that, The shallow trench isolation structure comprises at least two structures, and the polycrystalline silicon resistive layer is formed on the ends of two adjacent shallow trench isolation structures near the first surface.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The distance between the end of the deep trench isolation structure furthest from the second surface and the first surface is greater than 0.

6. The semiconductor structure according to claim 5, characterized in that, The distance between the end of the deep trench isolation structure furthest from the second surface and the first surface is 0.5µm to 2µm.

7. The semiconductor structure according to claim 5, characterized in that, The deep trench isolation structure extends to the shallow trench isolation structure, and the end of the deep trench isolation structure away from the second surface contacts the end of the shallow trench isolation structure away from the polysilicon resistive layer.

8. The semiconductor structure according to claim 7, characterized in that, There are at least two shallow trench isolation structures, which are distributed around the perimeter of the deep trench isolation structure.

9. The semiconductor structure according to claim 8, characterized in that, The deep trench isolation structure is located between two adjacent shallow trench isolation structures. The end of the deep trench isolation structure away from the second surface is in contact with the ends of the two adjacent shallow trench isolation structures away from the polysilicon resistor layer, and the distance between the two adjacent shallow trench isolation structures is less than or equal to the width of the deep trench isolation structure.

10. The semiconductor structure according to claim 5, characterized in that, The semiconductor structure also includes a light-limiting groove located on the second surface, the light-limiting groove being used to adjust the amount of light irradiated onto the second surface.

11. The semiconductor structure according to claim 10, characterized in that, The light-limiting groove has an inverted triangular structure.

12. A method for forming a semiconductor structure, characterized in that, The forming method includes: A substrate is provided; the substrate includes opposing first and second surfaces; A shallow trench isolation structure is formed within the substrate from the first surface of the substrate; At least two active regions are formed in the substrate; A polysilicon resistive layer is formed at the end of the shallow trench isolation structure near the first surface; the polysilicon resistive layer is electrically connected to the active region; A first contact hole is formed on the active region, and a second contact hole is formed on the surface of the polysilicon resistive layer away from the shallow trench isolation structure; wherein, the height between the surface of the polysilicon resistive layer away from the shallow trench isolation structure and the surface of the active region near the first surface is less than a preset height threshold, the preset height threshold being a threshold that allows the formation process of the first contact hole and the second contact hole to meet a preset process window. A deep trench isolation structure is formed within the substrate from the second surface of the substrate; the deep trench isolation structure and the shallow trench isolation structure are used to isolate adjacent active regions.

13. The method for forming a semiconductor structure according to claim 12, characterized in that, The method of forming a shallow trench isolation structure within the substrate from a first surface of the substrate includes: An isolation layer is formed on the first surface of the substrate, and a zero-layer photomask layer is formed on the isolation layer; a zero-layer marking pattern and a first-layer main chip region pattern are reconstructed in the zero-layer photomask layer; the first-layer main chip region pattern defines the dimensions of the shallow trench isolation structure and the positional relationship between the shallow trench isolation structure and the deep trench isolation structure. Using the zero-layer photomask as a mask, the isolation layer and a portion of the substrate are etched sequentially to form the shallow trench isolation structure in the substrate and to form a zero-layer mark in the dicing area; the end of the deep trench isolation structure away from the second surface is in contact with the end of the shallow trench isolation structure away from the polysilicon resistor layer.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, The shallow trench isolation structure comprises at least two structures, and the deep trench isolation structure is located between two adjacent shallow trench isolation structures. The end of the deep trench isolation structure away from the second surface contacts the ends of the two adjacent shallow trench isolation structures away from the polysilicon resistor layer, and the distance between two adjacent shallow trench isolation structures is less than or equal to the width of the deep trench isolation structure.

15. The method for forming a semiconductor structure according to claim 13, characterized in that, After forming the shallow trench isolation structure located within the substrate from the first surface of the substrate, the method further includes: The shallow trench isolation structure is filled with an insulating material using a high-density plasma method to obtain the filled shallow trench isolation structure. The filled shallow trench isolation structure is subjected to chemical mechanical polishing, stopping at the surface of the isolation layer away from the first surface, to obtain the polished shallow trench isolation structure.

16. The method for forming a semiconductor structure according to claim 15, characterized in that, The shallow trench isolation structure comprises at least two structures, wherein a polysilicon resistive layer is formed at the end of the shallow trench isolation structure near the first surface, including: The polysilicon resistive layer is deposited on the end of the target shallow trench isolation structure near the first surface; the target shallow trench isolation structure is two adjacent shallow trench isolation structures after polishing.

17. The method for forming a semiconductor structure according to claim 12, characterized in that, After forming a first contact hole on the active region and a second contact hole on the surface of the polysilicon resistive layer away from the shallow trench isolation structure, the method further includes: A metal stack is formed at the end of the first contact hole away from the active region and at the end of the second contact hole away from the polysilicon resistive layer; The structure forming the metal stack is fused and bonded to the carrier wafer, and the bonded structure is then flipped. The formation of a deep trench isolation structure within the substrate from the second surface of the substrate includes: The deep trench isolation structure is formed from the upper surface of the flipped structure; wherein the upper surface of the flipped semiconductor structure is the second surface.

18. The method for forming a semiconductor structure according to claim 17, characterized in that, The formation of the deep trench isolation structure from the upper surface of the flipped structure includes: A photoresist layer with a deep trench isolation structure pattern is formed on the upper surface of the flipped semiconductor structure; the dimensions of the deep trench isolation structure are defined in the photoresist layer. Using the deep trench isolation structure pattern as a mask, the substrate is etched in the direction of the shallow trench isolation structure. The etching stops when the shallow trench isolation structure is etched to the end away from the polysilicon resistor layer, thus forming the deep trench isolation structure.

19. The method for forming a semiconductor structure according to claim 12, characterized in that, The distance between the end of the deep trench isolation structure furthest from the second surface and the first surface is greater than 0.

20. The method for forming a semiconductor structure according to claim 19, characterized in that, The distance between the end of the deep trench isolation structure furthest from the second surface and the first surface is 0.5µm to 2µm.

21. The method for forming a semiconductor structure according to claim 12, characterized in that, The preset height threshold is proportional to the thickness of the polycrystalline silicon resistive layer.

22. The method for forming a semiconductor structure according to claim 21, characterized in that, The preset height threshold is 500 angstroms to 1000 angstroms.

23. The method for forming a semiconductor structure according to claim 12, characterized in that, The method further includes: A light-limiting groove is formed on the second surface; wherein the light-limiting groove is used to adjust the amount of light irradiated onto the second surface.

24. An electronic device, characterized in that, The electronic device includes a semiconductor structure as described in any one of claims 1-11.

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