Unit amplification circuit, amplifier, and reception circuit

Abstract

A unit amplification circuit, an amplifier, and a reception circuit are provided. The unit amplification circuit includes a push-pull circuit having a transistor having a gate connected to the input terminal, a symmetric circuit symmetrically connected to the push-pull circuit and configured to be turned off in a first mode of operation and turned on in a second mode of operation, and a path control circuit connected to the symmetric circuit and configured to be turned off in the first mode of operation and turned on in the second mode of operation. The path control circuit is connected to the drain of the transistor and is configured to connect the drain of the transistor and the output terminal in a first mode of operation and disconnect the drain of the transistor and the output terminal in a second mode of operation.

Description

Technical Field

[0001] Exemplary embodiments relate to a unit amplification circuit, an amplifier, and a receiving circuit. Background Art

[0002] Electronic devices that support wireless communication technologies including Wi-Fi and Bluetooth can be equipped with a radio-frequency integrated chip (RFIC). RFIC may include a transmitting circuit for transmitting RF signals and a receiving circuit for receiving RF signals. For example, the power consumption of the receiving circuit may have a significant impact on the overall power consumption of the electronic device. Therefore, a low-power design of the RFIC receiving circuit may be required to reduce the battery consumption of the electronic device and increase the day-of-usage (DOU). Summary of the invention

[0003] Example embodiments provide a unit amplification circuit, an amplifier, and a receiving circuit having improved amplification-related characteristics.

[0004] According to an example embodiment, a unit amplifier circuit includes: a push-pull circuit having a transistor having a gate connected to an input terminal; a symmetrical circuit symmetrically connected to the push-pull circuit and configured to be turned off in a first operating mode and turned on in a second operating mode; and a path control circuit connected to a drain of the transistor and configured to connect the drain of the transistor and an output terminal in the first operating mode and disconnect the drain of the transistor and the output terminal in the second operating mode.

[0005] According to an example embodiment, an amplifier includes a plurality of unit amplification circuits, each of which is configured to operate at a respective gain in a first operation mode and to operate at a different respective gain in a second operation mode. Each of the plurality of unit amplification circuits may include: a push-pull circuit having a transistor having a gate connected to an input terminal; a symmetric circuit symmetrically connected to the push-pull circuit and configured to be turned off in the first operation mode and turned on in the second operation mode; and a path control circuit connected to a drain of the transistor and configured to connect the drain of the transistor and an output terminal in the first operation mode and disconnect the drain of the transistor from the output terminal in the second operation mode.

[0006] According to an example embodiment, a receiving circuit includes: an amplifier configured to amplify a receiving signal through a plurality of unit amplification circuits, each of which is configured to operate at a respective gain in a first operation mode and operate at a different respective gain in a second operation mode; a mixer configured to convert the receiving signal into a baseband signal through a local oscillator (LO) signal; and an analog baseband filter configured to filter the baseband signal. Each of the plurality of unit amplification circuits may include: a push-pull circuit having a transistor having a gate to which the receiving signal is applied; a symmetric circuit symmetrically connected to the push-pull circuit and configured to be turned off in the first operation mode and turned on in the second operation mode; and a path control circuit connected to a drain of the transistor and configured to connect the drain of the transistor and the mixer in the first operation mode and disconnect the drain of the transistor and the mixer in the second operation mode.

[0007] According to an example embodiment, a unit amplifier circuit is configured to operate in an amplification mode and a deactivation mode. The unit amplifier circuit includes: a push-pull circuit including a first transistor and a second transistor, each of which has a gate coupled to an input terminal by alternating current (AC) and has a pair of conductive terminals; a symmetrical circuit symmetrically connected to the push-pull circuit and configured to be turned off in the amplification mode and turned on in the deactivation mode; and a path control circuit connected to the first transistor and the second transistor and configured to close a corresponding circuit path between one of the pair of conductive terminals of each of the first transistor and the second transistor and an output terminal in the amplification mode, and to open the corresponding circuit path in the deactivation mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0009] Figure 1 is a diagram illustrating a unit amplification circuit according to some example embodiments.

[0010] Figure 2A and Figure 2B According to some example embodiments Figure 1 Detailed circuit diagram of the unit amplifier circuit.

[0011] Figure 3is a diagram illustrating a unit amplification circuit in a first operation mode according to some example embodiments.

[0012] Figure 4 is a diagram illustrating a unit amplification circuit in a second operation mode according to some example embodiments.

[0013] Figure 5 is a diagram illustrating a unit amplification circuit according to some example embodiments.

[0014] Figure 6 is a diagram illustrating a unit amplifier circuit having a common source structure according to some example embodiments.

[0015] Figure 7 is a diagram illustrating a unit amplifying circuit having a cascade structure according to some example embodiments.

[0016] Figure 8 is a diagram illustrating an amplifier according to some example embodiments.

[0017] Fig. 9 is a diagram illustrating amplification stages according to some example embodiments.

[0018] Fig.10 and Fig.11 is a graph showing a comparison of a parameter S11 of amplifiers according to some example embodiments.

[0019] Fig.12 is a graph showing a comparison of IIP3 parameters of amplifiers according to some example embodiments.

[0020] Fig.13 is a table showing power consumption of an amplifier according to some example embodiments.

[0021] Fig.14 is a diagram illustrating a wireless communication device according to some example embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0023] In this document, when the first electrical component is said to be "connected" to a second electrical component or circuit node, one example of this connection is a direct electrical connection without intermediate electrical components (other than wiring or interconnects), for example, as can be shown in the corresponding schematic diagrams herein. However, in other embodiments, indirect connections with one or more intermediate components are feasible if the indirect connection does not conflict with the function of the overall circuit achieved by the direct connection.

[0024] In this document, for the sake of brevity, after a component is first introduced by a name followed by a label, the component may be referred to later by an abbreviation of the name followed by the label. For example, "first N-type transistor MN1" may be referred to later as "transistor MN1".

[0025] The unit amplifier circuit according to some example embodiments to be described below may refer to a single amplifier unit or a transconductance unit. A plurality of such single units may be connected in parallel to form a composite amplifier, such as a low noise amplifier (LNA) of a receiver. In embodiments of the inventive concept such as described below, each single unit may be individually controlled to be turned on in the amplification mode of the unit and turned off in the deactivation mode of the unit. When a lower gain is acceptable for the desired performance in the corresponding communication environment, the deactivation of one or more of the single units may be implemented separately to reduce the gain of the composite amplifier. When deactivated, the single unit may consume negligible power or substantially less power than when enabled, thereby causing the composite amplifier to consume less power. As described below, compared with conventional circuits, embodiments of the inventive concept may exhibit other performance advantages in the deactivation mode. These may include reduced power consumption, reduced feedback of high frequency components (otherwise nonlinearity may result when flowing to another unit amplifier circuit), and better matching of input impedance and output impedance with external interface components.

[0026] Figure 1 is a diagram illustrating a unit amplifying circuit 100 according to some example embodiments. The unit amplifying circuit 100 may include a push-pull circuit 110 , a symmetry circuit 120 , and a path control circuit 130 .

[0027] The push-pull circuit 110 may be configured to perform a push operation for outputting an output signal OUT at a high level or a pull operation for outputting an output signal OUT at a low level according to an input signal IN at an input terminal.

[0028] The push-pull circuit 110 may include a first N-type transistor MN1 and a first P-type transistor MP1, each transistor having a gate connected to an input terminal through a first node n1. In this article, each transistor described as having a gate is a field effect transistor (FET) that also has a pair of "conductive terminals", i.e., a source and a drain. The transistor MN1 may have a gate connected to the input terminal through a first capacitor C1, a grounded source, and a drain connected to the path control circuit 130 through a second node n2. The transistor MP1 may have a gate connected to the input terminal through a second capacitor C2, and may be supplied with a power supply voltage VDD from the source of the transistor MP1. The transistor MP1 may have a drain connected to the path control circuit 130 through a third node n3.

[0029] When the input signal IN is applied through the first node n1, the first capacitor C1 connected to the gate of the transistor MN1 may AC-couple the applied input signal IN. Similarly, when the input signal IN is applied through the first node n1, the second capacitor C2 connected to the gate of the transistor MP1 may AC-couple the applied input signal IN.

[0030] The transistor MN1 or the transistor MP1 may be turned on according to the magnitude of the input signal IN. When the transistor MN1 is turned on, the push-pull circuit 110 may perform a pull operation. When the transistor MP1 is turned on, the push-pull circuit 110 may perform a push operation.

[0031] Due to the above structure, the push-pull circuit 110 can boost transconductance based on current multiplexing. For example, the same current flows through the second node n2 and the third node n3 of the push-pull circuit 110. Therefore, the transconductance of the amplifier circuit can be twice the transconductance of each of the transistor MN1 and the transistor MP1.

[0032] The symmetrical circuit 120 can be symmetrically connected to the push-pull circuit 110 and configured to be turned off in the first operating mode and turned on in the second operating mode. Hereinafter, the first operating mode may be defined as an amplification mode in which the unit amplifier circuit 100 performs an amplification operation when it is turned on (or enabled), and the second operating mode may be defined as a deactivation mode in which the unit amplifier circuit 100 is turned off (or deactivated). In general, the unit amplifier circuit 100 may be considered to have a first gain in the first operating mode and may have a different gain (e.g., zero gain) in the second operating mode. Note that even if the unit amplifier circuit 100 can be turned off, the second operating mode can still be considered an "operation mode" because some of the transistors for preventing the output of any amplified signal as described below may be turned on, and other transistors for impedance matching may be turned on.

[0033] Symmetric circuit 120 may include a second N-type transistor MN2 and a second P-type transistor MP2. Transistor MN2 may be symmetrically connected to transistor MN1 and may be turned off in the first operating mode and turned on in the second operating mode. Similarly, transistor MP2 may be symmetrically connected to transistor MP1 and may be turned off in the first operating mode and turned on in the second operating mode.

[0034] The transistor MN2 being symmetrically connected to the transistor MN1 may mean that the drain of the transistor MN2 is connected to the second node n2 and the source of the transistor MN2 is grounded. In addition, the transistor MP2 being symmetrically connected to the transistor MP1 may mean that the drain of the transistor MP2 is connected to the third node n3 and the source of the transistor MP2 is supplied with the power supply voltage VDD.

[0035] Complementary signals may be applied to the gates of the transistor MN2 and the transistor MP2 so that the transistor MN2 and the transistor MP2 are collectively turned off in the first operating mode and turned on in the second operating mode. For example, the transistor MP2 may be applied with an enable signal EN having a high level in the first operating mode, and the transistor MN2 may be applied with an inverted enable bar signal ENB having a logic level opposite to that of the enable signal EN (e.g., a low level in the first operating mode).

[0036] When the transistor MP2 and the transistor MN2 are each turned on in the second operating mode, the symmetry circuit 120 may ground the transistor MN1 and may short the drain to the source of the transistor MP1 in an analog manner through the transistor MN2 and the transistor MP2. For example, in the second operating mode, the symmetry circuit 120 may be configured to ground the drain of the transistor MN1 to the ground GND and connect the drain of the transistor MP1 to the power supply voltage VDD (by shorting the drain to the source of the transistor MP1).

[0037] When the unit amplifier circuit is turned off, for example, in the second operating mode, the path to the output terminal may be blocked by the path control circuit 130, but the input signal IN may still be applied. When the input signal IN is applied to the transistor MN1 and the transistor MP1, a nonlinear signal component caused by the nonlinearity of the transistors may be fed back to the input terminal. For example, the nonlinear component may be fed back to the input terminal through the parasitic capacitance component of each transistor. According to some example embodiments, when the drains of the transistor MN1 and the transistor MP1 are shorted to their respective sources through the symmetry circuit 120 in an analog manner, the nonlinear signal component caused by each transistor may also leak to VDD or GND.

[0038] Therefore, the symmetry circuit 120 can prevent the inflow of the nonlinear component of the input signal IN and / or the feedback of the nonlinear component to the input terminal and the flow of the nonlinear component to another unit amplifier circuit (forming a synthetic amplifier with the unit amplifier circuit 100) that occurs when the unit amplifier circuit 100 is turned off.

[0039] The path control circuit 130 may be connected to the drain of the transistor within the push-pull circuit 110, and may be configured to connect or disconnect the path between the push-pull circuit 110 and the output terminal (e.g., the fourth node n4) where the output signal OUT is output according to the operation mode. For example, the path control circuit 130 may be connected to the second node n2 connected to the drain of the transistor MN1 and the third node n3 coupled to the drain of the transistor MP1.

[0040] The path control circuit 130 may be configured to connect the drain of the push-pull circuit 110 to the output terminal (fourth node n4) in the first operation mode and disconnect the drain of the push-pull circuit 110 from the output terminal (fourth node n4) in the second operation mode.

[0041] For example, the path control circuit 130 disconnecting the drain of the push-pull circuit 110 from the output terminal in the second operation mode may mean that the path through which unnecessary DC current flows to the output terminal is blocked when the unit amplifier circuit is turned off. Therefore, when the unit amplifier circuit is in the turned-off (OFF) state, unnecessary power consumption can be prevented by the path control circuit 130.

[0042] According to some example embodiments, the unit amplification circuit may further include a first compensation circuit 140 a and a second compensation circuit 140 b .

[0043] The first compensation circuit 140a may be connected to an input terminal (e.g., a first node n1) and configured to compensate for a change in impedance defined at the input terminal in the second operating mode. The second compensation circuit 140b may be connected to an output terminal (e.g., a fourth node n4) and configured to compensate for a change in impedance defined at the output terminal from an output impedance in the first operating mode to a different output impedance in the second operating mode.

[0044] When the unit amplifier circuit is turned off, its input impedance and output impedance may change. For example, as described above, no amplification is performed in the second operating mode (gain is zero), so that Miller capacitance may be lost or eliminated. For example, the input capacitance (and / or output capacitance) may also change according to the change of the gate-source voltage of the transistor MN1 and the transistor MP1.

[0045] Each of the first compensation circuit 140a and the second compensation circuit 140b may have a capacitor internally, which may be enabled in the second operating mode (but not enabled in the first operating mode) to compensate for changes in input impedance and output impedance that occur when the above-mentioned unit amplifier circuit is turned off.

[0046] According to the above embodiment, the unit amplifier circuit can compensate for the impedance change caused by the shutdown, which can improve the impedance matching characteristics. In addition, the unit amplifier circuit can block the DC current path of the push-pull circuit 110 to reduce unnecessary power consumption, and can block the feedback of the nonlinear component to significantly reduce linear degradation.

[0047] Figure 2A and Figure 2B According to some example embodiments Figure 1 Detailed circuit diagram of the unit amplifier circuit.

[0048] refer to Figure 2A According to some example embodiments, the path control circuit 130 may include a third N-type transistor MN3 and a third P-type transistor MP3. The transistor MN3 may have a source connected to the drain of the transistor MN1 and may be turned on in the first operation mode and turned off in the second operation mode. The transistor MP3 may have a source connected to the drain of the transistor MP1 and may be turned on in the first operation mode and turned off in the second operation mode.

[0049] For example, the transistor MN3 may have a drain connected to the fourth node n4 and a source connected to the second node n2. In addition, the transistor MP3 may have a drain connected to the fourth node n4 and a source connected to the third node n3. Therefore, when the transistor MN3 is turned off, the path between the second node n2 and the fourth node n4 may be blocked, and when the transistor MP3 is turned off, the path between the third node n3 and the fourth node n4 may be blocked.

[0050] In the first operation mode, an enable signal EN having a high level may be applied to the gate of the transistor MN3, and an inverted enable signal ENB may be applied to the gate of the transistor MP3. Therefore, the transistor MN3 and the transistor MP3 are turned off by the enable signal EN and the inverted enable signal ENB in ​​the second operation mode to prevent unnecessary DC current from flowing to the output terminal.

[0051] According to some example embodiments, the first compensation circuit 140a may include a first compensation capacitor CS1 and a first compensation transistor MN4. The capacitor CS1 may be connected to the input terminal. According to the above-described embodiments, the capacitor CS1 may compensate for a change in input impedance from a first input impedance when the unit amplifier circuit 100 is turned on to a second input impedance when the unit amplifier circuit is turned off. For example, the capacitor CS1 may have a value for compensating for a change in input capacitance caused by Miller capacitance and / or a change in gate-source voltage of a transistor of the push-pull circuit 110.

[0052] The first compensation transistor MN4 may have a drain connected to the capacitor CS1 and a source connected to ground. An inverted enable signal ENB may be applied to a gate of the transistor MN4. Therefore, according to the inverted enable signal ENB, the transistor MN4 may be turned off in the first operating mode and turned on in the second operating mode.

[0053] When the transistor MN4 is turned on in the second operation mode, the first compensation capacitor CS1 may be connected to the first node n1 and GND, and may compensate for a change in input impedance.

[0054] According to some example embodiments, the second compensation circuit 140b may include a second compensation capacitor CS2 and a second compensation transistor MN5. According to the above-described embodiments, the capacitor CS2 may be connected to the output terminal and may compensate for a change in output impedance from a first output impedance when the unit amplification circuit 100 is turned on to a second output impedance when the unit amplification circuit 100 is turned off. For example, the capacitor CS2 may have a value to compensate for a change in output capacitance caused by Miller capacitance and / or a change in gate-source voltage of a transistor of the push-pull circuit 110.

[0055] The second compensation transistor MN5 may have a drain connected to the second compensation capacitor CS2 and a source connected to ground. The transistor MN5 may have a gate supplied with an inverted enable signal ENB. Therefore, the transistor MN5 may be turned off in the first operation mode and turned on in the second operation mode.

[0056] When the transistor MN5 is turned on in the second operation mode, the capacitor CS2 may be connected to the fourth node n4 and GND, and may compensate for a change in output impedance.

[0057] refer to Figure 2B , in addition to the first compensation circuit 140a and the second compensation circuit 140b, Figure 2B The unit amplifier circuit 100 may have Figure 2A Same configuration as shown.

[0058] As for the first compensation circuit 140a, the first compensation transistor MP4 included in the first compensation circuit 140a can be implemented as a P-type transistor. For example, the transistor MP4 can have a drain connected to the first compensation capacitor CS1 and a source supplied with the power supply voltage VDD. The transistor MP4 can have a gate supplied with an enable signal EN. Therefore, according to the enable signal EN, the transistor MP4 can be turned off in the first operating mode and turned on in the second operating mode.

[0059] As for the second compensation circuit 140b, the second compensation transistor MP5 included in the second compensation circuit 140b can also be implemented as a P-type transistor. For example, the second compensation transistor MP5 can have a drain connected to the second compensation capacitor CS2 and a source supplied with the power supply voltage VDD. The transistor MP5 can have a gate supplied with an enable signal EN. Therefore, according to the enable signal EN, the transistor MP5 can be turned off in the first operating mode and turned on in the second operating mode.

[0060] For ease of description, refer to Figure 2A Draw Figure 3 and Figure 4 , but example embodiments are not limited thereto. For example, each compensation circuit may be based on Figure 2A and Figure 2B to configure.

[0061] Figure 3 is a diagram illustrating a unit amplification circuit in a first operation mode according to some example embodiments.

[0062] refer to Figure 3, in the first operation mode, the enable signal EN may be applied with a logic high level, and the inverted enable signal ENB may be applied with a logic low level. Therefore, the transistor MN3 having a gate to which a high level signal is applied and the transistor MP3 having a gate to which a low level signal is applied may be turned on. In addition, the transistor MP2 having a gate to which a high level signal is applied, the transistor MN2 having gates to which low level signals are applied, the first compensation transistor MN4, and the second compensation transistor MN5 may be turned off.

[0063] The path control circuit 130 including the transistor MN3 and the transistor MP3 that are turned on can provide an output path from the second node n2 and the third node n3 to the fourth node n4 to the push-pull circuit 110. Therefore, the push-pull circuit 110 can amplify the input signal IN applied to the input terminal in the first operation mode, and the amplified output signal OUT can be output to the fourth node n4. For example, the push-pull circuit 110 can amplify the input signal IN according to the AC-coupled input signal IN through the first capacitor C1 or the second capacitor C2 when performing a push operation or a pull operation.

[0064] Figure 4 is a diagram illustrating a unit amplification circuit in a second operation mode according to some example embodiments.

[0065] refer to Figure 4 , in the second operation mode, the enable signal EN may be applied with a logic low level, and the inverted enable signal ENB may be applied with a logic high level. Therefore, the transistor MN3 having a gate to which a low level signal is applied and the transistor MP3 having a gate to which a high level signal is applied may be turned off. In addition, the transistor MP2 having a gate to which a low level signal is applied, the transistor MN2 having gates to which high level signals are applied, the first compensation transistor MN4, and the second compensation transistor MN5 may be turned on.

[0066] The path control circuit 130 including the transistor MN3 and the transistor MP3 that are turned off can block the output path from the second node n2 and the third node n3 to the fourth node n4. Therefore, the DC current that may be generated in the push-pull circuit 110 in the second operation mode can be prevented from flowing into the output terminal, and power consumption caused by the flowing DC current can be prevented.

[0067] The symmetric circuit 120 including the transistor MN2 and the transistor MP2 that are turned on can provide an analog ground to the push-pull circuit 110. For example, the transistor MN2 can connect the drain of the transistor MN1 to the ground when the transistor MN2 is turned on, and the transistor MP2 can connect the drain of the transistor MP1 to the terminal of the power supply voltage VDD when the transistor MP2 is turned on. Therefore, a nonlinear component that may appear when the input signal IN is applied to the transistor MN1 and the transistor MP1 can flow to the ground through the symmetric circuit 120, so that the nonlinear component can be prevented from flowing into the input terminal through the parasitic component.

[0068] The first compensation circuit 140a including the first compensation transistor MN4 that is turned on can compensate for the input impedance change of the unit amplifier circuit 100 in the second operating mode (i.e., the change in input impedance that would otherwise occur from the first operating mode to the second operating mode). For example, when the transistor MN4 is turned on, the capacitor CS1 connected to the first node n1 can provide the unit amplifier circuit 100 with an impedance for input impedance compensation. In addition, when the transistor MN5 is turned on, the capacitor CS2 connected to the fourth node n4 can provide the unit amplifier circuit 100 with an impedance for output impedance compensation. For example, even when the input capacitance and / or the output capacitance decreases as the unit amplifier circuit 100 is turned off in the second operating mode, the capacitance can be compensated by the first compensation circuit 140a and the second compensation circuit 140b. Therefore, the impedance of the unit amplifier circuit 100 can be kept constant.

[0069] Figure 5 is a diagram illustrating a unit amplification circuit according to some example embodiments.

[0070] refer to Figure 5 , the unit amplifier circuit 200 according to some example embodiments may be implemented without Figure 1 and Figure 2A For example, the unit amplifier circuit 200 may include a push-pull circuit 210 , a symmetry circuit 220 , a path control circuit 230 , and a first compensation circuit 240 .

[0071] According to the example of implementing the unit amplifier circuit 200, the change in input impedance may be relatively greater than the change in output impedance. Figure 5 As shown, impedance variation compensation of the unit amplification circuit 200 can be fully achieved by adding the first compensation circuit 240 to the input terminal (first node) without an additional element for compensating for variation of output impedance at the output terminal.

[0072] Even when the first compensation circuit 240 is provided but the second compensation circuit is not provided, the unit amplifier circuit 200 can be operated in the same manner as Figure 1 or Figures 2A to 4 For example, in the first operation mode, the transistor MN2 and the transistor MP2 included in the symmetry circuit 220 can be turned off when the low-level inverted enable signal ENB and the high-level enable signal EN are applied respectively. In addition, the path control circuit 230 can be configured to connect the drains of the transistor MN1 and the transistor MP1 included in the push-pull circuit 210 to the fourth node n4 (output terminal). For example, the path control circuit 230 can be configured according to the above Figures 2A to 3 The first compensation circuit 240 may be disabled in the first operation mode.

[0073] For example, in the second operation mode, the second N-type transistor MN2 and the second P-type transistor MP2 may be turned on when a high-level inverted enable signal ENB and a low-level enable signal EN are applied respectively. Therefore, a nonlinear component that may appear in the push-pull circuit 210 due to the input signal IN may flow to the ground. The path control circuit 230 may block the path between the push-pull circuit 210 and the output terminal. The first compensation circuit 240 may operate to compensate for a capacitance change in the second operation mode in which amplification is not performed, or to compensate for a capacitance change depending on a change in the gate-source voltage of the transistor of the push-pull circuit 210. For example, the first compensation circuit 240 may be configured according to the above Figure 2A , Figure 2B and Figure 4 run.

[0074] Figure 6 is a diagram illustrating a unit amplifier circuit having a common source structure according to some example embodiments.

[0075] refer to Figure 6 , the unit amplifier circuit 300 can be implemented with a common source structure instead of using the above Figures 1 to 5 In an example embodiment, the unit amplifier circuit 300 may include fourth to eighth N-type transistors MN4 to MN8, a first compensation circuit 310a, and a second compensation circuit 310b, as shown in the figure.

[0076] The sixth N-type transistor MN6 may have a gate connected to the input terminal (fifth node n5) through the third capacitor C3, and a source connected to ground. The third capacitor C3 may be connected between the fifth node n5 and the gate of the sixth N-type transistor MN6 for AC coupling of the input signal IN. The drain of the sixth N-type transistor MN6 may be connected to the drain of the seventh N-type transistor MN7 and the source of the eighth N-type transistor MN8 through the sixth node n6.

[0077] The sixth N-type transistor MN6 may amplify the input signal IN in the first operation mode.

[0078] The transistor MN7 may be symmetrically connected to the transistor MN6. For example, the drain of the transistor MN7 may be connected to the sixth node n6, and the source of the transistor MN7 may be grounded. The inverted enable signal ENB may be applied to the gate of the transistor MN7.

[0079] The transistor MN7 can be turned off in the first operating mode and turned on in the second operating mode according to the inverted enable signal ENB applied to the gate of the transistor MN7. Therefore, in the second operating mode, the transistor MN7 can be turned on to provide "analog grounding" to the sixth N-type transistor MN6. For example, the transistor MN7 can be turned on to ground the drain of the transistor MN6. Therefore, the nonlinear component that may appear when the input signal IN is applied to the transistor MN6 can flow to the ground through the symmetrical circuit (transistor MN7), so that the nonlinear component can be prevented from flowing into the input terminal through the parasitic component.

[0080] The transistor MN8 may have a drain connected to the output terminal (seventh node n7) and a source connected to the sixth node n6. When an enable signal EN is applied to the gate of the transistor MN8, the transistor MN8 may be turned on in the first operation mode and turned off in the second operation mode.

[0081] In the first operation mode, the transistor MN8 may be turned on to allow the unit amplification circuit 300 to amplify the input signal IN through the transistor MN6. In the second operation mode, the transistor MN8 may be turned off to block a DC current path to the output terminal to reduce power consumption.

[0082] The first compensation circuit 310a may be connected to the fifth node n5 (input terminal) and may be configured to compensate for the impedance change defined at the input terminal in the second operation mode. The second compensation circuit 310b may be connected to the seventh node n7 (output terminal) and may be configured to compensate for the impedance change defined at the output terminal in the second operation mode (otherwise the change in output impedance occurring from the first operation mode to the second operation mode).

[0083] For example, the first compensation circuit 310a and the second compensation circuit 310b may be configured in the same manner as Figure 2A For example, the first compensation circuit 310a may include a first compensation capacitor CS1 connected to the fifth node n5 and a first compensation transistor MN4. As described above, the transistor MN4 may be turned on in the second operation mode to allow the capacitor CS1 to compensate for input impedance variations.

[0084] The second compensation circuit 310b may include a second compensation capacitor CS2 connected to the seventh node n7 and a second compensation transistor MN5. As described above, the transistor MN5 may be turned on in the second operation mode to allow the capacitor CS2 to compensate for output impedance variations.

[0085] Each transistor included in the first compensation circuit 310a and the second compensation circuit 310b can also be implemented as a P-type transistor, such as Figure 2B shown.

[0086] exist Figure 6 In the above-mentioned embodiment, the second compensation circuit 310b may be omitted according to the implementation scheme.

[0087] Figure 7 is a diagram showing a unit amplifier circuit having a cascade structure according to some example embodiments. Figure 6 A detailed description of the overlap.

[0088] refer to Figure 7 , the unit amplifier circuit 400 can use a cascade structure instead of Figures 1 to 5 In an example embodiment, the unit amplifier circuit 400 may include a fourth N-type transistor MN4 to an eighth N-type transistor MN8, a first compensation circuit 410a and a second compensation circuit 410b, as shown in the figure. In an example embodiment, each compensation circuit may be implemented with a P-type transistor or an N-type transistor, as shown in the figure.

[0089] replace Figure 6 The enable signal EN of the eighth N-type transistor MN8 may be connected to the gate of the eighth N-type transistor MN8. For example, the bias capacitor CB and the bias resistor RB may be connected to the eighth node n8 corresponding to the gate of the transistor MN8. The bias capacitor CB has one end connected to the eighth node n8 and the other end grounded. The bias voltage VB may be charged to the bias capacitor CB or provide a bias to the transistor MN8 through the bias resistor RB.

[0090] The transistor MN8 can be turned on or off according to the bias. For example, the transistor MN8 can be turned on in the first operation mode and turned off in the second operation mode. The transistor MN8 can be turned off in the second operation mode to block the DC current path to the output terminal.

[0091] Figure 8 is a diagram illustrating an amplifier according to some example embodiments.

[0092] refer to Figure 8The amplifier 500 may include a plurality of unit amplifier circuits UAC, each of which is configured to operate with a first gain in a first operating mode and a different second gain in a second operating mode (the second gain may be zero when the second operating mode is a deactivated mode, so that although the input signal continues to be applied, there is no output signal.) Each of the plurality of unit amplifier circuits UAC may be implemented as described above Figures 1 to 7 The unit amplifier circuits 100, 200 or 300 in the embodiment of the present invention are selected from the group consisting of: a plurality of unit amplifier circuits UAC and a plurality of unit amplifier circuits 100, 200 or 300. The plurality of unit amplifier circuits UAC may have the same transconductance gm or different transconductance gm, respectively.

[0093] Each of the plurality of unit amplifier circuits UAC can operate either in a first operating mode or in a second operating mode. The unit amplifier circuit UAC operating in the first operating mode can be turned on (or enabled) to amplify the input signal IN based on a specific gain, and the unit amplifier circuit UAC operating in the second operating mode can be turned off (or disabled). Therefore, the amplifier 500 can adjust the number of unit amplifier circuits UAC that are turned on to adjust the gain of the entire amplifier 500. Therefore, the amplifier 500 can have a wide dynamic range and can consume less power when a smaller gain is required. The wide dynamic range can be understood as the ability to appropriately amplify an input signal with a wide dynamic range and / or output an amplified signal with a wide dynamic range as needed.

[0094] For example, the amplifier 500 may turn on more unit amplification circuits UAC to increase the gain, and may turn off more unit amplification circuits UAC to decrease the gain.

[0095] In an example embodiment, the input impedance and / or output impedance of the amplifier 500 may be changed according to the unit amplification circuit UAC being turned on / off. In addition, the parameter S11 and the resonant frequency may also be changed according to the impedance change. However, when the unit amplification circuit UAC is implemented according to an example embodiment (for example, including Figures 1 to 7 By using the first compensation circuit and / or the second compensation circuit in the embodiment of the present invention, impedance changes that may otherwise occur can be compensated for, and the parameter S11 and the resonant frequency can be kept as satisfactory as possible due to the compensation.

[0096] In addition, each unit amplifier circuit UAC that is turned off may be configured to pass through a path control circuit (eg, Figures 1 to 7 The DC current of the path control circuit) is blocked to reduce power consumption.

[0097] In addition, each turned-off unit amplifier circuit UAC may ground the transistor, in an analog manner through a symmetrical circuit according to an example embodiment (eg, Figures 1 to 5 The symmetrical circuit and Figure 6 and Figure 7The sixth transistor of the present invention) performs an amplification operation to prevent the nonlinear component from flowing into the input terminal and the linearity from being reduced.

[0098] Fig. 9 is a diagram illustrating amplification stages according to some example embodiments.

[0099] refer to Fig. 9 , the amplification stage 600 may include an amplifier 610 and an impedance matching circuit 620 connected to an input terminal of the amplifier 610 .

[0100] The amplifier 610 can be configured according to the above Figure 8 The impedance matching circuit 620 connected to the input terminal of the amplifier 610 can provide impedance matching to the amplifier 610. For example, the impedance matching circuit 620 can be implemented based on an LC tank circuit (LC tank), a transformer, etc.

[0101] Separately from the impedance matching circuit 620, each unit amplification circuit according to the above-described embodiment (eg, Figure 7 ) may include a compensation circuit for compensating for impedance changes (e.g., Figures 1 to 6 Therefore, the input / output terminal impedance of the amplifier 610 that may vary when switching between modes in which the unit amplification circuit is turned on or off can also be compensated.

[0102] Fig.10 and Fig.11 is a graph showing comparison of parameter S11 (reflection coefficient) of amplifiers according to some example embodiments.

[0103] Fig.10 Parameter S11 simulation results of an exemplary conventional amplifier are shown, and an example is provided where the exemplary amplifier includes a push-pull circuit without a path control circuit, a symmetry circuit, and a compensation circuit as taught herein. Fig.11 Parameter S11 simulation results of amplifiers according to some example embodiments are shown, and an example is provided in which a frequency band of a signal required by the amplifier (hereinafter referred to as a required frequency band) is 2.4 GHz to 2.5 GHz.

[0104] When the gain changes to the maximum gain, the intermediate gain, and the minimum gain, Fig.10 The frequency band range near the desired frequency band and with parameter S11 less than -10dB is about 2.39GHz to 2.56GHz. Fig.10 The size of the frequency band in which the parameter S11 is less than -10 dB is approximately 170 MHz.

[0105] However, in Fig.11, the frequency band period in which parameter S11 is less than -10 dB near the desired frequency band is about 2.38 GHz to 2.61 GHz, and its magnitude is about 230 MHz. Therefore, it can be confirmed that when the impedance variation is compensated according to the exemplary embodiment, parameter S11 (input matching characteristics) can be improved.

[0106] Fig.12 is a graph illustrating a comparison of input-referred third-order intercept point (IIP3) parameters of amplifiers according to some example embodiments.

[0107] refer to Fig.12 In the case of a conventional amplifier including a push-pull circuit represented by a curve 701, even if some unit amplifier circuits are turned off when the gain is changed to the maximum gain, the intermediate gain, and the minimum gain, it is not possible to block the entry of nonlinear components. Therefore, it can be confirmed that the IIP3 parameter reflecting linearity deteriorates as the gain decreases.

[0108] In the case of the amplifier according to some example embodiments represented by the curve 702, the nonlinear component can be prevented from being fed back to the input terminal according to the above-mentioned embodiments (e.g., adopting a symmetrical circuit). For example, when the unit amplifier circuit (e.g., 100) is turned off, the gain of the turned-off unit amplifier circuit can be zero, and the nonlinear component that would otherwise be generated can be blocked. Therefore, it can be confirmed that the IIP3 parameter reflecting linearity is also improved.

[0109] Fig.13 is a table showing power consumption of an amplifier according to some example embodiments.

[0110] refer to Fig.13 In the case where a conventional amplifier corresponding to data 801 includes a push-pull circuit, the same power consumption (arbitrary real number I) can be maintained when the gain is changed to a maximum gain (an arbitrary real number A), an intermediate gain A / 2, and a minimum gain A / 4.

[0111] In the case of an amplifier according to some example embodiments corresponding to data 802, direct current (DC) to the output terminal can be blocked in the second operating mode according to the above-mentioned embodiments (e.g., path control circuit). Therefore, power consumption can also be reduced at the same rate as gain is reduced.

[0112] Fig.14 is a diagram illustrating a wireless communication device according to some example embodiments.

[0113] Reference Fig.14, the wireless communication device 900 may include a modem 910, a radio frequency integrated circuit (RFIC) 920, a power amplifier PA, a duplexer 930, a power modulator 940, and an antenna ANT.

[0114] The modem 910 may include a digital processing circuit 911, a first digital-to-analog converter (DAC) 912, a second DAC 913, an analog-to-digital converter (ADC) 914, and a mobile industry processor interface (MIPI). The modem 910 may process a baseband signal BB_T (including, for example, an I signal and a Q signal), the baseband signal BB_T including information to be transmitted through the digital processing circuit 911 using various communication schemes. The modem 910 may process a received baseband signal BB_R through the digital processing circuit 911 using various communication schemes.

[0115] For example, the modem 910 may process a signal to be transmitted or a received signal using a communication scheme such as orthogonal frequency division multiplexing (OFDM), orthogonal frequency division multiple access (OFDMA), wideband code division multiple access (WCDMA), high speed packet access + (HSPA +), etc. In addition, the modem 910 may process the baseband signal BB_T or BB_R using various communication schemes (e.g., various communication schemes using a technique for modulating or demodulating the amplitude and frequency of the baseband signal BB_T or BB_R).

[0116] According to some example embodiments, the modem 910 may extract the envelope of the baseband signal BB_T through the digital processing circuit 911 , and generate a digital envelope signal D_ENV based on the extracted envelope.

[0117] According to some example embodiments, the modem 910 may generate an average power signal D_REF based on an average power tracking (APT) table stored in a memory. The APT table may store preset power supply voltage information of the power amplifier PA based on the expected output power (transmit power) of the antenna ANT, and may store information of the average power signal D_REF corresponding to the preset power supply voltage of the power amplifier PA. Therefore, when the expected output power of the antenna ANT is determined, the modem 910 may generate the average power signal D_REF using the APT table, and provide the generated average power signal D_REF as a reference voltage signal to the power modulator 940.

[0118] Digital processing circuit 911 may perform various processing operations on the baseband signal in the digital domain.

[0119] For example, the digital processing circuit 911 can perform the above-mentioned average power signal generation, as well as envelope extraction operations, digital envelope signal generation, crest factor reduction (CFR), shaping function (SF), digital pre-distortion (DPD), delay compensation operations, etc.

[0120] CFR can reduce the peak-to-average power ratio (PAPR) of the communication signal (e.g., baseband signal BB_T). SF can correct the digital envelope signal D_ENV to improve the efficiency and linearity of the power amplifier PA. DPD can compensate and linearize the distortion of the power amplifier PA in the digital domain. In addition, the delay compensation operation can compensate for the delay of the digital envelope signal D_ENV or the baseband signal BB_T.

[0121] The digital processing circuit 911 can output a digital envelope signal D_ENV and a baseband signal BB_T. The digital envelope signal D_ENV can be converted into an analog envelope signal A_ENV by a first DAC 912 and then provided to a power modulator 940, and the baseband signal BB_T can be converted into a transmission signal TX by a second DAC 913 and provided to a transmission circuit TXC.

[0122] Although not shown in the drawings, the digital processing circuit 911 may include additional internal components that perform the above-mentioned operations (eg, baseband signal processing, envelope extraction, digital envelope signal generation, etc.).

[0123] The second DAC 913 and the ADC 914 may be provided in a single or multiple form. The modem 910 may use the second DAC 913 to convert the baseband signal BB_T in an analog manner to generate a transmission signal TX. In addition, the modem 910 may receive a reception signal RX (analog signal) from the RFIC 920. The modem 910 may use the ADC 914 provided therein to perform digital conversion on the reception signal RX to extract the baseband signal BB_R, which is a digital signal. For example, the reception signal RX may be a differential signal including a positive signal and a negative signal.

[0124] RFIC 920 may perform up-conversion on a transmission signal TX to generate an RF input signal RF_IN, or perform down-conversion on an RF reception signal RF_R to generate a reception signal RX. For example, RFIC 920 may include a transmission circuit TXC for up-conversion, a reception circuit RXC for down-conversion, and a local oscillator LO.

[0125] The transmission circuit TXC may include a first analog baseband filter ABF1, a first mixer MX1, and a driver amplifier 921. For example, the first analog baseband filter ABF1 may include a low-pass filter.

[0126] The first analog baseband filter ABF1 can filter the transmit signal TX received from the modem 910, and provide the filtered transmit signal TX to the first mixer MX1. For example, the first analog baseband filter ABF1 can filter the baseband signal. The first mixer MX1 ​​can use the LO signal provided by the local oscillator LO to perform an up-conversion for converting the frequency of the filtered transmit signal TX from baseband to high frequency band. As described above, the up-conversion can enable the transmit signal TX of the high frequency band to be provided to the driver amplifier 921, and the driver amplifier 921 can perform the first power amplification to the transmit signal TX of the high frequency band and provide the amplified signal as the RF input signal RF_IN to the power amplifier PA.

[0127] The power amplifier PA may receive a DC voltage or a variable power supply voltage (eg, a dynamically changing output voltage), and may perform a second power amplification on the RF input signal RF_IN based on the received DC voltage or power supply voltage to generate an RF output signal RF_OUT. The power amplifier PA may provide the generated RF output signal RF_OUT to the duplexer 930.

[0128] The receiving circuit RXC may include a second analog baseband filter ABF2, a second mixer MX2, and a low-noise amplifier (LNA) 922. For example, the second analog baseband filter ABF2 may include a low-pass filter.

[0129] The LNA 922 may amplify the RF receive signal RF_R received from the duplexer 930 and provide the amplified RF receive signal RF_R to the second mixer MX2. The second mixer MX2 may perform down-conversion for converting the frequency of the amplified RF receive signal RF_R from a high frequency band to a baseband using an LO signal provided by a local oscillator LO. For example, the second mixer MX2 may convert the amplified RF receive signal RF_R into a baseband signal using the LO signal.

[0130] The down conversion can enable the RF receive signal RF_R corresponding to the baseband signal to be provided to the second analog baseband filter ABF2, and the second analog baseband filter ABF2 can filter the RF receive signal RF_R corresponding to the baseband signal and provide the filtered signal as the transmit signal RX to the modem 910.

[0131] In an embodiment, the wireless communication device 900 may use carrier aggregation (CA) technology to transmit a transmission signal on multiple frequency bands. And, for this purpose, the wireless communication device 900 may include multiple power amplifiers PA, which respectively amplify multiple RF input signals RF_IN corresponding to multiple carriers. In this embodiment, for ease of description, an example in which a single power amplifier PA is provided will be provided.

[0132] The duplexer 930 may be connected to the antenna ANT to separate the transmission frequency and the reception frequency. For example, the duplexer 930 may separate the RF output signal RF_OUT provided from the power amplifier PA for each frequency band, and provide the separated RF output signal RF_OUT to the corresponding antenna ANT. In addition, the duplexer 930 may provide an external signal received from the antenna ANT to the LNA 922 included in the receiving circuit RXC of the RFIC 920. For example, the duplexer 930 may include a front end module with an integrated duplexer (FEMiD).

[0133] In an embodiment, the wireless communication device 900 may be provided with a switch structure for separating the transmission frequency and the reception frequency without being provided with the duplexer 930. In addition, the wireless communication device 900 may be provided with a structure including the duplexer 930 and a switch for separating the transmission frequency and the reception frequency. In this embodiment, for ease of description, an example will be provided in which the wireless communication device 900 is provided with the duplexer 930 to separate the transmission frequency and the reception frequency.

[0134] The power modulator 940 may generate a modulated output voltage having a dynamically changing level based on the analog envelope signal A_ENV and the average power signal D_REF, and may provide the output voltage as a supply voltage of the power amplifier PA.

[0135] For example, the power modulator 940 may receive an average power signal D_REF and an analog envelope signal A_ENV from the modem 910. The power modulator 940 may be driven in an ET mode or an APT mode as a tracking mode based on the received average power signal D_REF and the analog envelope signal A_ENV to generate a dynamically changing output voltage. In addition, the power modulator 940 may provide the generated output voltage as a power supply voltage to the power amplifier PA.

[0136] Generally, when a power supply voltage having a fixed level is applied to the power amplifier PA, the power efficiency of the power amplifier PA may be reduced. Therefore, the power modulator 940 may modulate the input voltage (power supplied from the battery) based on at least one of the analog envelope signal A_ENV and the average power signal D_REF, and provide the modulated voltage as the power supply voltage to the power amplifier PA to efficiently manage the power of the power amplifier PA.

[0137] The antenna ANT may transmit the frequency-separated RF output signal RF_OUT to an external entity or provide an externally received RF reception signal RF_R to the duplexer 930. For example, the antenna ANT may include an array antenna, but example embodiments are not limited thereto.

[0138] In an embodiment, the modem 910, the RFIC 920, the power amplifier PA, the duplexer 930, and the power modulator 940 may each be implemented separately as an IC, a chip, or a module. The modem 910, the RFIC 920, the power amplifier PA, the duplexer 930, and the power modulator 940 may also be mounted together on a printed circuit board (PCB). However, example embodiments are not limited thereto, and in some embodiments, at least a portion of the modem 910, the RFIC 920, the power amplifier PA, the duplexer 930, and the power modulator 940 may be implemented as a single communication chip.

[0139] At least one of the driver amplifier 921, the LNA 922, and the power amplifier PA included in the above-mentioned wireless communication device and performing an amplification operation may be implemented as Figures 1 to 8 The unit amplifier circuit and amplifier of the embodiment, or implemented as according to Fig. 9In an exemplary embodiment, the driver amplifier 921, the LNA 922, and the power amplifier PA can adjust the gain of the amplification by turning on or off a plurality of unit amplification circuits. In addition, the impedance change caused by turning on or off a plurality of unit amplification circuits can be compensated. When a plurality of unit amplification circuits are turned off, the DC path can be blocked to reduce power consumption. In addition, when a plurality of unit amplification circuits are turned off, the nonlinear signal component of the transistor can be prevented from being fed back to the input terminal (thereby preventing it from entering the input terminal of another unit amplification circuit).

[0140] For example, the LNA 922 included in the receiving circuit RXC in the RFIC 920 may have a relatively high power consumption ratio. In example embodiments, in the case where the LNA 922 according to some example embodiments is implemented to block a DC path when a unit amplifier circuit is turned off, power consumption may be more effectively reduced.

[0141] also, Fig.14 The wireless communication device 900 shown in FIG. 1 may be included in a wireless communication system using a cellular network (such as 5G or LTE), or may be included in a wireless local area network (WLAN) system or any other wireless communication system. For reference, Fig.14 The configuration of the wireless communication device 900 shown in FIG. 1 is merely an exemplary embodiment, and the exemplary embodiment is not limited thereto. The configuration of the wireless communication device may vary according to a communication protocol or a communication scheme.

[0142] As described above, according to example embodiments, a unit amplification circuit, an amplifier, and a receiving circuit having improved amplification-related characteristics may be provided.

[0143] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined in the appended claims.

Claims

1. A unit amplifier circuit, the unit amplifier circuit comprising: a push-pull circuit having a transistor having a gate connected to an input terminal; a symmetrical circuit symmetrically connected to the push-pull circuit and configured to be turned off in a first operating mode and turned on in a second operating mode; as well as A path control circuit is connected to the drain of the transistor and is configured to connect the drain of the transistor and an output terminal in the first operation mode and disconnect the drain of the transistor and the output terminal in the second operation mode.

2. The unit amplifier circuit according to claim 1, wherein: The transistor of the push-pull circuit includes at least one of the following: a first N-type transistor having a gate connected to the input terminal through a first capacitor and a source connected to ground; and A first P-type transistor having a gate connected to the input terminal through a second capacitor and a source supplied with a power supply voltage.

3. The unit amplifier circuit according to claim 2, wherein: When the transistor of the push-pull circuit includes the first N-type transistor and the first P-type transistor, the symmetrical circuit includes: a second N-type transistor symmetrically connected to the first N-type transistor and configured to be turned off in the first operation mode and turned on in the second operation mode; and a second P-type transistor, the second P-type transistor being symmetrically connected to the first P-type transistor, and is configured to be turned off in the first operating mode and turned on in the second operating mode.

4. The unit amplifier circuit according to claim 3, wherein: In the second operation mode, the symmetrical circuit is configured to connect the drain of the first N-type transistor to the ground and the drain of the first P-type transistor to the power supply voltage.

5. The unit amplifier circuit according to claim 3, wherein: The path control circuit comprises: a third N-type transistor having a source connected to the drain of the first N-type transistor and configured to be turned on in the first operation mode and turned off in the second operation mode; and A third P-type transistor has a source connected to the drain of the first P-type transistor and is configured to be turned on in the first operation mode and turned off in the second operation mode.

6. The unit amplifier circuit according to claim 1, further comprising: A first compensation circuit is connected to the input terminal and is configured to compensate for an impedance change defined at the input terminal from an input impedance in the first operation mode to an input impedance in the second operation mode.

7. The unit amplifier circuit according to claim 6, wherein: The first compensation circuit comprises: a first compensation capacitor connected to the input terminal; and A first compensation transistor has a drain connected to the first compensation capacitor and is configured to be turned off in the first operation mode and turned on in the second operation mode.

8. The unit amplifier circuit according to claim 6, further comprising: A second compensation circuit is connected to the output terminal and is configured to compensate for an impedance change defined at the output terminal from an output impedance in the first operation mode to an output impedance in the second operation mode.

9. The unit amplifier circuit according to claim 8, wherein: The second compensation circuit comprises: a second compensation capacitor connected to the output terminal; and A second compensation transistor has a drain connected to the second compensation capacitor and is configured to be turned off in the first operation mode and turned on in the second operation mode.

10. The unit amplifier circuit according to claim 1, wherein: The push-pull circuit is configured to amplify an input signal applied to the input terminal and output the amplified signal to the output terminal in the first operation mode, and to be deactivated in the second operation mode.

11. An amplifier, comprising: a plurality of unit amplifier circuits, each of the plurality of unit amplifier circuits being configured to operate at a respective gain in a first operating mode and to operate at a different respective gain in a second operating mode, in, Each of the plurality of unit amplifier circuits comprises: a push-pull circuit having a transistor having a gate connected to an input terminal; a symmetrical circuit symmetrically connected to the push-pull circuit and configured to be turned off in the first operation mode and turned on in the second operation mode; and A path control circuit is connected to the drain of the transistor and is configured to connect the drain of the transistor to an output terminal in the first operating mode and disconnect the drain of the transistor from the output terminal in the second operating mode.

12. The amplifier according to claim 11, wherein The input terminal and the output terminal are commonly connected to the plurality of unit amplification circuits.

13. The amplifier according to claim 11, wherein Each of the plurality of unit amplification circuits is configured to, in the first operation mode, amplify an input signal applied to the input terminal and output the amplified signal to the output terminal.

14. The amplifier of claim 11, further comprising: An impedance matching circuit is connected to the input terminal for impedance matching.

15. The amplifier according to claim 11, wherein The transistor of the push-pull circuit comprises: a first N-type transistor having a gate connected to the input terminal through a first capacitor and a source connected to ground; and a first P-type transistor having a gate connected to the input terminal through a second capacitor and a source supplied with a power supply voltage, and The symmetrical circuit comprises: a second N-type transistor symmetrically connected to the first N-type transistor and configured to be turned off in the first operation mode and turned on in the second operation mode; and A second P-type transistor is symmetrically connected to the first P-type transistor and is configured to be turned off in the first operation mode and turned on in the second operation mode.

16. The amplifier according to claim 15, wherein The path control circuit comprises: a third N-type transistor having a source connected to the drain of the first N-type transistor and configured to be turned on in the first operation mode and turned off in the second operation mode; and A third P-type transistor has a source connected to the drain of the first P-type transistor and is configured to be turned on in the first operation mode and turned off in the second operation mode.

17. The amplifier according to claim 11, wherein Each of the plurality of unit amplifier circuits further includes: A first compensation circuit is connected to the input terminal and is configured to compensate for impedance variation defined at the input terminal in the second operation mode.

18. A receiving circuit, the receiving circuit comprising: an amplifier configured to amplify a received signal through a plurality of unit amplification circuits, the plurality of unit amplification circuits being each configured to operate at a respective gain in a first operating mode and to operate at a different respective gain in a second operating mode; a mixer configured to convert the received signal into a baseband signal by a local oscillator signal; and an analog baseband filter configured to filter the baseband signal; in, Each of the plurality of unit amplifier circuits comprises: a push-pull circuit having a transistor having a gate to which the reception signal is applied; a symmetrical circuit symmetrically connected to the push-pull circuit and configured to be turned off in the first operation mode and turned on in the second operation mode; and A path control circuit is connected to the drain of the transistor and is configured to connect the drain of the transistor to the mixer in the first operating mode and disconnect the drain of the transistor from the mixer in the second operating mode.

19. The receiving circuit according to claim 18, wherein: The transistor of the push-pull circuit includes at least one of the following: a first N-type transistor having a gate to which the reception signal is applied through the first capacitor and a source connected to ground; and A first P-type transistor having a gate to which the reception signal is applied through the second capacitor and a source to which a power supply voltage is supplied.

20. The receiving circuit according to claim 19, wherein: When the transistor of the push-pull circuit includes the first N-type transistor and the first P-type transistor, the symmetrical circuit includes: a second N-type transistor, the second N-type transistor being symmetrically connected to the first N-type transistor, and is configured to be turned off in the first operating mode and turned on in the second operating mode; and A second P-type transistor is symmetrically connected to the first P-type transistor and is configured to be turned off in the first operation mode and turned on in the second operation mode.

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