Signal calibration device and method, display driving chip and electronic equipment

Abstract

The invention provides a signal calibration device and method, a display driving chip and electronic equipment. The signal calibration device is coupled with a plurality of data channels. The signal calibration device comprises a reference signal selection module and a first calibration module. Wherein the reference signal selection module is coupled with the plurality of data channels, and is configured to obtain data signals of the plurality of data channels, and output reference signals according to the data signals; the first calibration module is coupled with the reference signal selection module and the plurality of data channels, and is configured to receive the data signals and the reference signals, and calibrate one or more of the data signals based on a phase relationship between the data signals and the reference signals.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technology, and in particular to a signal calibration device and method, a display driver chip, and an electronic device. Background Art

[0002] In order to improve the efficiency of signal transmission, interfaces including multiple data channels and clock channels have been proposed, such as MIPI (Mobile Industry Processor Interface), which can achieve high-speed communication between components of mobile devices. However, when transmitting signals through multiple parallel channels, skew is likely to occur between data signals and between data signals and clock signals, which will affect the reliability of signal transmission. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a signal calibration device and method, a display driver chip, and an electronic device.

[0004] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a signal calibration device, wherein the signal calibration device is coupled to a plurality of data channels; the signal calibration device comprises a reference signal selection module and a first calibration module; wherein:

[0006] The reference signal selection module is coupled to the multiple data channels and is configured to: acquire data signals of the multiple data channels and output a reference signal according to the data signals;

[0007] The first calibration module is coupled to the reference signal selection module and the plurality of data channels, and is configured to: receive the data signal and the reference signal, and calibrate one or more of the data signals based on a phase relationship between the data signal and the reference signal.

[0008] In some embodiments, the signal calibration device is coupled to N data channels; N is an integer greater than 1; the reference signal selection module includes at least one selection circuit; the at least one selection circuit is configured to: perform N-1 selection operations to determine the reference signal; each selection operation includes: obtaining two of the data signals, and outputting the data signal with the larger delay among the two data signals; the reference signal is the data signal with the largest delay among the data signals of the multiple data channels.

[0009] In some embodiments, the selection circuit comprises:

[0010] A trigger, wherein a data input terminal of the trigger receives a first data signal, a clock input terminal receives a second data signal, and an output terminal outputs a selection signal; wherein the first data signal and the second data signal are any two different data signals among the plurality of data signals;

[0011] A selector, wherein a first input terminal of the selector receives the first data signal, a second input terminal receives the second data signal, and a control terminal receives the selection signal; the selector is configured to output the first data signal or the second data signal in response to the selection signal.

[0012] In some embodiments, the trigger is a rising edge triggered D trigger; if the selection signal is a first level signal, the selector outputs the second data signal; wherein the first level signal indicates that the delay of the second data signal is greater than the delay of the first data signal; if the selection signal is a second level signal, the selector outputs the first data signal; wherein the second level signal indicates that the delay of the first data signal is greater than the delay of the second data signal.

[0013] In some embodiments, the first calibration module comprises:

[0014] A first processing circuit is configured to: receive the data signal and the reference signal, and output a first phase difference signal according to the data signal and the reference signal; the first phase difference signal indicates a phase relationship between the data signal and the reference signal;

[0015] A first controller is coupled to the first processing circuit and is configured to: determine a current first delay amount of the data signal according to the first phase difference signal;

[0016] The first delay circuit is coupled to the first controller and is configured to: if the first delay amount is greater than a first preset delay amount, adjust the delay amount of the data signal until the first delay amount of the data signal is less than or equal to the first preset delay amount.

[0017] In some embodiments, the first processing circuit is specifically configured to: perform an XOR operation on the data signal and the reference signal to determine the first phase difference signal;

[0018] The first controller is specifically configured to: determine the first delay amount according to the duration of the first level period in one cycle of the first phase difference signal; output a first control signal according to a comparison result between the first delay amount and the first preset delay amount;

[0019] The first delay circuit is specifically configured to: in response to the first control signal indicating that the first delay amount is greater than the first preset delay amount, adjust the delay amount of the data signal; in response to the first control signal indicating that the first delay amount is less than or equal to the first preset delay amount, stop adjusting the delay amount of the data signal and output the data signal.

[0020] In some embodiments, the signal calibration device is further coupled to at least one clock channel, and the signal calibration device further comprises:

[0021] The second calibration module is coupled to the reference signal selection module and the clock channel, and is configured to: receive the clock signal of the clock channel and the reference signal, and calibrate the clock signal based on the phase relationship between the clock signal and the reference signal.

[0022] In some embodiments, the second calibration module comprises:

[0023] a second processing circuit, configured to: receive the clock signal and the reference signal, and output a second phase difference signal according to the clock signal and the reference signal; the second phase difference signal indicates a phase relationship between the clock signal and the reference signal;

[0024] A second controller is coupled to the second processing circuit and is configured to: determine a current second delay amount of the clock signal according to the second phase difference signal;

[0025] The second delay circuit is coupled to the second controller and is configured to: if the second delay amount is greater than a second preset delay amount, adjust the delay amount of the clock signal until the second delay amount of the clock signal is less than or equal to the second preset delay amount.

[0026] In some embodiments, the second processing circuit is specifically configured to: perform an XOR operation on the clock signal and the reference signal to determine the second phase difference signal;

[0027] The second controller is specifically configured to: determine the second delay amount according to the difference between the duration of the first level period and the duration of the second level period in one cycle of the second phase difference signal; output a second control signal according to the comparison result of the second delay amount and the second preset delay amount;

[0028] The second delay circuit is specifically configured to: in response to the second control signal indicating that the second delay amount is greater than the second preset delay amount, adjust the delay amount of the clock signal; in response to the second control signal indicating that the second delay amount is less than or equal to the second preset delay amount, stop adjusting the delay amount of the clock signal and output the clock signal.

[0029] In some embodiments, the second controller comprises:

[0030] an inverter, configured to: receive the second phase difference signal, and output an inverted second phase difference signal;

[0031] A first measurement circuit is configured to: receive the inverted second phase difference signal, measure the duration of a first level period of the inverted second phase difference signal, and output a first measurement result;

[0032] a second measuring circuit, configured to: receive the second phase difference signal, measure the duration of the first level period of the second phase difference signal, and output a second measurement result;

[0033] The comparator is configured to: receive the first measurement result and the second measurement result, and output a difference signal; the difference signal indicates the difference between the duration of the first level period and the duration of the second level period in one cycle of the second phase difference signal.

[0034] In a second aspect, an embodiment of the present disclosure provides a signal calibration method, including:

[0035] Acquire data signals of multiple data channels, and output reference signals according to the data signals;

[0036] The data signal and the reference signal are received, and one or more of the data signals are calibrated based on a phase relationship between the data signal and the reference signal.

[0037] In some embodiments, acquiring data signals of multiple data channels and outputting reference signals according to the data signals includes:

[0038] Acquire N data signals and perform N-1 selection operations to determine the reference signal; each selection operation includes: acquiring two data signals and outputting the data signal with the larger delay among the two data signals; the reference signal is the data signal with the largest delay among the data signals of the multiple data channels; N is an integer greater than 1.

[0039] In some embodiments, the acquiring the two data signals and outputting the data signal with a larger delay among the two data signals includes:

[0040] receiving a first data signal and a second data signal, and outputting a selection signal; wherein the first data signal and the second data signal are any two different data signals among the plurality of data signals;

[0041] In response to the selection signal, the first data signal or the second data signal is output.

[0042] In some embodiments, in response to the selection signal, outputting the first data signal or the second data signal comprises:

[0043] If the selection signal is a first level signal, the second data signal is output; wherein the first level signal indicates that the delay of the second data signal is greater than the delay of the first data signal;

[0044] If the selection signal is a second level signal, the first data signal is output; wherein the second level signal indicates that the delay of the first data signal is greater than the delay of the second data signal.

[0045] In some embodiments, the receiving the data signal and the reference signal, and calibrating one or more of the data signals based on a phase relationship between the data signal and the reference signal, comprises:

[0046] receiving the data signal and the reference signal, and outputting a first phase difference signal according to the data signal and the reference signal; the first phase difference signal indicates a phase relationship between the data signal and the reference signal;

[0047] Determine a current first delay amount of the data signal according to the first phase difference signal;

[0048] If the first delay is greater than a first preset delay, the delay of the data signal is adjusted until the first delay of the data signal is less than or equal to the first preset delay.

[0049] In some embodiments, the receiving the data signal and the reference signal, and outputting a first phase difference signal according to the data signal and the reference signal, comprises:

[0050] Performing an XOR operation on the data signal and the reference signal to determine the first phase difference signal;

[0051] The determining the current first delay amount of the data signal according to the first phase difference signal includes:

[0052] Determine the first delay amount according to the duration of a first level period in the first phase difference signal of one cycle;

[0053] The signal calibration method further includes:

[0054] Outputting a first control signal according to a comparison result between the first delay amount and the first preset delay amount;

[0055] If the first delay is greater than a first preset delay, adjusting the delay of the data signal until the first delay of the data signal is less than or equal to the first preset delay, comprising:

[0056] In response to the first control signal indicating that the first delay amount is greater than the first preset delay amount, adjusting the delay amount of the data signal;

[0057] In response to the first control signal indicating that the first delay amount is less than or equal to the first preset delay amount, the delay amount of the data signal is stopped from being adjusted and the data signal is output.

[0058] In some embodiments, the signal calibration method further comprises:

[0059] A clock signal of a clock channel and the reference signal are received, and the clock signal is calibrated based on a phase relationship between the clock signal and the reference signal.

[0060] In some embodiments, the receiving the clock signal of the clock channel and the reference signal, and calibrating the clock signal based on a phase relationship between the clock signal and the reference signal, comprises:

[0061] receiving the clock signal and the reference signal, and outputting a second phase difference signal according to the clock signal and the reference signal; the second phase difference signal indicates a phase relationship between the clock signal and the reference signal;

[0062] Determine a current second delay amount of the clock signal according to the second phase difference signal;

[0063] If the second delay is greater than the second preset delay, the delay of the clock signal is adjusted until the second delay of the clock signal is less than or equal to the second preset delay.

[0064] In some embodiments, determining the current second delay amount of the clock signal according to the second phase difference signal includes:

[0065] Determine the second delay amount according to the difference between the duration of the first level period and the duration of the second level period in the second phase difference signal of one cycle;

[0066] The signal calibration method further includes:

[0067] Outputting a second control signal according to a comparison result between the second delay amount and the second preset delay amount;

[0068] If the second delay is greater than the second preset delay, adjusting the delay of the clock signal until the second delay of the clock signal is less than or equal to the second preset delay, comprising:

[0069] In response to the second control signal indicating that the second delay amount is greater than the second preset delay amount, adjusting the delay amount of the clock signal;

[0070] In response to the second control signal indicating that the second delay amount is less than or equal to the second preset delay amount, the delay amount of the clock signal is stopped from being adjusted and the clock signal is output.

[0071] In some embodiments, determining the second delay amount according to the difference between the duration of the first level period and the duration of the second level period in one cycle of the second phase difference signal includes:

[0072] receiving the second phase difference signal, and outputting an inverted second phase difference signal;

[0073] Measuring the duration of the first level period of the inverted second phase difference signal, and outputting a first measurement result;

[0074] measuring the duration of the first level period of the second phase difference signal, and outputting a second measurement result;

[0075] The first measurement result and the second measurement result are received, and a difference signal is output; the difference signal indicates the difference between the duration of a first level period and the duration of a second level period in one cycle of the second phase difference signal.

[0076] In a third aspect, an embodiment of the present disclosure provides a display driver chip, including a mobile industry processor interface; the mobile industry processor interface includes:

[0077] The signal calibration device described in any of the above embodiments.

[0078] In a fourth aspect, an embodiment of the present disclosure provides an electronic device, including: a processor and a memory for storing a computer program that can be run on the processor;

[0079] Wherein, when the processor is used to run the computer program, it executes the signal calibration method described in any of the above-mentioned embodiments.

[0080] In the technical solution provided in the present disclosure, a signal calibration device including a reference signal selection module and a first calibration module can realize the calibration of data signals transmitted through multiple data channels. The reference signal selection module can determine the reference signal based on the data signals transmitted through multiple data channels. The first calibration module can calibrate the data signal based on the phase relationship between the data signal and the reference signal, so that the phase difference between one or more data signals is maintained within a preset range, thereby reducing the degree of skewness between data signals and improving the reliability of data signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] Figure 1 A schematic diagram of a signal calibration device provided by an embodiment of the present disclosure;

[0082] Figure 2 A schematic diagram of a selection circuit in a signal calibration device provided in an embodiment of the present disclosure;

[0083] Figure 3 Signal waveform during calibration of the signal calibration device provided in the embodiment of the present disclosure Figure 1 ;

[0084] Figure 4 Signal waveform during calibration of the signal calibration device provided in the embodiment of the present disclosure Figure 2 ;

[0085] Figure 5 A schematic diagram of a first calibration module in a signal calibration device provided in an embodiment of the present disclosure;

[0086] Figure 6 A schematic diagram of a first processing circuit in a signal calibration device provided in an embodiment of the present disclosure;

[0087] Figure 7 A schematic diagram of a first controller in a signal calibration device provided in an embodiment of the present disclosure;

[0088] Figure 8 Signal waveform during calibration of the signal calibration device provided in the embodiment of the present disclosure Figure 3 ;

[0089] Fig. 9 Signal waveform during calibration of the signal calibration device provided in the embodiment of the present disclosure Figure 4 ;

[0090] Fig.10 A schematic diagram of a second calibration module in a signal calibration device provided in an embodiment of the present disclosure;

[0091] Fig.11 A schematic diagram of a second processing circuit in a signal calibration device provided by an embodiment of the present disclosure;

[0092] Fig.12 A schematic diagram of a first part of a second controller in a signal calibration device provided by an embodiment of the present disclosure;

[0093] Fig.13 A schematic diagram of a second part of a second controller in a signal calibration device provided by an embodiment of the present disclosure;

[0094] Fig.14 Signal waveform during calibration of the signal calibration device provided in the embodiment of the present disclosure Figure 5 ;

[0095] Fig.15 A flow chart of a signal calibration method provided by an embodiment of the present disclosure;

[0096] Fig.16 A flowchart of another signal calibration method provided by an embodiment of the present disclosure;

[0097] Fig.17 A schematic diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0098] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0099] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0100] In the drawings, like reference numerals refer to like elements throughout.

[0101] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0102] In order to improve the efficiency of signal transmission, an interface including multiple data channels and clock channels has been proposed, such as MIPI (Mobile Industry Processor Interface), which can realize high-speed communication between components of mobile devices. However, when transmitting signals through multiple parallel channels, skew is easily generated between data signals and between data signals and clock signals, which will affect the reliability of signal transmission. Therefore, how to reduce the skew between signals to improve the reliability of signal transmission has become a problem that needs to be solved urgently.

[0103] In this regard, the present disclosure proposes the following implementation modes.

[0104] The present disclosure provides a signal calibration device. Figure 1 A schematic diagram of a signal calibration device provided by an embodiment of the present disclosure, such as Figure 1 As shown, the signal calibration device 10 is coupled to multiple data channels 101 and at least one clock channel 102; the signal calibration device 10 includes a reference signal selection module 200 and a first calibration module 300; wherein the reference signal selection module 200 is coupled to the multiple data channels 101, and is configured to: obtain data signals of the multiple data channels 101, and output a reference signal D_REF according to the data signals; the first calibration module 300 is coupled to the reference signal selection module 200 and the multiple data channels 101, and is configured to: receive the data signal and the reference signal D_REF, and calibrate one or more data signals based on the phase relationship between the data signal and the reference signal D_REF.

[0105] In some embodiments, the signal calibration device 10 is coupled to N data channels; N is an integer greater than 1; the reference signal selection module 200 includes at least one selection circuit 201; at least one selection circuit 201 is configured to: perform N-1 selection operations to determine the reference signal D_REF; each selection operation includes: acquiring two data signals, and outputting the data signal with the larger delay of the two data signals; the reference signal D_REF is the data signal with the largest delay among the data signals of multiple data channels 101.

[0106] In some embodiments, Figure 2 A schematic diagram of a selection circuit in a signal calibration device provided in an embodiment of the present disclosure, such as Figure 2 As shown, the selection circuit 201 includes: a trigger 202 and a selector 203, wherein the data input terminal of the trigger 202 receives the first data signal Da, the clock input terminal receives the second data signal Db, and the output terminal outputs a selection signal; the first data signal Da and the second data signal Db are any two different data signals among a plurality of data signals; the first input terminal of the selector 203 receives the first data signal Da, the second input terminal receives the second data signal Db, and the control terminal receives the selection signal; the selector 203 is configured to: output the first data signal Da or the second data signal Db in response to the selection signal.

[0107] In some specific examples, the trigger 202 is a rising edge triggered D trigger, then at each rising edge of the second data signal Db, the trigger 202 samples the first data signal Da and outputs a selection signal at the output end, the level of the selection signal is the same as the level of the first data signal Da at the time of sampling, and the selector 203 responds to the selection signal and outputs the data signal with a larger delay between the first data signal Da and the second data signal Db. Specifically, in conjunction with reference Figure 2 and Figure 3 , if the selection signal is a first level signal, the selector 203 outputs a second data signal Db; wherein the first level signal indicates that the delay of the second data signal Db is greater than the delay of the first data signal Da; combined with reference Figure 2 and Figure 4 If the selection signal is a second level signal, the selector 203 outputs the first data signal Da; wherein the second level signal indicates that the delay of the first data signal Da is greater than the delay of the second data signal Db.

[0108] In the embodiment of the present disclosure, it is taken as an example that the first level is a high level and the second level is a low level.

[0109] In a specific example, the reference signal selection module 200 includes a selection circuit 201, and the selection circuit 201 can perform N-1 selection operations in sequence, and each selection operation includes: obtaining two data signals, and outputting the data signal with a larger delay in the two data signals. Here, the two data signals can be data signals obtained from two data channels respectively. When one selection operation is completed, the selection circuit 201 will again obtain the data signal with a larger delay output from the last selection operation and the data signal of another data channel until N-1 selection operations are completed. The data signal output at the end is the reference signal D_REF, which is the data signal with the largest delay in the data signals of the multiple data channels 101.

[0110] In another specific example, the reference signal selection module 200 includes N-1 selection circuits 201, each selection circuit 201 performs a selection operation and transmits the output data signal with a larger delay to the next selection circuit 201 until the N-1 selection circuits 201 complete the selection operation. The data signal output by the last selection circuit 201 is the reference signal D_REF, which is the data signal with the largest delay among the data signals of multiple data channels 101.

[0111] In the embodiment of the present disclosure, the reference signal selection module 200 including at least one selection circuit 201 can complete the phase comparison of the data signals of multiple data channels 101 to determine the data signal with the largest delay among the data signals of the multiple data channels and use it as the reference signal D_REF for signal calibration.

[0112] In some embodiments, Figure 5 The first calibration module 300 is a schematic diagram of a first calibration module in a signal calibration device provided in an embodiment of the present disclosure, and includes: a first processing circuit 301, configured to: receive a data signal Dx and a reference signal D_REF, and output a first phase difference signal XOR_X according to the data signal Dx and the reference signal D_REF; the first phase difference signal XOR_X indicates a phase relationship between the data signal Dx and the reference signal D_REF; a first controller 302, coupled to the first processing circuit 301, and configured to: determine a current first delay amount of the data signal according to the first phase difference signal XOR_X; a first delay circuit 303, coupled to the first controller 302, and configured to: if the first delay amount is greater than a first preset delay amount, adjust the delay amount of the data signal Dx until the first delay amount of the data signal Dx is less than or equal to the first preset delay amount.

[0113] It should be noted that, in the embodiment of the present disclosure, data signals of multiple data channels 101 can be transmitted in parallel to the first processing circuit 301, and the first processing circuit 301 can output in parallel first phase difference signals corresponding to the multiple data signals respectively, and the first delay circuit 303 can adjust the delay amount of multiple data signals at the same time. For the sake of simplicity, any one data signal Dx among the multiple data signals is taken as an example for explanation.

[0114] In some specific examples, the first processing circuit 301 is specifically configured to: perform an XOR operation on the data signal Dx and the reference signal D_REF to determine the first phase difference signal XOR_X.

[0115] In a specific example, Figure 6 A schematic diagram of a first processing circuit in a signal calibration device provided in an embodiment of the present disclosure, referring to Figure 6 , the first processing circuit 301 includes a plurality of XOR gates, two input ends of the XOR gates receive the data signal Dx and the reference signal D_REF respectively, and the output end of the XOR gates outputs the first phase difference signal XOR_X. Here, when the signal calibration device 10 is coupled to N data channels, the first processing circuit 301 may include N-1 XOR gates, each of which receives a data signal and a reference signal D_REF, and outputs a first phase difference signal corresponding to the data signal.

[0116] In some embodiments, the first controller 302 is specifically configured to: determine the first delay amount according to the length of the first level period in the first phase difference signal XOR_X of one cycle; output a first control signal according to the comparison result of the first delay amount and the first preset delay amount; the first delay circuit 303 is specifically configured to: in response to the first control signal indicating that the first delay amount is greater than the first preset delay amount, adjust the delay amount of the data signal Dx; in response to the first control signal indicating that the first delay amount is less than or equal to the first preset delay amount, stop adjusting the delay amount of the data signal Dx.

[0117] In some specific examples, Figure 7 A schematic diagram of a first controller in a signal calibration device provided in an embodiment of the present disclosure, with reference to Figure 7 and Figure 8 The first controller 302 may be configured to: receive a first phase difference signal XOR_X corresponding to the data signal Dx, and determine a first delay amount T according to the duration of a first level period in a cycle of the first phase difference signal XOR_X. (XOR_X) ; The first delay T (XOR_X) is compared with the first preset delay time T0, and the (XOR_X) The comparison result with the first preset delay amount T0 outputs a first control signal.

[0118] In some specific examples, if the first delay amount T (XOR_X) is greater than the first preset delay T0, the phase difference between the data signal Dx and the reference signal D_REF is large, and the delay of the data signal Dx needs to be adjusted. (XOR_X) If the first preset delay T0 is less than or equal to the first preset delay T0, the phase difference between the data signal Dx and the reference signal D_REF can be ignored or the phase difference is 0, and there is no need to adjust the delay of the data signal Dx. (XOR_X) Specifically, if the receiving circuit of the data signal is sensitive to the first delay T (XOR_X) The tolerance is low. In order to make the first delay T (XOR_X) As small as possible, the first preset delay amount T0 can be small; if the receiving circuit of the data signal is (XOR_X) The tolerance is high. In order to improve the efficiency of the calibration data signal, the first preset delay amount T0 can be larger. In practical applications, the present application does not limit the first preset delay amount T0, which can be determined according to specific circumstances.

[0119] In some specific examples, the first control signal may be XOR_X_OUT. When the first delay time T (XOR_X) When the delay time is greater than the first preset delay time T0, the waveform of the first control signal XOR_X_OUT may be the same as the waveform of the first phase difference signal XOR_X, that is, when the first control signal XOR_X_OUT includes a first level period and a second level period, the first control signal XOR_X_OUT indicates the first delay time T (XOR_X) The first delay circuit 303 may be configured to: respond to the first control signal XOR_X_OUT indicating the first delay amount T (XOR_X) The delay of the data signal Dx is adjusted according to the duration of the first level period in the first control signal XOR_X_OUT of one cycle, and the longer the duration of the first level period in the first control signal XOR_X_OUT of one cycle, the greater the increased delay.

[0120] In some specific examples, the data signal Dx after a calibration can be transmitted to the input end of the first calibration module 300 again, and it may be necessary to increase the delay amount of the data signal Dx through the above process again until the first delay amount T of the data signal Dx is (XOR_X) Less than or equal to the first preset delay amount T0.

[0121] In some specific examples, the first delay circuit 303 may further include a delay setting circuit and a delay line coupled to a data channel for transmitting the data signal Dx. For example, the delay line may include an even number of inverters connected in series, and the delay setting circuit may determine the number of inverters to be added to the delay line based on the duration of the first level period in the first control signal XOR_X_OUT, so that the delay amount of the data signal Dx may be increased by increasing the number of inverters, and the number of added inverters is positively correlated with the duration of the first level period in one cycle of the first control signal XOR_X_OUT.

[0122] It should be noted that the method of increasing the data signal delay in the above specific example is only an example, and the present disclosure does not impose any specific limitation on this.

[0123] Combined with reference Figure 8 and Fig. 9 When the delay of the data signal Dx is less than or equal to the first preset delay T0, the first control signal XOR_X_OUT remains at the second level without the first level period, that is, when the first control signal XOR_X_OUT only includes the second level period, the first control signal XOR_X_OUT indicates the first delay T (XOR_X) The first delay circuit 303 may be configured to: respond to the first control signal XOR_X_OUT indicating the first delay amount T (XOR_X) When the delay time is less than or equal to the first preset delay time T0, the adjustment of the delay time of the data signal Dx is stopped and the data signal Dx is output through the adjusted delay line, thereby completing the calibration of the data signal Dx.

[0124] In an embodiment of the present disclosure, calibration of data signals transmitted over multiple data channels can be achieved through a signal calibration device including a reference signal selection module and a first calibration module. The reference signal selection module can select a data signal with the largest delay among multiple data signals as a reference signal. The first calibration module can calibrate the data signal based on the phase relationship between the data signal and the reference signal, so that the phase difference between any two data signals among the multiple data signals is maintained within a preset range, thereby reducing the degree of skewness between the multiple data signals and improving the reliability of data signal transmission.

[0125] In some embodiments, refer back to Figure 1 The signal calibration device 10 also includes: a second calibration module 400, coupled to the reference signal selection module 200 and the clock channel 102, and configured to: receive the clock signal and the reference signal D_REF of the clock channel 102, and calibrate the clock signal based on the phase relationship between the clock signal and the reference signal.

[0126] In some embodiments, Fig.10 The schematic diagram of the second calibration module in the signal calibration device provided in the embodiment of the present disclosure is as follows. The second calibration module 400 includes: a second processing circuit 401, configured to: receive a clock signal CLK and a reference signal D_REF, and output a second phase difference signal XOR_C according to the clock signal CLK and the reference signal D_REF; the second phase difference signal XOR_C indicates the phase relationship between the clock signal CLK and the reference signal D_REF; a second controller 402, coupled to the second processing circuit 401, and configured to: determine the current second delay amount of the clock signal CLK according to the second phase difference signal XOR_C; a second delay circuit 403, coupled to the second controller 402, and configured to: if the second delay amount is greater than the second preset delay amount, adjust the delay amount of the clock signal CLK until the second delay amount of the clock signal is less than or equal to the second preset delay amount.

[0127] In some embodiments, the second processing circuit 401 is specifically configured to: perform an exclusive OR operation on the clock signal CLK and the reference signal D_REF to determine the second phase difference signal XOR_C.

[0128] In a specific example, Fig.11 A schematic diagram of a second processing circuit in a signal calibration device provided in an embodiment of the present disclosure, referring to Fig.11 The second processing circuit 401 includes an XOR gate, two input terminals of the XOR gate receive the clock signal CLK and the reference signal D_REF respectively, and an output terminal of the XOR gate outputs the second phase difference signal XOR_C.

[0129] In some embodiments, the second controller 402 is specifically configured to: determine the second delay amount according to the difference between the duration of the first level period and the duration of the second level period in a cycle of the second phase difference signal XOR_C; output a second control signal according to the comparison result of the second delay amount and the second preset delay amount; the second delay circuit 403 is specifically configured to: in response to the second control signal indicating that the second delay amount is greater than the second preset delay amount, adjust the delay amount of the clock signal; in response to the second control signal indicating that the second delay amount is less than or equal to the second preset delay amount, stop adjusting the delay amount of the clock signal and output the clock signal.

[0130] In the disclosed embodiment, the clock signal can be used as a sampling clock signal for data signals transmitted by multiple data channels. For example, the sampling circuit can sample the data signal at each transition edge of the clock signal to obtain data information transmitted by the data signal. Therefore, there should be a fixed phase difference between the clock signal and the data signal, so that when the data signal is sampled based on the transition edge of the clock signal, the data signal has completed the transition, thereby improving the reliability of data signal sampling. Therefore, when the clock signal is calibrated using the reference signal D_REF determined by the reference signal selection module 200, the second delay amount of the clock signal can be determined based on the difference between the duration of the first level period and the duration of the second level period in the second phase difference signal XOR_C of one cycle. Below, the phase difference between the clock signal and the data signal is 1 / 4 cycle as an example for explanation.

[0131] In some specific examples, Fig.12 The present invention is a schematic diagram of a first part 4021 of a second controller in a signal calibration device provided in an embodiment of the present invention, wherein the second controller 402 includes: an inverter 404, configured to receive a second phase difference signal XOR_C and output an inverted second phase difference signal XOR_C_N; a first measurement circuit 405, configured to receive the inverted second phase difference signal XOR_C_N, measure the duration of a first level period of the inverted second phase difference signal XOR_C_N, and output a first measurement result; a second measurement circuit 406, configured to receive the second phase difference signal XOR_C, measure the duration of a first level period of the second phase difference signal XOR_C, and output a second measurement result; a comparator 407, configured to receive the first measurement result and the second measurement result, and output a difference signal COMP_C; the difference signal COMP_C indicates the difference between the duration of a first level period and the duration of a second level period in one cycle of the second phase difference signal XOR_C.

[0132] Here, the first measurement circuit 405 and the second measurement circuit 406 may have the same circuit structure, wherein the first measurement circuit 405 includes a first constant current source 4051, a first transistor 4052, a first inductor 4053 and a first capacitor 4054, and the second measurement circuit 406 includes a second constant current source 4061, a second triode 4062, a second inductor 4063 and a second capacitor 4064. In one cycle of the second phase difference signal XOR_C, during the first level period of the inverted second phase difference signal XOR_C_N, that is, the second level period of the second phase difference signal XOR_C, the first triode 4052 may be turned on, the first constant current source 4051 may charge the first capacitor 4054, and the first measurement result output by the first measurement circuit 405 is the voltage connected between the first capacitor 4054 and the comparator 407 after the first constant current source 4051 charges the first capacitor 4054 during the first level period of the inverted second phase difference signal XOR_C_N. The potential u1 accumulated on the electrode plate; in the second level period of the inverted second phase difference signal XOR_C_N, that is, the first level period of the second phase difference signal XOR_C, the second triode 4062 can be turned on, and the second constant current source 4061 can charge the second capacitor 4064. The second measurement result output by the second measurement circuit 406 is the potential u2 accumulated on the electrode plate connected to the second capacitor 4064 and the comparator 407 after the second constant current source 4061 charges the second capacitor 4064 in the first level period of the inverted second phase difference signal XOR_C. The two input terminals of the comparator 407 receive the first measurement result and the second measurement result respectively. The comparator 407 can output the difference signal COMP_C according to the first measurement result and the second measurement result. The duration of each first level period in the difference signal COMP_C is the difference between the duration of the first level period and the duration of the second level period of one cycle of the second phase difference signal XOR_C.

[0133] In some specific examples, Fig.13 Schematic diagram of the second part 4022 of the second controller in the signal calibration device provided in an embodiment of the present disclosure. The second controller 402 is specifically configured to: determine the second delay amount T of the clock signal according to the difference signal COMP_C (COMP_C) According to the second delay T (COMP_C) The comparison result with the second preset delay amount T1 is used to output a second control signal.

[0134] In some specific examples, if the second delay amount T (COMP_C) is greater than the second preset delay T1, then the second delay T of the clock signal CLK (COMP_C) is large, and the delay of the clock signal CLK needs to be adjusted. If the second delay T (COMP_C)is less than or equal to the second preset delay T1, then the second delay T of the clock signal CLK (COMP_C) It can be ignored or equal to 0, and there is no need to adjust the delay of the clock signal CLK. (COMP_C) Specifically, if the receiving circuit of the clock signal is sensitive to the second delay T (COMP_C) The tolerance is low. In order to make the second delay T (COMP_C) As small as possible, the second preset delay T1 can be smaller; if the receiving circuit of the clock signal is (COMP_C) The tolerance is high. In order to improve the efficiency of calibrating the clock signal, the second preset delay T1 can be larger. In practical applications, the present application does not limit the second preset delay T1, which can be determined according to specific circumstances.

[0135] In some specific examples, the second control signal may be COMP_C_OUT. When the second delay time T (COMP_C) When the delay time is greater than the second preset delay time T1, the waveform of the second control signal COMP_C_OUT is the same as the waveform of the difference signal COMP_C, that is, when the second control signal COMP_C_OUT includes the first level period and the second level period, the second control signal COMP_C_OUT indicates the second delay time T (COMP_C) The second delay circuit 403 may be configured to: respond to the second control signal COMP_C_OUT indicating the second delay amount T (COMP_C) is greater than a second preset delay amount T1, and the delay amount of the clock signal CLK is adjusted according to the length of the first level period in one cycle of the second control signal COMP_C_OUT.

[0136] In some specific examples, the clock signal CLK after a calibration can be transmitted to the input end of the second calibration module 400 again, and the delay amount of the clock signal CLK may need to be adjusted again through the above process until the second delay amount T of the clock signal CLK is (COMP_C) Less than or equal to the second preset delay T1.

[0137] In some specific examples, the second delay circuit 403 may further include a delay setting circuit and a delay line coupled to the clock channel. For example, the delay line may include an even number of inverters connected in series, and the delay setting circuit may determine the number of inverters in the delay line based on the duration of the first level period in the second control signal COMP_C_OUT, so that the delay amount of the clock signal CLK may be adjusted by adjusting the number of inverters.

[0138] It should be noted that the method of adjusting the clock signal delay in the above specific example is only an example, and the present disclosure does not impose any specific limitation on this.

[0139] Reference Fig.14 , when the second delay time T of the clock signal CLK (COMP_C) When the delay time is less than or equal to the second preset delay time T1, the second control signal COMP_C_OUT remains at the second level without the first level period, that is, when the second control signal COMP_C_OUT only includes the second level period, the second control signal COMP_C_OUT indicates the second delay time T (COMP_C) The second delay circuit 403 may be configured to: respond to the second control signal COMP_C_OUT indicating the second delay amount T (COMP_C) When the delay amount T1 is less than or equal to the second preset delay amount T1, the adjustment of the delay amount of the clock signal CLK is stopped and the clock signal CLK is output through the adjusted delay line, thereby completing the calibration of the clock signal CLK.

[0140] The above embodiments take the phase difference between the clock signal and the data signal as 1 / 4 cycle as an example. In other embodiments, the phase difference between the clock signal and the data signal can be greater than 1 / 4 cycle or less than 1 / 4 cycle. Correspondingly, the size of the second preset delay amount T1 can be adjusted to achieve calibration of the clock signal.

[0141] In an embodiment of the present disclosure, a signal calibration device including a reference signal selection module, a first calibration module and a second calibration module can be used to calibrate data signals transmitted through multiple data channels and calibrate clock signals transmitted through clock channels. The reference signal selection module can select a data signal with the largest delay among data signals transmitted through multiple data channels as a reference signal. The first calibration module can calibrate the data signal based on the phase relationship between the data signal and the reference signal. The second calibration module can calibrate the clock signal based on the phase relationship between the clock signal and the reference signal. This can reduce the degree of skew between data signals and the degree of skew between data signals and clock signals, thereby improving the reliability of signal transmission.

[0142] Based on a concept similar to that of the above-mentioned signal calibration device, the present disclosure further provides a signal calibration method, which can be implemented by the signal calibration device 10 in the above-mentioned embodiment. Fig.15 A flow chart of a signal calibration method provided by an embodiment of the present disclosure is shown as follows: Fig.15 As shown, the signal calibration method includes the following steps:

[0143] Step S101, acquiring data signals of multiple data channels, and outputting reference signals according to the data signals;

[0144] Step S102: Receive a data signal and a reference signal, and calibrate one or more data signals based on a phase relationship between the data signal and the reference signal.

[0145] In some embodiments, the specific process of executing step S101 may include: obtaining N data signals and performing N-1 selection operations to determine a reference signal; each selection operation includes: obtaining two data signals and outputting the data signal with the larger delay among the two data signals; the reference signal is the data signal with the largest delay among the data signals of multiple data channels; N is an integer greater than 1.

[0146] In some embodiments, two data signals are obtained, and the data signal with the larger delay of the two data signals is output, including: receiving a first data signal and a second data signal, and outputting a selection signal; the first data signal and the second data signal are any two different data signals among a plurality of data signals; and in response to the selection signal, outputting the first data signal or the second data signal.

[0147] In some embodiments, in response to a selection signal, a first data signal or a second data signal is output, including: if the selection signal is a first level signal, the second data signal is output; wherein the first level signal indicates that the delay of the second data signal is greater than the delay of the first data signal; if the selection signal is a second level signal, the first data signal is output; wherein the second level signal indicates that the delay of the first data signal is greater than the delay of the second data signal.

[0148] In some embodiments, the specific process of step S102 may include: receiving a data signal and a reference signal, and outputting a first phase difference signal based on the data signal and the reference signal; the first phase difference signal indicates the phase relationship between the data signal and the reference signal; determining the current first delay amount of the data signal based on the first phase difference signal; if the first delay amount is greater than the first preset delay amount, adjusting the delay amount of the data signal until the first delay amount of the data signal is less than or equal to the first preset delay amount.

[0149] In some embodiments, a data signal and a reference signal are received, and a first phase difference signal is output according to the data signal and the reference signal, including: performing an XOR operation on the data signal and the reference signal to determine the first phase difference signal; determining a current first delay amount of the data signal according to the first phase difference signal, including: determining the first delay amount according to the length of a first level period in a cycle of the first phase difference signal; the signal calibration method also includes: outputting a first control signal according to a comparison result of the first delay amount and a first preset delay amount; if the first delay amount is greater than the first preset delay amount, adjusting the delay amount of the data signal until the first delay amount of the data signal is less than or equal to the first preset delay amount, including: in response to the first control signal indicating that the first delay amount is greater than the first preset delay amount, adjusting the delay amount of the data signal; in response to the first control signal indicating that the first delay amount is less than or equal to the first preset delay amount, stopping adjusting the delay amount of the data signal and outputting the data signal.

[0150] In some embodiments, the signal calibration method further includes: receiving a clock signal and a reference signal of a clock channel, and calibrating the clock signal based on a phase relationship between the clock signal and the reference signal.

[0151] In some embodiments, a clock signal and a reference signal of a clock channel are received, and the clock signal is calibrated based on the phase relationship between the clock signal and the reference signal, including: receiving the clock signal and the reference signal, and outputting a second phase difference signal based on the clock signal and the reference signal; the second phase difference signal indicates the phase relationship between the clock signal and the reference signal; determining the current second delay amount of the clock signal based on the second phase difference signal; if the second delay amount is greater than the second preset delay amount, adjusting the delay amount of the clock signal until the second delay amount of the clock signal is less than or equal to the second preset delay amount.

[0152] In some embodiments, determining the current second delay amount of the clock signal according to the second phase difference signal includes: determining the second delay amount according to the difference between the duration of the first level period and the duration of the second level period in one cycle of the second phase difference signal; the signal calibration method also includes: outputting a second control signal according to the comparison result of the second delay amount and the second preset delay amount; if the second delay amount is greater than the second preset delay amount, adjusting the delay amount of the clock signal until the second delay amount of the clock signal is less than or equal to the second preset delay amount, including: in response to the second control signal indicating that the second delay amount is greater than the second preset delay amount, adjusting the delay amount of the clock signal; in response to the second control signal indicating that the second delay amount is less than or equal to the second preset delay amount, stopping adjusting the delay amount of the clock signal and outputting the clock signal.

[0153] In some embodiments, the second delay amount is determined based on the difference between the duration of a first level period and the duration of a second level period in a second phase difference signal of one cycle, including: receiving the second phase difference signal and outputting an inverted second phase difference signal; measuring the duration of the first level period of the inverted second phase difference signal and outputting a first measurement result; measuring the duration of the first level period of the second phase difference signal and outputting a second measurement result; receiving the first measurement result and the second measurement result and outputting a difference signal; the difference signal indicates the difference between the duration of the first level period and the duration of the second level period in the second phase difference signal of one cycle.

[0154] Fig.16 This is a flowchart of another signal calibration method provided by an embodiment of the present disclosure. The specific process of the signal calibration method may include:

[0155] Step S201, acquiring data signals, that is, acquiring any two data signals from data signals of multiple data channels;

[0156] Step S202, performing a selection operation to determine the data signal with a larger delay among the two data signals;

[0157] Step S203, determine whether the reference signal has been determined, if so, execute step S204 and step S207, if not, return to execute step S201, continue to obtain the next set of data signals, until the reference signal is determined. The reference signal can be a data signal with the largest delay among multiple data signals. If the data signals of N data channels are calibrated, it can be determined based on whether the number of executions of the selection operation reaches N-1 times, and the reference signal is a data signal with a larger delay determined by the last selection operation;

[0158] Step S204, determining a first delay amount of the data signal, may include determining a first phase difference signal based on the data signal and the reference signal, the first phase difference signal indicating a phase relationship between the data signal and the reference signal, and determining the first delay amount of the data signal based on a duration of a first level period in one cycle of the first phase difference signal;

[0159] Step S205, determining whether the first delay is less than or equal to the first preset delay, if not, executing step S206, adjusting the delay of the data signal until the first delay is less than or equal to the first preset delay, and ending the calibration of the data signal;

[0160] Step S207, determining a second delay amount of the clock signal, including determining a second phase difference signal based on the clock signal and the reference signal, the second phase difference signal indicating a phase relationship between the clock signal and the reference signal, and determining the second delay amount of the clock signal based on a difference between a duration of a first level period and a duration of a second level period in one cycle of the second phase difference signal;

[0161] Step S208, determine whether the second delay is less than or equal to the second preset delay. If not, execute step S209 to adjust the delay of the clock signal until the second delay is less than or equal to the second preset delay, and end the calibration of the clock signal.

[0162] Here, the specific implementation method in each step can refer to the aforementioned embodiment and will not be repeated here.

[0163] In an embodiment of the present disclosure, a signal calibration method includes determining a reference signal based on data signals of multiple data channels, where the reference signal is a data signal with the largest delay among the multiple data signals, and calibrating the data signal based on a phase relationship between the data signal and the reference signal, and calibrating the clock signal based on a phase relationship between the clock signal and the reference signal. Thus, the degree of skew between data signals and the degree of skew between data signals and clock signals can be reduced, thereby improving the reliability of signal transmission.

[0164] The embodiment of the present disclosure provides a display driver IC (DDI), the display driver IC includes a mobile industry processor interface, and the mobile industry processor interface includes the signal calibration device 10 in any of the above embodiments.

[0165] In some specific examples, the display driver chip can be linked to the processor through a mobile industry processor interface to form multiple data channels and at least one clock channel between the display driver chip and the processor. The signal calibration device 10 is located in the mobile industry processor interface of the display driver chip, coupled with multiple data signals and at least one clock channel, and is configured to calibrate the data signal transmitted to the display driver chip through at least one data channel and the clock signal transmitted to the display driver chip through at least one clock channel, thereby improving the reliability of signal transmission between the processor and the display driver chip.

[0166] The present disclosure provides an electronic device, Fig.17 A schematic diagram of an electronic device provided by an embodiment of the present disclosure, such as Fig.17As shown, the electronic device 500 includes: a processor 501 and a memory 502 for storing a computer program 5021 that can be run on the processor 501; wherein, when the processor 501 is used to run the computer program 5021, it executes the signal calibration method described in any of the above embodiments.

[0167] In some specific examples, the processor 501 may be at least one of an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a central processing unit (CPU), a controller, a microcontroller, and a microprocessor.

[0168] In some specific examples, the above-mentioned memory 502 can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory (Flash Memory), a magnetic surface memory, an optical disk, or a compact disc read-only memory (CD-ROM) and the like; it can also be various terminals including one or any combination of the above-mentioned memories, such as a mobile phone, a computer, a tablet device, a personal digital assistant, etc.

[0169] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0170] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0171] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A signal calibration device, characterized in that: The signal calibration device is coupled to a plurality of data channels; the signal calibration device comprises a reference signal selection module and a first calibration module; wherein, The reference signal selection module is coupled to the multiple data channels and is configured to: acquire data signals of the multiple data channels and output a reference signal according to the data signals; The first calibration module is coupled to the reference signal selection module and the plurality of data channels, and is configured to: receive the data signal and the reference signal, and calibrate one or more of the data signals based on a phase relationship between the data signal and the reference signal.

2. The signal calibration device according to claim 1, characterized in that: The signal calibration device is coupled to N data channels; N is an integer greater than 1; the reference signal selection module includes at least one selection circuit; The at least one selection circuit is configured to: perform N-1 selection operations to determine the reference signal; Each selection operation includes: acquiring the two data signals, and outputting the data signal with a larger delay among the two data signals; The reference signal is a data signal with the largest delay among the data signals of the multiple data channels.

3. The signal calibration device according to claim 2, characterized in that: The selection circuit comprises: A trigger, wherein a data input terminal of the trigger receives a first data signal, a clock input terminal receives a second data signal, and an output terminal outputs a selection signal; wherein the first data signal and the second data signal are any two different data signals among the plurality of data signals; A selector, wherein a first input terminal of the selector receives the first data signal, a second input terminal receives the second data signal, and a control terminal receives the selection signal; the selector is configured to output the first data signal or the second data signal in response to the selection signal.

4. The signal calibration device according to claim 3, characterized in that: The trigger is a rising edge triggered D trigger; if the selection signal is a first level signal, the selector outputs the second data signal; wherein the first level signal indicates that the delay of the second data signal is greater than the delay of the first data signal; if the selection signal is a second level signal, the selector outputs the first data signal; wherein the second level signal indicates that the delay of the first data signal is greater than the delay of the second data signal.

5. The signal calibration device according to claim 1, characterized in that: The first calibration module comprises: A first processing circuit is configured to: receive the data signal and the reference signal, and output a first phase difference signal according to the data signal and the reference signal; the first phase difference signal indicates a phase relationship between the data signal and the reference signal; A first controller is coupled to the first processing circuit and is configured to: determine a current first delay amount of the data signal according to the first phase difference signal; The first delay circuit is coupled to the first controller and is configured to: if the first delay amount is greater than a first preset delay amount, adjust the delay amount of the data signal until the first delay amount of the data signal is less than or equal to the first preset delay amount.

6. The signal calibration device according to claim 5, characterized in that: The first processing circuit is specifically configured to: perform an XOR operation on the data signal and the reference signal to determine the first phase difference signal; The first controller is specifically configured to: determine the first delay amount according to the duration of the first level period in one cycle of the first phase difference signal; output a first control signal according to a comparison result between the first delay amount and the first preset delay amount; The first delay circuit is specifically configured to: in response to the first control signal indicating that the first delay amount is greater than the first preset delay amount, adjust the delay amount of the data signal; in response to the first control signal indicating that the first delay amount is less than or equal to the first preset delay amount, stop adjusting the delay amount of the data signal and output the data signal.

7. The signal calibration device according to claim 2, characterized in that: The signal calibration device is also coupled to at least one clock channel, and the signal calibration device further comprises: The second calibration module is coupled to the reference signal selection module and the clock channel, and is configured to: receive the clock signal of the clock channel and the reference signal, and calibrate the clock signal based on the phase relationship between the clock signal and the reference signal.

8. The signal calibration device according to claim 7, characterized in that: The second calibration module comprises: a second processing circuit, configured to: receive the clock signal and the reference signal, and output a second phase difference signal according to the clock signal and the reference signal; the second phase difference signal indicates a phase relationship between the clock signal and the reference signal; A second controller is coupled to the second processing circuit and is configured to: determine a current second delay amount of the clock signal according to the second phase difference signal; The second delay circuit is coupled to the second controller and is configured to: if the second delay amount is greater than a second preset delay amount, adjust the delay amount of the clock signal until the second delay amount of the clock signal is less than or equal to the second preset delay amount.

9. The signal calibration device according to claim 8, characterized in that: The second processing circuit is specifically configured to: perform an XOR operation on the clock signal and the reference signal to determine the second phase difference signal; The second controller is specifically configured to: determine the second delay amount according to the difference between the duration of the first level period and the duration of the second level period in one cycle of the second phase difference signal; output a second control signal according to the comparison result of the second delay amount and the second preset delay amount; The second delay circuit is specifically configured to: in response to the second control signal indicating that the second delay amount is greater than the second preset delay amount, adjust the delay amount of the clock signal; in response to the second control signal indicating that the second delay amount is less than or equal to the second preset delay amount, stop adjusting the delay amount of the clock signal and output the clock signal.

10. The signal calibration device according to claim 9, characterized in that: The second controller comprises: an inverter, configured to: receive the second phase difference signal, and output an inverted second phase difference signal; A first measurement circuit is configured to: receive the inverted second phase difference signal, measure the duration of a first level period of the inverted second phase difference signal, and output a first measurement result; a second measuring circuit, configured to: receive the second phase difference signal, measure the duration of the first level period of the second phase difference signal, and output a second measurement result; The comparator is configured to: receive the first measurement result and the second measurement result, and output a difference signal; the difference signal indicates the difference between the duration of the first level period and the duration of the second level period in one cycle of the second phase difference signal.

11. A signal calibration method, characterized in that: include: Acquire data signals of multiple data channels, and output reference signals according to the data signals; The data signal and the reference signal are received, and one or more of the data signals are calibrated based on a phase relationship between the data signal and the reference signal.

12. The signal calibration method according to claim 11, characterized in that: The acquiring data signals of a plurality of data channels and outputting reference signals according to the data signals comprises: Acquire N data signals and perform N-1 selection operations to determine the reference signal; each selection operation includes: acquiring two data signals and outputting the data signal with the larger delay among the two data signals; the reference signal is the data signal with the largest delay among the data signals of the multiple data channels; N is an integer greater than 1.

13. The signal calibration method according to claim 12, characterized in that: The acquiring the two data signals and outputting the data signal with a larger delay among the two data signals comprises: receiving a first data signal and a second data signal, and outputting a selection signal; wherein the first data signal and the second data signal are any two different data signals among the plurality of data signals; In response to the selection signal, the first data signal or the second data signal is output.

14. The signal calibration method according to claim 13, characterized in that: The step of outputting the first data signal or the second data signal in response to the selection signal comprises: If the selection signal is a first level signal, the second data signal is output; wherein the first level signal indicates that the delay of the second data signal is greater than the delay of the first data signal; If the selection signal is a second level signal, the first data signal is output; wherein the second level signal indicates that the delay of the first data signal is greater than the delay of the second data signal.

15. The signal calibration method according to claim 11, characterized in that: The receiving the data signal and the reference signal, and calibrating one or more of the data signals based on a phase relationship between the data signal and the reference signal, comprises: receiving the data signal and the reference signal, and outputting a first phase difference signal according to the data signal and the reference signal; the first phase difference signal indicates a phase relationship between the data signal and the reference signal; Determine a current first delay amount of the data signal according to the first phase difference signal; If the first delay is greater than a first preset delay, the delay of the data signal is adjusted until the first delay of the data signal is less than or equal to the first preset delay.

16. The signal calibration method according to claim 15, characterized in that: The receiving the data signal and the reference signal, and outputting a first phase difference signal according to the data signal and the reference signal, comprises: Performing an XOR operation on the data signal and the reference signal to determine the first phase difference signal; The determining the current first delay amount of the data signal according to the first phase difference signal includes: Determine the first delay amount according to the duration of a first level period in the first phase difference signal of one cycle; The signal calibration method further includes: Outputting a first control signal according to a comparison result between the first delay amount and the first preset delay amount; If the first delay is greater than a first preset delay, adjusting the delay of the data signal until the first delay of the data signal is less than or equal to the first preset delay, comprising: In response to the first control signal indicating that the first delay amount is greater than the first preset delay amount, adjusting the delay amount of the data signal; In response to the first control signal indicating that the first delay amount is less than or equal to the first preset delay amount, the delay amount of the data signal is stopped from being adjusted and the data signal is output.

17. The signal calibration method according to claim 12, characterized in that: The signal calibration method further comprises: A clock signal of a clock channel and the reference signal are received, and the clock signal is calibrated based on a phase relationship between the clock signal and the reference signal.

18. The signal calibration method according to claim 17, characterized in that: The receiving a clock signal of a clock channel and the reference signal, and calibrating the clock signal based on a phase relationship between the clock signal and the reference signal, comprises: receiving the clock signal and the reference signal, and outputting a second phase difference signal according to the clock signal and the reference signal; the second phase difference signal indicates a phase relationship between the clock signal and the reference signal; Determine a current second delay amount of the clock signal according to the second phase difference signal; If the second delay is greater than the second preset delay, the delay of the clock signal is adjusted until the second delay of the clock signal is less than or equal to the second preset delay.

19. The signal calibration method according to claim 18, characterized in that: The determining the current second delay amount of the clock signal according to the second phase difference signal comprises: Determine the second delay amount according to the difference between the duration of the first level period and the duration of the second level period in the second phase difference signal of one cycle; The signal calibration method further includes: Outputting a second control signal according to a comparison result between the second delay amount and the second preset delay amount; If the second delay is greater than the second preset delay, adjusting the delay of the clock signal until the second delay of the clock signal is less than or equal to the second preset delay, comprising: In response to the second control signal indicating that the second delay amount is greater than the second preset delay amount, adjusting the delay amount of the clock signal; In response to the second control signal indicating that the second delay amount is less than or equal to the second preset delay amount, the delay amount of the clock signal is stopped from being adjusted and the clock signal is output.

20. The signal calibration method according to claim 19, characterized in that: The determining the second delay amount according to the difference between the duration of the first level period and the duration of the second level period in the second phase difference signal in one cycle includes: receiving the second phase difference signal, and outputting an inverted second phase difference signal; Measuring the duration of the first level period of the inverted second phase difference signal, and outputting a first measurement result; measuring the duration of the first level period of the second phase difference signal, and outputting a second measurement result; The first measurement result and the second measurement result are received, and a difference signal is output; the difference signal indicates the difference between the duration of a first level period and the duration of a second level period in one cycle of the second phase difference signal.

21. A display driver chip, characterized in that: Includes mobile industry processor interfaces; The mobile industry processor interface includes: A signal calibration device as claimed in any one of claims 1 to 10.

22. An electronic device, characterized in that: include: a processor and a memory for storing a computer program capable of running on said processor; Wherein, when the processor is used to run the computer program, it executes the signal calibration method described in any one of claims 11 to 20.

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