A memory-based radar signal pulse width filtering method in FPGA

Abstract

The application provides a memory-based radar signal pulse width filtering method in FPGA, which realizes filtering of radar signals within a certain width by processing the delayed radar signals with the original signals. The radar signals are sampled by amplitude quantization ADC to obtain discrete levels; the data and threshold comparison levels of the radar signals are combined into a data set and stored in a memory; the read address corresponding to the write address of each clock cycle is calculated according to the pulse width requirement of the required filtering; the data set in the memory is read out by using the calculated read address in a continuous reading mode, and the data set is the radar signal sampling data after delay and the threshold comparison level; the threshold comparison level after delay is ANDed with the original threshold comparison level to obtain the filtered signals within the specified pulse width, and the original relative time relationship of the read ADC sampling signal and the front edge of the final threshold signal after filtering pulse width is unchanged.

Description

Technical Field

[0001] The present application relates to the field of electronic information processing technology, and in particular to a radar signal pulse width filtering method based on memory in FPGA. Background Art

[0002] The electromagnetic environment refers to the sum of electromagnetic activities and phenomena within space that affect combat. A complex electromagnetic environment, an integral and integral part of electronic countermeasures, is both a requirement and a challenge. In a complex electromagnetic environment, electronic countermeasures must accurately identify target signals amidst high-density signals and implement jamming measures. This requires electronic countermeasure equipment to possess multi-dimensional screening methods to quickly and accurately identify target signals within this complex electromagnetic environment, including azimuth, elevation, amplitude, repetition rate, pulse width, and signal type.

[0003] Pulse width filtering is widely used in various jamming devices as an effective means of identifying different pulse width signals in complex electromagnetic environments. This function can eliminate narrow or wide pulse widths as needed. For self-defense jamming devices, when frequency, azimuth, elevation, and amplitude cannot accurately distinguish the wide pulses being jammed from the narrow pulse signals of other radars, the large amount of jamming resources required can lead to interference signals caused by false triggering of narrow pulse widths, which can significantly waste jamming resources. Therefore, it is particularly important to safely and effectively filter out narrow pulse width signals.

[0004] The traditional narrow pulse width filtering method counts the radar's detection signal. When the count value exceeds the pulse width currently required for filtering, a flag bit is used to notify the interference signal generation module, initiating operation. To ensure that the generation of this flag bit is synchronized with the arrival of the radar sampling signal at the interference signal generation module, the radar signal sampled by the ADC must be delayed. The length of this delay is the filtered pulse width. In practice, the narrow pulse width required for filtering each interference will vary depending on the task. Therefore, the traditional method of using D-type flip-flops to delay the signal at different times and then selecting data based on the requirements consumes a large number of D-type flip-flops and data selectors, significantly wasting FPGA logic resources. Therefore, achieving finer-step pulse width filtering control while conserving resources has become a pressing issue. Summary of the Invention

[0005] The present application provides a memory-based radar signal pulse width filtering method in an FPGA, which can be used to solve the technical problem that the existing technology cannot achieve the control of the pulse width filtering function with finer steps under the premise of controlling resources.

[0006] The method of the present application comprises the following steps:

[0007] The first step is ADC sampling and quantization. This involves sampling the input RF signal through an amplitude quantization ADC. Based on the amplitude of the input analog signal, a discrete level representing the input signal amplitude is obtained. This level can be represented by a binary code. At the same time, a detection threshold signal describing the pulse width is obtained through amplitude comparison and sent to the FPGA.

[0008] The second step is to combine the sampled data and the detection threshold into a data set, establish a data memory, and store the data set in the memory in a continuous storage manner. That is, regardless of whether the sampling signal or the detection threshold is valid, the write enable signal of the memory is always high and the write address is continuously accumulated;

[0009] The third step is data reading. The delay t is calculated based on the minimum pulse width of the signal to be filtered, and the delay is converted into the number of memory clock beats. This value is the difference between the write address and the read address of the memory. When reading data, a continuous reading method is also used. The read address of each beat is the write address minus the difference, and the read enable is always high. In this way, there is a fixed delay between the data read and the data written.

[0010] The fourth step is threshold processing. The threshold signal is extracted from the data read from the memory. Compared with the original threshold, this signal has undergone a delay of t. If the width meets the requirements after the AND operation with the original threshold, the rising edge of the signal generated by the AND operation is the rising edge of the delayed signal. The time relationship with the delayed ADC sampling data remains unchanged, and this rising edge can be used for subsequent signal processing.

[0011] Compared with the existing technology, the present invention has the following significant advantages: (1) the ADC sampling data or threshold signal is stored in the memory regardless of whether it is valid or not by adopting a continuous storage method, and there is no need to count and calculate the width of the continuous high level of the threshold signal; (2) the delay time determines the difference between the read and write addresses. By changing this value, different delays of the signal can be achieved, avoiding the situation where the delay value cannot be changed arbitrarily after the traditional use of D flip-flops for delay; (3) after reading the data according to the read address calculated by the delay value, the delay between the data read from the memory and the original data meets the requirements, and no data selection is required; (4) the read threshold detection signal and the original threshold detection signal are ANDed together to filter out the pulse signal that does not meet the requirements, and the relative relationship between the rising edge of the original threshold signal and the time of the ADC sampling data can also be retained. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is an algorithm diagram of the pulse width filtering module provided in the embodiment of the present application;

[0013] Figure 2 An example diagram of a data storage device provided in an embodiment of the present application;

[0014] Figure 3A schematic diagram of wide pulse width signal processing provided in an embodiment of the present application;

[0015] Figure 4 A schematic diagram of narrow pulse width signal processing provided in an embodiment of the present application. DETAILED DESCRIPTION

[0016] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0017] The following first introduces the embodiments of the present application with reference to the accompanying drawings.

[0018] Unlike the traditional method of counting radar signal threshold signals to filter out pulse widths smaller than the required value, this application achieves this by delaying the threshold signal and performing an AND operation. To meet different small pulse width filtering requirements in practical applications while saving resources, a memory-based method is used to store the radar signal sampling data and threshold comparison level in memory, which is then read out after a delay. The threshold levels before and after the delay are then ANDed together to ultimately filter out other signals with pulse widths smaller than the required value. This also ensures that the relationship between the delayed sampling data and the leading edge of the filtered threshold signal is consistent with that before the delay, facilitating subsequent signal processing.

[0019] In the first step, the RF signal is continuously sampled through the amplitude quantization ADC to convert the signal from analog to digital. At the same time, the RF analog signal is detected to obtain the corresponding detection threshold signal, which is then sent to the FPGA.

[0020] The second step is to combine the sampled data and the detection threshold into a data set, establish a data memory, and store the data set into the memory in a continuous storage manner;

[0021] There is no need to count and detect the width of the radar threshold comparison signal. Instead, the ADC sampling data is combined into a data set, and a memory that can be read and written at the same time is set. The bit width of the memory is equal to the sum of the bit width of the ADC sampling data and the signal detection level. The capacity of the memory is greater than the maximum pulse width to be filtered and meets the N-th power of 2, such as Figure 2 As shown,

[0022] The digital signal data obtained after ADC conversion adc and detection signal data dlva Synthetic data data, that is: data = {data adc , data dlva}, as the input data of the memory;

[0023] The write enable signal of the memory is always valid. The write address is accumulated in units of 1 and the clock signal as the beat from the start of the program. When the memory size is exceeded, it starts to accumulate again from zero. The size of the memory is the number of beats converted by the maximum pulse width to be filtered and is 2 to the power of N. The memory write address and write enable generation module are as follows: Figure 1 shown.

[0024] The third step is data reading, which uses a pipeline reading method. The read enable is always valid, and the difference between the read address and the write address is kept constant.

[0025] The required filtered pulse width is converted into the number of memory clock beats, which is the difference between the write address and the read address. When reading data, a pipeline read method is used, the read enable is always valid, and the difference between the read address and the write address is kept constant. Taking the filtered pulse width τ as an example, the read and write clock frequency is f clk , then the difference between the read and write addresses is Δaddr=τ×f clk , the read address is addr read =addr write -Δaddr, when the write address is less than Δaddr, the read address addr read =addr max +addr write -Δaddr, where addr max is the size of the memory.

[0026] Assume that the pulse width to be filtered is t and the FPGA internal clock frequency is f clk , the pulse width value is converted into the clock beat number τ×f clk At this time, the read address of the memory is obtained by subtracting this value from the write address. At the same time, the read enable signal is always valid. The time that the read data q lags behind the data written into the memory is the pulse width τ. By changing the size of τ, different delays of data are achieved, and the step is the internal clock frequency of the FPGA. The memory read address and read enable generation module is as follows: Figure 1 shown.

[0027] Step 4: Threshold signal processing

[0028] The delay length of the data read from the memory compared with the original data is the pulse width that needs to be filtered out. After the detection signal is delayed by t, when the pulse signal width does not meet the minimum pulse width requirement, compared with the original detection signal, there is no overlap between the two threshold detection signals. After the AND operation, the signal becomes low level, and the signal smaller than the minimum pulse width is filtered out;

[0029] When the pulse signal width is greater than the minimum pulse width requirement, the signal is retained and used as the threshold signal for final use.

[0030] Specifically, after pulse width filtering, the detection signal passes through the memory, and there is a delay of τ compared to the original signal. When there is a radar pulse signal, the delay between the two pulses is also τ. When the width of the radar pulse signal is greater than τ, there is overlap between the original detection level and the delayed detection level. After the two signals are ANDed, the rising edge is the position of the delayed detection signal, as shown in Figure 3 As shown, the relationship between the edge and the delayed ADC sampling data is maintained. At this time, the signal storage and delay counting of DRFM are re-performed based on the edge. When the width of the radar pulse signal is less than τ, the two signals are low level after the AND operation. At this time, the detection signal no longer exists, as shown in Figure 4 As shown, the stored ADC sampling data is discarded at the same time, and the pulse signal smaller than the pulse width is successfully filtered out.

[0031] The above-described embodiments of the present application do not constitute a limitation on the scope of protection of the present application.

Claims

1. A radar signal pulse width filtering method based on memory in FPGA, characterized in that: The method comprises: The first step is to continuously sample the RF signal through the amplitude quantization ADC, converting the signal from analog to digital. At the same time, the RF analog signal is detected to obtain the corresponding detection threshold signal, which is then sent to the FPGA. The second step is to combine the sampled data and the detection threshold into a data set, establish a data memory, and store the data set into the memory in a continuous storage manner; The third step is data reading, which uses a pipeline reading method. The read enable is always valid, and the difference between the read address and the write address is kept constant. The fourth step is threshold signal processing; The third step, data reading, uses a pipeline reading method, the read enable is always valid, and the difference between the read address and the write address is kept constant, including: The required filtered pulse width is converted into the number of memory clock beats, which is the difference between the write address and the read address. When reading data, a pipeline read method is adopted, the read enable is always valid, and the difference between the read address and the write address is kept constant; the filtered pulse width τ, the read and write clock frequency is f clk , then the difference between the read and write addresses is Δaddr=τ×f clk , the read address is addr read =addr write -Δaddr, when the write address is less than Δaddr, the read address addr read =addr max +addr write -Δaddr, where addr max is the size of the memory; By changing the size of τ, different delays of data are achieved, and the step is the internal clock frequency of FPGA; The fourth step is threshold signal processing, including: The delay length of the data read from the memory compared with the original data is the pulse width that needs to be filtered out. After the detection signal is delayed by t, when the pulse signal width does not meet the minimum pulse width requirement, compared with the original detection signal, there is no overlap between the two threshold detection signals. After the AND operation, the signal becomes low level, and the signal smaller than the minimum pulse width is filtered out. When the pulse signal width is greater than the minimum pulse width requirement, the signal is retained and used as the threshold signal for final use.

2. The method according to claim 1, characterized in that The second step is to combine the sampled data and the detection threshold into a data set, establish a data memory, and store the data set in the memory in a continuous storage manner; including: Set up a memory that can read and write at the same time. The bit width of the memory is equal to the sum of the bit width of the ADC sampling data and the signal detection level. The capacity of the memory is greater than the maximum pulse width to be filtered and meets the N-th power of 2. The digital signal data obtained after ADC conversion adc and detection signal data dlva Synthetic data data, that is: data={data adc , data dlva }, as the input data of the memory; The write enable signal of the memory is always valid. The write address is continuously accumulated in units of 1 and in cycles of the clock signal from the start of program execution. When the memory size is exceeded, it starts to accumulate again from zero.

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