Display device and driving method

Abstract

The present disclosure relates to the field of display technology, and discloses a display device and a driving method. The display device includes: at least two display panels that are spliced ​​together, the display panel includes multiple pixel circuits and a gating control circuit, the multiple pixel circuits include a target pixel circuit, the target pixel circuit is connected to the gating control circuit, a source driving circuit is connected to the display panel, the source driving circuit outputs a compensation data voltage to the target pixel circuit during a blank time period, and outputs a compensated data voltage to each pixel circuit according to a threshold compensation voltage during a display frame period, the gating control circuit is also connected to the source driving circuit, and during the blank time period, in response to a signal from a gating control terminal, provides a driving voltage signal generated after the target pixel circuit receives the compensation data voltage to the source driving circuit to determine the threshold compensation voltage. The setting of the gating control circuit compensates for the brightness difference between the at least two display panels at the splicing point, thereby improving the display effect.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology and provides a display device and a driving method. Background Art

[0002] In related technologies, due to differences in process technology, the pixel characteristics of the pixel units in each display panel of the spliced ​​screen are different. When the same data voltage is written in the above-mentioned display panels, the splicing points of adjacent display panels will show different display brightness, resulting in linear defects at the splicing points that are recognizable to the human eye, affecting the display effect. Summary of the Invention

[0003] Embodiments of the present disclosure provide a display device and a driving method for compensating for brightness differences at a joint of at least two display panels, thereby improving display effects.

[0004] The specific technical solutions provided by this disclosure are as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a display device, comprising: at least two display panels arranged in a spliced ​​manner, the display panel comprising a plurality of pixel circuits and a gating control circuit, the plurality of pixel circuits comprising a target pixel circuit, the target pixel circuit being connected to the gating control circuit;

[0006] At least two source driver circuits, the at least two source driver circuits being connected to the at least two display panels in a one-to-one correspondence, the source driver circuits being configured to output a compensated data voltage to a target pixel circuit during a blanking period, and to output a compensated data voltage to each target pixel circuit according to a threshold compensation voltage during a display frame period;

[0007] The gating control circuit is also connected to the source driving circuit. The gating control circuit is configured to provide a driving voltage signal generated after the target pixel circuit receives the compensation data voltage to the source driving circuit in response to a signal from the gating control terminal during the blank time period to determine the threshold compensation voltage, wherein the driving voltage signal is determined based on the compensation data voltage and the threshold voltage of the driving transistor in the target pixel circuit.

[0008] In some possible implementations provided by the present disclosure, at least two display panels include an adjacent first display panel and a second display panel, and the target pixel circuit in the first display panel and the target pixel circuit in the second display panel are located at the junction of the first display panel and the second display panel.

[0009] In some possible implementations provided by the present disclosure, the first display panel includes m rows and n columns of gate control circuits and m rows and n columns of target pixel circuits;

[0010] The gate control circuits in the m rows and n columns are connected to the target pixel circuits in the m rows and n columns in a one-to-one correspondence, where m and n are positive integers.

[0011] In some possible implementations provided by the present disclosure, the second display panel includes a row a and a column gating control circuit and a row a and a column b target pixel circuit;

[0012] The selection control circuits in row a and column b are connected to the target pixel circuits in row a and column b in one-to-one correspondence, where a and b are positive integers respectively.

[0013] In some possible implementations provided by the present disclosure, the target pixel circuit includes a driving transistor;

[0014] The gate control circuit is connected to the control terminal of the driving transistor.

[0015] In some possible implementations provided by the present disclosure, the gating control circuit includes: a gating transistor;

[0016] The control end of the gate transistor is connected to the gate control end, the first end of the gate transistor is connected to the source driving circuit, and the second end of the gate transistor is connected to the control end of the driving transistor.

[0017] In some possible implementations provided by the present disclosure, each display panel further includes a gate drive circuit;

[0018] In the same display panel, the gate driving circuit is connected to the gate control terminal in the target pixel circuit.

[0019] In some possible implementations provided by the present disclosure, each pixel circuit further includes a data writing transistor, wherein a first terminal of the data writing transistor is connected to a first terminal of the driving transistor;

[0020] Each display panel further includes a compensation gate driving circuit. In the same display panel, the compensation gate driving circuit is connected to the control terminal of the data writing transistor in the target pixel circuit.

[0021] In some possible implementations provided by the present disclosure, each display panel further includes a display gate driving circuit;

[0022] In the same display panel, the display gate driving circuit is connected to the control terminal of the data writing transistor in each pixel circuit.

[0023] In some possible implementations provided by the present disclosure, each pixel circuit further includes a reset transistor, wherein a first terminal of the reset transistor is connected to a control terminal of the drive transistor;

[0024] Each display panel further includes a first reset gate driving circuit. In the same display panel, the first reset gate driving circuit is connected to the control terminal of the reset transistor in the target pixel circuit.

[0025] In some possible implementations provided by the present disclosure, each display panel further includes a second reset gate driving circuit. In the same display panel, the second reset gate driving circuit is connected to the control terminal of the reset transistor in each pixel circuit.

[0026] In some possible implementations provided by the present disclosure, it further includes a mobile phone motherboard end;

[0027] The mobile phone mainboard end is connected to at least two source driving circuits, and the mobile phone mainboard end is configured to determine the threshold voltage of the driving transistor in each target pixel circuit based on the driving voltage signal and the compensation data voltage signal, determine the threshold voltage average based on each threshold voltage, and determine the threshold compensation voltage based on the threshold voltage average and the threshold voltage.

[0028] In a second aspect, an embodiment of the present disclosure further provides a method for driving any of the above display devices, comprising:

[0029] During the blanking period, the source driving circuit outputs the compensation data voltage to the target pixel circuit; the gating control circuit provides the driving voltage signal generated by the target pixel circuit after receiving the compensation data voltage to the source driving circuit to determine the threshold compensation voltage, wherein the driving voltage signal is determined according to the compensation data voltage and the threshold voltage of the driving transistor in the target pixel circuit;

[0030] During a display frame phase, the source driving circuit outputs a compensated data voltage to each target pixel circuit according to the threshold compensation voltage.

[0031] The beneficial effects of the present disclosure are as follows:

[0032] In summary, a display device and a driving method are provided in an embodiment of the present disclosure. The display device includes: at least two display panels arranged in a spliced ​​manner, the display panels including a plurality of pixel circuits and a gating control circuit, the plurality of pixel circuits including a target pixel circuit, the target pixel circuit being connected to the gating control circuit, at least two source driving circuits, the at least two source driving circuits being connected to the at least two display panels in a one-to-one correspondence, the source driving circuit being configured to output a compensated data voltage to the target pixel circuit during a blank time period, and to output a compensated data voltage to each pixel circuit according to a threshold compensation voltage during a display frame period, the gating control circuit being further connected to the source driving circuit, and the gating control circuit being configured to output a compensated data voltage to the target pixel circuit during a blank time period, and to output a compensated data voltage to each pixel circuit according to a threshold compensation voltage during a display frame period, the gating control circuit being further connected to the source driving circuit, and the gating control circuit being configured to output a compensated data voltage to each pixel circuit according to a threshold compensation voltage during a display frame period, The circuit is configured to provide a driving voltage signal generated after the target pixel circuit receives the compensated data voltage to the source driving circuit in response to a signal from the selection control terminal during the blank time period to determine the threshold compensation voltage, wherein the driving voltage signal is determined based on the compensated data voltage and the threshold voltage of the driving transistor in the target pixel circuit. The setting of the above-mentioned selection control circuit realizes the extraction of the driving voltage signal during the blank time period, and further determines the threshold compensation voltage based on the driving voltage signal, so that the source driving circuit outputs the compensated data voltage to each pixel circuit during the display frame stage, thereby compensating for the brightness difference at the splicing point of at least two display panels and improving the display effect.

[0033] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. The purposes and other advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0035] Figure 1 This is a connection diagram of a splicing screen in the related art;

[0036] Figure 2 Schematic diagram of the connection between a display panel and a source driving circuit in a display device according to an embodiment of the present disclosure;

[0037] Figure 3 This is a connection diagram of a display device according to an embodiment of the present disclosure;

[0038] Figure 4 is a circuit connection diagram of a display device according to an embodiment of the present disclosure;

[0039] Figure 5is a connection diagram between a gating control circuit and a target pixel circuit in an embodiment of the present disclosure;

[0040] Figure 6 is a circuit structure diagram of a display device according to an embodiment of the present disclosure;

[0041] Figure 7 Schematic diagram of the connection of the first pixel circuit in the embodiment of the present disclosure;

[0042] Figure 8 is a circuit structure diagram of a first pixel circuit in an embodiment of the present disclosure;

[0043] Figure 9 Schematic diagram of the connection of the second pixel circuit in the embodiment of the present disclosure;

[0044] Figure 10 is a circuit structure diagram of a second pixel circuit in an embodiment of the present disclosure;

[0045] Figure 11 2 is a connection diagram of a third pixel circuit in an embodiment of the present disclosure;

[0046] Figure 12 is a circuit structure diagram of a fourth pixel circuit in an embodiment of the present disclosure;

[0047] Figure 13 This is a schematic diagram of the connection between the source driver circuit and the mobile phone mainboard in the embodiment of the present disclosure;

[0048] Figure 14 Schematic diagram of the connection between the display panel and each gate driving circuit in an embodiment of the present disclosure;

[0049] Figure 15 Schematic diagram of the distribution of gate driving circuits in a display panel according to an embodiment of the present disclosure;

[0050] Figure 16 This is a working timing diagram of a display device according to an embodiment of the present disclosure;

[0051] Figure 17 This is a flowchart of a driving method applied to a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the technical solutions of the present disclosure, but not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments described in this disclosure without making any creative efforts shall fall within the scope of protection of the technical solutions of the present disclosure.

[0053] The terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be practiced using orders other than those illustrated or described herein.

[0054] In related technologies, the use of spliced ​​screens is becoming increasingly common. With the continuous development of AMOLED flexible display technology, new applications such as flexible special-shaped displays are constantly being explored. Among them, spliced ​​display products in the AMOLED field are developing rapidly. However, due to differences in process technology, the pixel characteristics of each display panel in the spliced ​​screen are different. When the same data voltage is written to each of the above display panels, the spliced ​​area of ​​adjacent display panels will show different brightness.

[0055] For example, see Figure 1 As shown, the spliced ​​screen includes four display panels: display panel 1, display panel 2, display panel 3 and display panel 4. Figure 1 The four display panels arranged in this manner form four seams, namely, seams 1, 2, 3 and 4. The pixel characteristics (for example, threshold voltage Vth) of the pixel units at the above-mentioned seams will be different due to different process steps, resulting in different driving currents of the pixel units at the seams, and thus different display brightness at the seams. That is, there are defective seams that can be detected by the human eye, which affects the screen display effect and product yield.

[0056] The preferred embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0057] A display device proposed in an embodiment of the present application includes: at least two display panels spliced ​​together, the display panel includes multiple pixel circuits and a gating control circuit 00, the multiple pixel circuits include a target pixel circuit 10, and the target pixel circuit 10 is connected to the gating control circuit 00.

[0058] The following first introduces the display panel in the embodiment of the present application. The above-mentioned display device includes at least two display panels arranged in a spliced ​​manner, and at least one spliced ​​portion is formed between the at least two display panels. Each display panel includes multiple pixel circuits and a gating control circuit 00, wherein the pixel circuit includes multiple target pixel circuits 10, that is, the display panel includes multiple pixel units, each pixel unit is connected to a pixel circuit or a target pixel circuit 10. Preferably, the pixel units at the spliced ​​portion of the display panel are connected to the target pixel circuit 10, and the pixel units at the non-spliced ​​portion of the display panel are connected to the pixel circuit.

[0059] The above-mentioned pixel circuit and the target pixel circuit 10 have the same circuit composition, and both the pixel circuit and the target pixel circuit 10 are connected to the source driving circuit. The difference is that the target pixel circuit 10 also needs to be connected to the selection control circuit 00, that is, the selection control circuit 00 is used to compensate for the threshold voltage of the pixel unit at the splicing point, thereby improving the display effect of the pixel unit at the splicing point.

[0060] See Figure 2 As shown, the display panel a is connected to the source driver circuit a, and the display panel a includes k pixel circuits, namely pixel circuit 1 to pixel circuit k, and the above k pixel circuits are all connected to the source driver circuit a. At the same time, the display panel a also includes L target pixel circuits, namely target pixel circuit 1 to target pixel circuit L, and the above L target pixel circuits are also connected to the source driver circuit a. In order to perform threshold compensation on the target pixel circuit 10, the display panel a also includes L gating control circuits, namely gating control circuit 1 to gating control circuit L, and the above L gating control circuits are respectively connected to the L target pixel circuits 10 in a one-to-one correspondence. In the embodiment of the present application, the gating control circuit 00 is triggered by the signal of the gating control terminal, that is, each gating control circuit 00 is connected to a gating control terminal SEN in a one-to-one correspondence. When the signal of the gating control terminal SEN is valid, the gating control circuit 00 starts working.

[0061] Exemplarily, the at least two display panels include adjacent first and second display panels, and the target pixel circuit 10 in the first display panel and the target pixel circuit 10 in the second display panel are located at a joint between the first and second display panels.

[0062] See Figure 3 As shown, a certain spliced ​​screen is configured by splicing display panel a and display panel b vertically, wherein display panel a is connected to source driver circuit a, and display panel b is connected to source driver circuit b. The above-mentioned display panel a includes k pixel circuits, namely pixel circuit a1 to pixel circuit ak, and the above-mentioned k pixel circuits are all connected to source driver circuit a. At the same time, display panel a also includes x target pixel circuits, namely target pixel circuit a1 to target pixel circuit ax, and the above-mentioned x target pixel circuits are also connected to source driver circuit a. In order to perform threshold compensation on the target pixel circuits, display panel a also includes x gating control circuits, namely gating control circuit a1 to gating control circuit ax, and the above-mentioned x gating control circuits are respectively connected to the x target pixel circuits in a one-to-one correspondence.

[0063] The display panel b includes k pixel circuits, namely pixel circuit b1 through pixel circuit bk, each of which is connected to the source driver circuit b. Furthermore, the display panel b also includes y target pixel circuits, namely target pixel circuit b1 through target pixel circuit by, each of which is also connected to the source driver circuit b. To perform threshold compensation on the target pixel circuits, the display panel b also includes y gating control circuits, namely gating control circuit b1 through gating control circuit by, each of which is connected in a one-to-one correspondence with the y target pixel circuits 10.

[0064] Exemplarily, the first display panel includes m rows and n columns of gate control circuits and m rows and n columns of target pixel circuits.

[0065] The gate control circuits 00 in the mth row and the nth column and the target pixel circuits 10 in the mth row and the nth column are connected in a one-to-one correspondence, where m and n are positive integers.

[0066] Exemplarily, the second display panel includes a row and b columns of gate control circuits and a row and b columns of target pixel circuits 10 .

[0067] The strobe control circuits 00 in row a and column b are connected to the target pixel circuits 10 in row a and column b in a one-to-one correspondence, where a and b are positive integers.

[0068] It is also necessary to add that, see Figure 3 As shown, the display panel a and the display panel b are spliced ​​together to form a splice, which includes a target pixel circuit located in the x row and 1 column of the display panel a and a target pixel circuit 10 located in the y row and 1 column of the display panel b. Accordingly, the number of the gate control circuits 00 in the display panel a is also x, and the number of the gate control circuits in the display panel b is also y. The connection relationship between each gate control circuit 00 and each target pixel circuit 10 is shown in FIG. Figure 3 As shown, I will not go into details here.

[0069] For example, see Figure 4 As shown, the target pixel circuits 10 in display panel 1 have a total of m rows and n columns, and each target pixel circuit 10 is connected to the source driver circuit 1 via the gate control circuits M111…M1mn. The target pixel circuits 10 in display panel 2 have a total of m rows and n columns, and each target pixel circuit 10 is connected to the source driver circuit 2 via the gate control circuits M211…M2mn. The target pixel circuits in display panel 3 have a total of m rows and n columns, and each target pixel circuit 10 is connected to the source driver circuit 3 via the gate control circuits M311…M3mn. The target pixel circuits 10 in display panel 4 have a total of m rows and n columns, and each target pixel circuit 10 is connected to the source driver circuit 4 via the gate control circuits M411…M4mn.

[0070] The above-mentioned selection control circuit 00 is also connected to the source driving circuit. The selection control circuit 00 is configured to provide the driving voltage signal generated after the target pixel circuit 10 receives the compensation data voltage to the source driving circuit in response to the signal of the selection control terminal SEN during the blank time period to determine the threshold compensation voltage, wherein the driving voltage signal is determined based on the compensation data voltage and the threshold voltage of the driving transistor in the target pixel circuit 10.

[0071] In the embodiment of the present application, the threshold compensation voltage is obtained based on the driving voltage signal, and the driving voltage signal is obtained by the gate control circuit 00. During implementation, during the blanking period, which is usually between two display frames, and when the signal of the gate control terminal SEN is valid, the gate control circuit SEN provides the driving voltage signal to the source driver circuit. The driving voltage signal is the difference between the compensation data voltage and the threshold voltage of the driving transistor DTFT in the target pixel circuit.

[0072] In addition, see Figure 5 and Figure 6 As shown, the target pixel circuit 10 in the embodiment of the present application includes a driving transistor DTFT.

[0073] The gate control circuit 00 is connected to the control terminal of the driving transistor DTFT.

[0074] For example, see Figure 6 As shown, the gating control circuit 00 includes: a gating transistor M1.

[0075] The control terminal of the gate transistor M1 is connected to the gate control terminal SEN, the first terminal of the gate transistor M1 is connected to the source driving circuit, and the second terminal of the gate transistor M1 is connected to the control terminal of the driving transistor DTFT.

[0076] Exemplarily, the gate transistor M1 can be turned on under the control of the active level of the gate control terminal SEN, and can be turned off under the control of the inactive level of the gate control terminal SEN. Exemplarily, if the gate transistor M1 is configured as an N-type transistor, the active level of the signal at the gate control terminal SEN is a high level, and the inactive level of the signal at the gate control terminal SEN is a low level. Alternatively, if the gate transistor M1 is configured as a P-type transistor, the active level of the signal at the gate control terminal SEN is a low level, and the inactive level of the signal at the gate control terminal SEN is a high level.

[0077] See Figure 6 As shown, the selection transistor M1 is a P-type transistor. When the signal of the selection control terminal SEN is at a low level, the selection transistor M1 is turned on, and the driving voltage signal of the control terminal of the driving transistor DTFT is provided to the source driving circuit through the turned-on selection transistor M1.

[0078] The following continues to introduce the circuit composition of the pixel circuit (including the target pixel circuit 10) in this application.

[0079] See Figure 7 As shown, the pixel circuit includes: a driving transistor DTFT, a light-emitting device OLED, a conduction control subcircuit 10, a data writing subcircuit 20, a first light-emitting control subcircuit 30 and a second light-emitting control subcircuit 40.

[0080] The driving transistor DTFT is configured to generate a driving current according to the compensated data voltage.

[0081] In an embodiment of the present application, during the blank time period, the light-emitting device OLED in the pixel circuit does not emit light, that is, the driving transistor DTFT does not generate current according to the driving voltage signal; during the display frame stage, the driving transistor DTFT can generate a driving current according to the compensation data voltage, thereby causing the light-emitting device OLED to emit light under the action of the driving current.

[0082] See Figure 8 As shown, the conduction control subcircuit 10 is connected to the control terminal and the second terminal of the driving transistor DTFT, and is configured to conduct the control terminal and the second terminal of the driving transistor DTFT in response to the signal of the scanning signal terminal Gate.

[0083] See Figure 8 As shown, the conduction control subcircuit 10 includes: a first transistor T1.

[0084] The control end of the first transistor T1 is connected to the scan signal end Gate, the first end of the first transistor T1 is connected to the control end of the driving transistor DTFT, and the second end of the first transistor T1 is connected to the second end of the driving transistor DTFT.

[0085] Exemplarily, the first transistor T1 can be turned on under the control of the active level of the scan signal terminal Gate, and can be turned off under the control of the inactive level of the scan signal terminal Gate. Exemplarily, if the first transistor T1 is configured as an N-type transistor, the active level of the signal at the scan signal terminal Gate is a high level, and the inactive level of the signal at the scan signal terminal Gate is a low level. Alternatively, if the first transistor T1 is configured as a P-type transistor, the active level of the signal at the scan signal terminal Gate is a low level, and the inactive level of the signal at the scan signal terminal Gate is a high level.

[0086] See Figure 8 As shown, the first transistor T1 is a P-type transistor. When the signal of the scanning signal terminal Gate is at a low level, the first transistor T1 is turned on, and the control terminal of the driving transistor DTFT is turned on through the turned-on first transistor T1 and the second terminal of the driving transistor DTFT.

[0087] See Figure 8 As shown, the data writing sub-circuit 20 is connected to the first end of the driving transistor DTFT and is configured to respond to the signal of the scanning signal terminal Gate with different timings to provide the preselected data voltage and the compensation data voltage of the data signal terminal to the first end of the driving transistor DTFT respectively.

[0088] See Figure 8 As shown, the data writing sub-circuit 20 includes: a data writing transistor M2.

[0089] The control end of the data writing transistor M2 is connected to the scan signal end Gate, the first end of the data writing transistor M2 is connected to the first end of the driving transistor DTFT, and the second end of the data writing transistor M2 is connected to the data signal end.

[0090] Exemplarily, the data write transistor M2 can be turned on under the control of the active level of the scan signal terminal Gate, and can be turned off under the control of the inactive level of the scan signal terminal Gate. Exemplarily, if the data write transistor M2 is configured as an N-type transistor, the active level of the signal at the scan signal terminal Gate is a high level, and the inactive level of the signal at the scan signal terminal Gate is a low level. Alternatively, if the data write transistor M2 is configured as a P-type transistor, the active level of the signal at the scan signal terminal Gate is a low level, and the inactive level of the signal at the scan signal terminal Gate is a high level.

[0091] See Figure 8 As shown, the data writing transistor M2 is a P-type transistor. When the signal of the scanning signal terminal Gate is at a low level, the data writing transistor M2 is turned on, and the compensated data voltage of the data signal terminal or the compensated data voltage is provided to the first end of the driving transistor DTFT through the turned-on data writing transistor M2.

[0092] See Figure 8 As shown, the first light emitting control sub-circuit 30 is connected to the first power supply terminal ELVDD and the first end of the driving transistor DTFT, and is configured to connect the first end of the driving transistor DTFT to the first power supply terminal ELVDD in response to the signal of the first light emitting control signal terminal EM.

[0093] See Figure 8 As shown, the first light emitting control sub-circuit 30 includes: a second transistor T2.

[0094] The control end of the second transistor T2 is connected to the first light emitting control signal end EM, the first end of the second transistor T2 is connected to the first power supply end ELVDD, and the second end of the second transistor T2 is connected to the first end of the driving transistor DTFT and the first end of the data writing transistor M2.

[0095] Exemplarily, the second transistor T2 can be turned on under the control of the active level of the first light-emitting control signal terminal EM, and can be turned off under the control of the inactive level of the first light-emitting control signal terminal EM. Exemplarily, if the second transistor T2 is configured as an N-type transistor, the active level of the signal at the first light-emitting control signal terminal EM is a high level, and the inactive level of the signal at the first light-emitting control signal terminal EM is a low level. Alternatively, if the second transistor T2 is configured as a P-type transistor, the active level of the signal at the first light-emitting control signal terminal EM is a low level, and the inactive level of the signal at the first light-emitting control signal terminal EM is a high level.

[0096] See Figure 8 As shown, the second transistor T2 is a P-type transistor. When the signal of the first light-emitting control signal terminal EM is at a low level, the second transistor T2 is turned on, and the first power supply terminal ELVDD is turned on through the turned-on second transistor T2, the first terminal of the driving transistor DTFT, and the first terminal of the data writing transistor M2.

[0097] See Figure 8 As shown, the second light emitting control sub-circuit 40 is connected to the anode of the light emitting device OLED and the second end of the driving transistor DTFT, and is configured to connect the second end of the driving transistor DTFT to the anode of the light emitting device OLED in response to the signal of the first light emitting control signal terminal EM.

[0098] See Figure 8 As shown, the second light emitting control sub-circuit 40 includes: a third transistor T3.

[0099] The control end of the third transistor T3 is connected to the first light emitting control signal end EM, the first end of the third transistor T3 is connected to the second end of the driving transistor DTFT, and the second end of the third transistor T3 is connected to the anode of the light emitting device OLED.

[0100] Exemplarily, the third transistor T3 can be turned on under the control of the active level of the first light-emitting control signal terminal EM, and can be turned off under the control of the inactive level of the first light-emitting control signal terminal EM. Exemplarily, if the third transistor T3 is configured as an N-type transistor, the active level of the signal at the first light-emitting control signal terminal EM is a high level, and the inactive level of the signal at the first light-emitting control signal terminal EM is a low level. Alternatively, if the third transistor T3 is configured as a P-type transistor, the active level of the signal at the first light-emitting control signal terminal EM is a low level, and the inactive level of the signal at the first light-emitting control signal terminal EM is a high level.

[0101] See Figure 8As shown, the third transistor T3 is a P-type transistor. When the signal of the first light-emitting control signal terminal EM is at a low level, the third transistor T3 is turned on, and the second end of the driving transistor DTFT is connected to the anode of the light-emitting device OLED through the turned-on third transistor T3.

[0102] See Figure 8 As shown, the above pixel circuit further includes a first capacitor C1.

[0103] A first end of the first capacitor C1 is connected to the first power supply terminal ELVDD and the first end of the second transistor T2 , and a second end of the first capacitor C1 is connected to the control end of the driving transistor DTFT and the first end of the first transistor T1 .

[0104] The first capacitor C1 is provided between the first power supply terminal ELVDD and the control terminal of the driving transistor DTFT. The driving voltage signal of the driving transistor DTFT can be obtained by utilizing the voltage stabilization function of the first capacitor C1.

[0105] See Figure 9 As shown, the above pixel circuit further includes a first reset sub-circuit 50 .

[0106] See Figure 10 As shown, the first reset sub-circuit 50 is connected to the second end of the first capacitor C1, the control end of the driving transistor DTFT and the first end of the first transistor T1, and is configured to respond to the signal of the first reset signal end Reset and provide the signal of the first initialization signal end Vint to the second end of the first capacitor C1, the control end of the driving transistor DTFT and the first end of the first transistor T1.

[0107] During the implementation process, when the signal of the first reset signal terminal Reset is valid, the first reset sub-circuit 50 is turned on, and the signal of the first initialization signal terminal Vint is provided to the second end of the first capacitor C1, the control end of the driving transistor DTFT and the first end of the first transistor T1 through the turned-on first reset sub-circuit 50.

[0108] See Figure 10 As shown, the first reset sub-circuit 50 includes: a reset transistor M3.

[0109] The control end of the reset transistor M3 is connected to the first reset signal end Reset, the first end of the reset transistor M3 is connected to the second end of the first capacitor C1, the control end of the driving transistor DTFT and the first end of the first transistor T1, and the second end of the reset transistor M3 is connected to the first initialization signal end Vint.

[0110] Exemplarily, the reset transistor M3 can be turned on under the control of the active level of the first reset signal terminal Reset, and can be turned off under the control of the inactive level of the first reset signal terminal Reset. Exemplarily, if the reset transistor M3 is configured as an N-type transistor, the active level of the signal at the first reset signal terminal Reset is a high level, and the inactive level of the signal at the first reset signal terminal Reset is a low level. Alternatively, if the reset transistor M3 is configured as a P-type transistor, the active level of the signal at the first reset signal terminal Reset is a low level, and the inactive level of the signal at the first reset signal terminal Reset is a high level.

[0111] See Figure 10 As shown, the reset transistor M3 is a P-type transistor. When the signal of the first reset signal terminal Reset is at a low level, the reset transistor M3 is turned on, and the signal of the first initialization signal terminal Vint is provided to the second end of the first capacitor C1, the control end of the driving transistor DTFT and the first end of the first transistor T1 through the turned-on reset transistor M3.

[0112] See Figure 11 As shown, the above pixel circuit further includes a second reset sub-circuit 60 .

[0113] The second reset sub-circuit 60 is connected to the anode of the light-emitting device OLED and the second end of the third transistor T3, and is configured to provide the signal of the first initialization signal terminal Vint to the anode of the light-emitting device OLED and the second end of the third transistor T3 in response to the signal of the scan signal terminal Gate.

[0114] During implementation, when the signal at the scanning signal terminal Gate is valid, the second reset subcircuit 60 is turned on, and the signal at the first initialization signal terminal Vint is provided to the anode of the light emitting device OLED and the second terminal of the third transistor T3 via the turned-on second reset subcircuit 60 .

[0115] See Figure 12 As shown, the second reset sub-circuit 60 includes: a fourth transistor T4.

[0116] The control end of the fourth transistor T4 is connected to the scan signal end Gate, the first end of the fourth transistor T4 is connected to the anode of the light emitting device OLED and the second end of the third transistor T3, and the second end of the fourth transistor T4 is connected to the first initialization signal end Vint.

[0117] Exemplarily, the fourth transistor T4 can be turned on under the control of the active level of the scan signal terminal Gate, and can be turned off under the control of the inactive level of the scan signal terminal Gate. Exemplarily, the fourth transistor T4 is configured as an N-type transistor, then the active level of the signal at the scan signal terminal Gate is a high level, and the inactive level of the signal at the scan signal terminal Gate is a low level. Alternatively, the fourth transistor T4 is configured as a P-type transistor, then the active level of the signal at the scan signal terminal Gate is a low level, and the inactive level of the signal at the scan signal terminal Gate is a high level.

[0118] See Figure 12 As shown, the fourth transistor T4 is a P-type transistor. When the signal of the scanning signal terminal Gate is at a low level, the fourth transistor T4 is turned on, and the signal of the first initialization signal terminal Vint is provided to the anode of the light-emitting device OLED and the second end of the third transistor T3 through the turned-on fourth transistor T4.

[0119] After introducing the pixel circuit and the target pixel circuit 10 in the embodiment of the present application, the source driving circuit and the gate control circuit 00 in the embodiment of the present application are specifically introduced below.

[0120] The display device in the embodiment of the present application includes: at least two source driving circuits, the at least two source driving circuits are connected to at least two display panels in a one-to-one correspondence, and the source driving circuit is configured to output a compensated data voltage to the target pixel circuit 10 during the blank time period, and to output a compensated data voltage to each pixel circuit according to the threshold compensation voltage during the display frame period.

[0121] In the embodiment of the present application, each display panel operates independently under the drive of the corresponding source driver circuit. That is, during the blanking period, the source driver circuit outputs a compensated data voltage to the target pixel circuit 10, thereby obtaining a drive voltage signal. During the display frame period, the source driver circuit outputs the compensated data voltage to the target pixel circuit 10, thereby compensating for the brightness difference between at least two display panels at the splicing point.

[0122] At the same time, in order to obtain the compensated data voltage based on the acquired driving voltage signals of each display panel, in one embodiment, each source driving circuit can be connected to each other, and one of the source driving circuits is selected as the executor for calculating the compensated data voltage, that is, the source driving circuits connected to each display panel respectively send the compensated data voltage and the acquired driving voltage signal to the source driving circuit, and the source driving circuit calculates the final compensated data voltage based on the compensated data voltage and each driving voltage signal. The source driving circuit will also send the compensated data voltage to each source driving circuit respectively, and then the source driving circuit provides the compensated data voltage to each pixel circuit.

[0123] In another embodiment, see Figure 13 As shown, the above-mentioned display device also includes a mobile phone mainboard end.

[0124] The mobile phone motherboard end is connected to at least two source driving circuits, and the mobile phone motherboard end is configured to determine the threshold voltage of the driving transistor DTFT in each target pixel circuit 10 according to the driving voltage signal and the compensation data voltage signal, determine the threshold voltage average according to each threshold voltage, and determine the threshold compensation voltage according to the threshold voltage average and the threshold voltage.

[0125] Each source driver circuit is connected to the mobile phone motherboard terminal, for example, see Figure 13 As shown, source driver circuit 1, source driver circuit 2, source driver circuit 3...source driver circuit n are all connected to the mobile phone motherboard. During implementation, each source driver circuit sends the compensated data voltage and the acquired drive voltage signal to the mobile phone motherboard, and the mobile phone motherboard calculates the final compensated data voltage based on the compensated data voltage and each drive voltage signal. During specific implementation, for any display panel, the mobile phone motherboard will determine the threshold voltage of the driving transistor DTFT in each target pixel circuit based on the drive voltage signal and the compensated data voltage signal, and then determine the threshold voltage average based on each threshold voltage, and determine the threshold compensation voltage based on the threshold voltage average and the threshold voltage. The source driver circuit will also calculate the threshold compensation voltage, so that the source driver circuit can calculate the compensated data voltage based on the threshold compensation voltage and provide the compensated data voltage to each pixel circuit.

[0126] In addition, see Figure 14 As shown, each display panel further includes a gate driving circuit.

[0127] In the same display panel, the gate driving circuit is connected to the gate control terminal SEN in the target pixel circuit.

[0128] In the embodiments of this application, see Figure 14 As shown, for the same display panel, the selection gate driving circuit is connected to the selection control terminal SEN in the target pixel circuit. For example, the selection gate driving circuit 1 is connected to the selection control circuit 1 via the selection control terminal 1... The selection gate driving circuit L is connected to the selection control circuit L via the selection control terminal L.

[0129] During the blank time period, each gate driving circuit sends a valid gate control terminal SEN signal to the connected gate control terminal SEN, so that each gate control circuit 00 obtains a driving voltage signal.

[0130] See Figure 14As shown, each display panel further includes a compensation gate driving circuit. In the same display panel, the compensation gate driving circuit is connected to the control end of the data writing transistor M2 in the target pixel circuit.

[0131] In the embodiments of this application, see Figure 14 As shown, for the same display panel, the compensation gate driving circuit is connected to the control terminal of the data writing transistor M2 in the target pixel circuit. Exemplarily, the compensation gate driving circuit L is connected to the data writing transistor M211 in the target pixel circuit L via the control terminal L1.

[0132] During the blank time period, each compensation gate driving circuit sends a valid signal to the connected control terminal, so that the data writing transistor M2 of each target pixel circuit writes the compensation data voltage to the control terminal of the driving transistor DTFT.

[0133] See Figure 14 As shown, each display panel further includes a first reset gate driving circuit. In the same display panel, the first reset gate driving circuit is connected to the control terminal of the reset transistor M3 in the target pixel circuit 10 .

[0134] In the embodiments of this application, see Figure 14 As shown, for the same display panel, the first reset gate driving circuit is connected to the control terminal of the reset transistor M3 in the target pixel circuit. Exemplarily, the first reset gate driving circuit L is connected to the reset transistor M3 in the target pixel circuit L via the control terminal L2.

[0135] During the blank time period, each first reset gate driving circuit sends a valid signal to the connected control terminal, thereby resetting the reset transistor M3 of each target pixel circuit, specifically resetting the control terminal of the driving transistor DTFT.

[0136] See Figure 14 As shown, each display panel further includes a second reset gate driving circuit. In the same display panel, the second reset gate driving circuit is connected to the control end of the reset transistor M3 in each pixel circuit.

[0137] In the embodiments of this application, see Figure 14 As shown, for the same display panel, the second reset gate driver circuit is connected to the control terminal of the reset transistor M3 in each pixel circuit. The second reset gate driver circuit is configured to reset the signal during the display frame phase. For example, the second reset gate driver circuit 11 is connected to the reset transistor M311 in the pixel circuit 1 via the control terminal 12. It should be noted that the second reset gate driver circuit also needs to be connected to the target pixel circuit 10, which will not be further described here.

[0138] See Figure 14 As shown, each display panel also includes a display gate driving circuit.

[0139] In the same display panel, the display gate driving circuit is connected to the control end of the data writing transistor M2 in each pixel circuit.

[0140] In the embodiments of this application, see Figure 14 As shown, for the same display panel, the display gate driver circuit is connected to the control terminal of the data write transistor M2 in each pixel circuit. For example, the display gate driver circuit 11 is connected to the data write transistor M211 in the pixel circuit 1 via the control terminal 11. It should be noted that the display gate driver circuit also needs to be connected to the target pixel circuit 10, which will not be repeated here.

[0141] During implementation, in a display frame phase, when the display gate driving circuit sends a valid signal to the corresponding control terminal, the compensated data voltage is written into the data writing transistor M2 of each pixel circuit and each target pixel circuit 10 .

[0142] In addition, in the embodiment of the present application, the gate drive circuit, the compensation gate drive circuit, the first reset gate drive circuit, the second reset gate drive circuit and the display gate drive circuit are generally arranged in the non-display area of ​​the display panel. In addition, in order to facilitate layout and wiring, the gate drive circuit, the compensation gate drive circuit and the first reset gate drive circuit are generally arranged on one side of the display panel, and the second reset gate drive circuit and the display gate drive circuit are generally arranged on the other side of the display panel. Figure 15 shown.

[0143] It is also necessary to explain that in order to make the blank time phase and the display frame phase work in a time-sharing manner, see Figure 15 As shown, the above-mentioned second reset gate drive circuit and the display gate drive circuit are usually connected to the first frame start signal terminal, the above-mentioned selection gate drive circuit, the compensation gate drive circuit and the first reset gate drive circuit are usually connected to the second frame start signal terminal, the signal waveform of the above-mentioned second frame start signal terminal is different from that of the first frame start signal terminal, and the valid signal of the second frame start signal terminal is earlier than the valid signal of the first frame start signal terminal.

[0144] The following combination Figure 15 and timing Figure 16 The working process of the pixel circuit (including the target pixel circuit) in the display device in the embodiment of the present application is described in detail.

[0145] Timing t01 stage: STV2 = 0, STV1 = 1, Reset = 1, Gate = 1, SEN = 1, EM = 1

[0146] When the second frame start signal terminal is at a low level, the gate drive circuit, the compensation gate drive circuit and the first reset gate drive circuit start to operate.

[0147] Timing t02 stage: STV2 = 1, STV1 = 1, Reset = 0, Gate = 1, SEN = 1, EM = 1

[0148] The signal of the first reset signal terminal Reset is at a low level, the reset transistor M3 is turned on, and the signal of the first initialization signal terminal Vint is provided to the second terminal of the first capacitor C1, the control terminal of the driving transistor DTFT and the first terminal of the first transistor T1 via the turned-on reset transistor M3.

[0149] Timing t03 stage: STV2 = 1, STV1 = 1, Reset = 1, Gate = 0, SEN = 1, EM = 1

[0150] The signal at the scan signal terminal Gate is at a low level, the data writing transistor M2 is turned on, and the compensation data voltage at the data signal terminal is provided to the first terminal of the driving transistor DTFT through the turned-on data writing transistor M2; the signal at the scan signal terminal Gate is at a low level, the first transistor T1 is turned on, and the compensation data voltage is provided to the second terminal of the driving transistor DTFT through the turned-on driving transistor DTFT, and the compensation data voltage is provided from the second terminal of the driving transistor DTFT to the control terminal of the driving transistor DTFT through the turned-on first transistor T1, thereby causing the driving transistor DTFT to generate a driving voltage signal; the signal at the scan signal terminal Gate is at a low level, the fourth transistor T4 is turned on, and the signal of the first initialization signal terminal Vint is provided to the anode of the light-emitting device OLED and the second terminal of the third transistor T3 through the turned-on fourth transistor T4, thereby resetting the anode of the light-emitting device OLED and the second terminal of the third transistor T3.

[0151] Timing stage t04: STV2 = 1, STV1 = 1, Reset = 1, Gate = 1, SEN = 0, EM = 1

[0152] The signal of the selection control terminal SEN is low level, the selection transistor M1 is turned on, and the driving voltage signal of the control terminal of the driving transistor DTFT is provided to the source driving circuit through the turned-on selection transistor M1, so that the driving transistor DTFT obtains the compensated data voltage.

[0153] Timing t11 stage: STV2 = 1, STV1 = 0, Reset = 1, Gate = 1, SEN = 1, EM = 1

[0154] When the first frame start signal terminal is at a low level, the second reset gate driving circuit and the display gate driving circuit start to work.

[0155] Timing t21 stage: STV2 = 1, STV1 = 1, Reset = 0, Gate = 1, SEN = 1, EM = 1

[0156] The signal of the first reset signal terminal Reset is at a low level, the reset transistor M3 is turned on, and the signal of the first initialization signal terminal Vint is provided to the second terminal of the first capacitor C1, the control terminal of the driving transistor DTFT and the first terminal of the first transistor T1 via the turned-on reset transistor M3.

[0157] Timing t31 stage: STV2 = 1, STV1 = 1, Reset = 1, Gate = 0, SEN = 1, EM = 1

[0158] The signal at the scan signal terminal Gate is at a low level, the data write transistor M2 is turned on, and the compensated data voltage at the data signal terminal is provided to the first end of the driving transistor DTFT through the turned-on data write transistor M2; the signal at the scan signal terminal Gate is at a low level, the first transistor T1 is turned on, and the compensated data voltage is provided to the second end of the driving transistor DTFT through the turned-on driving transistor DTFT, and the compensated data voltage is provided from the second end of the driving transistor DTFT to the control end of the driving transistor DTFT through the turned-on first transistor T1, thereby causing the driving transistor DTFT to generate a driving current; the signal at the scan signal terminal Gate is at a low level, the fourth transistor T4 is turned on, and the signal of the first initialization signal terminal Vint is provided to the anode of the light-emitting device OLED and the second end of the third transistor T3 through the turned-on fourth transistor T4, thereby resetting the anode of the light-emitting device OLED and the second end of the third transistor T3.

[0159] Timing t41 stage: STV2 = 1, STV1 = 1, Reset = 1, Gate = 1, SEN = 1, EM = 0

[0160] When the signal at the first light-emitting control signal terminal EM is at a low level, the second transistor T2 is turned on, and the first power supply terminal ELVDD is electrically connected to the first terminal of the driving transistor DTFT and the first terminal of the data writing transistor M2 via the turned-on second transistor T2. When the signal at the first light-emitting control signal terminal EM is at a low level, the third transistor T3 is turned on, and the second terminal of the driving transistor DTFT is electrically connected to the anode of the light-emitting device OLED via the turned-on third transistor T3. The first power supply terminal ELVDD is connected to the second power supply terminal ELVSS via the second transistor T2, the driving transistor DTFT, the third transistor T3, and the light-emitting device OLED, and the light-emitting device OLED emits light under the action of the driving current.

[0161] Based on the same inventive concept, an embodiment of the present disclosure provides a driving method for the display device described above. Figure 17 Shown, including:

[0162] Step 201: During the blank time period, the source driving circuit outputs the compensation data voltage to the target pixel circuit 10; the selection control circuit 00 provides the driving voltage signal generated after the target pixel circuit receives the compensation data voltage to the source driving circuit to determine the threshold compensation voltage, wherein the driving voltage signal is determined based on the compensation data voltage and the threshold voltage of the driving transistor DTFT in the target pixel circuit.

[0163] During the implementation process, during the blanking period, for each display panel constituting the spliced ​​screen, the source driver circuit first outputs the compensation data voltage to the target pixel circuit 10. In this way, the target pixel circuit 10 receives the compensation data voltage and generates a driving voltage signal. The gate control circuit 00 then obtains the driving voltage signal and provides it to the source driver circuit.

[0164] Step 202: In the display frame stage, the source driving circuit outputs the compensated data voltage to each pixel circuit according to the threshold compensation voltage.

[0165] During the display frame stage, for each display panel that makes up the spliced ​​screen, the source driver circuit determines the compensated data voltage based on the threshold compensation voltage and outputs the compensated data voltage to each pixel circuit. In this way, the pixel circuits in each display panel can uniformly display according to the compensated data voltage, thereby compensating for the brightness difference between at least two display panels at the splicing point.

[0166] In summary, a display device and a driving method are provided in an embodiment of the present disclosure. The display device includes: at least two display panels arranged in a spliced ​​manner, the display panels including a plurality of pixel circuits and a gating control circuit, the plurality of pixel circuits including a target pixel circuit, the target pixel circuit being connected to the gating control circuit, at least two source driving circuits, the at least two source driving circuits being connected one-to-one with the at least two display panels, the source driving circuit being configured to output a compensated data voltage to the target pixel circuit during a blank time period, and to output a compensated data voltage to each pixel circuit according to a threshold compensation voltage during a display frame period, the gating control circuit being further connected to the source driving circuit, and the gating control circuit The circuit is configured to provide a driving voltage signal generated after the target pixel circuit receives the compensated data voltage to the source driving circuit in response to a signal from the selection control terminal during the blank time period to determine the threshold compensation voltage, wherein the driving voltage signal is determined based on the compensated data voltage and the threshold voltage of the driving transistor in the target pixel circuit. The setting of the above-mentioned selection control circuit realizes the extraction of the driving voltage signal during the blank time period, and further determines the threshold compensation voltage based on the driving voltage signal, so that the source driving circuit outputs the compensated data voltage to each pixel circuit during the display frame stage, thereby compensating for the brightness difference at the splicing point of at least two display panels and improving the display effect.

[0167] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program product systems. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0168] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program product systems according to the present disclosure. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0169] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0170] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0171] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A display device, characterized in that: include: At least two display panels are spliced ​​together, the display panels comprising a plurality of pixel circuits and a gating control circuit, the plurality of pixel circuits including a target pixel circuit, the target pixel circuit being connected to the gating control circuit, the at least two display panels comprising a first display panel and a second adjacent display panel, the target pixel circuit in the first display panel and the target pixel circuit in the second display panel being located at a splice between the first display panel and the second display panel; At least two source driver circuits, the at least two source driver circuits being connected to the at least two display panels in a one-to-one correspondence, the source driver circuits being configured to output a compensated data voltage to the target pixel circuit during a blanking period, and to output a compensated data voltage to each pixel circuit according to a threshold compensation voltage during a display frame period; The gating control circuit is also connected to the source driving circuit, and the gating control circuit is configured to, in the blank time period, respond to the signal of the gating control terminal to provide the driving voltage signal generated after the target pixel circuit receives the compensation data voltage to the source driving circuit to determine the threshold compensation voltage, wherein the driving voltage signal is determined based on the compensation data voltage and the threshold voltage of the driving transistor in the target pixel circuit.

2. The display device according to claim 1, wherein The first display panel includes m rows and n columns of the gate control circuit and m rows and n columns of the target pixel circuit; The gate control circuits in the m rows and n columns are connected to the target pixel circuits in the m rows and n columns in a one-to-one correspondence, and m and n are positive integers respectively.

3. The display device according to claim 1, wherein The second display panel includes the gate control circuit in row a and column b and the target pixel circuit in row a and column b; The selection control circuits in row a and column b are connected to the target pixel circuits in row a and column b in one-to-one correspondence, and a and b are positive integers respectively.

4. The display device according to any one of claims 1 to 3, wherein: The target pixel circuit includes a driving transistor; The gating control circuit is connected to the control terminal of the driving transistor.

5. The display device according to claim 4, wherein The gating control circuit includes: a gating transistor; The control end of the gating transistor is connected to the gating control end, the first end of the gating transistor is connected to the source driving circuit, and the second end of the gating transistor is connected to the control end of the driving transistor.

6. The display device according to any one of claims 1 to 3, wherein: Each of the display panels further includes a gate drive circuit; In the same display panel, the gate driving circuit is connected to the gate control terminal in the target pixel circuit.

7. The display device according to claim 6, wherein Each of the pixel circuits further includes a data writing transistor, wherein a first end of the data writing transistor is connected to a first end of the driving transistor; Each of the display panels further includes a compensation gate driving circuit. In the same display panel, the compensation gate driving circuit is connected to the control terminal of the data writing transistor in the target pixel circuit.

8. The display device according to claim 7, wherein: Each of the display panels further includes a display gate drive circuit; In the same display panel, the display gate driving circuit is connected to the control end of the data writing transistor in each pixel circuit.

9. The display device according to claim 6, wherein: Each of the pixel circuits further includes a reset transistor, wherein a first terminal of the reset transistor is connected to a control terminal of the drive transistor; Each of the display panels further includes a first reset gate driving circuit. In the same display panel, the first reset gate driving circuit is connected to the control terminal of the reset transistor in the target pixel circuit.

10. The display device according to claim 9, wherein Each of the display panels further includes a second reset gate driving circuit. In the same display panel, the second reset gate driving circuit is connected to the control end of the reset transistor in each of the pixel circuits.

11. The display device according to claim 1, wherein It also includes the mobile phone motherboard end; The mobile phone mainboard end is connected to the at least two source driving circuits, and the mobile phone mainboard end is configured to determine the threshold voltage of the driving transistor in each of the target pixel circuits based on the driving voltage signal and the compensation data voltage signal, determine the threshold voltage average based on each of the threshold voltages, and determine the threshold compensation voltage based on the threshold voltage average and the threshold voltage.

12. A driving method for a display device according to any one of claims 1 to 11, characterized in that: include: During the blank time period, the source driving circuit outputs the compensation data voltage to the target pixel circuit; The gating control circuit provides a driving voltage signal generated by the target pixel circuit after receiving the compensation data voltage to the source driving circuit to determine the threshold compensation voltage, wherein the driving voltage signal is determined according to the compensation data voltage and the threshold voltage of the driving transistor in the target pixel circuit; In a display frame phase, the source driving circuit outputs a compensated data voltage to each target pixel circuit according to a threshold compensation voltage.

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