Integrated thermal resistance scanning probe and method of manufacturing the same

Abstract

This invention provides an integrated resistance-of-thermal scanning thermal probe and its fabrication method, belonging to the fields of micro / nano fabrication, nanoscale thermal characterization, and scanning probe technology. The integrated resistance-of-thermal scanning thermal probe of this invention includes a substrate, an oxide layer, a low-resistivity silicon layer, a probe arm, a tip, and a metal electrode. Based on an AFM probe, this invention employs a probe arm separation structure and fabricates electrodes on the separated probe arms to inject current into the probe. Furthermore, this invention uses an ion implantation process to form a high-implantation, low-resistivity region outside the tip, while the tip region is a high-resistivity region without implantation. This ensures that most of the injected electrical energy is generated as heat in the tip region, creating a significant temperature difference between the tip and the sample being measured, facilitating the measurement and determination of the sample's temperature. The tip size of this invention can be reduced to below 10 nanometers, and the scanning thermal probe fabricated by this invention can provide a nanoscale temperature distribution.

Description

Technical Field

[0001] This invention belongs to the fields of micro-nano fabrication, nanoscale thermal characterization, and scanning probe technology, specifically relating to an integrated resistance thermometer scanning thermal probe and its preparation method. Background Technology

[0002] With the continuous improvement of large-scale integrated circuit manufacturing processes, the size of micro- and nano-devices has shrunk to the nanometer scale, and the device integration density has significantly increased. This has led to significant and highly challenging issues such as the transformation of phonon transport mechanisms and energy dissipation. Meanwhile, studying temperature distribution and energy dissipation in micro- and nano-devices has important practical application value for improving device performance and reliability. Traditional temperature detection methods (such as fluorescence thermometry, infrared thermal imagers, thermal reflection microscopy, and Raman spectroscopy) struggle to achieve spatial resolution of temperature above the micrometer level.

[0003] Scanning thermal microscopy (SThM) is a high-resolution temperature measurement method developed in recent years, achieving spatial resolution below 10 nm while maintaining high temperature resolution. SThM is a temperature characterization technique developed based on atomic force microscopy (AFM), achieving the determination of nanoscale temperature distribution by integrating miniature thermocouples or resistance thermometers onto traditional AFM probes. Traditional thermocouple tip fabrication processes are complex and have low yields. Resistance thermometer methods, on the other hand, have relatively simple fabrication processes and high yields, ensuring future large-scale production and application.

[0004] Chinese invention patent CN102175894A discloses a method for fabricating a micro thermocouple probe for scanning thermal microscopy. This method uses a nanoscale thermal sensor fabricated on the tip of a commercially available AFM cantilever to enable the probe to sense temperature. However, this method involves complex fabrication processes, and the probe yield is significantly affected by the performance and overall yield of the integrated MEMS device. Furthermore, due to the limitations of thermocouple size, the scanning thermal probe fabricated using this method can only characterize heat distribution at the tens of nanometer scale, and its spatial resolution is insufficient to meet the higher precision requirements of micro / nano devices. Summary of the Invention

[0005] This invention is proposed to solve the above-mentioned problems, and aims to provide an integrated resistance temperature detector (RTD) scanning thermal probe and its preparation method.

[0006] This invention provides an integrated resistance temperature detector (RTD) scanning thermal probe, characterized by the following features: a Si substrate serving as the base for the integrated RTD scanning thermal probe; a first oxide layer disposed on the Si substrate; and a low-resistivity silicon layer disposed on the first oxide layer. The low-resistivity silicon layer has two probe arms extending from the same side of the low-resistivity silicon layer and connecting at their tips to form a peak shape. The end of the probe arm connected to the low-resistivity silicon layer is designated as the thick probe arm, and the end of the probe arm away from the low-resistivity silicon layer is designated as the thin probe arm. The thickness of the thick probe arm is greater than that of the thin probe arm. The ends of the two thin probe arms, which are far from the low-resistivity silicon layer, are pointed and connected to each other. The low-resistivity silicon layer and the probe arms are doped silicon materials prepared by intrinsic silicon through ion implantation, forming a highly doped low-resistivity region. The needle tip, made of intrinsic silicon, is located at the tip of the two thin probe arms and connects them. The resistance of the needle tip is much higher than that of the low-resistivity silicon layer and the probe arms. There are also two metal electrodes, which are located on the low-resistivity silicon layer and correspond to the two probe arms.

[0007] The integrated resistance scanning thermal probe provided by the present invention may also have the following features: the material of the first oxide layer includes SiO2, and the thickness of the first oxide layer is 0.2μm to 0.5μm.

[0008] The integrated resistance thermal scanning probe provided by this invention may also have the following feature: the phosphorus doping concentration of the low-resistivity silicon layer is 6 × 10⁻⁶. 17 atom / cm 3 .

[0009] The integrated resistance scanning thermal probe provided by the present invention may also have the following feature: the thickness of the low-resistivity silicon layer is 0.2 mm to 0.6 mm.

[0010] The integrated resistance thermometer scanning probe provided by this invention may also have the following features: the tip diameter is less than 20 nm, and the tip is not subjected to ion implantation process.

[0011] The integrated resistance thermometer scanning probe provided by this invention may also have the following feature: the tip and two probe thin arms are integrally formed.

[0012] The integrated resistance thermometer scanning probe provided by this invention may also have the following feature: the material of the metal electrode includes Au.

[0013] This invention also provides a method for fabricating an integrated resistance temperature detector (RTD) scanning thermal probe, characterized in that it is used to fabricate an integrated RTD scanning thermal probe according to any of the preceding claims, comprising the following steps: S10, selecting an SOI substrate of a certain size, wherein the SOI substrate includes a Si substrate, a first oxide layer deposited on the Si substrate, and a thin Si layer deposited on the first oxide layer; S20, depositing a mask layer of a certain thickness on the thin Si layer; S30, patterning the mask layer using photolithography to mask the area of ​​the preset low-resistivity silicon layer and the probe thick arm; S40, partially masking the area of ​​the Si thin layer exposed after step S30 using electron beam lithography, wherein the masked area is the area of ​​the preset probe tip; S50, using reactive ion etching... In step S40, the area of ​​the Si thin layer still exposed after processing is etched to form the preset shapes of the probe thick arm, probe thin arm, and tip. In step S60, the exposed Si thin layer surface is oxidized using an oxidation process to form a second oxide layer. In step S70, the second oxide layer in step S60 is removed to sharpen the tip. In step S80, the preset area in the Si thin layer with the preset shape obtained in step S70 is subjected to an ion implantation process to form a highly doped low-resistivity region, thereby obtaining a low-resistivity silicon layer, probe thick arm, and probe thin arm made of phosphorus-doped silicon. In step S90, a metal electrode is vacuum-deposited at a preset position, and then a deep etching process is used to etch away the probe thick arm, probe thin arm, the first oxide layer under the tip, and the Si substrate to obtain an integrated thermal resistance scanning probe.

[0014] The method for preparing the integrated resistance thermometer scanning thermal probe provided by the present invention may also have the following feature: the Si thin layer is made of intrinsic silicon.

[0015] The method for preparing an integrated resistance scanning thermal probe provided by the present invention may also have the following features: in step S20, the material of the mask layer includes SiO2, and the thickness of the mask layer is 500nm to 1000nm.

[0016] The role and effect of invention

[0017] According to the present invention, an integrated resistance temperature scanning thermal probe and its preparation method are based on an AFM probe, a probe arm separation structure is adopted and electrodes are prepared on the separated probe arms to provide electrodes for probe heating.

[0018] Furthermore, this invention uses an ion implantation process to create a high-resistance region at the tip and a high-resistance region outside the tip, ensuring that most of the injected electrical energy is used to generate heat in the tip region, thus creating a significant temperature difference between the tip and the sample being tested, which facilitates the measurement and determination of the sample's temperature.

[0019] The tip size of the present invention can be reduced to less than 10 nanometers, and the scanning thermal probe prepared by the present invention can provide a nanoscale temperature distribution. Attached Figure Description

[0020] Figure 1 This is a side view of an integrated resistance temperature detector (RTD) scanning thermal probe according to an embodiment of the present invention.

[0021] Figure 2 This is a top view of an integrated resistance temperature detector (RTD) scanning thermal probe according to an embodiment of the present invention;

[0022] Figure 3 This is a schematic flowchart of the preparation method of the integrated resistance temperature detector scanning thermal probe according to an embodiment of the present invention. Detailed Implementation

[0023] To make the technical means, creative features, objectives and effects of the present invention easy to understand, the following embodiments, in conjunction with the accompanying drawings, specifically illustrate an integrated resistance temperature detector (RTD) scanning thermal probe and its preparation method.

[0024] <Example>

[0025] Figure 1 This is a side view of an integrated resistance temperature detector (RTD) scanning thermal probe according to an embodiment of the present invention. Figure 2 This is a top view of an integrated resistance temperature detector (RTD) scanning thermal probe according to an embodiment of the present invention.

[0026] like Figure 1 and 2 As shown, this embodiment provides an integrated resistance thermal scanning probe 100, including a Si substrate 10, a first oxide layer 20, a low-resistivity silicon layer 30, a tip 40, and a metal electrode 50.

[0027] Si substrate 10 serves as the substrate for the integrated resistance thermal scanning probe 100.

[0028] The first oxide layer 20 is disposed on the Si substrate 10, and it is a SiO2 layer with a thickness of 0.2μm to 0.5μm.

[0029] A low-resistivity silicon layer 30 is disposed on the first oxide layer 20, and is a silicon layer with a thickness of 0.2 mm to 0.6 mm. The low-resistivity silicon layer 30 has two laterally extending probe arms 30a, which are integrally formed from the same side of the low-resistivity silicon layer 30 to form interconnected spikes.

[0030] The probe arm 30a includes a thick probe arm 30a-1 and a thin probe arm 30a-2 that are connected to each other.

[0031] The thickness of the thick probe arm 30a-1 is greater than the thickness of the thin probe arm 30a-2. One end of the thick probe arm 30a-1 is connected to the low-resistivity silicon layer 30, and the other end is connected to the thin probe arm 30a-2.

[0032] Each of the two probe arms 30a has a thin probe arm 30a-2 that is close to and connected to each other at the end away from the low-resistivity silicon layer 30.

[0033] The low-resistivity silicon layer 30 and probe arm 30a are low-resistivity regions of highly doped phosphorus-doped silicon material formed from intrinsic silicon through an ion implantation process, with a phosphorus doping concentration of 6 × 10⁻⁶. 17 atom / cm 3 .

[0034] A needle tip 40 is disposed at the tip of two probe arms 30a-2 and indirectly connects the two. The needle tip 40 and the probe arms 30a-2 are integrally molded. The needle tip 40 is made of intrinsic silicon and is not subjected to ion implantation. The resistance of the needle tip 40 is much higher than that of the low-resistance silicon layer 30 and the probe arms 30a. In this embodiment, the diameter of the needle tip 40 is less than 20 nm.

[0035] Two metal electrodes 50 are disposed on the low-resistivity silicon layer 30 and correspond to the two probe arms 30a. In this embodiment, the metal electrodes 50 are made of Au.

[0036] Figure 3 This is a schematic flowchart of the preparation method of the integrated resistance temperature detector scanning thermal probe according to an embodiment of the present invention.

[0037] like Figure 3 As shown, this embodiment also provides a method for fabricating an integrated resistance temperature detector (RTD) scanning thermal probe, used to fabricate the integrated RTD scanning thermal probe 100 in this embodiment, specifically including the following steps:

[0038] S10, Select an SOI substrate of a certain size. The SOI substrate includes a Si substrate 10, a first oxide layer 20 deposited on the Si substrate 10, and a thin Si layer 60 deposited on the first oxide layer 20.

[0039] S20, a 1 μm thick SiO2 layer is deposited on the Si thin layer 60 as a mask layer 70. This step yields... Figure 3 The structure shown in Figure a is shown in the figure.

[0040] S30, a patterned mask layer 70 is obtained using photolithography, thereby masking the area containing the preset low-resistivity silicon layer 30 and the probe thick arm 30a-1. This step yields... Figure 3 The structure shown in Figure b is as follows.

[0041] S40, using electron beam lithography, partially mask the area of ​​the exposed Si thin layer 60 from step S30. The masked area is the region where the pre-defined tip 40 is located. This step yields... Figure 3 The structure shown in Figure c is as follows.

[0042] S50, reactive ion etching is used to etch the area of ​​the Si thin layer 60 still exposed after step S40, thereby etching it into the predetermined shape of probe thick arm 30a-1, probe thin arm 30a-2, and tip 40. This step yields... Figure 3 The structure shown in Figure d is as follows.

[0043] S60 involves oxidizing the exposed Si thin layer 60 surface using an oxidation process to form a second oxide layer 80. This step yields... Figure 3 The structure shown in Figure e is as follows.

[0044] S70: Remove the second oxide layer 80 obtained in step S60 to complete the sharpening of the tip 40, resulting in a tip 40 structure with a diameter of less than 5 nm. This step yields... Figure 3 The structure shown in Figure f is as follows.

[0045] S80, ion implantation is performed on a predetermined region of the Si thin layer 60 with a predetermined shape obtained in step S70 to form a highly doped, low-resistivity region, thus obtaining a low-resistivity silicon layer 30 of phosphorus-doped silicon, a thick probe arm 30a-1, and a thin probe arm 30a-2 (the region of the predetermined tip 40 is not subjected to ion implantation). This step yields... Figure 3 The structure shown in Figure g is as follows.

[0046] S90, a 1μm thick Au metal electrode 50 is vacuum-deposited at a predetermined position. Subsequently, a deep etching process is used to remove the thick probe arm 30a-1, the thin probe arm 30a-2, the first oxide layer 20 beneath the probe tip 40, and the Si substrate 10, forming a cantilever beam structure. This step yields... Figure 3 The structure shown in Figure h is the integrated resistance temperature detector scanning thermal probe 100.

[0047] Those skilled in the art should understand that this invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to this invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. An integrated resistance temperature detector (RTD) scanning thermal probe, characterized in that, include: A Si substrate is used as the base for the integrated resistance scanning thermal probe. A first oxide layer is disposed on the Si substrate; A low-resistivity silicon layer is disposed on the first oxide layer. The low-resistivity silicon layer has two probe arms extending from the same side of the low-resistivity silicon layer and connecting at their tips to form a peak. The end of the probe arm connected to the low-resistivity silicon layer is designated as the thick probe arm, and the end of the probe arm away from the low-resistivity silicon layer is designated as the thin probe arm. The thickness of the thick probe arm is greater than the thickness of the thin probe arm. The ends of the two thin probe arms away from the low-resistivity silicon layer form a peak shape that approaches and connects with each other. The low-resistivity silicon layer and the probe arm are made of doped silicon material prepared from intrinsic silicon through ion implantation process, forming a highly doped low-resistivity region. The needle tip, made of intrinsic silicon, is disposed at the tip of the two probe arms and connects the two. The resistance of the needle tip is much higher than that of the low-resistance silicon layer and the probe arms. as well as Two metal electrodes are disposed on the low-resistivity silicon layer and correspond to the two probe arms. The diameter of the needle tip is less than 20 nm, and the needle tip is not subjected to ion implantation. The needle tip and the two probe arms are integrally molded. The integrated resistance thermometer scanning thermal probe is prepared through the following steps: S10, Select an SOI substrate of a certain size, wherein the SOI substrate includes the Si substrate, the first oxide layer deposited on the Si substrate, and a thin Si layer deposited on the first oxide layer; S20, depositing a mask layer of a certain thickness on the Si thin layer; S30, the mask layer is patterned using photolithography to mask the area where the preset low-resistivity silicon layer and the probe thick arm are located. S40, use electron beam lithography to partially mask the area of ​​the Si thin layer exposed after step S30, the masked area is the area where the needle tip is located; S50, using reactive ion etching process to etch the area of ​​the Si thin layer that is still exposed after step S40, thereby etching it into the preset shape of the probe thick arm, the probe thin arm and the tip. S60, the exposed Si thin layer surface is oxidized using an oxidation process to form a second oxide layer; S70, remove the second oxide layer from step S60 to complete the sharpening of the needle tip; S80, perform ion implantation on the preset region of the Si thin layer with the preset shape obtained in step S70 to form a highly doped low-resistivity region, thereby obtaining the low-resistivity silicon layer, the probe thick arm, and the probe thin arm made of phosphorus-doped silicon material. S90, the metal electrode is vacuum-deposited at a preset position, and then a deep etching process is used to etch away the thick probe arm, the thin probe arm, the first oxide layer below the probe tip, and the Si substrate to obtain the integrated resistance scanning thermal probe.

2. The integrated resistance temperature detector (RTD) scanning thermal probe according to claim 1, characterized in that: in, The material of the first oxide layer includes SiO2. The thickness of the first oxide layer is 0.2 μm to 0.5 μm.

3. The integrated resistance temperature detector (RTD) scanning thermal probe according to claim 1, characterized in that: in, The phosphorus doping concentration of the low-resistivity silicon layer is 6 × 10⁻⁶. 17 atom / cm 3 .

4. The integrated resistance temperature detector (RTD) scanning thermal probe according to claim 1, characterized in that: in, The thickness of the low-resistivity silicon layer is 0.2 mm to 0.6 mm.

5. The integrated resistance temperature detector (RTD) scanning thermal probe according to claim 1, characterized in that: in, The metal electrode is made of Au.

6. The integrated resistance temperature detector (RTD) scanning thermal probe according to claim 1, characterized in that: in, The Si thin layer is made of intrinsic silicon.

7. The integrated resistance temperature detector (RTD) scanning thermal probe according to claim 1, characterized in that: in, In step S20, the material of the mask layer includes SiO2. The thickness of the mask layer is 500 nm to 1000 nm.

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