LDO circuit with over-temperature and over-load protection function and control method thereof

Abstract

The application discloses an LDO circuit with over-temperature and over-load protection function and a control method thereof, which comprises an error amplifier, a current bias circuit, a current sampling circuit, a voltage sampling circuit, an LDO circuit and a current limiting circuit. The application controls the output current of the LDO through detection of the output current and detection of the temperature, limits the power of the LDO by limiting the output current when a soft short circuit is output, so as to reduce the heat generation of the chip; if the temperature of the chip continues to rise, the value of the output current will be gradually reduced; when the set temperature threshold is reached, the LDO output current is further limited, so as to reduce the temperature rise of the chip and protect the chip.

Description

Technical Field

[0001] This invention relates to an LDO circuit and its control method, particularly an LDO circuit and its control method with over-temperature and overload protection functions, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] Some high-performance DC-DC chips integrate linear low-dropout regulators (LDOs) with external capacitor compensation, which power the internal analog and digital circuits of the DC-DC chip. Typically, these LDOs experience significant conduction losses when the output voltage difference is too large and the output current is also high, usually due to a short circuit at the LDO output. Traditional solutions address this by detecting the LDO output voltage and hard-shutting it off when the output voltage falls below a certain threshold. However, if the LDO output is soft-short-circuited (i.e., the output is not short-circuited to the output short-circuit protection threshold), the output current is still very high. Due to the large output voltage difference and high output current, heat will gradually accumulate, eventually leading to thermal damage, especially in high-temperature applications where this heat accumulation-induced thermal damage is more frequent. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide an LDO circuit with over-temperature and overload protection function and its control method, so as to reduce the temperature rise of the chip and protect the chip.

[0004] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0005] An LDO circuit with over-temperature and overload protection includes an error amplifier, a current bias circuit, a current sampling circuit, a voltage sampling circuit, an LDO circuit, and a current limiting circuit. The LDO circuit includes a PMOS transistor MP7, resistors R6 and R7, and a capacitor COUT. The source of the PMOS transistor MP7 is connected to the power supply VIN. The gate of the PMOS transistor MP7 is connected to the output of the current bias circuit and the input of the current sampling circuit. The drain of the PMOS transistor MP7 is connected to one end of resistor R6, one end of capacitor COUT, and the second input of the voltage sampling circuit. The other end of resistor R6 is connected to one end of resistor R7. The system generates a feedback voltage FB. The first input of the error amplifier is connected to the feedback voltage FB, and the second input of the error amplifier is connected to the reference voltage VREF1. The output of the error amplifier is connected to the input of the current bias circuit and the output of the current limiting circuit. The output of the current sampling circuit is connected to the first input of the voltage sampling circuit and generates a sampling current ISNS. The output of the voltage sampling circuit generates a sampling voltage VSNS. The first input of the current limiting circuit is connected to the reference voltage VREF2, the second input of the current limiting circuit is connected to the sampling voltage VSNS, and the third input of the current limiting circuit is connected to a zero-temperature coefficient reference source VBG.

[0006] Furthermore, the error amplifier includes PMOS transistors MP1, MP2, MP3, MP4, NMOS transistors MN1, MN2, and MN3, and resistor R1. The sources of PMOS transistors MP1 and MP4 are connected to the power supply VDDPRE. The gates of PMOS transistors MP1 and MP4 are connected to the bias voltage Vbias. The drain of PMOS transistor MP1 is connected to the sources of PMOS transistors MP2 and MP3. The gate of PMOS transistor MP2 serves as the first input terminal of the error amplifier and is connected to the feedback voltage FB. The gate of PMOS transistor MP3 serves as the second input terminal of the error amplifier and is connected to the reference voltage VREF1. The drain of PMOS transistor MP2 is connected to the drain and gate of NMOS transistor MN1. The drain of PMOS transistor MP3 is connected to the drain and gate of NMOS transistor MN2, one end of resistor R1, and the gate of NMOS transistor MN3. The drain of PMOS transistor MP4 is connected to the other end of resistor R1 and the drain of NMOS transistor MN3 at node A and serves as the output terminal of the error amplifier. The sources of NMOS transistors MN1, MN2, and MN3 are grounded.

[0007] Furthermore, the current biasing circuit includes a PMOS transistor MP5, a resistor R3, an NMOS transistor MN5, an NMOS transistor MN4, and a resistor R2. The source of the PMOS transistor MP5 is connected to the power supply VIN. The gate of the PMOS transistor MP5 is connected to the drain of the PMOS transistor MP5 and one end of the resistor R3, serving as the output terminal of the current biasing circuit. The other end of the resistor R3 is connected to the drain of the NMOS transistor MN5. The gate of the NMOS transistor MN5 is connected to the power supply VDDPRE. The source of the NMOS transistor MN5 is connected to the drain of the NMOS transistor MN4. The gate of the NMOS transistor MN4 serves as the input terminal of the current biasing circuit. The source of the NMOS transistor MN4 is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded.

[0008] Furthermore, the current sampling circuit includes a PMOS transistor MP6, the source of which is connected to the power supply VIN, the gate of which serves as the input terminal of the current sampling circuit, and the drain of which serves as the output terminal of the current sampling circuit and generates a sampling current ISNS.

[0009] Furthermore, the voltage sampling circuit includes transistors Q1 and Q2, resistors R4 and R5. The emitter of transistor Q1 serves as the first input terminal of the voltage sampling circuit, and the emitter of transistor Q2 serves as the second input terminal of the voltage sampling circuit. The base of transistor Q1 is connected to the base of transistor Q2, the collector of transistor Q2, and one end of resistor R5. The collector of transistor Q1 is connected to one end of resistor R4 and serves as the output terminal of the voltage sampling circuit to generate the sampling voltage VSNS. The other ends of resistors R4 and R5 are grounded.

[0010] Furthermore, the width-to-length ratio of PMOS transistors MP7 and MP6 is k1, and the width-to-length ratio of PMOS transistors MP7 and MP5 is k2.

[0011] Further, the current limiting circuit includes PMOS transistors MP8, MP9, MP10, MP11, NMOS transistors MN6, MN7, and MN8, capacitor C1, resistors R8, R9, and R10, transistors Q3 and Q4. The source of PMOS transistor MP8 is connected to the power supply VDDPRE, the gate of PMOS transistor MP8 is connected to the bias voltage Vbias, and the drain of PMOS transistor MP8 is connected to the sources of PMOS transistors MP9 and MP10. The gate of PMOS transistor MP9 serves as the first input terminal of the current limiting circuit and is connected to the reference voltage VREF2. The gate of PMOS transistor MP10 serves as the second input terminal of the current limiting circuit and is connected to the sampling voltage VSNS. The drain of PMOS transistor MP9 is connected to NMOS transistor MN6, MN7, and MN8. The drain of transistor MN6, the gate of NMOS transistor MN6, and the gate of NMOS transistor MN7 are connected. The drain of PMOS transistor MP10, the drain of NMOS transistor MN7, one end of capacitor C1, the collector of transistor Q4, and the gate of PMOS transistor MP11 are connected to node B. The source of PMOS transistor MP11 serves as the output terminal of the current limiting circuit. The base of transistor Q4 is connected to one end of resistor R9 and one end of resistor R10. The other end of resistor R9 is connected to the emitter of transistor Q3 at node C. The base of transistor Q3 is connected to the zero-temperature coefficient reference source VBG. The collector of transistor Q3 is connected to the source of NMOS transistor MN8. The gate of NMOS transistor MN8 is connected to the power supply VDDPRE. The drain of NMOS transistor MN8 is connected to one end of resistor R8. The other end of resistor R8 is connected to the power supply VIN.

[0012] A control method for an LDO circuit with over-temperature and overload protection includes the following steps:

[0013] When the circuit is running stably, the current flowing through PMOS transistor MP6 is the sampling current ISNS. Since the width-to-length ratio of PMOS transistor MP7 and PMOS transistor MP6 is k1, the output current IOUT flowing through PMOS transistor MP7 is IOUT = k1 * ISNS. The current flowing through resistor R4 is the sampling current ISNS, so the sampling voltage VSNS = ISNS * R4. Since the current limiting circuit, current bias circuit, current sampling circuit, and voltage sampling circuit constitute a current closed-loop control, VSNS = VREF2. Therefore, IOUT = k1 * ISNS = k1 * VSNS / R4 = k1 * VREF2 / R4.

[0014] When the circuit starts up, as the output current IOUT flowing through the PMOS transistor MP7 gradually reaches k1*VREF2 / R4, the voltage at node B gradually decreases, and the voltage at node A also gradually decreases. Since the voltage at node A controls the current flowing through the NMOS transistor MN4, it in turn controls the current of the PMOS transistor MP7.

[0015] As the temperature gradually increases, the voltage at node C gradually increases, and the voltage at node D also gradually increases. At this time, the voltage at node B will further decrease, and thus the voltage at node A will further decrease.

[0016] If the temperature continues to rise, the voltage at node A will be clamped to a value close to the gate-source voltage VGS4 of the NMOS transistor MN4; the minimum voltage at node A is approximately the gate-source voltage VGS11 of the PMOS transistor MP11, and the minimum output current of the LDO circuit is clamped to k2*(VGS11-VGS4) / R2, making k2*(VGS11-VGS4) / R2 greater than the static current of the DC-DC chip itself.

[0017] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides an LDO circuit and its control method with over-temperature and overload protection functions. By detecting the output current and temperature, the output current of the LDO is controlled. When the output is softly short-circuited, the power of the LDO is limited by limiting the output current, thereby reducing chip heating. If the chip temperature continues to rise, the value of the output current will be gradually reduced. When the set temperature threshold is reached, the LDO output current is further limited, thereby reducing the chip temperature rise and protecting the chip. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an LDO circuit with over-temperature and overload protection function according to the present invention. Detailed Implementation

[0019] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0020] like Figure 1 As shown, an LDO circuit with over-temperature and overload protection functions according to the present invention includes an error amplifier, a current bias circuit, a current sampling circuit, a voltage sampling circuit, an LDO circuit, and a current limiting circuit. The LDO circuit includes a PMOS transistor MP7, resistors R6 and R7, and a capacitor COUT. The source of the PMOS transistor MP7 is connected to the power supply VIN. The gate of the PMOS transistor MP7 is connected to the output terminal of the current bias circuit and the input terminal of the current sampling circuit. The drain of the PMOS transistor MP7 is connected to one end of resistor R6, one end of capacitor COUT, and the second input terminal of the voltage sampling circuit. The other end of resistor R6 is connected to one end of resistor R7. The error amplifier is connected to the first input terminal and generates a feedback voltage FB. The second input terminal of the error amplifier is connected to the reference voltage VREF1. The output terminal of the error amplifier is connected to the input terminal of the current bias circuit and the output terminal of the current limiting circuit. The output terminal of the current sampling circuit is connected to the first input terminal of the voltage sampling circuit and generates a sampling current ISNS. The output terminal of the voltage sampling circuit generates a sampling voltage VSNS. The first input terminal of the current limiting circuit is connected to the reference voltage VREF2. The second input terminal of the current limiting circuit is connected to the sampling voltage VSNS. The third input terminal of the current limiting circuit is connected to a zero temperature coefficient reference source VBG.

[0021] The error amplifier includes PMOS transistors MP1, MP2, MP3, MP4, NMOS transistors MN1, MN2, and MN3, and resistor R1. The sources of PMOS transistors MP1 and MP4 are connected to the power supply VDDPRE. The gates of PMOS transistors MP1 and MP4 are connected to the bias voltage Vbias. The drain of PMOS transistor MP1 is connected to the sources of PMOS transistors MP2 and MP3. The gate of PMOS transistor MP2 serves as the first input terminal of the error amplifier and is connected to the feedback voltage FB. The gate of S-channel transistor MP3 serves as the second input terminal of the error amplifier and is connected to the reference voltage VREF1. The drain of PMOS transistor MP2 is connected to the drain and gate of NMOS transistor MN1. The drain of PMOS transistor MP3 is connected to the drain and gate of NMOS transistor MN2, one end of resistor R1, and the gate of NMOS transistor MN3. The drain of PMOS transistor MP4 is connected to the other end of resistor R1 and the drain of NMOS transistor MN3 at node A and serves as the output terminal of the error amplifier. The sources of NMOS transistors MN1, MN2, and MN3 are grounded.

[0022] The function of resistor R1 is to clamp the voltage at node A of the gate of NMOS transistor MN4 through NMOS transistor MN2 when the LDO circuit starts up, thereby limiting the start-up output current and eliminating the need for a start-up circuit. At the same time, resistor R1 effectively reduces the AC impedance of node A, making the dominant pole of the LDO circuit at the output position of the LDO circuit, which makes the system easier to compensate.

[0023] The current bias circuit includes a PMOS transistor MP5, a resistor R3, an NMOS transistor MN5, an NMOS transistor MN4, and a resistor R2. The source of PMOS transistor MP5 is connected to the power supply VIN. The gate of PMOS transistor MP5 is connected to the drain of PMOS transistor MP5 and one end of resistor R3, serving as the output of the current bias circuit. The other end of resistor R3 is connected to the drain of NMOS transistor MN5. The gate of NMOS transistor MN5 is connected to the power supply VDDPRE. The source of NMOS transistor MN5 is connected to the drain of NMOS transistor MN4. The gate of NMOS transistor MN4 serves as the input of the current bias circuit. The source of NMOS transistor MN4 is connected to one end of resistor R2, and the other end of resistor R2 is grounded.

[0024] The current sampling circuit includes a PMOS transistor MP6. The source of the PMOS transistor MP6 is connected to the power supply VIN. The gate of the PMOS transistor MP6 serves as the input terminal of the current sampling circuit, and the drain of the PMOS transistor MP6 serves as the output terminal of the current sampling circuit and generates a sampling current ISNS.

[0025] The voltage sampling circuit includes transistors Q1 and Q2, resistors R4 and R5. The emitter of transistor Q1 serves as the first input terminal of the voltage sampling circuit, and the emitter of transistor Q2 serves as the second input terminal. The bases of transistors Q1 and Q2, the collector of transistor Q2, and one end of resistor R5 are connected. The collector of transistor Q1 is connected to one end of resistor R4 and serves as the output terminal of the voltage sampling circuit, generating the sampling voltage VSNS. The other ends of resistors R4 and R5 are grounded.

[0026] PMOS transistors MP5, MP6, and MP7 form a current mirror circuit. The width-to-length ratio of PMOS transistors MP7 and MP6 is k1, and the width-to-length ratio of PMOS transistors MP7 and MP5 is k2. PMOS transistors MP5, MP6, and MP7, as well as NMOS transistors MN5 and MN8, are all high-voltage MOS transistors with high source-drain voltage withstand capability.

[0027] The current limiting circuit includes PMOS transistors MP8, MP9, MP10, and MP11, NMOS transistors MN6, MN7, and MN8, capacitor C1, resistors R8, R9, and R10, and transistors Q3 and Q4. The source of PMOS transistor MP8 is connected to the power supply VDDPRE, and its gate is connected to the bias voltage Vbias. The drain of PMOS transistor MP8 is connected to the sources of PMOS transistors MP9 and MP10. The gate of PMOS transistor MP9 serves as the first input of the current limiting circuit and is connected to the reference voltage VREF2. The gate of PMOS transistor MP10 serves as the second input of the current limiting circuit and is connected to the sampling voltage VSNS. The drain of PMOS transistor MP9 is connected to the NMOS transistor... The drain of MN6, the gate of NMOS transistor MN6, and the gate of NMOS transistor MN7 are connected. The drain of PMOS transistor MP10, the drain of NMOS transistor MN7, one end of capacitor C1, the collector of transistor Q4, and the gate of PMOS transistor MP11 are connected to node B. The source of PMOS transistor MP11 serves as the output terminal of the current limiting circuit. The base of transistor Q4 is connected to one end of resistor R9 and one end of resistor R10. The other end of resistor R9 is connected to the emitter of transistor Q3 at node C. The base of transistor Q3 is connected to the zero-temperature coefficient reference source VBG. The collector of transistor Q3 is connected to the source of NMOS transistor MN8. The gate of NMOS transistor MN8 is connected to the power supply VDDPRE. The drain of NMOS transistor MN8 is connected to one end of resistor R8. The other end of resistor R8 is connected to the power supply VIN.

[0028] Among them, capacitor C1 is the compensation capacitor of the current limiting circuit.

[0029] A control method for an LDO circuit with over-temperature and overload protection includes the following steps:

[0030] When the circuit is running stably, the current flowing through PMOS transistor MP6 is the sampling current ISNS. Since the width-to-length ratio of PMOS transistor MP7 and PMOS transistor MP6 is k1, the output current IOUT flowing through PMOS transistor MP7 is IOUT = k1 * ISNS. The current flowing through resistor R4 is the sampling current ISNS, so the sampling voltage VSNS = ISNS * R4. Since the current limiting circuit, current bias circuit, current sampling circuit, and voltage sampling circuit constitute a current closed-loop control, VSNS = VREF2. Therefore, IOUT = k1 * ISNS = k1 * VSNS / R4 = k1 * VREF2 / R4.

[0031] When the circuit starts up, as the output current IOUT flowing through the PMOS transistor MP7 gradually reaches k1*VREF2 / R4, the voltage at node B gradually decreases, and the voltage at node A also gradually decreases. Since the voltage at node A controls the current flowing through the NMOS transistor MN4, it in turn controls the current of the PMOS transistor MP7.

[0032] As the temperature gradually increases, the voltage at node C gradually increases, and the voltage at node D also gradually increases. At this time, the voltage at node B will further decrease, and thus the voltage at node A will further decrease.

[0033] If the temperature continues to rise, the voltage at node A will be clamped to a value close to the gate-source voltage VGS4 of the NMOS transistor MN4; the minimum voltage at node A is approximately the gate-source voltage VGS11 of the PMOS transistor MP11, and the minimum output current of the LDO circuit is clamped to k2*(VGS11-VGS4) / R2, making k2*(VGS11-VGS4) / R2 greater than the static current of the DC-DC chip itself.

[0034] This invention provides an LDO circuit and its control method with over-temperature and overload protection. By detecting the output current and temperature, the output current of the LDO is controlled. When the output is softly short-circuited, the power of the LDO is limited by limiting the output current, thereby reducing chip heating. If the chip temperature continues to rise, the value of the output current will be gradually reduced. When the set temperature threshold is reached, the output current of the LDO is further limited, thereby reducing the chip temperature rise and protecting the chip.

[0035] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. An LDO circuit with over-temperature and overload protection functions, characterized in that: The circuit includes an error amplifier, a current bias circuit, a current sampling circuit, a voltage sampling circuit, an LDO circuit, and a current limiting circuit. The LDO circuit includes a PMOS transistor MP7, resistors R6 and R7, and a capacitor COUT. The source of PMOS transistor MP7 is connected to the power supply VIN. The gate of PMOS transistor MP7 is connected to the output of the current bias circuit and the input of the current sampling circuit. The drain of PMOS transistor MP7 is connected to one end of resistor R6, one end of capacitor COUT, and the second input of the voltage sampling circuit. The other end of resistor R6 is connected to one end of resistor R7 to generate a feedback voltage FB. The first input of the error amplifier is connected to the feedback voltage FB, and the second input of the error amplifier is connected to the reference voltage V. REF1, the output of the error amplifier is connected to the input of the current bias circuit and the output of the current limiting circuit. The output of the current sampling circuit is connected to the first input of the voltage sampling circuit and generates a sampling current ISNS. The output of the voltage sampling circuit generates a sampling voltage VSNS. The first input of the current limiting circuit is connected to the reference voltage VREF2. The second input of the current limiting circuit is connected to the sampling voltage VSNS. The third input of the current limiting circuit is connected to a zero-temperature coefficient reference source VBG. The current limiting circuit includes PMOS transistors MP8, MP9, MP10, MP11, NMOS transistors MN6, MN7, and MN8, and capacitor C1. Resistors R8, R9, and R10; transistors Q3 and Q4; the source of PMOS transistor MP8 is connected to power supply VDDPRE; the gate of PMOS transistor MP8 is connected to bias voltage Vbias; the drain of PMOS transistor MP8 is connected to the source of PMOS transistors MP9 and MP10; the gate of PMOS transistor MP9 serves as the first input terminal of the current limiting circuit and is connected to reference voltage VREF2; the gate of PMOS transistor MP10 serves as the second input terminal of the current limiting circuit and is connected to sampling voltage VSNS; the drain of PMOS transistor MP9 is connected to the drain of NMOS transistor MN6, the gate of NMOS transistor MN6, and the gate of NMOS transistor MN7. The drain of MP10 is connected to the drain of NMOS transistor MN7, one end of capacitor C1, the collector of transistor Q4, and the gate of PMOS transistor MP11 at node B. The source of PMOS transistor MP11 serves as the output of the current limiting circuit. The base of transistor Q4 is connected to one end of resistor R9 and one end of resistor R10. The other end of resistor R9 is connected to the emitter of transistor Q3 at node C. The base of transistor Q3 is connected to the zero-temperature coefficient reference source VBG. The collector of transistor Q3 is connected to the source of NMOS transistor MN8. The gate of NMOS transistor MN8 is connected to the power supply VDDPRE. The drain of NMOS transistor MN8 is connected to one end of resistor R8. The other end of resistor R8 is connected to the power supply VIN.

2. The LDO circuit with over-temperature and overload protection function according to claim 1, characterized in that: The error amplifier includes PMOS transistors MP1, MP2, MP3, MP4, NMOS transistors MN1, MN2, and MN3, and resistor R1. The sources of PMOS transistors MP1 and MP4 are connected to the power supply VDDPRE. The gates of PMOS transistors MP1 and MP4 are connected to the bias voltage Vbias. The drain of PMOS transistor MP1 is connected to the sources of PMOS transistors MP2 and MP3. The gate of PMOS transistor MP2 serves as the first input terminal of the error amplifier and is connected to the feedback voltage FB. The gate of the OS transistor MP3 serves as the second input terminal of the error amplifier and is connected to the reference voltage VREF1. The drain of the PMOS transistor MP2 is connected to the drain and gate of the NMOS transistor MN1. The drain of the PMOS transistor MP3 is connected to the drain and gate of the NMOS transistor MN2, one end of the resistor R1, and the gate of the NMOS transistor MN3. The drain of the PMOS transistor MP4 is connected to the other end of the resistor R1 and the drain of the NMOS transistor MN3 at node A and serves as the output terminal of the error amplifier. The sources of the NMOS transistors MN1, MN2, and MN3 are grounded.

3. The LDO circuit with over-temperature and overload protection function according to claim 1, characterized in that: The current bias circuit includes a PMOS transistor MP5, a resistor R3, an NMOS transistor MN5, an NMOS transistor MN4, and a resistor R2. The source of the PMOS transistor MP5 is connected to the power supply VIN. The gate of the PMOS transistor MP5 is connected to the drain of the PMOS transistor MP5 and one end of the resistor R3, serving as the output terminal of the current bias circuit. The other end of the resistor R3 is connected to the drain of the NMOS transistor MN5. The gate of the NMOS transistor MN5 is connected to the power supply VDDPRE. The source of the NMOS transistor MN5 is connected to the drain of the NMOS transistor MN4. The gate of the NMOS transistor MN4 serves as the input terminal of the current bias circuit. The source of the NMOS transistor MN4 is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded.

4. The LDO circuit with over-temperature and overload protection function according to claim 1, characterized in that: The current sampling circuit includes a PMOS transistor MP6. The source of the PMOS transistor MP6 is connected to the power supply VIN. The gate of the PMOS transistor MP6 serves as the input terminal of the current sampling circuit, and the drain of the PMOS transistor MP6 serves as the output terminal of the current sampling circuit and generates a sampling current ISNS.

5. An LDO circuit with over-temperature and overload protection function according to claim 4, characterized in that: The voltage sampling circuit includes transistors Q1 and Q2, resistors R4 and R5. The emitter of transistor Q1 serves as the first input terminal of the voltage sampling circuit, and the emitter of transistor Q2 serves as the second input terminal. The base of transistor Q1 is connected to the base of transistor Q2, the collector of transistor Q2, and one end of resistor R5. The collector of transistor Q1 is connected to one end of resistor R4 and serves as the output terminal of the voltage sampling circuit to generate the sampling voltage VSNS. The other ends of resistors R4 and R5 are grounded.

6. An LDO circuit with over-temperature and overload protection function according to claim 5, characterized in that: The width-to-length ratio of PMOS transistors MP7 and MP6 is k1, and the width-to-length ratio of PMOS transistors MP7 and MP5 is k2.

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