Gate driving circuit, display panel and display device
By introducing isolation and reset modules into the gate drive circuit, the problem of thin-film transistor threshold voltage drift caused by touch signal insertion is solved, achieving stable display and efficient touch control of the display panel.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGZHOU CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
- Filing Date
- 2024-12-13
- Publication Date
- 2026-07-07
AI Technical Summary
In the prior art, when multiple touch signals are inserted into an embedded touch display panel, the threshold voltage of the thin-film transistor in the gate driving unit drifts, resulting in scanning signal differences, causing pitting patterns, and affecting the display effect.
Design a gate drive circuit including an input module, an output module, an isolation module, a sustaining module, and a reset module. By isolating the first node and the second node, it maintains a high potential and resets it to a low potential during the touch phase, avoiding inconsistent transistor stress and preventing the appearance of stop marks.
It effectively prevents voltage differences between gate driving units, maintains consistent display effects, avoids the appearance of pitting, and improves the touch performance and display quality of the display panel.
Smart Images
Figure CN119600913B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to a gate driving circuit, a display panel, and a display device. Background Technology
[0002] Currently, to improve the touch sensitivity of embedded touch display panels, touch signals are typically inserted multiple times within the display time of a single frame, requiring multiple pauses. This interrupts the normal display. In the gate drive circuit, some gate drive units store charge over-pits, which causes the threshold voltage of the thin-film transistors in some gate drive units to drift positively. When displaying the image, the scanning signals generated by these gate drive units differ from those generated by other gate drive units, resulting in horizontal lines (also known as "pause lines") and affecting the display effect. Summary of the Invention
[0003] Embodiments of this application provide a gate driving circuit, a display panel, and a display device to solve the problem in related technologies where pitting patterns on the display panel affect the display effect.
[0004] To solve the above problems, the technical solution provided in this application is as follows:
[0005] In a first aspect, this application provides a gate driving circuit, including a plurality of cascaded gate driving units, at least one of the gate driving units comprising:
[0006] The input module is electrically connected to the first node and is used to receive the cascaded signal output from the previous stage and input a preset high potential to the first node.
[0007] The output module is electrically connected to the second node and the signal output node of this stage, and is used to control the output potential of the signal output node of this stage according to the potential of the first node and the potential of the second node;
[0008] An isolation module, electrically connected to the first node and the second node, is used to isolate the potential of the first node and the second node in response to the inverted signal of the touch signal;
[0009] A maintenance module, electrically connected to the first node, the second node, and the signal output node of this stage, is used to maintain the potential of the first node, the second node, and the signal output node of this stage; and,
[0010] The reset module is electrically connected to the first node, the second node, and the signal output node of this level, and is used to reset the potential of the first node, the second node, and the signal output node of this level.
[0011] In one embodiment, the input module includes:
[0012] The first transistor includes a control electrode connected to the cascaded signal output from the previous stage, a first electrode electrically connected to the control electrode, and a second electrode electrically connected to the first node.
[0013] In one embodiment, the output module includes:
[0014] The second transistor includes a control electrode electrically connected to the second node, a first electrode connected to a first clock signal, and a second electrode electrically connected to the signal output node of this stage; and...
[0015] The first capacitor includes a first electrode electrically connected to the first node and a second electrode electrically connected to the signal output node of this stage.
[0016] In one embodiment, the isolation module includes:
[0017] The third transistor includes a control electrode for receiving the inverted signal of the touch signal, a first electrode electrically connected to the first node, and a second electrode electrically connected to the second node.
[0018] In one embodiment, the maintenance module includes:
[0019] The first maintenance submodule is electrically connected to the first node and is used to maintain the potential of the first node;
[0020] The second maintenance submodule is electrically connected to the second node and is used to maintain the potential of the second node;
[0021] The third maintenance submodule is electrically connected to the signal output node of this level and is used to maintain the potential of the signal output node of this level.
[0022] In one embodiment, the first maintenance submodule includes:
[0023] The fourth transistor includes a second electrode, a control electrode electrically connected to the first node, and a first electrode; and,
[0024] The fifth transistor includes a control electrode electrically connected to the second electrode of the fourth transistor, a first electrode connected to the touch signal, and a second electrode electrically connected to the first node.
[0025] In one embodiment, the second maintenance submodule includes:
[0026] The first inverter includes an output terminal and an input terminal electrically connected to the second node; and,
[0027] The sixth transistor includes a control electrode electrically connected to the output of the first inverter, a first electrode electrically connected to the second node, and a second electrode connected to a constant low-potential signal.
[0028] In one embodiment, the third maintenance submodule includes:
[0029] The first inverter includes an output terminal and an input terminal electrically connected to the second node; and,
[0030] The seventh transistor includes a control electrode electrically connected to the output terminal of the first inverter, a first electrode electrically connected to the signal output node of the current stage, and the second electrode of the sixth transistor is connected to a constant low potential signal.
[0031] In one embodiment, the reset module includes:
[0032] The first reset submodule is electrically connected to the first node and resets the potential of the first node in response to the cascade signal of the next level.
[0033] The second reset submodule is electrically connected to the second node and is used to discharge and reset the potential of the second node.
[0034] The third reset submodule is electrically connected to the signal output node of this stage and is used to reset the potential of the signal output node of this stage.
[0035] In one embodiment, the first reset submodule includes:
[0036] The eighth transistor includes a control electrode that receives the cascaded signal for the next stage, a first electrode that is electrically connected to the first node, and a second electrode that receives a constant low-potential signal.
[0037] In one embodiment, the second reset submodule includes:
[0038] The ninth transistor includes a control electrode that receives a touch signal, a first electrode that is electrically connected to the second node, and a second electrode that receives a constant low-potential signal.
[0039] In one embodiment, the third reset submodule includes:
[0040] The tenth transistor includes a control electrode whose gate is connected to the touch signal, a first electrode electrically connected to the signal output node of this stage, and a second electrode connected to a constant low potential signal.
[0041] Secondly, this application also provides a display panel including the aforementioned gate driving circuit.
[0042] Thirdly, this application also provides a display device, including the aforementioned display panel.
[0043] This application provides a gate driving circuit, a display panel, and a display device. The gate driving circuit includes multiple cascaded gate driving units, and at least one of the gate driving units includes: an input module electrically connected to a first node, used to input a preset high potential to the first node by receiving a cascaded signal output from the previous stage; an output module electrically connected to a second node and a signal output node of the same stage, used to control the output potential of the signal output node of the same stage under the control of the potentials of the first node and the second node; an isolation module electrically connected to the first node and the second node, used to isolate the potentials of the first node and the second node in response to the inverted signal of a touch signal; a maintenance module electrically connected to the first node, the second node, and the signal output node of the same stage, used to maintain the potentials of the first node, the second node, and the signal output node of the same stage; and a reset module electrically connected to the first node, the second node, and the signal output node of the same stage, used to reset the potentials of the first node, the second node, and the signal output node of the same stage. By implementing the above solution and setting up an isolation module to separate the first node and the second node, the display device can display normally during the display phase. During the touch phase, the first node is kept at a high potential, while the second node and the signal output node of this stage are both pulled down to a continuous low potential by the reset module. This ensures that the stress of the transistors in the gate drive circuit remains consistent, eliminating pitting issues. Attached Figure Description
[0044] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0045] Appendix Figure 1 This is a schematic diagram of the overall module of the gate driving unit in the embodiments of this application;
[0046] Appendix Figure 2 This is a schematic diagram of the specific modules of the gate driving unit in the embodiments of this application;
[0047] Appendix Figure 3 This is a circuit structure diagram of the gate driving unit in an embodiment of this application;
[0048] Appendix Figure 4 This is a timing diagram of the gate driving unit in an embodiment of this application;
[0049] Appendix Figure 5 This is a schematic diagram of the display panel structure in an embodiment of this application;
[0050] Appendix Figure 6 This is a schematic diagram of the display device in the embodiments of this application.
[0051] 1. Display device; 10. Display panel; 11. Gate driving circuit;
[0052] 100 Gate drive unit; 110 Input module; 120 Output module; 130 Isolation module; 140 Maintenance module; 141 First maintenance submodule; 142 Second maintenance submodule; 143 Third maintenance submodule; 150 Reset module; 151 First reset submodule; 152 Second reset submodule; 153 Third reset submodule. Detailed Implementation
[0053] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0054] It should be noted that the transistors used in the embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no distinction between them. In the embodiments of this application, to distinguish the source and drain of the transistor, one of them is called the first terminal and the other is called the second terminal. In addition, the gate of the transistor is called the control terminal. Furthermore, according to the characteristics of transistors, they can be divided into N-type and P-type. The following embodiments are described using N-type transistors. When using an N-type transistor, the first terminal is the source of the N-type transistor, and the second terminal is the drain of the N-type transistor. When the gate input is high, the source and drain are turned on. The opposite is true for P-type transistors. It is conceivable that using a P-type transistor is something that those skilled in the art can easily conceive of without creative effort, and therefore it is also within the protection scope of the embodiments of this application.
[0055] Since the transistors used in this embodiment are all N-type transistors, the working level signal in this embodiment refers to a high-level signal, and the non-working level signal refers to a low-level signal.
[0056] Reference Figure 1According to a first aspect of this application, a gate driving circuit 11 is provided, the gate driving circuit 11 including a plurality of cascaded gate driving units 100, at least one gate driving unit 100 including: an input module 110, an output module 120, an isolation module 130, a sustaining module 140 and a reset module 150. The input module 110 is electrically connected to the first node Q and is used to input a preset high potential to the first node Q by receiving the cascaded signal G(N-1) output from the previous stage; the output module 120 is electrically connected to the second node O and the signal output node G of this stage and is used to control the output potential of the signal output node G of this stage under the control of the potentials of the first node Q and the second node O; the isolation module 130 is electrically connected to the first node Q and the second node O and is used to isolate the potentials of the first node Q and the second node O in response to the inverted signal of the touch signal; the maintenance module 140 is electrically connected to the first node Q, the second node O and the signal output node G of this stage and is used to maintain the potentials of the first node Q, the second node O and the signal output node G of this stage; the reset module 150 is electrically connected to the first node Q, the second node O and the signal output node G of this stage and is used to reset the potentials of the first node Q, the second node O and the signal output node G of this stage to a low potential.
[0057] It should be noted that the output signal of this output node, which is the current row output signal, not only drives the pixels in this row, but also serves as both the reset signal for the previous row and the input signal for the next row. In the entire gate driving circuit 11, the input signal of the gate driving unit 100 of the first row is the frame start signal STV, and the first row does not output a reset signal; the gate driving unit 100 of the last row is connected to a row dummy, realizing the reset of the gate driving unit 100 of the last row.
[0058] Specifically, refer to Figure 2 In some embodiments of this application, the maintenance module 140 includes: a first maintenance submodule 141, a second maintenance submodule 142, and a third maintenance submodule 143. The first maintenance submodule 141 is electrically connected to the first node Q and is used to maintain the potential of the first node Q; the second maintenance submodule 142 is electrically connected to the second node O and is used to maintain the potential of the second node O; the third maintenance submodule 143 is electrically connected to the signal output node G of this stage and is used to maintain the potential of the signal output node G of this stage.
[0059] In some embodiments of this application, the reset module 150 includes: a first reset submodule 151, a second reset submodule 152, and a third reset submodule 153. The first reset submodule 151 is electrically connected to the first node Q and resets the potential of the first node Q in response to the cascaded signal G(N+1) of the next stage. The second reset submodule 152 is electrically connected to the second node O and is used to discharge and reset the potential of the second node O. The third reset submodule 153 is electrically connected to the signal output node G of the current stage and is used to reset the potential of the signal output node G of the current stage.
[0060] More specifically, refer to Figure 3 In some embodiments of this application, the input module 110 includes: a first transistor T1, the control electrode of the first transistor T1 is connected to the cascaded signal G(N-1) output from the previous stage, the first electrode of the first transistor T1 is electrically connected to the control electrode of the first transistor T1, and the second electrode of the first transistor T1 is electrically connected to the first node Q.
[0061] In some embodiments of this application, the output module 120 includes a second transistor T2 and a first capacitor C1. The control electrode of the second transistor T2 is connected to the second node O, the first electrode of the second transistor T2 is connected to the first clock signal, and the second electrode of the second transistor T2 is connected to the signal output node G of this stage. The first electrode of the first capacitor C1 is connected to the first node Q, and the second electrode of the first capacitor C1 is connected to the signal output node G of this stage. It should be noted that the second node O is the pull-up control node, the signal output node G of this stage is connected to the control electrode signal scan line of this stage, the second transistor T2 performs pull-up output and pull-down clearing of the control electrode signal scan line of this stage, and the first capacitor C1 is a bootstrap capacitor. The bootstrap capacitor is used to raise and stabilize the potential of the pull-up control node during the output process through capacitive coupling, thereby improving the charging speed of the scan signal line.
[0062] In some embodiments of this application, the isolation module 130 includes a third transistor T3, the control electrode of the third transistor T3 is connected to the inverted signal of the touch signal, the first electrode of the third transistor T3 is connected to the first node Q, and the second electrode of the third transistor T3 is connected to the second node O.
[0063] In some embodiments of this application, the first sustaining submodule 141 includes a fourth transistor T4 and a fifth transistor T5, wherein the control electrode and the first electrode of the fourth transistor T4 are both electrically connected to the first node Q; the control electrode of the fifth transistor T5 is electrically connected to the second electrode of the fourth transistor T4, the first electrode of the fifth transistor T5 is connected to a touch signal, and the second electrode of the fifth transistor T5 is electrically connected to the first node Q.
[0064] In some embodiments of this application, the second sustaining submodule 142 includes a first inverter and a sixth transistor T6, wherein the input terminal of the first inverter is electrically connected to the second node O; and the control terminal of the sixth transistor T6 is electrically connected to the output terminal of the first inverter; the first terminal of the sixth transistor T6 is electrically connected to the second node O, and the second terminal of the sixth transistor T6 is connected to a constant low-potential signal. It should be noted that the constant low-potential signal in the embodiments of this application can be the control terminal shutdown voltage VGL of the display panel 10.
[0065] In some embodiments of this application, the third sustaining submodule 143 includes a first inverter and a seventh transistor T7, wherein the input terminal of the first inverter is electrically connected to the second node O; the control terminal of the seventh transistor T7 is electrically connected to the output terminal of the first inverter, the first terminal of the seventh transistor T7 is electrically connected to the signal output node G of this stage, and the second terminal of the sixth transistor T6 is connected to a constant low-potential signal. It should be noted that in this embodiment, both the third sustaining submodule 143 and the second sustaining submodule 142 use the first inverter, which can be the same inverter. The sixth transistor T6 and the seventh transistor T7 are connected to different output terminals of the first inverter. In some embodiments, the second sustaining submodule 142 and the third sustaining submodule 143 may also use different inverters; this application does not impose any restrictions on this.
[0066] In some embodiments of this application, the first reset submodule 151 includes an eighth transistor T8, the control electrode of the eighth transistor T8 is connected to the cascade signal G(N+1) of the next stage, the first electrode of the eighth transistor T8 is electrically connected to the first node Q, and the second electrode of the eighth transistor T8 is connected to a constant low potential signal.
[0067] In some embodiments of this application, the second reset submodule 152 includes a ninth transistor T9. The control electrode of the ninth transistor T9 is connected to a touch signal, the first electrode of the ninth transistor T9 is electrically connected to the second node O, and the second electrode of the ninth transistor T9 is connected to a constant low-potential signal. In addition to replacing a general reset circuit, the ninth transistor T9 can also clear the charge from the second node O each time the circuit stops, reducing the risk of charge residue.
[0068] In some embodiments of this application, the third reset submodule 153 includes a tenth transistor T10. The control electrode of the tenth transistor T10 is connected to a touch signal, the first electrode of the tenth transistor T10 is electrically connected to the signal output node G of this stage, and the second electrode of the tenth transistor T10 is connected to a constant low-potential signal. It should be noted that the control electrode of the ninth transistor T9 is interconnected with the control electrode of the tenth transistor T10 and is connected to a touch signal. The function of the tenth transistor T10 is similar to that of the ninth transistor T9; in addition to replacing a general reset circuit, it can also clear the charge on the signal output node G of this stage each time the circuit stops, reducing the risk of charge residue. Furthermore, the tenth transistor T10 can also synchronously output a small waveform to the signal output node G of this stage, reducing the in-plane loading time of the display panel 10 and improving the touch performance of the display panel 10.
[0069] It should be noted that during the touch phase, the gate drive circuit 11 needs to be paused to collect touch signals. At this time, the clock signal requires the paused pulse signal to be set to a constant low potential signal. The clock signal can only resume normal pulse signal after the touch phase ends. This inevitably requires some pull-up nodes of the gate drive unit 100 (i.e., the second node O in this application) to store high voltage during the touch period. The gate drive circuit 11 can only continue to work normally after the touch period ends. Among them, the pull-up nodes store high voltage during the touch phase, which is called the stop pit level. However, the potential of the pull-up nodes of most gate drive units 100 is low during the touch period. Since the related technology does not have an isolation module to separate the first node Q and the second node O, the voltage difference between the pull-up nodes of the stop pit level and the non-stop pit level may form the problem of stop pit lines.
[0070] Reference Figure 4 As shown, Figure 3 The timing diagram of some signals in the gate drive unit 100 shown is analyzed in stages below:
[0071] In display stage 1, the inverted signal of the touch signal set in this application is at a high potential, the third transistor T3 is normally open, the first node Q and the second node O are both at a high potential, and the display panel 10 displays normally.
[0072] During the touch phase, the inverted touch signal becomes low, at which point the third transistor T3 is turned off, the first node Q remains high, and the second node O and the signal output node G of this stage are continuously pulled low by the ninth transistor T9 and the tenth transistor T10, respectively. This application allows the second node O to also be pulled low during the touch phase, without needing to remain consistently high, thus avoiding stress problems caused by the second transistor being consistently on. This ensures that the stresses of the second transistor T2, the sixth transistor T6, and the seventh transistor T7 remain consistent. It is important to note that transistors are subject to stress during operation, such as from temperature changes, electric fields, and mechanical stress. Maintaining consistent stress across multiple transistors is crucial because stress differences between different transistors can lead to performance imbalances, reliability issues, or device failures. Excessive stress differences between transistors can cause performance degradation or even failure of some transistors.
[0073] When the pit stops, i.e., in stage 2 shown in the figure, the inverted signal of the touch signal changes from low potential to high potential, the third transistor T3 turns on, the first node Q charges the second node O, and at this time the second transistor T2 turns on, i.e., the normal transmission is restored.
[0074] According to a second aspect of this application, a display panel 10 is provided, including the gate driving circuit 11 described above. This display panel 10 possesses all the beneficial effects of the aforementioned gate driving circuit 11, which will not be elaborated further here.
[0075] Reference Figure 5As shown, specifically, in some embodiments of this application, the display panel 10 includes multiple scan lines, multiple data lines, multiple sub-pixels arranged in an array, and a gate driving circuit 11 provided in any of the above embodiments. The gate driving circuit 11 is electrically connected to the scan lines, and each sub-pixel is electrically connected to a scan line and a data line. The gate driving circuit 11 includes multiple cascaded gate driving units 100. Each gate driving unit 100 includes at least: an input module 110 electrically connected to the first node Q, used to input a preset high potential to the first node Q by receiving the cascaded signal G(N-1) output from the previous stage; an output module 120 electrically connected to the second node O and the current stage signal output node G, used to control the output potential of the current stage signal output node G under the control of the potentials of the first node Q and the second node O; an isolation module 130 electrically connected to the first node Q and the second node O, used to isolate the potentials of the first node Q and the second node O in response to the inverted signal of the touch signal; a maintenance module 140 electrically connected to the first node Q, the second node O and the current stage signal output node G, used to maintain the potentials of the first node Q, the second node O and the current stage signal output node G; and a reset module 150 electrically connected to the first node Q, the second node O and the current stage signal output node G, used to reset the potentials of the first node Q, the second node O and the current stage signal output node G to a low potential.
[0076] Therefore, the display panel provided in this application embodiment, when including the above-described gate driving circuit, has all the beneficial effects of the above-described gate driving circuit, which will not be repeated here.
[0077] It should be noted that the display panel provided in this application embodiment can be applied to any product or component with display function, such as television, monitor, digital photo frame, mobile phone, tablet computer, etc. The display panel can also be used in combination with flexible circuit board, printed circuit board and back plate, etc.
[0078] Reference Figure 6 As shown, according to a third aspect of this application, a display device 1 is provided, including the display panel 10 of any of the above embodiments, and further including a source drive circuit, a system on chip, a power management chip, and a timing driver, etc. The display device 1 has all the beneficial effects of the aforementioned display panel 10, which will not be repeated here.
[0079] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer.
[0080] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0081] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0082] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.
[0083] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A gate driving circuit, characterized in that, It includes multiple cascaded gate driving units, at least one of the gate driving units comprising: The input module is electrically connected to the first node and is used to receive the cascaded signal output from the previous stage and input a preset high potential to the first node. The output module is electrically connected to the second node and the signal output node of this stage, and is used to control the output potential of the signal output node of this stage according to the potential of the first node and the potential of the second node; An isolation module, electrically connected to the first node and the second node, is used to isolate the potential of the first node and the second node in response to the inverted signal of the touch signal; A maintenance module, electrically connected to the first node, the second node, and the signal output node of this stage, is used to maintain the potential of the first node, the second node, and the signal output node of this stage; and, A reset module, electrically connected to the first node, the second node, and the signal output node of this stage, is used to reset the potentials of the first node, the second node, and the signal output node of this stage to a low potential; The reset module includes: a first reset submodule electrically connected to the first node, which resets the potential of the first node in response to a cascade signal from the next level; a second reset submodule electrically connected to the second node, which discharges and resets the potential of the second node; and a third reset submodule electrically connected to the signal output node of the current level, which resets the potential of the signal output node of the current level. The second reset submodule includes: a ninth transistor, comprising a control electrode that receives a touch signal, a first electrode that is electrically connected to the second node, and a second electrode that receives a constant low-potential signal; The maintenance module includes: a first maintenance submodule electrically connected to the first node for maintaining the potential of the first node; the first maintenance submodule includes: a fourth transistor including a second electrode, a control electrode electrically connected to the first node, and a first electrode; and a fifth transistor including a control electrode electrically connected to the second electrode of the fourth transistor, a first electrode for receiving touch signals, and a second electrode electrically connected to the first node. The isolation module includes a third transistor, comprising a control electrode for receiving the inverted signal of the touch signal, a first electrode electrically connected to the first node, and a second electrode electrically connected to the second node. During the touch phase, the third transistor is turned off in response to the inverted signal of the touch signal, causing the second node to be pulled low to a low potential by the ninth transistor. After the touch phase ends, the third transistor is turned on in response to the inverted signal of the touch signal, causing the first node to charge the second node.
2. The gate driving circuit according to claim 1, characterized in that, The input module includes: The first transistor includes a control electrode connected to the cascaded signal output from the previous stage, a first electrode electrically connected to the control electrode, and a second electrode electrically connected to the first node.
3. The gate driving circuit according to claim 1, characterized in that, The output module includes: The second transistor includes a control electrode electrically connected to the second node, a first electrode connected to a first clock signal, and a second electrode electrically connected to the signal output node of this stage; and... The first capacitor includes a first electrode electrically connected to the first node and a second electrode electrically connected to the signal output node of this stage.
4. The gate driving circuit according to claim 1, characterized in that, The maintenance module further includes: The second maintenance submodule is electrically connected to the second node and is used to maintain the potential of the second node; The third maintenance submodule is electrically connected to the signal output node of this level and is used to maintain the potential of the signal output node of this level.
5. The gate driving circuit according to claim 4, characterized in that, The second maintenance submodule includes: The first inverter includes an output terminal and an input terminal electrically connected to the second node; and, The sixth transistor includes a control electrode electrically connected to the output of the first inverter, a first electrode electrically connected to the second node, and a second electrode connected to a constant low-potential signal.
6. The gate driving circuit according to claim 4, characterized in that, The third maintenance submodule includes: The first inverter includes an output terminal and an input terminal electrically connected to the second node; and, The seventh transistor includes a control electrode electrically connected to the output terminal of the first inverter, a first electrode electrically connected to the signal output node of the same stage, and a second electrode of the seventh transistor connected to a constant low potential signal.
7. The gate driving circuit according to claim 1, characterized in that, The first reset submodule includes: The eighth transistor includes a control electrode that receives the cascaded signal for the next stage, a first electrode that is electrically connected to the first node, and a second electrode that receives a constant low-potential signal.
8. The gate driving circuit according to claim 1, characterized in that, The third reset submodule includes: The tenth transistor includes a control electrode that receives the touch signal, a first electrode that is electrically connected to the signal output node of this stage, and a second electrode that receives a constant low-potential signal.
9. A display panel, characterized in that, Includes the gate drive circuit as described in any one of claims 1 to 8.
10. A display device, characterized in that, Includes the display panel as described in claim 9.