Readout circuit for anti-fuse memory, readout method for anti-fuse memory, and anti-fuse memory

Abstract

The readout circuit of the anti-fuse memory is used for reading logic of a specific anti-fuse cell in the anti-fuse memory, and comprises a pre-charging PMOS, a source electrode of the pre-charging PMOS is connected to a memory internal power supply, a drain electrode of the pre-charging PMOS is connected to a bit line of a selected specific anti-fuse cell, a grid electrode of the pre-charging PMOS is input with a read enable signal, and the read enable signal is input into the pre-charging PMOS; the pre-charging PMOS is used for pre-charging the bit line to a specified level of the internal power supply of the memory; a comparator to which a level of the bit line is input, to which a reference level is input, and to which a positive input terminal of the comparator compares the level of the bit line with the reference level, and outputs a comparison result from an output terminal; the feedback circuit is composed of a PMOS (P-channel Metal Oxide Semiconductor), the source electrode of the PMOS is connected to an internal power supply of the memory, the drain electrode of the PMOS is connected to the bit line of the selected specific anti-fuse unit, and the grid electrode of the PMOS is connected to the output end of the comparator; and a latch that receives the comparison result output from the output terminal of the comparator, latches and outputs the comparison result, and the feedback circuit is configured to slow down the voltage drop speed of the bit line when the bit line of the selected specific anti-fuse cell is discharged due to a decrease in the resistance value of the specific anti-fuse cell.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a readout circuit of an anti-fuse memory, a readout method of an anti-fuse memory, and an anti-fuse memory. Background Art

[0002] Semiconductor memory devices are electronic devices used to store data and are widely used in computers, mobile phones, embedded systems and other devices. Semiconductor memory chips can be divided into many types according to the way and purpose of storing data. One-time programmable (OTP) memory is a non-volatile memory technology that allows data to be permanently stored and cannot be changed after programming. This feature makes OTP memory very suitable for applications that require high security and data integrity.

[0003] As a non-volatile memory technology, antifuse memory is mainly used in one-time programmable (OTP) applications. Antifuse memory is widely used in semiconductor memory to store the address of damaged main memory cells. Its working principle is to store data by permanently changing the resistance state of the memory cell during the programming process. Specifically, a very high voltage is applied to the gate oxide dielectric of the antifuse memory cell to break it down. After the breakdown, the impedance of the path is reduced. At this time, the storage logic 1 and logic 0 are determined by detecting the impedance of the antifuse memory cell. In the unprogrammed state, it is high impedance, usually indicating logic "0", and in the programmed state, it is low impedance, usually indicating logic "1". In short, the unprogrammed antifuse memory cell stores "0", and the programmed antifuse memory cell stores "1".

[0004] Due to the non-volatility of antifuse memory, data can still be retained after power failure, and once programming is completed, the data cannot be changed, which makes it suitable for application scenarios that require permanent storage. Since the data cannot be changed, antifuse memory is very useful in applications with high security requirements, and antifuse memory also shows good stability in high radiation environments. Therefore, antifuse memory is often used to store encryption keys, configuration data, and firmware, and is suitable for working in extreme environments. In addition, it is used to store configuration data and calibration parameters in ASIC (application-specific integrated circuit), for secure storage of configuration data in FPGA (field programmable gate array), and for storing firmware and configuration data in industrial control systems to ensure that the system can recover quickly after power failure. Due to these characteristics, antifuse memory is very useful in situations that require high security, durability, and reliability. Summary of the invention

[0005] Technical Problems to be Solved by the Invention

[0006] The working principle of the anti-fuse memory is to apply a very high voltage to the gate oxide dielectric of the anti-fuse memory cell to break it down. After the breakdown, the impedance of the path is reduced, and the storage logic "1" and storage logic "0" are determined by detecting the impedance of the anti-fuse cell. The impedance of the programmed anti-fuse memory cell is reduced, and the logic "1" is stored. The impedance of the anti-fuse memory cell that has not been programmed is very large, and the logic "0" is stored. Ideally, the anti-fuse memory cell that has not been programmed should read 0, but because there is sometimes leakage in the programming path, and the voltage used in the programming process is very high, it may also affect some non-target fuses, thereby causing their impedance to decrease. Therefore, the logic "0" stored in the cell may be mistakenly read as "1", resulting in a decrease in the read accuracy of the anti-fuse memory. In addition, due to the difference in process voltage and temperature, the impedance difference of the programmed fuse is also very large, which sometimes leads to a decrease in the read accuracy of the anti-fuse memory.

[0007] The present invention is completed to solve the above-mentioned problems, and its purpose is to provide a read circuit of an anti-fuse memory, a read method based on the read circuit and an anti-fuse memory having the read circuit, which can improve the read accuracy of the anti-fuse memory and adjust the margin of the read impedance.

[0008] Technical solutions adopted to solve technical problems

[0009] In one embodiment of the present invention, a readout circuit of an anti-fuse memory is provided, which is used to read the logic of a specific anti-fuse unit in the anti-fuse memory, and the readout circuit includes: a pre-charge PMOS, the source of which is connected to the internal power supply of the memory, the drain of which is connected to the bit line of the selected specific anti-fuse unit, and the gate of which is input with a read enable signal, and the pre-charge PMOS pre-charges the bit line to a specified level of the internal power supply of the memory; a comparator, the level of the bit line is input to the negative input terminal of the comparator, the reference level is input to the positive input terminal of the comparator, and the comparator compares the level of the bit line with the selected bit line. The invention relates to a memory device comprising a memory device and a feedback circuit, wherein the feedback circuit comprises a PMOS, wherein the source of the PMOS is connected to the internal power supply of the memory, the drain is connected to the bit line of the selected specific anti-fuse unit, and the gate is connected to the output terminal of the comparator; and a latch, wherein the latch receives the comparison result output from the output terminal of the comparator, latches and outputs the comparison result, and the feedback circuit is configured to slow down the voltage drop speed of the bit line when the bit line of the selected specific anti-fuse unit is discharged due to the reduction of the resistance value of the specific anti-fuse unit.

[0010] In one embodiment of the present invention, a readout circuit of an anti-fuse memory is provided, which is used to read the logic of a specific anti-fuse unit in the anti-fuse memory, and the readout circuit includes: a precharge PMOS, the source of which is connected to the internal power supply of the memory, the drain of which is connected to the bit line of the selected specific anti-fuse unit, and the gate of which is input with a read enable signal, and the precharge PMOS precharges the bit line to a specified level of the internal power supply of the memory; a comparator, the level of the bit line is input to the negative input terminal of the comparator, the reference level is input to the positive input terminal of the comparator, the comparator compares the level of the bit line with the reference level, and outputs the comparison result from the output terminal; a feedback circuit, which is composed of a main anti-fuse The invention relates to a circuit composed of a feedback PMOS, a first margin adjustment PMOS, a second margin adjustment PMOS and a third margin adjustment PMOS; and a latch, which receives the comparison result output from the output end of the comparator, latches and outputs the comparison result, the feedback circuit is configured to slow down the voltage drop speed of the bit line when the bit line of the selected specific anti-fuse unit is discharged due to the reduction of the resistance value of the specific anti-fuse unit, and is configured to adjust the maximum resistance value of the programmed specific anti-fuse unit that can be read by adjusting the number of on and off of the first margin adjustment PMOS, the second margin adjustment PMOS and the third margin adjustment PMOS.

[0011] In one embodiment of the present invention, a method for reading an anti-fuse memory is proposed, wherein the logic of a specific anti-fuse unit is read in the anti-fuse memory using the read circuit of the anti-fuse memory. The method comprises: using a precharge PMOS having a source connected to an internal power supply of the memory, a drain connected to a bit line of the selected specific anti-fuse unit, and a gate input with a read enable signal, to precharge the bit line to a specified level of the internal power supply of the memory; using a feedback circuit to slow down the voltage drop speed of the bit line when the bit line of the selected specific anti-fuse unit is discharged due to a decrease in the resistance value of the specific anti-fuse unit; using a comparator to compare the level of the bit line input to the negative input terminal of the comparator with the reference level input to the positive input terminal of the comparator, and outputting the comparison result from the output terminal of the comparator; using a latch to receive the comparison result output from the output terminal of the comparator, latching and outputting the comparison result.

[0012] In one embodiment of the present invention, an anti-fuse memory is proposed, which includes: a plurality of anti-fuse sub-arrays, each of the plurality of anti-fuse sub-arrays is composed of a plurality of anti-fuse units; a sub-array selection unit, the sub-array selection unit is used to select the anti-fuse sub-array; a bit line selection unit, the bit line selection unit is used to select the bit line of a specific anti-fuse unit in the anti-fuse sub-array; and a read circuit of the above-mentioned anti-fuse memory, the read circuit is used to read the logic of the specific anti-fuse unit in the anti-fuse memory.

[0013] Effects of the Invention

[0014] According to the readout circuit of the anti-fuse memory, the readout method based on the readout circuit and the anti-fuse memory having the readout circuit disclosed in the present invention, the readout accuracy of the anti-fuse memory can be improved and the readout impedance margin can be adjusted. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present disclosure may be better understood by describing exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, in which:

[0016] Figure 1 is a schematic diagram showing the structure of an anti-fuse memory.

[0017] Figure 2 FIG. 1 is a diagram showing a specific structure of a read circuit of an anti-fuse memory.

[0018] Figure 3 This is a diagram showing a specific configuration of a read circuit of the anti-fuse memory according to the first embodiment of the present invention.

[0019] Figure 4 This is a circuit diagram of a feedback circuit according to Embodiment 2 of the present invention.

[0020] Figure 5 FIG. 1 is a timing diagram of reading out the anti-fuse cell when reading out using a conventional reading circuit.

[0021] Figure 6 In the figure, the left figure is a timing diagram showing the current reading after the resistance of the anti-fuse unit is reduced, and the right figure is a timing diagram showing the reading after the resistance of the anti-fuse unit is reduced in the present invention.

[0022] Figure 7 This is a table for adjusting the resistance value margin of the anti-fuse unit based on the feedback circuit according to the second embodiment of the present invention.

[0023] Explanation of reference numerals: 100 anti-fuse memory, 101a, 101n anti-fuse sub-array, FASel sub-array selection unit, BLSW bit line selection unit, WL0, WL1, WLx word lines, BL0, BLn, DBL0 bit lines, 102, 102A readout circuit, A anti-fuse unit, 1021 pre-charge PMOS, 1022 comparator, 1023 latch, 1024, 1024A feedback circuit, PM main feedback PMOS, P0, P1, P2 margin adjustment PMOS. DETAILED DESCRIPTION

[0024] The specific implementation methods of the present disclosure will be described below. It should be noted that in the specific description of these implementation methods, in order to provide a concise description, it is impossible for this specification to provide a detailed description of all the features of the actual implementation methods. It should be understood that in the actual implementation of any implementation method, just as in the process of any engineering project or design project, in order to achieve the specific goals of the developer and to meet system-related or business-related restrictions, various specific decisions are often made, and this will also change from one implementation method to another. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for ordinary technicians in the field related to the content disclosed by the present disclosure, some changes in design, manufacturing or production based on the technical content disclosed in the present disclosure are just conventional technical means, and should not be understood as insufficient content of the present disclosure.

[0025] Unless otherwise defined, the technical or scientific terms used in the claims and the specification shall have the usual meaning understood by persons with ordinary skills in the technical field to which the present disclosure belongs. The words "first", "second" and similar words used in the patent application specification and the claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "one" or "one" do not indicate a quantitative limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalent elements, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, nor are they limited to direct or indirect connections.

[0026] In the present disclosure, unless otherwise specified, all embodiments and preferred embodiments mentioned herein can be combined with each other to form a new technical solution. In the present disclosure, unless otherwise specified, all technical features and preferred features mentioned herein can be combined with each other to form a new technical solution.

[0027] Hereinafter, a read circuit of an anti-fuse memory and an anti-fuse memory including the read circuit according to an embodiment of the present invention will be described in detail with reference to the drawings.

[0028] Figure 1 is a schematic diagram showing the structure of the anti-fuse memory 100 .

[0029] like Figure 1 As shown, the anti-fuse memory 100 includes a plurality of anti-fuse sub-arrays 101 a - 101 n , a sub-array selection unit FASel, a bit line selection unit BLSW and a readout circuit 102 , wherein n is a natural number greater than 1.

[0030] Each antifuse sub-array 101a-101n is composed of a plurality of antifuse cells, which are the basic building blocks of the antifuse memory and are used to store one bit of binary information. Each antifuse cell represents the stored data by its physical state (high impedance or low impedance). Each antifuse sub-array includes x×n antifuse cells (x and n are natural numbers greater than 1), whose rows constitute word lines WL0-WLx, and whose columns constitute bit lines BL0-BLn. Each sub-array 101a-101n can be selected by a sub-array selection unit FASel, and a specific antifuse cell can be selected according to the word lines WL0-WLx and the bit lines BL0-BLn.

[0031] The readout circuit 102 is used to read the state of the anti-fuse unit, and determines whether the anti-fuse unit has been programmed by reading "0" or "1". Generally, the readout circuit 102 can read more than 16 bits of the anti-fuse array, thereby realizing efficient state confirmation of the anti-fuse unit, but for ease of understanding, it is assumed that only the state of one anti-fuse unit is read.

[0032] Figure 1 In the figure, the solid line on the left represents the write path, i.e., the programming path, which is blown by applying a very high voltage to the selected anti-fuse unit. During the programming process, vbi_sw is a voltage much higher than the internal normal voltage VPP and VBB (not shown). The dotted line on the right represents the read path, through which the logic value stored in the anti-fuse unit can be read. During the read process, vbi_sw is the internal normal voltage VPP and VBB (not shown).

[0033] Figure 2 1 is a diagram showing a specific structure of the read circuit 102 of the anti-fuse memory. Here, as an example, the read circuit 102 is used to read the anti-fuse unit A (ie, Figure 2 The state of the leftmost anti-fuse unit A).

[0034] like Figure 2 As shown, the readout circuit 102 is a general anti-fuse readout circuit, which is connected to the output of the bit line selection unit BLSW of the anti-fuse memory 100 and includes a precharge PMOS 1021 , a comparator 1022 , and a latch 1023 .

[0035] Among them, precharge PMOS is usually used in dynamic logic circuits, especially in dynamic random access memory (DRAM) and dynamic logic circuits (such as dynamic CMOS circuits). The main function of the precharge circuit is to precharge the node to a high level so as to perform corresponding logic operations in the evaluation stage.

[0036] In this example, the source of the precharge PMOS 1021 is connected to the memory internal power supply vti, the drain is connected to the selected bit line DBL0, and the read enable signal RdEn is input to the gate of the precharge PMOS 1021. The voltage of the power supply vti is the memory internal voltage and is set to a predetermined level.

[0037] The comparator 1022 is an electronic comparator for comparing the magnitudes of two voltage (or current) signals and outputting a comparison result. The comparator 1022 has two input terminals, namely, a positive input (+) and a negative input (-). The voltage of the bit line DBL0 is input to "-", and the reference voltage VREF is input to "+". The comparator 1022 is used to compare the magnitudes of the outputted voltage of the bit line DBL0 and the reference voltage VREF, and outputs a comparison result. Specifically, when the voltage (level) of the bit line DBL0 is greater than the voltage (level) of VREF, a low level is output, and when the voltage (level) of the bit line DBL0 is less than the voltage (level) of VREF, a high level is output.

[0038] A latch is a basic storage element used to store one bit of binary information. It is a bistable circuit, which means it has two stable states and can maintain its state until the input signal changes. Latches are usually used in digital circuits as basic storage units. In this example, latch 1023 is connected to the output of comparator 1022, receives and latches the output from comparator 1022, and finally outputs DLAT, i.e., the logic of anti-fuse unit A. Next, the specific reading process of anti-fuse unit A is described.

[0039] First, the reading process when the anti-fuse cell A is in an unprogrammed state is described.

[0040] During the read process, the precharge (PRE) stage is first entered, the read word line RWL0, the bit line selection signal BLSW0 and the subarray selection signal FA0 are enabled, the read enable signal RdEn maintains a low level, and the bit lines DBL0 and BL0 are precharged to vti (the internal voltage of the memory, that is, the specified level described above).

[0041] Then enter the sensing stage (Sense), RdEn is pulled high, the precharge circuit is closed, and the latch is enabled. Since the selected anti-fuse unit A is in an unprogrammed state, its impedance is large (for ease of understanding, it can be regarded as a capacitor here), so it is impossible to discharge the bit lines DBL0 and BL0 through the anti-fuse unit A at this time. In the absence of internal leakage, the potential of the bit lines DBL0 and BL0 is approximately equal to the voltage vti (prescribed level). That is, the voltage input to the negative input terminal (-) of the comparator 1022 is vti. In addition, the voltage VREF is a reference for comparison, which is generally set to a fixed value, and is set to vti / 2 here. In other words, the voltage input to the positive input terminal (+) of the comparator 1022 is VREF=vti / 2. Since the voltage of the bit line DBL0 (i.e., vti)>VREF(vti / 2), the comparator 1022 outputs a low voltage, that is, outputs logic "0", which is input to the input D of the latch 1023, and the reading process ends.

[0042] Finally, in the local latch stage (Lat&load locally), the output DLAT of the latch will output logic "0".

[0043] Next, in order to make the description clearer, combined with the above description, and refer to Figure 5 The reading process when the anti-fuse cell A is in a programmed state is described.

[0044] Figure 5 1 is a timing chart of reading out the anti-fuse cell A when reading is performed using the conventional reading circuit 102 .

[0045] During the read process, the precharge (PRE) stage is first entered, the read word line RWL0, the bit line selection signal BLSW0 and the subarray selection signal FA0 are enabled, the read enable signal RdEn maintains a low level, and the bit lines DBL0 and BL0 are precharged to vti (internal voltage of the memory).

[0046] Then enter the sensing phase (Sense), RdEn is pulled high, the precharge circuit is closed, and the latch is enabled. Since the selected anti-fuse unit A is in a programmed state, its impedance is small (for ease of understanding, it can be regarded as a resistor here. Figure 5The resistance Rfuse is 500Ω), so the bit lines DBL0 and BL0 can be discharged through the anti-fuse unit A at this time.

[0047] like Figure 5 As shown, RdEn is a read enable signal, UDTEN is an internal signal, DBL and BL represent the voltages of the bit lines DBL0 and BL0 respectively (since the anti-fuse unit A for reading the bit line BL0 is selected, DBL and BL are actually the same and change synchronously), VREF represents a reference voltage, and DLAT represents the output of the latch 1023.

[0048] Since the anti-fuse unit A has been programmed, its resistance is small (e.g. Figure 5 As shown, in this example, it is 500Ω), the bit lines DBL0 and BL0 can be discharged through the anti-fuse unit A, so the voltage of the bit lines DBL0 and BL0 drops rapidly. Figure 5 As shown, in the sensing phase (Sense), the potentials of the bit lines DBL0 and BL0 drop rapidly below VREF (=vti / 2).

[0049] Similar to the case where the anti-fuse unit has not been programmed, the voltages of the bit lines DBL0 and BL0 are input to the negative input terminal (-) of the comparator 1022, and the reference voltage VREF (= vti / 2) is input to the positive input terminal (+) of the comparator 1022. At this time, the voltage of the bit line DBL0 is less than VREF (= vti / 2), so the comparator 1022 outputs a high voltage, that is, outputs logic "1", which is input to the input D of the latch 1023.

[0050] Finally, in the local latching stage (Lat&load locally), the output DLAT of the latch will output logic "1" and the reading process is completed.

[0051] As mentioned above, the anti-fuse storage array is generally used in semiconductor memory to store the addresses of damaged storage cells. As the capacity of semiconductor memory increases, more and more anti-fuse (storage) cells are required, that is, the capacity of anti-fuse memory increases. In order to save area, more anti-fuse cells share more common nodes. When a high voltage is applied to some anti-fuse cells for programming, it will inevitably affect some adjacent non-target anti-fuse cells and cause their impedance (resistance) to decrease. At this time, when reading these anti-fuse cells, the voltage on their bit lines will also decrease. On the other hand, during the reading process, although the programming path is closed, the transistors (MOSFET, IGBT, etc.) used in programming usually have high power, and their leakage will also reduce the voltage on the bit line.

[0052] In addition, due to the influence of process voltage, temperature, etc., the resistance values ​​of different anti-fuse units after being programmed are also different, and may be in a very large range. Figure 5 The anti-fuse unit is shown in an ideal state after programming, with a resistance value of 500Ω, indicating a good programming result. At this time, the bit line discharges faster and is less likely to have a misreading problem.

[0053] Therefore, as described above, when a high voltage is applied to some anti-fuse cells for programming, the adjacent non-target anti-fuse cells are affected and their impedance (resistance) is reduced, which may cause a problem of erroneous reading.

[0054] Figure 6 In the figure, the left figure is a timing diagram showing the current reading after the resistance of the anti-fuse unit A is reduced, and the right figure is a timing diagram showing the reading after the resistance of the anti-fuse unit A is reduced in the present invention.

[0055] like Figure 6 As shown, assuming that the resistance of the anti-fuse unit A is affected by the high voltage and decreases, for example, to 1000KΩ (=1MΩ). At this time, the anti-fuse unit A has not actually been programmed (in this case, it is equivalent to the anti-fuse unit A being misprogrammed or misburned), so it should be read as "not programmed", that is, logic "0".

[0056] However, if Figure 6 As shown in the left figure, when the existing read circuit 102 is used for reading, due to the reduction of its resistance, the bit lines DBL0 and BL0 can be discharged through the anti-fuse unit A. Although the voltage drop rate of the bit lines DBL0 and BL0 is relatively slow, in the sensing stage (Sense), the voltage of the bit line DBL0 still drops to a level lower than the reference voltage VREF (=vti / 2), so the comparator 1022 outputs a high voltage, that is, outputs logic "1", causing the reading result to become "programmed", that is, logic "1", which is opposite to the original logic, that is, an erroneous reading occurs.

[0057] In the embodiments of the present invention, a method for solving the above-mentioned problems is disclosed.

[0058] (Implementation Method 1)

[0059] Figure 3 This is a diagram showing a specific configuration of a read circuit 102A of the anti-fuse memory according to the first embodiment of the present invention.

[0060] like Figure 3As shown, the read circuit 102A according to the first embodiment of the present invention is connected to the output of the bit line selection unit BLSW of the anti-fuse memory 100 and includes a precharge PMOS 1021 , a feedback circuit 1024 , a comparator 1022 and a latch 1023 .

[0061] The configurations of the precharge PMOS 1021 , the comparator 1022 , and the latch 1023 are the same as those in the read circuit 102 , and therefore, the first embodiment of the present invention will be described below with the feedback circuit 1024 as the center.

[0062] In the first embodiment, the feedback circuit 1024 is composed of a PMOS, the source of which is connected to the memory internal power supply vti (a predetermined level vti is input), the drain of which is connected to the selected bit line DBL0, and the gate of which is connected to the output of the comparator 1022, so as to feed back the voltage of the memory internal power supply vti (i.e., feed back the predetermined level). The feedback circuit 1024 is configured to slow down the voltage drop speed of the bit line DBL0 when the selected bit line DBL0 is discharged due to the decrease in the resistance value of the anti-fuse unit A.

[0063] Below, refer to Figure 6 The effects of the readout circuit 102A according to the first embodiment of the present invention will be described. Figure 6 The right figure is a timing diagram showing when reading is performed after the resistance of the anti-fuse unit A is reduced in the present invention.

[0064] like Figure 6 As shown, assuming that the resistance of the anti-fuse unit A is reduced by the high voltage, for example, to 1000KΩ (=1MΩ). At this time, the anti-fuse unit A has not been programmed (i.e., misprogrammed or misburned), and should be read as "not programmed", i.e., logic "0".

[0065] like Figure 6As shown in the right figure of , when reading is performed using the readout circuit 102A involved in the first embodiment of the present invention, the anti-fuse unit A is affected by the high voltage when programming the adjacent anti-fuse unit, for example, causing its resistance to decrease. At this time, the bit lines DBL0 and BL0 can be discharged through the anti-fuse unit A. Since the feedback circuit 104 is provided, the power supply voltage vti (internal voltage of the memory) can be fed back through the feedback circuit 104, so the voltage drop speed of the bit lines DBL0 and BL0 slows down. In the sensing stage (Sense), the voltage (DBL) of the bit line DBL0 does not drop to a level lower than the reference voltage VREF (=vti / 2), so DBL>VREF, and the comparator 1022 outputs a low voltage, that is, outputs a logic "0". The result of the reading at this time is "not programmed", that is, a logic "0", which is in line with the actual situation, thereby avoiding the erroneous reading of the anti-fuse unit A that has not been programmed.

[0066] According to the first embodiment, the read accuracy of the anti-fuse memory can be improved, and a situation where an unprogrammed anti-fuse cell is erroneously read as a programmed anti-fuse cell can be avoided.

[0067] (Implementation Method 2)

[0068] In the above-mentioned Embodiment 1, even if the resistance of the anti-fuse unit A is reduced to 1000KΩ (=1MΩ), the erroneous reading of the anti-fuse unit that has not been programmed can be avoided. In other words, in Embodiment 1, the maximum resistance value Rmax of the programmed anti-fuse unit that can be read is 1000KΩ (=1MΩ). In order to achieve this resistance value, it can be achieved by changing the structure of the feedback circuit 1024, specifically, it can be achieved by changing the channel length of the PMOS constituting the feedback circuit 1024.

[0069] However, due to the difference in process voltage and temperature, the resistance of the programmed anti-fuse units is not the same, and their resistance values ​​are distributed in a range (Rmin~Rmax). If only a single PMOS is used as the feedback circuit 1024, it can only cope with a certain situation. When facing anti-fuse memories with different specifications, the PMOS constituting the feedback circuit 1024 needs to be manually replaced each time, so the applicability is poor and it cannot cope with multiple situations. In embodiment 2 of the present invention, a method for solving this problem is disclosed.

[0070] In order to cover the above resistance range more flexibly and thus improve the accuracy and margin of reading the programmed antifuse, use Figure 4 The circuit to achieve Figure 3 The feedback circuit 1024 in.

[0071] Figure 4 1024A is a circuit diagram of a feedback circuit 1024A according to Embodiment 2 of the present invention.

[0072] like Figure 4 As shown, the feedback circuit 1024A is composed of a main feedback PMOS PM, a margin adjustment PMOS P0 (a first margin adjustment PMOS), a margin adjustment PMOS P1 (a second margin adjustment PMOS), and a margin adjustment PMOS P2 (a third margin adjustment PMOS).

[0073] The source of the main feedback PMOS PM is connected to the power supply voltage vti (internal voltage of the memory), the drain is connected to the selected bit line DBL0, and the gate is connected to the output terminal of the comparator 1022. The margin adjustment PMOS P0, margin adjustment PMOS P1 and margin adjustment PMOS P2 are PMOSs of different specifications (for example, different channel lengths), and their sources are connected to the internal power supply vti of the memory (with a specified voltage level vti input), the drain is connected to the selected bit line DBL0, and the gate is connected to a control circuit not shown. The feedback circuit 1024A is configured to slow down the voltage drop speed of the bit line DBL0 when the selected bit line DBL0 is discharged due to the decrease in the resistance value of the anti-fuse unit A, and is configured to adjust the maximum resistance value Rmax of the programmed anti-fuse unit A that can be read by adjusting the number of on and off of the margin adjustment PMOS P0, margin adjustment PMOS P1 and margin adjustment PMOS P2.

[0074] Figure 7 This is a table for adjusting the resistance value margin of the anti-fuse cell readout based on the feedback circuit 1024A according to the second embodiment of the present invention.

[0075] like Figure 7 As shown, four different margin adjustment situations are shown. Among them, ST_RDM<1:0> represents various situations of read margin, specifically, including four situations of 'b00, 'b01, 'b02, and 'b03. PSel<2:0> represents the setting parameters of each margin adjustment PMOS when implementing various margin adjustments. The read margin represents the maximum resistance value Rmax of the programmed anti-fuse unit that can be read.

[0076] In the case of 'b00, the setting parameters of each margin adjustment PMOS are set to 'b011. At this time, the maximum resistance value Rmax of the programmed anti-fuse unit that can be read is 380KΩ (this setting is the default value).

[0077] In the case of 'b01, the setting parameters of each margin adjustment PMOS are set to 'b101, and the maximum resistance value Rmax of the programmed anti-fuse unit that can be read is 450KΩ.

[0078] In the case of 'b10, the setting parameters of each margin adjustment PMOS are set to 'b001, and the maximum resistance value Rmax of the programmed anti-fuse unit that can be read is 330KΩ.

[0079] In the case of 'b11, the setting parameters of each margin adjustment PMOS are set to 'b000, and the maximum resistance value Rmax of the programmed anti-fuse unit that can be read is 250KΩ.

[0080] Through the feedback circuit 1024A involved in embodiment 2 of the present invention, as in the above-mentioned embodiment 1, the read accuracy of the anti-fuse memory can be improved, and the situation where an unprogrammed anti-fuse unit is mistakenly read as a programmed one can be avoided. In addition, the read impedance (resistance value) margin of the anti-fuse unit can also be adjusted.

[0081] The adjustment of each margin adjustment PMOS can be automatically performed by the program. Therefore, when facing anti-fuse memories with different specifications, the feedback circuit 1024A can be automatically set according to the maximum resistance value Rmax of the programmed anti-fuse unit that can be read. It has good applicability and can cope with various situations. According to the readout circuit involved in the present invention, the accuracy of reading logic "1" and logic "0" is improved, and the readout resistance value margin of the anti-fuse unit can be adjusted. According to the resistance distribution diagram of the programmed anti-fuse, the margin of logic "1" and logic "0" can be read more balanced.

[0082] In addition, the present invention proposes a readout method of an anti-fuse memory, which uses the readout circuit of the anti-fuse memory described in embodiment 1 or 2 of the present invention to read the logic of a specific anti-fuse unit in the anti-fuse memory, and the readout method includes: using a pre-charge PMOS whose source is connected to the internal power supply of the memory, the drain is connected to the bit line of the selected specific anti-fuse unit, and the gate is input with a read enable signal, to pre-charge the bit line to a specified level of the internal power supply of the memory; using a feedback circuit to slow down the voltage drop speed of the bit line when the bit line of the selected specific anti-fuse unit is discharged due to the reduction of the resistance value of the specific anti-fuse unit; using a comparator to compare the level of the bit line input to the negative input terminal of the comparator with the reference level input to the positive input terminal of the comparator, and output the comparison result from the output terminal of the comparator; using a latch to receive the comparison result output from the output terminal of the comparator, latch the comparison result and output it.

[0083] In addition, the present invention proposes an anti-fuse memory, which includes: a plurality of anti-fuse sub-arrays, each of the plurality of anti-fuse sub-arrays is composed of a plurality of anti-fuse units; a sub-array selection unit, the sub-array selection unit being used to select the anti-fuse sub-array; a bit line selection unit, the bit line selection unit being used to select the bit line of a specific anti-fuse unit in the anti-fuse sub-array; and a read-out circuit of the anti-fuse memory described in embodiments 1 or 2 of the present invention, the read-out circuit being used to read the logic of a specific anti-fuse unit in the anti-fuse memory.

[0084] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or their various aspects) can be used in combination with each other. In addition, without departing from the scope of the present invention, many modifications can be made to adapt specific conditions or materials to the teachings of the various embodiments of the present invention. Although the size and type of the material described herein are used to define the parameters of the various embodiments of the present invention, the various embodiments are not meant to be restrictive, but exemplary embodiments. In the case of reading the above description, many other embodiments are obvious to those skilled in the art. Therefore, the scope of the various embodiments of the present invention should be determined with reference to the attached claims, and the full range of equivalent forms claimed by these claims.

Claims

1. A readout circuit of an anti-fuse memory, used for reading the logic of a specific anti-fuse unit in the anti-fuse memory, wherein the readout circuit is characterized in that it includes: A precharge PMOS, wherein the source of the precharge PMOS is connected to the internal power supply of the memory, the drain is connected to the bit line of the selected specific anti-fuse unit, and a read enable signal is input to the gate. The precharge PMOS precharges the bit line to a specified level of the internal power supply of the memory; a comparator, the level of the bit line is input to a negative input terminal of the comparator, a reference level is input to a positive input terminal of the comparator, the comparator compares the level of the bit line with the reference level, and outputs a comparison result from an output terminal; A feedback circuit, the feedback circuit is composed of a PMOS, the source of the PMOS is connected to the internal power supply of the memory, the drain is connected to the bit line of the selected specific anti-fuse unit, and the gate is connected to the output end of the comparator; as well as a latch receiving the comparison result outputted from the output terminal of the comparator, latching and outputting the comparison result, The feedback circuit is configured to slow down a voltage drop speed of the bit line when the bit line of the selected specific anti-fuse cell is discharged due to a decrease in a resistance value of the specific anti-fuse cell.

2. The readout circuit of the anti-fuse memory according to claim 1, wherein: The reference level is set to half of the specified level of the internal power supply of the memory. A particular anti-fuse cell is selected based on a sub-array of anti-fuse cells, a bit line, and a word line in the anti-fuse memory.

3. A readout circuit of an anti-fuse memory, used for reading the logic of a specific anti-fuse unit in the anti-fuse memory, wherein the readout circuit is characterized in that it includes: A precharge PMOS, wherein the source of the precharge PMOS is connected to the internal power supply of the memory, the drain is connected to the bit line of the selected specific anti-fuse unit, and a read enable signal is input to the gate. The precharge PMOS precharges the bit line to a specified level of the internal power supply of the memory; a comparator, the level of the bit line is input to a negative input terminal of the comparator, a reference level is input to a positive input terminal of the comparator, the comparator compares the level of the bit line with the reference level, and outputs a comparison result from an output terminal; A feedback circuit, the feedback circuit is composed of a circuit consisting of a main feedback PMOS, a first margin adjustment PMOS, a second margin adjustment PMOS and a third margin adjustment PMOS; as well as a latch receiving the comparison result outputted from the output terminal of the comparator, latching and outputting the comparison result, The feedback circuit is configured to slow down the voltage drop speed of the bit line when the bit line of the selected specific anti-fuse unit is discharged due to the reduction of the resistance value of the specific anti-fuse unit, and is configured to adjust the maximum resistance value of the programmed specific anti-fuse unit that can be read by adjusting the number of on and off of the first margin adjustment PMOS, the second margin adjustment PMOS and the third margin adjustment PMOS.

4. The readout circuit of the anti-fuse memory according to claim 3, characterized in that: The source of the main feedback PMOS is connected to the internal power supply of the memory, the drain is connected to the bit line of the selected specific anti-fuse unit, and the gate is connected to the output terminal of the comparator. The first margin adjustment PMOS, the second margin adjustment PMOS and the third margin adjustment PMOS have their sources connected to the memory internal power supply, their drains connected to the bit line of the selected specific anti-fuse unit, and their gates connected to the control circuit. The number of on / off states of the first margin adjustment PMOS, the second margin adjustment PMOS and the third margin adjustment PMOS is adjusted by the control circuit.

5. The readout circuit of the anti-fuse memory according to claim 4, characterized in that: The first margin adjustment PMOS, the second margin adjustment PMOS, and the third margin adjustment PMOS have different channel lengths.

6. The readout circuit of the anti-fuse memory according to claim 4, characterized in that: The control circuit automatically adjusts the first margin adjustment PMOS, the second margin adjustment PMOS, and the third margin adjustment PMOS through a program.

7. The readout circuit of the anti-fuse memory according to claim 3, characterized in that: The feedback circuit adjusts the maximum resistance value of the specific programmed anti-fuse unit that can be read to 250KΩ, 330KΩ, 450KΩ or 380KΩ.

8. The readout circuit of the anti-fuse memory according to claim 3, characterized in that: The reference level is set to half of the specified level of the internal power supply of the memory. A particular anti-fuse cell is selected based on a sub-array of anti-fuse cells, a bit line, and a word line in the anti-fuse memory.

9. A method for reading an anti-fuse memory, using the read circuit of the anti-fuse memory according to any one of claims 1 to 8 to read the logic of a specific anti-fuse unit in the anti-fuse memory, wherein the read method is characterized by comprising: Using a precharge PMOS having a source connected to a power supply inside the memory, a drain connected to a bit line of the selected specific anti-fuse unit, and a gate input with a read enable signal, the bit line is precharged to a specified level of the power supply inside the memory; Using a feedback circuit, when the bit line of the selected specific anti-fuse unit is discharged due to the decrease in the resistance value of the specific anti-fuse unit, the voltage drop speed of the bit line is slowed down; using a comparator to compare the level of the bit line input to the negative input terminal of the comparator with a reference level input to the positive input terminal of the comparator, and outputting the comparison result from the output terminal of the comparator; as well as The comparison result outputted from the output terminal of the comparator is received by a latch, and the comparison result is latched and outputted.

10. An anti-fuse memory, characterized in that: include: A plurality of antifuse sub-arrays, each of the plurality of antifuse sub-arrays being composed of a plurality of antifuse units; A subarray selection unit, the subarray selection unit is used to select the antifuse subarray; A bit line selection unit, the bit line selection unit is used to select a bit line of a specific anti-fuse unit in the anti-fuse sub-array; And the readout circuit according to any one of claims 1 to 8, which is used to read the logic of the specific anti-fuse unit in the anti-fuse memory.

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