System for improving phase noise of phase-locked loop based on external mixing mode
By adopting external mixing technology in the PLL phase-locked loop, combined with DDS, PLL, loop filter and VCO, the problem of insufficient phase noise performance in the prior art is solved, and the effect of improving phase noise performance under conditions of wide frequency range, low cost and high integration is achieved.
Patent Information
- Application Number
- CN202411451012.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-17
- Publication Date
- 2025-03-11
AI Technical Summary
The prior art has shortcomings in improving the phase noise performance of PLL phase locked loops, especially under the requirements of wide frequency range, low cost and high integration, it is difficult to effectively improve the phase noise of the phase locked loop.
Using an external mixing method, combined with the direct digital frequency synthesizer DDS, PLL phase-locked loop, loop filter and voltage-controlled oscillator VCO, the reference signal is provided through DDS, the PLL phase-locked loop controls the reference frequency, the VCO provides the RF frequency output, and phase noise is improved through external mixing and integer dividers.
It has achieved the improvement of PLL phase locked loop phase noise performance under the conditions of wide frequency range, low cost and high integration, so that the frequency synthesis technology will develop towards integration, program control, digitalization, miniaturization, broadband of the frequency range, microscopicity of frequency intervals, and rapid frequency conversion.
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Figure CN119602789A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of PLL loops, in particular to the field of radio frequency PLL phase-locked loop technology, and specifically refers to a system for improving phase noise of a phase-locked loop based on an external frequency mixing method. Background Art
[0002] With the rapid development of information technology, the demand for signal synthesis sources is increasing, especially the requirements for phase noise are constantly increasing. Signal sources with a wide frequency range and low phase noise have become the basic requirements of users. An important component of the signal synthesis source is the PLL loop. Frequency synthesizer is the main source of signal source and the key component that determines the entire system. With the vigorous development of communication, satellite, radar, aerospace and other technologies, higher and higher requirements are put forward for phase-locked loops. Good phase noise performance is more easily adopted and accepted. Early frequency synthesizers were mainly realized by discrete components. Since the 1980s, the rapid development of microelectronics and computer technology has made frequency synthesizers tend to be fully integrated, and all circuits are concentrated on a chip. The development trend of frequency synthesizers is higher frequency, stronger system functions, more advanced manufacturing processes, higher integration and lower cost. In actual use, PLL has been integrated with the radio frequency circuit of the communication system transceiver to form a SOC chip integrating receiver, transmitter and frequency synthesizer. The development of modern communication and electronic systems has put forward higher requirements for frequency synthesis technology in multiple performance aspects. Summary of the invention
[0003] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a system for improving the phase noise of a phase-locked loop based on an external mixing method, which has high integration, low cost and a wide range of applications.
[0004] In order to achieve the above object, the system of the present invention for improving the phase noise of a phase-locked loop based on an external mixing method is as follows:
[0005] The system for improving the phase noise of a phase-locked loop based on an external mixing method has the following main features: the system includes a direct digital frequency synthesizer DDS, a phase-locked loop PLL, a loop filter, and a voltage-controlled oscillator VCO; the direct digital frequency synthesizer DDS is connected to a system clock and outputs a variable reference signal to the input end of the phase-locked loop PLL; the output end of the phase-locked loop PLL is connected to the voltage-controlled oscillator VCO; the direct digital frequency synthesizer DDS is used to provide a reference signal for the entire loop and perform phase comparison; the phase-locked loop PLL is used to lock the entire loop and control the reference frequency; the voltage-controlled oscillator VCO is used to provide a radio frequency output and provide a frequency output range with a large bandwidth; the output end of the voltage-controlled oscillator VCO is respectively connected to an output path and a feedback path.
[0006] Preferably, the direct digital frequency synthesizer DDS includes a phase accumulator, a DAC converter and a low-pass filter. The phase accumulator is formed by cascading an N-bit full adder and an N-bit accumulation register, and is used to perform accumulation operations on binary codes representing frequencies. The output end of the phase accumulator is connected to the DAC converter and the low-pass filter. At each clock pulse Fclk, the N-bit full adder adds the frequency control data and the accumulated phase data output by the accumulation register, and transmits the added result to the input end of the accumulation register. The waveform data is converted into a required analog waveform through the DAC converter and the low-pass filter. The phase accumulator performs linear phase accumulation under the action of the system clock, and an overflow occurs when the phase accumulator is full.
[0007] Preferably, the output path includes a doubler and a pre-divider, the doubler is connected to a voltage-controlled oscillator VCO, the pre-divider is connected to the doubler, the doubler is used to generate an output frequency twice the VCO frequency, and the pre-divider is used to output a frequency in a low frequency band.
[0008] Preferably, the feedback path includes a switch, a mixer and an integer divider N, the mixer is connected to the output end of the voltage-controlled oscillator VCO through the switch, the integer divider N is connected to the mixer, and the low-frequency signal output by the mixer enters the integer divider N.
[0009] Preferably, the integer frequency divider N divides the signal by N, where N is the frequency division ratio, and different frequencies are output by changing the frequency division ratio N.
[0010] The system for improving the phase noise of a phase-locked loop based on an external mixing method of the present invention is adopted. Through a direct digital frequency synthesizer DDS, a PLL phase-locked loop, a loop filter and a VCO, the frequency synthesis technology is developed in the direction of integration, program control, digitization, miniaturization, broadband frequency range, fine frequency interval, and high-speed frequency conversion, so that the frequency synthesis technology is more widely used in the fields of signal synthesis, instrumentation, modern communications, software radio, etc. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 The schematic diagram of the structure of the system for improving the phase noise of a phase-locked loop based on an external mixing method of the present invention is shown. DETAILED DESCRIPTION
[0012] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.
[0013] The system for improving the phase noise of a phase-locked loop based on an external mixing method of the present invention comprises a direct digital frequency synthesizer DDS, a phase-locked loop PLL, a loop filter, and a voltage-controlled oscillator VCO. The direct digital frequency synthesizer DDS is connected to a system clock and outputs a variable reference signal to the input end of the phase-locked loop PLL. The output end of the phase-locked loop PLL is connected to the voltage-controlled oscillator VCO. The direct digital frequency synthesizer DDS is used to provide a reference signal for the entire loop and perform phase comparison. The phase-locked loop PLL is used to lock the entire loop and control the reference frequency. The voltage-controlled oscillator VCO is used to provide an output of a radio frequency and provide a frequency output range with a large bandwidth. The output end of the voltage-controlled oscillator VCO is respectively connected to an output path and a feedback path.
[0014] As a preferred embodiment of the present invention, the direct digital frequency synthesizer DDS includes a phase accumulator, a DAC converter and a low-pass filter. The phase accumulator is formed by cascading an N-bit full adder and an N-bit accumulation register, and is used to perform accumulation operations on binary codes representing frequencies. The output end of the phase accumulator is connected to the DAC converter and the low-pass filter. At each clock pulse Fclk, the N-bit full adder adds the frequency control data and the accumulated phase data output by the accumulation register, and transmits the added result to the input end of the accumulation register. The waveform data is converted into the required analog waveform through the DAC converter and the low-pass filter. The phase accumulator performs linear phase accumulation under the action of the system clock, and an overflow occurs when the phase accumulator is full.
[0015] As a preferred embodiment of the present invention, the output path includes a doubler and a pre-divider, the doubler is connected to a voltage-controlled oscillator VCO, the pre-divider is connected to the doubler, the doubler is used to generate an output frequency that is twice the VCO frequency, and the pre-divider is used to output a frequency in a low frequency band.
[0016] As a preferred embodiment of the present invention, the feedback path includes a switch, a mixer and an integer divider N. The mixer is connected to the output end of the voltage-controlled oscillator VCO through the switch, the integer divider N is connected to the mixer, and the low-frequency signal output by the mixer enters the integer divider N.
[0017] As a preferred implementation of the present invention, the integer frequency divider N divides the signal by N, where N is the frequency division ratio, and different frequencies are output by changing the frequency division ratio N.
[0018] In a specific embodiment of the present invention, a method for improving the phase noise of a phase-locked loop based on an external mixing method is disclosed. The system mainly includes a direct digital frequency synthesis chip (DDS), a phase-locked loop chip (PLL), a voltage-controlled oscillator (VCO), an external loop filter (LPF), a mixer (MIX), and a local oscillator (LO). The function of the DDS is to provide a reference signal for the entire loop for phase comparison, and its frequency output accuracy can reach 0.001Hz. The phase-locked loop PLL is used to lock the entire loop, and the comparison of the reference signal and the feedback signal drives the charge pump to control the VCO. The VCO provides an output of a radio frequency frequency, which can provide a frequency output range with a large bandwidth, and is also used for a feedback path.
[0019] The technical solution adopted in this scheme includes direct digital frequency synthesizer DDS, PLL phase-locked loop, loop filter, VCO, mixer and local oscillator source.
[0020] In actual working engineering, DDS outputs a variable reference signal to the input of the phase-locked loop. There are also programmable input multipliers and pre-dividers in the input path of the phase-locked loop to further control the reference frequency. VCO is the output of the RF signal and also the signal fed back to the phase detector. The selection of this VCO also requires a wide bandwidth frequency range. Under normal circumstances, the VCO is directly fed back to the PD through the internal integer and fractional dividers.
[0021] This solution proposes to mix the frequency first and reduce the frequency first, so as to significantly reduce the integer N, thereby improving the phase noise of the output signal. At the same time, the selection of loop bandwidth is equally important. It should be measured according to the VCO index and the PLL noise index. A lower loop bandwidth will affect the locking state of the loop and the time required for locking, and a higher loop bandwidth will deteriorate the phase noise index. At the same time, the fractional frequency division inside the PLL will bring integer boundary spurs. Selecting DDS as the reference signal can avoid the use of fractional frequency dividers and only use integer frequency dividers.
[0022] Combination Figure 1 , the present invention includes the following structure:
[0023] 1. Input path: system clock, DDS.
[0024] The DDS circuit consists of a phase accumulator, a sine lookup table, a DAC, a low-pass filter, etc. The working principle of DDS is essentially to generate a sine wave with controllable frequency and phase in a digitally controlled manner. The phase accumulator is cascaded by an N-bit full adder and an N-bit accumulator register. The binary code representing the frequency is accumulated.
[0025] Specific working process: Every time a clock pulse Fclk comes, the N-bit adder adds the frequency control data and the accumulated phase data output by the accumulator register, and sends the result of the addition to the input end of the accumulator register, so that the adder continues to add the frequency control data under the action of the next clock, and finally converts the waveform data into the required analog waveform through the DAC converter and low-pass filter. The phase accumulator performs linear phase accumulation under the action of the system clock. When the phase accumulator is full, an overflow will occur, thus completing a cycle, which is the output signal frequency cycle of the DDS.
[0026] Output frequency: Fdds = k × Fclk / 2^n;
[0027] Output frequency resolution: △f = Fclk / 2^n;
[0028] Phase increment: △φ=k×2π / 2^n;
[0029] Among them, k is the frequency control word, n is the number of phase accumulator bits, and Fclk is the system clock.
[0030] 2. Output path: VCO, doubler, programmable divider.
[0031] The VCO is used to provide the RF output frequency of the entire system. The VCO takes the voltage from the loop filter and converts it to frequency. In order to reduce the VCO tuning gain and thus improve the VCO phase noise performance, the VCO frequency range can be divided into several different frequency bands. The gain index of the VCO can vary depending on the core, and it will also vary with temperature and process changes, so pay special attention to this when selecting a VCO. The doubler is used to generate an output frequency that is twice the VCO frequency. When the VCO frequency is doubled, the fundamental wave will leak into the RF output. This is the subharmonic, and the use of the doubler should be minimized as much as possible. The programmable divider is actually a divider with multiple segments and tap points, which can be used for frequency outputs in lower frequency bands.
[0032] 3. Feedback path: switch, mixer, integer divider N.
[0033] One path of the VCO is used for output, and the other is used for feedback. The feedback signal first passes through the mixer, and the low-frequency signal of the mixer output enters the integer divider N. At this time, N will not be very large, and the phase noise index of the system is related to N. The larger N is, the worse the phase noise is.
[0034] 4. How the whole system works
[0035] An integer divider is added to the feedback loop between the output of the VCO and the input of the phase detector. The reference signal and the signal obtained by mixing and dividing by integer N are compared in frequency and phase in the frequency detector. When the loop is in the locked state,
[0036] Feedback: fPD = (fLO-fVCO) / PLL_N;
[0037] Input: fPD = fOSC / PLL_R;
[0038] Among them, fPD is the phase detection frequency, fLO is the local oscillator frequency, fVCO is the VCO output frequency, PLL_N is the integer division number, fOSC is the reference signal frequency output by the DDS, and PLL_R is the pre-division number.
[0039] Obviously, different frequencies can be outputted by changing the frequency division ratio N. In practical applications, especially in ultra-high frequency working conditions, in order to obtain a larger frequency range output and a smaller frequency step, high-precision DDS and ultra-wideband VCO are used as much as possible.
[0040] Taking the LMX2820 phase-locked loop chip as an example, the LMX2820 is a high-performance broadband frequency synthesizer with an integrated VCO and an output divider. The VCO operates in the range of 5650MHz to 11300MHz.
[0041] Assuming the system clock is 800MHz and the reference signal output by DDS is 200MHz, the phase detection frequency Fpd = 200MHz. Assuming the system needs to output a 6GHz signal, the frequency of the VCO is 6GHz, and assuming the mixing local oscillator is 7.6GHz, the feedback signal is 1.6GHz, and the N division number is 8.
[0042] The phase noise of the test output signal is measured using a phase noise meter. The specific data is shown in the table below.
[0043]
[0044] It can be seen from the above table that the external mixing method reduces the frequency division number and improves the near-end phase noise, which shows that the experimental method is feasible and can improve the phase noise in principle.
[0045] The specific implementation scheme of this embodiment can refer to the relevant description in the above embodiment, which will not be repeated here.
[0046] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.
[0047] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.
[0048] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0049] The system for improving the phase noise of a phase-locked loop based on an external mixing method of the present invention is adopted. Through a direct digital frequency synthesizer DDS, a PLL phase-locked loop, a loop filter and a VCO, the frequency synthesis technology is developed in the direction of integration, program control, digitization, miniaturization, broadband frequency range, fine frequency interval, and high-speed frequency conversion, so that the frequency synthesis technology is more widely used in the fields of signal synthesis, instrumentation, modern communications, software radio, etc.
[0050] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it is apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.
Claims
1. A system for improving phase noise of a phase-locked loop based on an external mixing method, characterized in that: The system comprises a direct digital frequency synthesizer DDS, a phase-locked loop PLL, a loop filter, and a voltage-controlled oscillator VCO. The direct digital frequency synthesizer DDS is connected to a system clock and outputs a variable reference signal to the input end of the phase-locked loop PLL. The output end of the phase-locked loop PLL is connected to the voltage-controlled oscillator VCO. The direct digital frequency synthesizer DDS is used to provide a reference signal for the entire loop and perform phase comparison. The phase-locked loop PLL is used to lock the entire loop and control the reference frequency. The voltage-controlled oscillator VCO is used to provide a radio frequency output and provide a frequency output range with a large bandwidth. The output end of the voltage-controlled oscillator VCO is respectively connected to an output path and a feedback path.
2. The system for improving phase noise of a phase-locked loop based on an external mixing method according to claim 1, characterized in that: The direct digital frequency synthesizer DDS includes a phase accumulator, a DAC converter and a low-pass filter. The phase accumulator is formed by cascading an N-bit full adder and an N-bit accumulation register, and is used to perform accumulation operations on binary codes representing frequencies. The output end of the phase accumulator is connected to the DAC converter and the low-pass filter. At each clock pulse Fclk, the N-bit full adder adds the frequency control data and the accumulated phase data output by the accumulation register, and transmits the added result to the input end of the accumulation register. The waveform data is converted into a required analog waveform through the DAC converter and the low-pass filter. The phase accumulator performs linear phase accumulation under the action of the system clock, and an overflow occurs when the phase accumulator is full.
3. The system for improving phase noise of a phase-locked loop based on an external mixing method according to claim 1, characterized in that: The output path includes a frequency doubler and a pre-divider, the frequency doubler is connected to a voltage-controlled oscillator VCO, the pre-divider is connected to the frequency doubler, the frequency doubler is used to generate an output frequency twice the VCO frequency, and the pre-divider is used to output a frequency in a low frequency band.
4. The system for improving phase noise of a phase-locked loop based on an external mixing method according to claim 1, characterized in that: The feedback path includes a switch, a mixer and an integer divider N. The mixer is connected to the output end of the voltage-controlled oscillator VCO through the switch, the integer divider N is connected to the mixer, and the low-frequency signal output by the mixer enters the integer divider N.
5. The system for improving phase noise of a phase-locked loop based on an external mixing method according to claim 4, characterized in that: The integer frequency divider N divides the signal by N, where N is the frequency division ratio, and different frequencies are output by changing the frequency division ratio N.