Signal receiving method and device

Abstract

The invention discloses a signal receiving method and device, which can reduce the peak power of a signal input to an analog-to-digital converter (ADC), thereby reducing quantization noise and improving signal receiving performance. The method comprises the following steps: receiving a first signal by a receiving device, performing down-conversion on the first signal to obtain a second signal, determining a third signal according to the second signal, sampling the third signal, and determining a target signal. Wherein the first signal comprises a target signal, and the target signal adopts comb mapping, that is, the target signal occupies one subcarrier in every M continuous subcarriers. The third signal comprises superposition of K delay signals of the second signal, the delay time associated with the kth delay signal in the K delay signals is # imgabs0 #, T is the time length of the first signal, k = 1, 2,..., K, delta is greater than or equal to 0, M is a positive integer greater than 1, and K is a positive integer greater than or equal to M.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communications, and in particular, to a signal receiving method and device. Background Art

[0002] In the future, wireless sensing may be an important part of mobile communication systems. In order to achieve friendly coexistence of communication and sensing, so that communication and sensing can share radio frequency and baseband devices, orthogonal frequency domain multiplexing (OFDM) waveforms can be used in mobile communication systems to achieve communication and sensing.

[0003] In a wireless sensing scenario based on OFDM waveform, a sensing device may send signals in the form of comb or interlace. For example, Figure 1 As shown, one subcarrier in every M (such as M=2) consecutive subcarriers can be used for the sensing device to send a sensing signal, and the remaining subcarriers in the M consecutive subcarriers can be used for other sensing devices or communication devices to send signals.

[0004] In the signal reception process based on OFDM waveform, the receiver inputs the time domain signal over the entire bandwidth into the analog to digital converter (ADC) to convert the time domain analog signal into a time domain digital signal. Then, the frequency domain digital signal is obtained through sequence to parallel conversion (S->P) and fast Fourier transform (FFT). Finally, the signal on the subcarrier where the perception signal is located is extracted from the frequency domain digital signal for subsequent processing.

[0005] Due to the limited quantization accuracy of the ADC, additional quantization noise is usually generated after the signal passes through the ADC. In the above signal reception process, the quantization noise of the ADC depends on the sum of the power of the perceived signal and other user signals. If the power of other user signals received by the receiver is too large, it will cause large quantization noise, thus affecting the reception performance. Summary of the invention

[0006] The embodiments of the present application provide a signal receiving method and device, which can reduce the peak power of a signal input to an ADC, thereby reducing quantization noise and improving signal receiving performance.

[0007] In a first aspect, a signal receiving method is provided, which can be executed by a receiving device, or by a component of the receiving device, such as a processor, chip, or chip system of the receiving device, or by a logic module or software that can implement all or part of the functions of the receiving device. The method includes: receiving a first signal, the first signal includes a target signal, the target signal occupies one subcarrier in every M consecutive subcarriers, M is a positive integer greater than 1; down-converting the first signal to obtain a second signal; determining a third signal based on the second signal, the third signal including the superposition of K delayed signals of the second signal, the delay time associated with the kth delayed signal among the K delayed signals is Wherein, T is the time length of the first signal, k=1, 2, ..., K, δ is greater than or equal to 0, and K is a positive integer greater than or equal to M; the third signal is sampled to determine the target signal.

[0008] Based on this scheme, since the delay time associated with the kth delayed signal is Therefore, the K delayed signals of the second signal can be equivalent to the periodic extension of the second signal. Since sampling in the frequency domain is equivalent to periodically extending the signal in the time domain, and extracting the target signal from the entire bandwidth can be understood as a sampling in the frequency domain, after periodically extending and superimposing in the time domain, it can be considered that the target signal has been extracted, so that the signal input to the ADC does not include the signals of other users during sampling, that is, the peak power of the signal input to the ADC is the power of the target signal, and does not include the power of other user signals. In other words, the peak power of the signal input to the ADC can be reduced, thereby reducing the quantization noise and improving the signal reception performance.

[0009] In a possible design, the time length of the first signal is the length of one OFDM symbol. That is, the first signal can be understood as a signal on one OFDM symbol. The length of one OFDM symbol can refer to the length excluding the CP part.

[0010] In one possible design, the frequency of the down-conversion is related to the carrier frequency of the first signal and / or the position of the target signal. Exemplarily, the frequency of the down-conversion may be the same as the frequency of a subcarrier included in (or occupied by) the target signal.

[0011] Based on this possible design, after down-conversion, the high-frequency RF signal (i.e., the first signal) can be moved to the baseband for processing. In addition, the down-conversion frequency is determined according to the carrier frequency of the first signal and / or the position of the target signal, and the target signal can be aligned with the baseband zero frequency after down-conversion, thereby facilitating subsequent processing.

[0012] In one possible design, determining the third signal according to the second signal includes: delaying the second signal K times to obtain K delayed signals of the second signal, wherein the delay time associated with the kth delayed signal is The third signal is obtained by superimposing K delayed signals. Based on this possible design, the third signal can be obtained by directly delaying the second signal K times and superimposing them.

[0013] In a possible design, determining the third signal according to the second signal includes: determining the third signal through X-level circuits, in which: the output signal of the i-th level circuit is: a signal obtained by superimposing the input signal of the i-th level circuit and the delayed signal of the input signal of the i-th level circuit, i=1,2,…,X, and X is a positive integer greater than 1. When i=1, the input signal of the i-th level circuit is a signal obtained by delaying the second signal by δ, and when i>1, the input signal of the i-th level circuit is the output signal of the i-1-th level circuit, and the third signal is the output signal of the X-th level circuit, and the output signal of the X-th level circuit includes the superposition of K delayed signals of the second signal.

[0014] In one possible design, K = 2 X The output signal of the i-th stage circuit is: the input signal of the i-th stage circuit and the input signal of the i-th stage circuit are delayed The signal after superposition of the signals.

[0015] Based on this possible design, since the input signal of the i-th stage circuit only needs to be delayed once, only one delay device is required in each stage circuit, that is, only X delay devices are needed in total to determine the third signal, which can reduce the number of delay devices and thus save the cost of the receiving device.

[0016] In one possible design, The output signal of the i-th stage circuit is: the input signal of the i-th stage circuit and the input signal of the i-th stage circuit are delayed respectively. The signal after the superposition of the signals, Π represents the cumulative multiplication, K i Is a positive integer.

[0017] In a possible design, K=M, sampling the third signal includes: in the time range The third signal is sampled within a time range, and the reference point of the time range is the start time of the first signal.

[0018] Based on this possible design, the length of the time domain range can be That is to say, within the time length T of an OFDM symbol, the ADC used for sampling is turned on or works for only Compared with turning on the ADC for the time length T, the sampling power consumption of the ADC can be reduced, thereby reducing the power consumption of the receiving device. In addition, based on this possible design, if the sampling rate of sampling the third signal within the time range is NΔf C , then the length of the time domain range is In this case, the target signal includes sampling points. The frequency domain signal corresponding to the target signal can be obtained by performing a discrete Fourier transform (DFT) of N points. Compared with the solution of performing at least N-point DFT on the signal on the entire OFDM symbol, the number of DFT points can be reduced, and the capability requirements and cost of the DFT module can be reduced.

[0019] In a possible design, K=M, sampling the third signal includes: delaying the third signal A times to obtain A delayed signals of the third signal, where A is a positive integer, and the delay time associated with the a-th delayed signal is δ a Greater than or equal to 0, a=1,2,…,A; in the time range The ath delayed signal of the third signal is sampled within the time range, and the reference point of the time range is the start time of the first signal. Exemplarily, A is a positive integer less than or equal to M. Specifically, A=M.

[0020] In a possible design, the sampling frequency used when sampling the ath delayed signal of the third signal is greater than or equal to NΔf C / A, where N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, N is a positive integer, Δf C Alternatively, the sampling frequency of the ath delayed signal of the third signal is B / A, where B is the bandwidth of the first signal.

[0021] Based on this possible design, the receiving device delays the third signal A times and samples the delayed signal of the third signal within the above time domain range, which is equivalent to making an additional copy of the target signal in the time domain and sampling multiple copied time domain signals. It can be considered that the time length of the total sampled samples is increased. When the total number of sampling points remains unchanged, each sampled sample can be sampled separately at a lower sampling frequency, thereby reducing the sampling frequency and also reducing the performance requirements and cost of the ADC.

[0022] In a possible design, among the A delayed signals of the third signal, sampling positions of any two delayed signals are different.

[0023] Based on this possible design, different sampling positions of any two delayed signals can ensure that the sampling points of any two delayed signals are different, and the corresponding sampling results are not repeated, thereby ensuring sufficient sampling and improving sampling performance.

[0024] In a possible design, K=M-1+C, where C is a positive integer. For example, C is a positive integer less than or equal to M. Specifically, C=M.

[0025] In a possible design, sampling the third signal includes: sampling the third signal in segments C. The c-th segment sampling corresponds to the third signal being within a time range c, where c=1, 2, ..., C, and the time range c is:

[0026]

[0027] The reference point of the time range c is the start time of the first signal.

[0028] In a possible design, the sampling frequency used when performing C-segment sampling on the third signal is greater than or equal to NΔf C / C, N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, N is a positive integer, Δf C is the bandwidth of the subcarrier.

[0029] Based on the above two possible designs, the sampling frequency and the number of DFT points can also be reduced, thereby reducing the capability requirements and costs of the ADC and DFT modules.

[0030] In a possible design, in the C-segment sampling of the third signal, the sampling positions of any two segments are different.

[0031] In one possible design, the third signal is sampled to determine the target signal, including: sampling the third signal to obtain a first time domain sequence, performing an N / M-point discrete Fourier transform DFT on the first time domain sequence to obtain a frequency domain signal corresponding to the target signal; wherein N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer.

[0032] Based on this possible design, only The frequency domain signal corresponding to the target signal can be obtained by performing a single-point DFT. Compared with the solution of performing at least N-point DFT on the signal on the entire OFDM symbol, the number of DFT points can be reduced, and the capacity requirements and costs of the DFT module can be reduced.

[0033] In a second aspect, a device is provided, which may be a communication device or a sensing device. The device includes a first circuit. The first circuit is used to determine a third signal according to a second signal, wherein the third signal includes a superposition of K delayed signals of the second signal, and the delay time associated with the kth delayed signal among the K delayed signals is The second signal is a signal after down-converting the first signal, the first signal includes a target signal, the target signal occupies one subcarrier in every M consecutive subcarriers, M is a positive integer greater than 1, T is the time length of the first signal, k = 1, 2, ..., K, δ is greater than or equal to 0, K is a positive integer greater than or equal to M; the third signal is an input signal of the analog-to-digital converter. The technical effects brought about by the second aspect can refer to the technical effects brought about by the first aspect above, and will not be repeated here.

[0034] In one possible design, the apparatus further includes at least one of the following: an antenna, a mixer, an analog-to-digital converter, a DFT module, and a second circuit.

[0035] In one possible design, the first circuit includes K delays and an adder. The kth delay of the K delays is used to delay the second signal The kth delayed signal of the second signal is obtained. The adder is used to superimpose the K delayed signals of the second signal to obtain a third signal. The adder is a K-input adder.

[0036] In a possible design, the special δ=0, then the delay associated with the first delayed signal in the above design is 0, which is equivalent to the second signal itself, so the first delayed signal can be obtained without passing through the delayer. Therefore, the first circuit can include K-1 delayers and an adder. The kth delayer among the K-1 delayers is used to delay the second signal The kth delayed signal of the second signal is obtained. The adder is used to superimpose the second signal and K-1 delayed signals of the second signal to obtain a third signal. The adder is a K-input adder. Based on this possible design, one delayer can be reduced.

[0037] In a possible design, the first circuit includes X-level circuits, in which: the output signal of the i-th level circuit is: a signal obtained by superimposing the input signal of the i-th level circuit and the delayed signal of the input signal of the i-th level circuit, i=1, 2, ..., X, and X is a positive integer greater than 1. When i=1, the input signal of the i-th level circuit is a signal obtained by delaying the second signal by δ, when i>1, the input signal of the i-th level circuit is the output signal of the i-1-th level circuit, the third signal is the output signal of the X-th level circuit, and the output signal of the X-th level circuit includes the superposition of K delayed signals of the second signal.

[0038] In one possible design, K = 2 X In the case of , the i-th stage circuit includes a delay device and an adder. The delay device is used to delay the input signal of the i-th stage circuit. The adder is used for superimposing the input signal of the i-th stage circuit and the output signal of the delay device in the i-th stage circuit.

[0039] In one possible design, In the case of i -1 delay and one adder. The K i -1 delayer, used to delay the input signal of the i-th circuit The adder is used to superimpose the input signal of the i-th circuit and the K in the i-th circuit. i -1 delay output signal.

[0040] In one possible design, where K = M, the analog-to-digital converter is used in the time range The third signal is sampled within a time range, and the reference point of the time range is the start time of the first signal.

[0041] In a possible design, when K=M, the second circuit is used to delay the third signal A times to obtain A delayed signals of the third signal, where A is a positive integer, and the delay time associated with the a-th delayed signal is Greater than or equal to 0, a=1,2,…,A. Analog-to-digital converter, used in the time range The ath delayed signal of the third signal is sampled within the time range, and the reference point of the time range is the start time of the first signal.

[0042] In a possible design, K=M-1+B, when B is a positive integer, the analog-to-digital converter is used to perform C-segment sampling on the third signal. The c-segment sampling corresponds to the signal of the third signal in the time range c, c=1,2,…,C, and the time range c is:

[0043]

[0044] The reference point of the time range c is the start time of the first signal.

[0045] In one possible design, the DFT module is used to perform an N / M-point discrete Fourier transform DFT on the first time domain sequence to obtain a frequency domain signal corresponding to the target signal; wherein the first time domain sequence is a sampling result corresponding to the third signal, N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer.

[0046] In one possible design, the antenna is used to receive a first signal. The first signal includes a target signal, and the target signal occupies one subcarrier in every M consecutive subcarriers.

[0047] In one possible design, a mixer is used to down-convert a first signal to obtain a second signal.

[0048] In one possible design, the device described in the second aspect is a chip or a chip system.

[0049] Among them, the technical effects brought about by any possible design of the second aspect can refer to the technical effects brought about by the corresponding design in the above-mentioned first aspect, and will not be repeated here.

[0050] In a third aspect, a device is provided, which may be a communication device or a perception device. The device includes a unit or module, which is used to perform any of the methods described in the first aspect. The module or unit may be implemented by hardware, software, or by hardware executing corresponding software implementations. The hardware or software includes one or more modules or units corresponding to the functions.

[0051] In some possible designs, the device may include a processing module and a transceiver module. The processing module may be used to implement the processing function in any of the above aspects and any possible implementations thereof. The transceiver module may include a receiving module and a sending module, respectively used to implement the receiving function and the sending function in any of the above aspects and any possible implementations thereof.

[0052] In some possible designs, the transceiver module may be composed of a transceiver circuit, a transceiver, a transceiver or a communication interface.

[0053] In a fourth aspect, a device is provided, which may be a communication device or a perception device. The device includes a processor, which is configured to execute any of the methods described in the first aspect. The processor may be one or more. The device may also include a memory, which is used to store computer instructions, and when the processor executes the instructions, the device executes any of the methods described in the first aspect. The memory may be coupled to the processor, or may be independent of the processor. The device may also include a communication interface, which is used to communicate with a module outside the device.

[0054] The apparatus in the second aspect, the third aspect and the fourth aspect may be the receiving device in the first aspect, or an apparatus contained in the receiving device, such as a chip or a chip system. When the apparatus is a chip, the sending action / function of the apparatus may be understood as output information, and the receiving action / function of the apparatus may be understood as input information.

[0055] In a fifth aspect, a computer-readable storage medium is provided, wherein a computer program or instruction is stored in the computer-readable storage medium, and when the computer program or instruction is executed on a device, the device can execute any of the methods described in the first aspect. The device can be a communication device or a perception device.

[0056] In a sixth aspect, a computer program product comprising instructions is provided, which, when executed on a device, enables the device to execute any of the methods described in the first aspect. The device may be a communication device or a perception device.

[0057] Among them, the technical effects brought about by any design method in the second to sixth aspects can refer to the technical effects brought about by different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 A schematic diagram of the structure of a comb tooth provided in this application;

[0059] Figure 2 A schematic diagram of a signal receiving process provided by the present application;

[0060] Figure 3 A schematic diagram of the structure of a communication system provided for this application;

[0061] Figure 4 A flowchart of a signal receiving method provided by the present application;

[0062] Figure 5 A schematic diagram of a comb or staggered structure provided by the present application;

[0063] Figure 6 A schematic diagram of a signal receiving process provided by the present application;

[0064] Figure 7 A schematic diagram of another signal receiving process provided by the present application;

[0065] Figure 8 A schematic diagram of another signal receiving process provided by the present application;

[0066] Fig. 9 A schematic diagram of another signal receiving process provided by the present application;

[0067] Fig.10 A schematic diagram of the location of a sampling point provided for this application;

[0068] Fig.11 A schematic diagram of the structure of a communication device provided by the present application;

[0069] Fig.12A schematic diagram of the structure of another communication device provided by the present application;

[0070] Fig.13 A schematic diagram of the structure of another communication device provided by the present application;

[0071] Fig.14 A schematic diagram of the structure of another communication device provided in the present application. DETAILED DESCRIPTION

[0072] In the description of this application, unless otherwise specified, " / " indicates that the objects associated with each other are in an "or" relationship, for example, A / B can represent A or B; "and / or" in this application is merely a description of the association relationship between associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.

[0073] In the description of this application, unless otherwise specified, "plurality" means two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b and / or c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0074] In addition, in order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit the difference.

[0075] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way for easy understanding.

[0076] It is understood that the "embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the various embodiments in the entire specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It is understood that in various embodiments of the present application, the size of the sequence number of each process does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0077] It can be understood that in the present application, "when...", "when...", "when..." and "if" all mean that corresponding processing will be carried out under certain objective circumstances, but do not limit the time, nor do they require any judgment action when implementing them, nor do they mean the existence of other limitations.

[0078] It can be understood that some optional features in the embodiments of the present application may be implemented independently in certain scenarios without relying on other features, such as the solution on which they are currently based, to solve corresponding technical problems and achieve corresponding effects, or may be combined with other features according to needs in certain scenarios. Accordingly, the devices provided in the embodiments of the present application may also realize these features or functions accordingly, which will not be elaborated here.

[0079] In this application, unless otherwise specified, the same or similar parts between the various embodiments can refer to each other. In this application, if there is no special description or logical conflict between the various embodiments, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other, and different embodiments can be combined to form new embodiments according to their inherent logical relationships. The following description of the implementation methods of this application does not constitute a limitation on the scope of protection of this application.

[0080] Wireless sensing is an important technology for the future. In wireless sensing, the transmitting device can send a specific signal (called a transmitted signal), and the receiving device can receive the signal reflected by the environment (called a received signal). Afterwards, the transceiver can compare the correlation between the received signal and the transmitted signal to analyze relevant information about the surrounding environment. For example, it can analyze whether there are objects to be detected or sensed in the surrounding environment, the distance between the scatterer and the transceiver, the orientation or angle of the scatterer relative to the transceiver, and the moving speed of the scatterer relative to the transceiver.

[0081] Wireless sensing can be widely used in various fields. For example, in the scenario of connected vehicles, vehicles can obtain surrounding environmental information through wireless sensing, such as the location information and speed information of moving objects such as other vehicles and pedestrians, and information about relatively stationary objects such as roads and fences. For another example, in environments such as airports, special equipment can be deployed to sense and monitor flying objects such as drones to prevent other flying objects from causing safety impacts on aircraft takeoff and landing. For another example, in a home environment, wireless sensing can be used to detect intruders to improve the security and privacy of the home environment.

[0082] Wireless sensing can be achieved through frequency modulation continuous wave (FMCW), pulse waveform, orthogonal frequency domain multiplexing (OFDM) waveform, etc. Wireless sensing may be an important part of future mobile communication systems. In order to achieve friendly coexistence of communication and sensing, as well as sharing of RF and baseband devices, in mobile communication systems, it is possible to consider using the same waveform as the communication waveform to achieve wireless sensing, that is, using the OFDM waveform to achieve wireless sensing.

[0083] In the OFDM waveform, the time-frequency resources can be divided into different subcarriers in the frequency domain and can be divided into different OFDM symbols in the time domain. Furthermore, in the cyclic prefix (CP)-OFDM waveform, the OFDM symbol in the time domain includes the CP to combat multipath delay spread.

[0084] In addition, the time-frequency resources can be divided into a time-frequency resource grid. In the OFDM waveform, the smallest time-frequency resource unit is a resource element (RE). An RE includes one subcarrier in the frequency domain and one OFDM symbol in the time domain. Generally, the length of an OFDM symbol (excluding the CP) is inversely proportional to the subcarrier spacing, that is, if the subcarrier spacing is Δf c , then the length of OFDM symbol T = 1 / Δf c .

[0085] In wireless sensing, it is usually necessary to use a signal with a larger bandwidth to sense the surrounding environment. In theory, the larger the bandwidth, the higher the delay resolution of the reflection path caused by the scatterer, and the better the sensing performance. In a wireless sensing scenario based on OFDM waveform, a sensing device can send signals in the form of comb or interlace. For example, taking the CP-OFDM waveform as an example, Figure 1As shown, one subcarrier in every M (such as M=2) consecutive subcarriers can be used for the sensing device to send a sensing signal, and the remaining subcarriers in the M consecutive subcarriers can be used for other sensing devices or communication devices to send signals.

[0086] When the perception signal is sent in a comb-tooth or staggered form, on the one hand, the perception signal can have a larger bandwidth, and on the other hand, the perception signal occupies fewer subcarriers in the bandwidth, so that the remaining subcarriers can be used by other perception devices or communication devices, thereby improving the user capacity in the perception system and the communication system.

[0087] At present, the signal reception process based on OFDM waveform is as follows Figure 2 As shown. Assume that the receiver works in a frequency band with bandwidth B = NΔfx, Δf c represents the subcarrier spacing, N represents the total number of subcarriers included in the bandwidth, for example, see Figure 2 , the receiver first receives the bandwidth B = NΔf c The time domain analog signal is then input into an analog to digital converter (ADC) to sample the analog signal to obtain a time domain digital signal.

[0088] The time domain digital signal obtained after sampling is usually a serial signal, so the receiver can perform serial-to-parallel conversion (sequence to parallel, S->P). After the converted signal is subjected to fast Fourier transform (FFT), the frequency domain digital signal (which can also be understood as the signal reception value on each subcarrier) can be obtained. The frequency domain digital signal includes the signals of all subcarriers in the bandwidth. When the perception signal is sent in the form of comb teeth or interleaving, the receiver needs to extract the signal on the subcarrier corresponding to the comb teeth or interleaving to obtain the perception signal, and then perform subsequent processing based on the perception signal.

[0089] In the above process, when sampling, according to the Nyquist sampling theorem, the sampling frequency needs to be greater than or equal to the signal bandwidth B, otherwise the sampled digital signal will be a signal after the original signal is aliased in the frequency domain, affecting the receiving performance. In addition, the number of FFT points needs to be greater than or equal to the total number of subcarriers N included in the signal bandwidth.

[0090] However, the higher the sampling frequency of the ADC, the higher the cost of the ADC will be, and the worse the sampling accuracy will be. And because the quantization accuracy of the ADC is limited, additional quantization noise will be generated after the signal passes through the ADC. The quantization noise generally depends on the number of quantization bits of the ADC and the peak power of the signal input to the ADC. In the above signal reception process, when the perception signal to be received by the receiver and the signals of other users are frequency-division multiplexed on the same OFDM symbol, the peak power of the signal input to the ADC is the sum of the power of the perception signal and the power of the other user signals. If the power of other user signals is too large, the quantization noise generated after the signal passes through the ADC will also be large, and may even cause the problem of ADC blocking, that is, the power of the quantization noise is much greater than the power of the target perception signal, thereby affecting the receiving performance.

[0091] Based on this, the present application provides a signal receiving method, when the target signal is sent in the form of comb teeth or interlaced, the received signal (including the target signal and the signal of other users) can be extended in the time domain and the extended time domain signal can be superimposed to obtain a time domain aliasing signal. The time domain aliasing signal is then sampled to obtain the target signal. Since sampling in the frequency domain is equivalent to periodically extending the signal in the time domain, and extracting the target signal from the entire bandwidth can be understood as a sampling in the frequency domain, after extension and aliasing in the time domain, it can be considered that the target signal has been extracted, so that the signal input to the ADC does not include the signals of other users, that is, the peak power of the signal input to the ADC is the power of the target signal, excluding the power of other user signals. In other words, the peak power of the signal input to the ADC can be reduced, thereby reducing the quantization noise and improving the signal reception performance.

[0092] The technical solution of the embodiment of the present application can be used for various systems, which can be a third generation partnership project (3GPP) system, for example, a fifth generation (5G) or sixth generation (6G) mobile communication system, a sidelink (SL) system, an ultra-wideband (UWB) system, a vehicle to everything (V2X) system, or a device-to-device (D2D) communication system, a machine to machine (M2M) communication system, an Internet of Things (IoT), and other next generation communication systems. The communication system can also be a non-3GPP communication system, such as a wireless local area network (WLAN) system such as Wi-Fi, without limitation.

[0093] The technical solutions of the embodiments of the present application can be applied to perception or communication in various scenarios, for example, can be applied to perception or communication in one or more scenarios such as smart home, D2D, V2X, and IoT.

[0094] Among them, the above-mentioned systems and scenarios applicable to the present application are only examples, and the systems and scenarios applicable to the present application are not limited to these. They are uniformly explained here and will not be repeated below.

[0095] See also Figure 3 , is a system provided in an embodiment of the present application. The system includes a sending device and a receiving device. The system can be a communication system, a perception system, or a communication perception integrated system.

[0096] In a possible implementation, in a perception system or a communication perception integrated system, the sending device and the receiving device may be the same device, i.e., a self-transmitting and self-receiving scenario; or, the sending device and the receiving device may be different devices, i.e., a self-transmitting and other-receiving scenario. In a communication system, the sending device and the receiving device may be different devices.

[0097] In a possible implementation, the sending device and the receiving device may both be terminal devices, or may both be network devices. Alternatively, one of the sending device and the receiving device may be a terminal device, and the other may be a network device, which is not specifically limited in this application. Alternatively, the sending device and / or the receiving device may be a sensing device, such as a radar, or a device with a radar function.

[0098] Optionally, the receiving device may be a communication device or a sensing device. The communication device may have channel coding and decoding and channel modulation and demodulation capabilities, and further, the communication device may also have a sensing capability. The sensing device may have a sensing capability. Further, the sensing device may not have channel coding and decoding and channel modulation and demodulation capabilities, or may have channel coding and decoding and channel modulation and demodulation capabilities, without limitation.

[0099] In the embodiment of the present application, the terminal device may be a user-side device with wireless transceiver functions, or may be a chip or chip system arranged in the device. The terminal device may also be referred to as user equipment (UE), terminal, access terminal, user unit, user station, mobile station (MS), remote station, remote terminal, mobile terminal (MT), user terminal, wireless communication device, user agent or user device, etc. The terminal device may be, for example, a terminal device in IoT, V2X, D2D, M2M, 5G network, or a future evolved public land mobile network (PLMN). The terminal device may be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; it may also be deployed on water (such as ships, etc.); it may also be deployed in the air (such as airplanes, balloons and satellites, etc.).

[0100] Exemplarily, the terminal device may be a drone, an IoT device (e.g., a sensor, an electric meter, a water meter, etc.), a V2X device, a station (ST) in a wireless local area network (WLAN), a cellular phone, a cordless phone, a session initiation protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA) device, a handheld device with a wireless communication function, a computing device or other processing device connected to a wireless modem, an in-vehicle device, a wearable device (also referred to as a wearable smart device), a tablet computer or a computer with a wireless transceiver function, a virtual reality (VR) terminal, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a smart home, or a wireless terminal in a smart city. The terminal device may be a wireless terminal in a home, a vehicle-mounted terminal, a vehicle with vehicle-to-vehicle (V2V) communication capability, an intelligent connected vehicle, a drone with unmanned aerial vehicle (UAV) to unmanned aerial vehicle (UAV to UAV, U2U) communication capability, etc. The terminal device may be mobile or fixed, and this application does not make specific restrictions on this.

[0101] In an embodiment of the present application, the network device may be a network-side device with wireless transceiver functions, or may be a chip or chip system arranged in the device, located in the radio access network (RAN) of the mobile communication system, and used to provide access services for terminal devices. The network device may be an evolutionary Node B (eNB or eNodeB) in an LTE or evolved LTE system (LTE-Advanced, LTE-A), such as a traditional macro base station eNB and a micro base station eNB in ​​a heterogeneous network scenario; or it may be a next generation node B (gNodeB or gNB) in a 5G system; or it may be a transmission reception point (TRP); or it may be a base station in a future evolved PLMN; or it may be a broadband network service gateway (BNG), an aggregation switch or a non-3GPP access device; or it may be a wireless controller in a cloud radio access network (CRAN); or it may be an access point (AP) in a WiFi system; or it may be a wireless relay node or a wireless backhaul node; or it may be a device that implements a base station function in IoT, V2X, D2D, or M2M, and the embodiments of the present application do not specifically limit this. Exemplarily, the base stations in the embodiments of the present application may include various forms of base stations, such as: macro base stations, micro base stations (also called small stations), relay stations, access points, etc., and the embodiments of the present application do not specifically limit this.

[0102] In some implementation scenarios, the network device may also be a module or unit capable of implementing some or all of the functions of a base station, for example, the network device may be a centralized unit (CU), a distributed unit (DU), a CU and a DU, a CU-control plane (CP), a CU-user plane (UP), or a radio unit (RU). The CU and the DU may be separately configured, or may be included in the same network element, such as a baseband unit (BBU). The RU may be included in a radio frequency device or a radio frequency unit, such as a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH).

[0103] In different systems, CU (or CU-CP and CU-UP), DU or RU may also have different names, but those skilled in the art can understand their meanings. For example, the network device may be a network device or a module of a network device in an open radio access network (open RAN, ORAN) system. In the ORAN system, CU may also be referred to as open (open, O)-CU, DU may also be referred to as O-DU, CU-CP may also be referred to as O-CU-CP, CU-UP may also be referred to as O-CU-UP, and RU may also be referred to as O-RU. Any of the CU (or CU-CP, CU-UP), DU and RU in this application may be implemented by a software module, a hardware module, or a combination of a software module and a hardware module.

[0104] In some implementation scenarios, the network device may also be referred to as a RAN node or a RAN device or an access network device, or the network device may also have other naming methods, which is not specifically limited in this application.

[0105] All or part of the functions of the terminal device or network device in this application can also be implemented by software functions running on hardware, or by virtualization functions instantiated on a platform (such as a cloud platform). The terminal device or network device in this application can also be a logical node, logical module or software that can implement all or part of the functions of the terminal device or network device.

[0106] The following will be combined with the accompanying drawings to Figure 3 Taking the interaction between the sending device and the receiving device shown as an example, the signal receiving method provided in the embodiment of the present application is described in detail.

[0107] like Figure 4 FIG. 1 is a flow chart of a signal receiving method provided in an embodiment of the present application, and the signal receiving method includes the following steps:

[0108] S401. A receiving device receives a first signal.

[0109] The bandwidth of the first signal is B. The first signal includes a target signal. The target signal occupies one subcarrier in every M consecutive subcarriers, where M is a positive integer greater than 1.

[0110] Exemplarily, the first signal may be sent by another sending device, in which case the sending device and the receiving device may be considered to be different devices. Alternatively, the first signal may be a signal sent by the receiving device after being reflected by the environment, in which case the sending device and the receiving device may be considered to be the same device. The embodiments of the present application are not limited to this.

[0111] In a possible implementation, the target signal occupies one subcarrier in every M consecutive subcarriers in bandwidth B. Specifically, the target signal may occupy one subcarrier every M-1 consecutive subcarriers in bandwidth B. That is, it can be considered that the target signal is comb-tooth distributed or staggered in bandwidth B, or in other words, the target signal is mapped in bandwidth B in a comb-tooth or staggered manner. The comb-tooth index associated with the target signal can be determined by the position of the subcarrier occupied by the target signal (which can also be understood as the staggered index), and the position of the subcarrier occupied by the target signal can also be determined by the comb-tooth index associated with the target signal. Exemplarily, assuming that the subcarriers in bandwidth B can be associated with indexes 0, 1, 2, ... respectively, when the target signal occupies subcarriers 0, M, 2M, ..., the comb-tooth index or staggered index associated with the target signal can be 0, or, when the comb-tooth index associated with the target signal is 0, the target signal occupies subcarriers 0, M, 2M, ...; when the target signal occupies subcarriers 1, M+1, 2M+1, ..., the comb-tooth index or staggered index associated with the target signal can be 1, and so on. like Figure 5 As shown, taking M=4 as an example, the target signal occupies one subcarrier in every 4 consecutive subcarriers, the target signal occupies subcarriers 2, 6, 10, ..., and the comb index or interleaving index associated with the target signal is 2.

[0112] In a possible implementation manner, M may also be understood as the number of comb teeth. The subcarriers occupied by the target signal may also be understood as the interlace where the target signal is located.

[0113] In a possible implementation, in addition to the subcarriers occupied by the target signal, other subcarriers in the bandwidth can carry signals of other users or devices. Figure 5 In the figure, comb tooth 0 (including subcarriers 0, 4, 8, etc.), comb tooth 1 (including subcarriers 1, 5, 9, etc.), and comb tooth 3 (including subcarriers 3, 7, 11, etc.) in bandwidth B can be used to carry signals of the other three users respectively.

[0114] S402: The receiving device down-converts the first signal to obtain a second signal.

[0115] In a possible implementation, the down-conversion frequency f c The carrier frequency f of the first signal 0 same.

[0116] In a possible implementation, the down-conversion frequency f c The carrier frequency f of the first signal 0 and / or the position of the target signal. Exemplarily, the frequency of the down-conversion may be the same as the frequency of a certain subcarrier included in (or occupied by) the target signal.

[0117] As an example, the frequency of the down-conversion may be the frequency of the central subcarrier of the target signal. Taking the case where the target signal occupies Y subcarriers, and Y is an odd number, the central subcarrier of the target signal is the subcarrier number of the Y subcarriers. subcarriers, Indicates rounding up; when Y is an even number, the center subcarrier of the target signal is the Y / 2th or Y / 2+1th subcarrier among the Y subcarriers. Figure 5 In the example shown, if the target signal occupies only subcarriers 2, 6, and 10, the center subcarrier is subcarrier 6; if the target signal occupies subcarriers 2, 6, 10, and 14, the center subcarrier is subcarrier 6 or 10.

[0118] As another example, the down-conversion frequency may be the frequency f of the subcarrier included in the target signal. 0 The frequency of the subcarrier closest to the subcarrier. In particular, if the target signal includes a subcarrier with a frequency that is the same as the carrier frequency f 0 Same as, or including the carrier frequency f 0 , then the down-conversion frequency can be the carrier frequency f 0 .based on Figure 5 In the example shown, if the carrier frequency f 0 is the frequency of subcarrier 5, then the subcarrier closest to the carrier frequency is subcarrier 6, and the down-converted frequency is the frequency of subcarrier 6.

[0119] As another example, the down-conversion frequency may be a frequency greater than (or greater than or equal to) the carrier frequency in the subcarrier included in the target signal, which is away from the carrier frequency f 0 The frequency of the subcarrier closest to the subcarrier. In particular, if the target signal includes a subcarrier with a frequency that is the same as the carrier frequency f 0 Same as, or including the carrier frequency f 0 , then the down-conversion frequency can be the carrier frequency f 0 .based on Figure 5 In the example shown, if the carrier frequency f 0 is the frequency of subcarrier 5, then among the subcarriers occupied by the target signal, the subcarriers whose frequencies are greater than the carrier frequency include subcarrier 6 and subcarrier 10, and the subcarrier closest to the carrier frequency is subcarrier 6, so the down-converted frequency is the frequency of subcarrier 6.

[0120] As another example, the down-conversion frequency may be the frequency of the subcarrier included in the target signal, which is less than (or less than or equal to) the carrier frequency and is away from the carrier frequency f 0 The frequency of the subcarrier closest to the subcarrier. In particular, if the target signal includes a subcarrier with a frequency that is the same as the carrier frequency f 0 Same as, or including the carrier frequency f0 , then the down-conversion frequency can be the carrier frequency f 0 .based on Figure 5 In the example shown, if the carrier frequency f 0 is the frequency of subcarrier 5, then among the subcarriers occupied by the target signal, the subcarriers whose frequencies are less than the carrier frequency include subcarrier 2, and the subcarrier closest to the carrier frequency is subcarrier 2, so the down-converted frequency is the frequency of subcarrier 2.

[0121] Optionally, the frequency of the subcarrier in the embodiment of the present application can be understood as the center frequency of the subcarrier, or the starting frequency of the subcarrier, or the ending frequency of the subcarrier, or other frequencies included in the subcarrier.

[0122] In a possible implementation, down-converting the first signal may include: multiplying the first signal by a single-frequency signal, where the frequency of the single-frequency signal is the down-conversion frequency. c For example, the single frequency signal can be expressed as y(t)=exp(-2πjf c t), where t represents time.

[0123] The above single-frequency signal is represented in complex form. There is no complex domain signal in the physical world. Therefore, in actual implementation, the first signal can be multiplied by cos(2πf c t) and sin(2πf c t), and then pass through a low-pass filter to obtain an I-path signal and a Q-path signal. That is, the second signal may include an I-path signal and a Q-path signal.

[0124] Optional, down-converted frequency f c When the first signal is down-converted once, the second signal is obtained, and the frequency of this down-conversion is f c Alternatively, the first signal may be subjected to a frequency f 0 Down-convert the intermediate signal to obtain the intermediate signal, and then perform the frequency conversion of the intermediate signal to ff 0 The second signal is obtained by down-converting.

[0125] After down-conversion, the high-frequency RF signal (i.e., the first signal) can be moved to the baseband for processing. In addition, the down-conversion frequency is determined according to the carrier frequency of the first signal and the position of the target signal, and the target signal can be aligned with the baseband zero frequency after down-conversion, thereby facilitating subsequent processing.

[0126] S403: The receiving device determines a third signal according to the second signal.

[0127] The third signal includes a superposition of K delayed signals of the second signal. The delay time associated with the kth delayed signal among the K delayed signals is Wherein, T is the time length of the first signal, k=1, 2,…, K, δ is greater than or equal to 0, and K is a positive integer greater than or equal to M.

[0128] In a possible implementation, the delay time associated with the delayed signal of the second signal can be understood as: after the second signal is delayed by the delay time, the delayed signal can be obtained. Exemplarily, delaying the signal can also be understood as shifting the signal backward in the time domain.

[0129] In a possible implementation, the time length of the first signal is the length of an OFDM symbol. That is, the first signal can be understood as a signal on an OFDM symbol. The length of an OFDM symbol can refer to the length excluding the CP part, for example, T = 1 / Δf c When the receiving device receives signals on multiple OFDM symbols, the signal on each OFDM symbol can be understood as a first signal, that is, the received signal on each OFDM symbol can be applied to the signal receiving method provided in the embodiment of the present application.

[0130] In a possible implementation, k may also start from 0, that is, k = 0, 1, 2, ..., K-1. In this scenario, the delay time associated with the kth delayed signal is The parts involving k in the text or formulas in the subsequent embodiments can be adaptively adjusted accordingly. In the following embodiments of the present application, k=1, 2, ..., K is used as an example for explanation.

[0131] In a possible implementation, K=M; or, K=M-1+C, where C is a positive integer, and further, C is a positive integer less than or equal to M. Exemplarily, C=M, that is, K=2M-1.

[0132] It can be understood that the above-mentioned first signal, second signal, and third signal are described from the perspective of time domain analog signals.

[0133] In one possible implementation, sampling a signal in the frequency domain is equivalent to periodically extending the signal in the time domain, and extracting the target signal from the entire bandwidth can be understood as a sampling in the frequency domain. Therefore, corresponding to the time domain, it can be equivalent to periodically extending the signal in the time domain. The aliased signal can be obtained by superimposing the signal after periodic extension, and the sequence of time domain sampling points of the aliased signal in one cycle is the discrete frequency domain serial number or discrete frequency domain sequence corresponding to the target signal after discrete Fourier transformation (DFT). In other words, the signal of the above-mentioned aliased signal in one cycle can be determined by the third signal, and the discrete frequency domain serial number or discrete frequency domain sequence corresponding to the target signal can be further determined. That is, after the receiving device determines the third signal, it can perform the following steps S404 and S405.

[0134] S404: The receiving device samples the third signal.

[0135] As a possible implementation, sampling the third signal can be understood as: converting the third signal from a time-domain analog signal to a time-domain digital signal (or referred to as a discrete time-domain signal or a discrete time-domain sequence).

[0136] As a possible implementation, after sampling the third signal in step S404, an N / M point discrete time domain sequence can be obtained. Wherein, N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer. The N / M point discrete time domain sequence can be understood as the time domain sampling points of the above-mentioned aliased signal in one cycle. In particular, when N / M is not an integer, N / M can be rounded up or down, that is, after sampling the third signal, or The embodiment of the present application is mainly described with N / M as an integer.

[0137] S405: The receiving device determines a target signal, wherein the target signal may refer to a discrete time domain signal or a discrete time domain sequence corresponding to the target signal, or may refer to a discrete frequency domain signal or a discrete frequency domain sequence corresponding to the target signal.

[0138] Optionally, when the target signal refers to a discrete time domain signal or a discrete time domain sequence corresponding to the target signal, the target signal can be obtained by sampling the third signal in step S404. This step S405 may not be performed, or step S405 may be understood as: determining the discrete time domain signal or discrete time domain sequence obtained after sampling the third signal as the target signal.

[0139] Optionally, when the target signal refers to a discrete frequency domain signal or a discrete frequency domain sequence corresponding to the target signal, the discrete time domain signal or discrete time domain sequence obtained after sampling the third signal in step S404 is called a first time domain sequence, and the receiving device can determine the target signal based on the first time domain sequence, which can also be understood as determining the discrete frequency domain signal or discrete frequency domain sequence corresponding to the target signal.

[0140] In a possible implementation, the receiving device may perform N / M point DFT on the first time domain sequence to obtain the target signal. That is, a discrete frequency domain signal or discrete frequency domain sequence corresponding to the target signal is obtained. Wherein, N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer. In particular, when N / M is not an integer, N / M may be rounded up or down, that is, or The embodiments of the present application are mainly described with N / M as an integer.

[0141] As a possible implementation, performing N / M-point DFT on the first time domain sequence may include: performing N / M-point FFT on the first time domain sequence, that is, FFT may be understood as a specific implementation manner of DFT.

[0142] As a possible implementation, performing N / M-point DFT on the first time domain sequence can be understood as performing N / M-point DFT on a sequence consisting of time domain sampling points of the aliased signal in one period.

[0143] Based on the above scheme, when the target signal is sent in the form of comb teeth or interleaving, the received signal (i.e., the first signal) can be extended in the time domain and the extended time domain signal can be superimposed to obtain the aliased time domain signal. The aliased time domain signal is then sampled to obtain the target signal. Since sampling in the frequency domain is equivalent to periodically extending the signal in the time domain, and extracting the target signal from the entire bandwidth can be understood as a sampling in the frequency domain, after extension and aliasing in the time domain, it can be considered that the target signal has been extracted, so that the signal input to the ADC does not include the signals of other users, that is, the peak power of the signal input to the ADC is the power of the target signal, and does not include the power of other user signals. In other words, the peak power of the signal input to the ADC can be reduced, thereby reducing the quantization noise and improving the signal reception performance.

[0144] The overall process of the signal receiving method provided in the embodiment of the present application is described above. The determination and sampling of the third signal are described in detail below.

[0145] Method for determining the third signal:

[0146] In a first possible implementation, determining the third signal according to the second signal may include: delaying the second signal K times to obtain K delayed signals of the second signal, and superimposing the K delayed signals to obtain the third signal.

[0147] Among them, the delay time associated with the kth delayed signal is That is, the second signal can be delayed by δ, K delayed signals of the second signal are obtained.

[0148] As a possible implementation, when δ=0, the signal after the second signal is delayed by δ can be understood as the second signal itself, that is, it can be considered that the first delayed signal of the second signal does not actually delay the second signal, but for the sake of simplicity and consistency in expression, in this case, we still call it the delayed signal of the second signal.

[0149] For example, taking δ=0, K=M=4 as an example, Figure 6 As shown, after receiving the first signal, the receiving device inputs the first signal into the mixer to down-convert the first signal to obtain the second signal x(t). Then, the second signal is delayed by 0, Get x(t), Then the K signals are input into the adder for superposition to obtain a third signal. Exemplarily, the third signal can be expressed as:

[0150]

[0151] The reference point of t is the start time of the first signal, that is, the time 0 corresponding to t (or understood as the time t=0) is the start time of the first signal.

[0152] Optionally, the start time of the first signal may be the start time excluding the CP part. Exemplarily, assuming that the start time of the OFDM symbol (including the CP) where the first signal is located is t1, the start time of the CP is t1, and the end time of the CP is t2, then the start time of the first signal may be t2, that is, the reference point of the first time range may be t2.

[0153] In a second possible implementation manner, determining the third signal according to the second signal may include: determining the third signal by an X-level circuit. In the X-level circuit:

[0154] The output signal of the i-th level circuit is: a signal obtained by superimposing the input signal of the i-th level circuit and the delayed signal of the input signal of the i-th level circuit, i=1, 2, ..., X, and X is a positive integer greater than 1. That is, the input signal of the i-th level circuit can be delayed to obtain a delayed signal of the input signal, and then the input signal and the delayed signal of the input signal are superimposed to obtain the output signal.

[0155] Wherein, when i=1, the input signal of the i-th circuit is the signal after the second signal is delayed by δ. When i>1, the input signal of the i-th circuit is the output signal of the i-1-th circuit. The third signal is the output signal of the X-th circuit. The output signal of the X-th circuit includes the superposition of K delayed signals of the second signal.

[0156] As a first possible implementation, when K = 2 X In the case of , the output signal of the i-th stage circuit is: the input signal of the i-th stage circuit and the input signal of the i-th stage circuit are delayed The signal after the superposition of the signals. For example, taking δ=0, K=M=4 as an example, Figure 7 As shown:

[0157] When i=1, the input signal of the first stage circuit is the second signal x(t), and the second signal x(t) is delayed Then get the delayed signal Therefore, the output signal of the first stage circuit is

[0158] When i=2, the input signal of the second-stage circuit is the output signal of the first-stage circuit, that is, The input signal of the second stage circuit is delayed The delayed signal obtained is Therefore, the output signal of the second stage circuit is

[0159] By analogy, the output signal of the X-th stage circuit (i.e., the third signal) can be expressed as:

[0160] As a second possible implementation, K can be expressed as the product of X positive integers, that is, Where Π represents cumulative multiplication. K i is a positive integer. Furthermore, K i is a positive integer greater than 1. In this scenario, the output signal of the i-th circuit is: the input signal of the i-th circuit and the input signal of the i-th circuit are delayed respectively. That is to say, in the i-th circuit, the input signal of the i-th circuit may be delayed multiple times.

[0161] In the above description, i=1,2,…,X. In addition, i can also start from 0, that is, i=0,1,2,…,X-1. In this scenario, the output signal of the i-th circuit is: the input signal of the i-th circuit and the input signal of the i-th circuit are delayed The signal after the superposition of the signals of the i-th stage circuit and the input signal of the i-th stage circuit are respectively delayed The part involving i in the text or formula in the subsequent embodiments can also be adaptively adjusted accordingly. The following embodiments of the present application are described by taking i=1, 2, ..., X as an example.

[0162] For example, δ=0, K=6, X=2, K i =2,3, that is, K = 2×3, for example, Figure 8 As shown:

[0163] When i=1, K i =2, the input signal of the first-stage circuit needs to be delayed once, and the associated delay time is The input signal of the first stage circuit is the second signal x(t), which is delayed Then get the delayed signal Therefore, the output signal of the first stage circuit is

[0164] When i=2, K i =3, the input signal of the second stage circuit needs to be delayed twice, and the associated delay time is The input signal of the second stage circuit is the output signal of the first stage circuit, that is, The input signal of the second stage circuit is delayed The delayed signal obtained is The input signal of the second stage circuit is delayed The delayed signal obtained is Therefore, the output signal of the second stage circuit is Right now Right now

[0165] In a third possible implementation, the third signal may be determined by combining the first and second possible implementations. In this scenario, K may be expressed as K′+2 X At this time, the intermediate signal 1 can be obtained by the first possible implementation method. The intermediate signal 1 is the superposition of K′ delayed signals of the second signal, wherein the delay time associated with the kth (k=1, 2, …, K′) delayed signal is Then delay the second signal After that, the intermediate signal 2 is obtained, and then the intermediate signal 2 is input to the X-level circuit for further delay, where the output signal of the i-th level circuit is: the input signal of the i-th level circuit and the input signal of the i-th level circuit are delayed The output signal of the Xth stage circuit is recorded as intermediate signal 3; finally, the intermediate signal 1 and the intermediate signal 3 are superimposed to obtain the third signal.

[0166] Alternatively, the intermediate signal 3 can also be obtained in the following manner: the intermediate signal 4 is obtained by the second possible implementation method, that is, the second signal is first passed through the X-stage circuit, wherein the output signal of the i-th stage circuit is: the input signal of the i-th stage circuit and the input signal of the i-th stage circuit are delayed The output signal of the X-th stage circuit is the intermediate signal 4, and then the intermediate signal 4 is delayed The intermediate signal 3 can be obtained. The above method can also be extended to The situation will not be described here.

[0167] For example, δ=0, K=9, K′=1, X=3, that is, K=1+2 3 For example, the second signal x(t) can be delayed by 0 to obtain the intermediate signal 1, that is, the intermediate signal 1 is the second signal x(t) itself, and then the second signal is delayed by Get the intermediate signal 2, that is Then, the intermediate signal 2 is delayed by a three-level circuit to obtain an intermediate signal 3. The delay times corresponding to the three-level circuits are Right now:

[0168] When i=1, the input signal of the first stage circuit is The input signal is delayed Then get the delayed signal Therefore, the output signal of the first stage circuit is

[0169] When i=2, the input signal of the second-stage circuit is the output signal of the first-stage circuit, that is, The input signal of the second stage circuit is delayed Then get the delayed signal Therefore, the output signal of the second stage circuit is

[0170] When i=3, the input signal of the third-level circuit is the output signal of the second-level circuit, that is, The input signal of the third stage circuit is delayed Then get the delayed signal Therefore, the output signal of the third stage circuit (i.e., intermediate signal 3) is

[0171] The signal after the intermediate signal 1 and the intermediate signal 3 are superimposed is Right now

[0172] It is understandable that the “third signal includes the superposition of K delayed signals of the second signal, and the delay time associated with the kth delayed signal among the K delayed signals is ". In addition, it is not limited that each delayed signal of the second signal has a specific corresponding circuit (for example, in the above second implementation, each delayed signal component is not directly generated, but the final generated signal is consistent with the form we need), that is, the embodiment of the present application does not limit the specific method of determining or obtaining the third signal.

[0173] For sampling of the third signal:

[0174] In a first possible implementation manner, when K=M, sampling the third signal may include: sampling the third signal within a first time range.

[0175] Exemplarily, the first time range may be one of the following: or The third signal within the first time range can be understood as the signal of the above-mentioned aliased signal in one cycle. Exemplarily, the third signal is sampled within the first time range, and the first time domain range is In this case, the sampled signal can be expressed as:

[0176]

[0177] For example, Figures 6 to 8 As shown, among the signals output by the adder, the signal within the rectangular dotted frame is the sampled signal, or can be understood as the signal of the target signal in the time domain.

[0178] The reference point of the first time range (or the reference point of t) is the starting time of the first signal, that is, the time 0 corresponding to the first time range (or the time t=0) is the starting time of the first signal, or the time interval between the starting time of the first time range and the starting time of the first signal is

[0179] Optionally, for a portion of the first signal outside the first time range (for example, including a CP portion in the OFDM symbol in which it is located), whether the receiving device samples the portion may depend on the implementation of the receiving device, and this application does not specifically limit this. Take the discrete time domain signal or discrete time domain sequence obtained after sampling the third signal within the first time range as the first time domain sequence as an example:

[0180] As a possible implementation, when the target signal refers to a discrete time domain signal or a discrete time domain sequence corresponding to the target signal, the first time domain sequence is the discrete time domain signal or the discrete time domain sequence corresponding to the target signal.

[0181] As another possible implementation, when the target signal refers to a discrete frequency domain signal or a discrete frequency domain sequence corresponding to the target signal, the receiving device may perform N / M point DFT on the first time domain sequence to obtain a discrete frequency domain signal or a discrete frequency domain sequence corresponding to the target signal, wherein N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer.

[0182] Based on this possible implementation, since sampling in the frequency domain is equivalent to periodically extending the signal in the time domain, extracting the target signal from the entire bandwidth can be understood as a sampling in the frequency domain, corresponding to (or equivalent to) periodic extension in the time domain. The signal of the third signal within the first time domain just corresponds to the signal of the signal after the above periodic extension in one cycle, so when the third signal is sampled within the first time domain, it can be considered that the signal input to the ADC does not include the signals of other users, that is, the peak power of the signal input to the ADC is the peak power of the target signal, and does not include the power of other user signals. In other words, the peak power of the signal input to the ADC can be reduced, thereby reducing the quantization noise and improving the signal reception performance.

[0183] In addition, the length of the first time domain range can be That is to say, within the time length T of an OFDM symbol, the ADC used for sampling is turned on or works for only Compared with turning on the ADC all the time within the time length T, the sampling power consumption of the ADC can be reduced, thereby reducing the power consumption of the receiving device.

[0184] Furthermore, based on this possible implementation, if the sampling rate of sampling the third signal within the first time range is NΔf C , then the length of the first time domain range is In this case, the target signal includes sampling points. The frequency domain signal corresponding to the target signal can be obtained by performing a point DFT. Where N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer. Compared with the solution of performing at least N-point DFT on the signal on the entire OFDM symbol, the number of DFT points can be reduced, and the capacity requirements and costs of the DFT module (such as the FFT module) can be reduced.

[0185] In a second possible implementation, when K=M, the A delayed signals of the third signal may be sampled respectively, and then the target signal is determined according to the sampling results of the A delayed signals. Wherein A is a positive integer, and further, A is a positive integer less than or equal to M. In particular, A=M. For example, Fig. 9 As shown, the following steps may be included:

[0186] a) Delay the third signal A times to obtain A delayed signals of the third signal. The delay time associated with the a-th delayed signal is δ a is greater than or equal to 0, a=1,2,…,A. Similarly, the value of a can also be 0,1,…,A-1, then the delay time associated with the ath delayed signal is The parts involving a in the text or formulas in the subsequent embodiments can be adaptively adjusted accordingly. In the following embodiments of this application, a=1, 2,…, A is used as an example for explanation.

[0187] As a possible implementation, when a takes different values, δ a The values ​​of can be the same or different. For example, a=1, δ a can be equal to 0; when a≠1, δ a Can be greater than or equal to 0.

[0188] b) sampling the ath delayed signal of the third signal within the second time range, that is, sampling each delayed signal of the third signal respectively. Different delayed signals of the third signal, that is, when a takes different values, have different corresponding second time ranges.

[0189] As a possible implementation, the reference point of the second time range is the start time of the first signal. Please refer to the relevant description of the first time range, which will not be repeated here.

[0190] As a possible implementation, the second time range corresponding to the a-th delayed signal may be one of the following: or

[0191] As a possible implementation, Fig. 9As shown, the A delayed signals of the third signal can be respectively input into the ADC for sampling at different times (ie, different second time ranges) through a selector.

[0192] Optionally, the signal of each delayed signal of the third signal within the second time range can also be understood as: the signal of the aliased signal after the second signal is periodically extended and superimposed in one cycle (that is, the signal of the target signal in the time domain, for example Fig. 9 That is to say, the target signal is copied A times in the time domain.

[0193] As a possible implementation, the sampling frequency used when sampling the ath delayed signal of the third signal is greater than or equal to NΔf C / A, or, the sampling frequency of the ath delayed signal of the third signal may be greater than or equal to B / A. Wherein, N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer. Δf C is the bandwidth of the subcarrier, or the subcarrier spacing. B is the bandwidth of the first signal.

[0194] Optionally, the ath delayed signal of the third signal may be processed within the second time range. Point sampling, that is, sampling the ath delayed signal of the third signal within the second time range to obtain a sampling result including The signal at each sampling point.

[0195] As a possible implementation, among the A delayed signals of the third signal, the sampling positions of any two delayed signals are different. For example, Fig.10 As shown, Taking A=2 as an example, it is originally necessary to sample the third signal at 10 points within the first time range. The sampling position of the first delayed signal of the third signal within the second time range 1 can correspond to the 1st, 3rd, 5th, 7th, and 9th sampling points of the third signal within the first time range, and the sampling position of the second delayed signal of the third signal within the second time range 2 can correspond to the 2nd, 4th, 6th, 8th, and 10th sampling points of the third signal within the first time range.

[0196] Fig.10 In the 1 =0,δ 2 ≠0 is used as an example for explanation. Therefore, when the reference points of the first time range and the second time range are the same, both of which are the start time of the first signal, the start time of the second time range 1 is the same as that of the first time range, and the time interval between the end time of the second time range 2 and the start time of the second time range 1 is δ 2 .

[0197] c) determining a target signal according to sampling results of A delayed signals of the third signal.

[0198] Optionally, the sampling results of the A delayed signals of the third signal may be reordered to obtain a first time domain sequence. Exemplarily, the sampling results of the A delayed signals may be arranged in sequence from front to back according to the time domain sequence of the sampling points of the third signal within the first time range corresponding to the actual sampling points within the second time range to obtain the first time domain sequence.

[0199] For example, based on Fig.10 In the example shown, 5 sampling points can be obtained in the second time range 1, and 5 sampling points can be obtained in the second time range 2. Then, the 10 sampling points are reordered, for example, the two groups of 5 sampling points are interspersed with each other, and the first time domain sequence can be: the sampling result of the first sampling point in the second time range 1 (corresponding to the first sampling point in the first time range), the sampling result of the first sampling point in the second time range 2 (corresponding to the second sampling point in the first time range), the sampling result of the second sampling point in the second time range 1 (corresponding to the third sampling point in the first time range), the sampling result of the second sampling point in the second time range 2 (corresponding to the fourth sampling point in the first time range). the sampling result, the sampling result of the 3rd sampling point in the second time range 1 (corresponding to the 5th sampling point in the first time range), the sampling result of the 3rd sampling point in the second time range 2 (corresponding to the 6th sampling point in the first time range), the sampling result of the 4th sampling point in the second time range 1 (corresponding to the 7th sampling point in the first time range), the sampling result of the 4th sampling point in the second time range 2 (corresponding to the 8th sampling point in the first time range), the sampling result of the 5th sampling point in the second time range 1 (corresponding to the 9th sampling point in the first time range), and the sampling result of the 5th sampling point in the second time range 2 (corresponding to the 10th sampling point in the first time range).

[0200] As a possible implementation, when the target signal refers to a discrete time domain signal or a discrete time domain sequence corresponding to the target signal, the first time domain sequence is the discrete time domain signal or the discrete time domain sequence corresponding to the target signal.

[0201] As another possible implementation, when the target signal refers to a discrete frequency domain signal or a discrete frequency domain sequence corresponding to the target signal, the receiving device can perform N / M point DFT on the first time domain sequence to obtain a discrete frequency domain signal or a discrete frequency domain sequence corresponding to the target signal.

[0202] Based on this possible implementation, the receiving device makes an additional copy of the target signal in the time domain, and performs a frequency NΔf on each of the copied signals. C / A, compared to sampling at frequency NΔf C Sampling is performed, which reduces the sampling frequency, thereby reducing the performance requirements and cost of the ADC.

[0203] In addition, based on this possible implementation, the time domain also only includes sampling points. The frequency domain signal corresponding to the target signal can be obtained by performing a single-point DFT. Compared with the solution of performing at least N-point DFT on the signal on the entire OFDM symbol, the number of DFT points can be reduced, and the capacity requirements and costs of the DFT module can be reduced.

[0204] In a third possible implementation, when K=M-1+C, the third signal may be sampled in sections, and the target signal may be determined according to the results of the section sampling. Exemplarily, the following steps may be included:

[0205] a) Perform C-segment sampling on the third signal.

[0206] The c-th sampling corresponds to the signal of the third signal in the third time range c, c = 1, 2, ..., C. That is to say, the third signal can be divided into C-segment sub-signals in time, and then the C-segment sub-signals are sampled respectively. The c-th sub-signal is the signal of the third signal in the third time range c.

[0207] The third time range c may be one of the following: or The reference point of the third time range c is the starting time of the first signal. Please refer to the relevant description of the first time range, which will not be repeated here.

[0208] Optionally, the value of c can also be 0, 1, ..., C-1, and the cth sub-signal is the signal of the third signal in the third time range c. The third time range c can be one of the following: or The parts involving c in the text or formulas in the subsequent embodiments can be adaptively adjusted accordingly. In the following embodiments of this application, c=1, 2, ..., C is used as an example for explanation.

[0209] As a possible implementation, the sampling frequency of the cth segment of the third signal is greater than or equal to NΔf C / C, or, the sampling frequency of the cth segment of the third signal may be greater than or equal to B / C. Wherein, N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer. Δf Cis the bandwidth of the subcarrier, or the subcarrier spacing. B is the bandwidth of the first signal.

[0210] Optionally, the cth segment sub-signal of the third signal may be processed within the third time range c. Point sampling, that is, sampling the cth sub-signal of the third signal within the third time range c to obtain a sampling result including The signal at each sampling point.

[0211] As a possible implementation, in the C segment sub-signals of the third signal, the sampling positions of any two sub-signals are different. Taking C=2 as an example, it is originally necessary to sample 10 points of the third signal within the first time range, then the sampling position of the first sub-signal of the third signal within the third time range can correspond to the 1st, 2nd, 3rd, 4th, and 5th sampling points of the third signal within the first time range, and the sampling position of the second sub-signal of the third signal within the third time range can correspond to the 6th, 7th, 8th, 9th, and 10th sampling points of the third signal within the first time range. For specific details, please refer to the relevant description of "Among the A delayed signals of the third signal, the sampling positions of any two delayed signals are different" in the previous text.

[0212] b) Determine the target signal based on the sampling results of segment C.

[0213] Optionally, the sampling results of the C-segment sampling may be reordered to obtain a first time domain sequence. Exemplarily, the sampling results of the C-segment sampling may be arranged from front to back in the time domain sequence of the sampling points of the third signal within the first time range corresponding to the actual sampling points within each third time range to obtain the first time domain sequence. For details, please refer to the relevant description of "reordering the sampling results of the A delayed signals of the third signal to obtain the first time domain sequence" in the previous text.

[0214] As a possible implementation, when the target signal refers to a discrete time domain signal or a discrete time domain sequence corresponding to the target signal, the first time domain sequence is the discrete time domain signal or the discrete time domain sequence corresponding to the target signal.

[0215] As another possible implementation, when the target signal refers to a discrete frequency domain signal or a discrete frequency domain sequence corresponding to the target signal, the receiving device can perform N / M point DFT on the first time domain sequence to obtain a discrete frequency domain signal or a discrete frequency domain sequence corresponding to the target signal.

[0216] Based on this possible implementation, the sampling frequency and the number of DFT points can also be reduced, thereby reducing the capability requirements and costs of the ADC and DFT modules.

[0217] In a possible implementation, the functions related to the above steps S401-S402 may be implemented in radio frequency, and the functions related to the above steps S403-S405 may be implemented in baseband (eg, through a baseband chip).

[0218] In the embodiments of the present application, a method of dividing an input signal into multiple signals and then delaying the signals of some of the signals is repeatedly involved, for example, delaying the second signal K times (such as Figure 6 ), or delay the input signal of the i-th path in the X-level circuit (as shown in Figure 7 , Figure 8 As shown). In an actual system, the step of dividing into multiple signals will cause the amplitude or energy of the multiple signals to be reduced compared to the original signal, but since the amplitude or energy of each signal evenly shares the amplitude or energy of the source signal, it will not affect the receiving performance of the receiver. In addition, after being divided into multiple signals, the multiple signals can be amplified by some amplifiers so that the average energy or amplitude of the multiple signals is consistent with the original signal. Therefore, the relevant mathematical expressions involved in this application do not take into account the reduction of the above amplitude or energy, but it does not affect the inventive nature of the present invention.

[0219] It is understandable that in the embodiment of the present application, the receiving device may perform some or all of the steps or operations in the embodiment of the present application, and these steps or operations are only examples. The embodiment of the present application may also perform other steps or operations or variations of each step or operation. In addition, each step or operation may be performed in a different order presented in the embodiment of the present application, and it is possible that not all steps or operations in the embodiment of the present application need to be performed. For example, when the receiving device only has a radio frequency processing function or only has a baseband processing function, it may only perform some of the steps or operations performed by the receiving device described in the embodiment of the present application, such as only performing steps S401-S402 when only having a radio frequency processing function, and only performing steps S403-S405 when only having a baseband processing function, and other operations may be performed by at least one other device.

[0220] It is understandable that in the above embodiments, the methods and / or steps of the receiving device may also be implemented by components (such as a processor, a chip, a chip system, a circuit, a logic module, or software) that can be used in the receiving device. The chip system may be composed of a chip, or the chip system may include a chip and other discrete devices.

[0221] It is understandable that, in order to realize the above functions, the communication device or the perception device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0222] The embodiment of the present application can divide the functional modules of the communication device or the perception device according to the above method embodiment. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0223] Device Fig.11 A schematic diagram of the structure of a communication device or a sensing device 110 is shown. The device 110 includes a processing module 1101 and a transceiver module 1102. The device 110 can be used to implement the functions of the above-mentioned receiving device.

[0224] In some embodiments, the device 110 may further include a storage module ( Fig.11 ), for storing program instructions and data.

[0225] In some embodiments, the transceiver module 1102 may also be referred to as a transceiver unit for implementing a sending and / or receiving function. The transceiver module 1102 may be composed of a transceiver circuit, a transceiver, a transceiver or a communication interface.

[0226] In some embodiments, the transceiver module 1102 may include a receiving module and a sending module, which are respectively used to execute the receiving and sending steps performed by the receiving device in the above method embodiments, and / or used to support other processes of the technology described herein; the processing module 1101 may be used to execute the processing steps (such as determination, etc.) performed by the receiving device in the above method embodiments, and / or used to support other processes of the technology described herein.

[0227] Among them, the transceiver module 1102 is used to receive a first signal, the first signal includes a target signal, the target signal occupies one subcarrier in every M consecutive subcarriers, and M is a positive integer greater than 1; the processing module 1101 is used to down-convert the first signal to obtain a second signal; the processing module 1101 is also used to determine a third signal based on the second signal, the third signal includes the superposition of K delayed signals of the second signal, and the delay time associated with the kth delayed signal among the K delayed signals is Wherein, T is the time length of the first signal, k=1, 2, ..., K, δ is greater than or equal to 0, and K is a positive integer greater than or equal to M; the processing module 1101 is also used to sample the third signal to determine the target signal.

[0228] Optionally, the processing module 1101 is further used to determine the third signal according to the second signal, including: the processing module 1101 is further used to delay the second signal K times to obtain K delayed signals of the second signal, wherein the delay time associated with the kth delayed signal is The processing module 1101 is further configured to superimpose K delayed signals to obtain a third signal.

[0229] Optionally, the processing module 1101 is further used to determine the third signal according to the second signal, including: the processing module 1101 is further used to determine the third signal through X-level circuits, in which: the output signal of the i-th level circuit is: the signal obtained by superimposing the input signal of the i-th level circuit and the delayed signal of the input signal of the i-th level circuit, i=1,2,…,X, and X is a positive integer greater than 1. Wherein, when i=1, the input signal of the i-th level circuit is the signal after the second signal is delayed by δ, when i>1, the input signal of the i-th level circuit is the output signal of the i-1-th level circuit, the third signal is the output signal of the X-th level circuit, and the output signal of the X-th level circuit includes the superposition of K delayed signals of the second signal.

[0230] Optionally, when K=M, the processing module 1101 is further used to sample the third signal, including: the processing module 1101 is further used to sample the third signal within the time range The third signal is sampled within a time range, and the reference point of the time range is the start time of the first signal.

[0231] Optionally, when K=M, the processing module 1101 is further used to sample the third signal, including: the processing module 1101 is further used to delay the third signal A times to obtain A delayed signals of the third signal, where A is a positive integer, and the delay time associated with the a-th delayed signal is δ a greater than or equal to 0, a=1,2,…,A; processing module 1101 is also used to The ath delayed signal of the third signal is sampled within the time range, and the reference point of the time range is the start time of the first signal.

[0232] Optionally, when K=M-1+C, and C is a positive integer, the processing module 1101 is further used to sample the third signal, including: the processing module 1101 is further used to perform C-segment sampling on the third signal. The c-segment sampling corresponds to the signal of the third signal being within a time range c, c=1, 2, ..., C, and the time range c is: The reference point of the time range c is the start time of the first signal.

[0233] Optionally, the processing module 1101 is also used to sample the third signal to determine the target signal, including: the processing module 1101 is used to sample the third signal to obtain a first time domain sequence, and is also used to perform an N / M-point discrete Fourier transform DFT on the first time domain sequence to obtain a frequency domain signal corresponding to the target signal; wherein N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer.

[0234] In a possible implementation manner, the functions / actions implemented by the processing module 1101 may also be implemented by the transceiver module 1102 .

[0235] Among them, all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, and will not be repeated here.

[0236] In the present application, the communication device or the sensing device 110 may be presented in the form of dividing various functional modules in an integrated manner. The "module" here may refer to a specific application-specific integrated circuit (ASIC), a circuit, a processor and a memory that executes one or more software or firmware programs, an integrated logic circuit, and / or other devices that can provide the above functions.

[0237] In some embodiments, when Fig.11 When the communication device or perception device 110 is a chip or a chip system, the function / implementation process of the transceiver module 1102 can be implemented through the input and output interface (or communication interface) of the chip or the chip system, and the function / implementation process of the processing module 1101 can be implemented through the processor (or processing circuit) of the chip or the chip system.

[0238] Since the communication device or perception device 110 provided in this embodiment can execute the above method, the technical effects that can be obtained can refer to the above method embodiments and will not be repeated here.

[0239] Device Fig.12FIG. 1 is a schematic diagram showing the structure of another communication device or sensing device 120 . The device 120 can be used to implement the functions of the above-mentioned receiving device. The device 120 includes a first circuit 1201 .

[0240] Optionally, the device 120 may further include at least one of the following: an antenna 1202, a mixer 1203, an analog-to-digital converter 1204, a DFT module 1205, a second circuit ( Fig.12 not shown).

[0241] The first circuit is used to determine the third signal according to the second signal, and the second signal is a signal after down-converting the first signal. The first signal includes a target signal, and the target signal occupies one subcarrier in every M consecutive subcarriers, where M is a positive integer greater than 1. The third signal is an input signal of the analog-to-digital converter. The third signal includes the superposition of K delayed signals of the second signal, and the delay time associated with the kth delayed signal among the K delayed signals is Wherein, T is the time length of the first signal, k=1, 2,…, K, δ is greater than or equal to 0, and K is a positive integer greater than or equal to M.

[0242] Optionally, antenna 1202 is configured to receive a first signal. The first signal includes a target signal, and the target signal occupies one subcarrier in every M consecutive subcarriers.

[0243] Optionally, the mixer 1203 is used to down-convert the first signal to obtain a second signal.

[0244] Optionally, the analog-to-digital conversion module 1204 is used to sample the third signal to obtain a first time domain sequence. The DFT module 1205 is used to determine the target signal according to the first time domain sequence.

[0245] As a possible implementation, the first circuit includes K delays and an adder. The kth delay of the K delays is used to delay the second signal The kth delayed signal of the second signal is obtained. The adder is used to superimpose the K delayed signals of the second signal to obtain a third signal. Exemplarily, the adder is a K-input adder.

[0246] As a possible implementation, the first circuit includes K-1 delay devices and an adder. The kth (k=1, 2, ..., K-1) delay device among the K-1 delay devices is used to delay the second signal The kth delayed signal of the second signal is obtained. The adder is used to superimpose the second signal and K-1 delayed signals of the second signal to obtain a third signal. Exemplarily, the adder is a K-input adder.

[0247] As another possible implementation, the first circuit includes X-level circuits, in which: the output signal of the i-th level circuit is: a signal obtained by superimposing the input signal of the i-th level circuit and the delayed signal of the input signal of the i-th level circuit, i=1, 2, ..., X, and X is a positive integer greater than 1. When i=1, the input signal of the i-th level circuit is a signal obtained by delaying the second signal by δ, when i>1, the input signal of the i-th level circuit is the output signal of the i-1-th level circuit, the third signal is the output signal of the X-th level circuit, and the output signal of the X-th level circuit includes the superposition of K delayed signals of the second signal.

[0248] As a possible example, K = 2 X In the case of , the i-th stage circuit includes a delay device and an adder. The delay device is used to delay the input signal of the i-th stage circuit. The adder is used to superimpose the input signal of the i-th stage circuit and the output signal of the delay device in the i-th stage circuit. Exemplarily, the adder is a 2-input adder.

[0249] As another possible example, In the case of i -1 and a delay and an adder. The K i -1 delayer, used to delay the input signal of the i-th circuit The adder is used to superimpose the input signal of the i-th circuit and the K in the i-th circuit. i -1 delay output signal. Exemplarily, the adder is K i Enter the adder.

[0250] Optionally, when K=M, the analog-to-digital converter 1204 is used to The third signal is sampled within a time range, and the reference point of the time range is the start time of the first signal.

[0251] Optionally, when K=M, the second circuit is used to delay the third signal A times to obtain A delayed signals of the third signal, where A is a positive integer, and the delay time associated with the a-th delayed signal is δ a is greater than or equal to 0, a=1,2,…,A. The analog-to-digital converter 1204 is used to The ath delayed signal of the third signal is sampled within the time range, and the reference point of the time range is the start time of the first signal.

[0252] Exemplarily, the second circuit includes A delayers, the A delayers are respectively used to delay the third signal The communication device or the sensing device may also include a selector for selecting a time range. is connected to the ath delay so that the analog-to-digital converter 1204 is within the time range The ath delayed signal of the third signal is sampled.

[0253] Optionally, when K=M-1+B, and B is a positive integer, the analog-to-digital converter 1204 is used to perform C-segment sampling on the third signal. The c-segment sampling corresponds to the signal of the third signal being within a time range c, where c=1, 2, ..., C, and the time range c is:

[0254]

[0255] The reference point of the time range c is the start time of the first signal.

[0256] Optionally, the DFT module 1205 is specifically used to perform an N / M-point discrete Fourier transform DFT on the first time domain sequence to obtain a frequency domain signal corresponding to the target signal; wherein N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer.

[0257] Among them, all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding circuit, component or functional module, and will not be repeated here.

[0258] As a possible product form, the receiving device described in the embodiment of the present application can also be implemented using the following: one or more field programmable gate arrays (FPGA), programmable logic devices (PLD), controllers, state machines, gate logic, discrete hardware components, any other suitable circuits, or any combination of circuits that can perform the various functions described throughout the present application.

[0259] As another possible product form, the receiving device described in the embodiment of the present application can be implemented by a general bus architecture. Fig.13 , Fig.13 1 is a schematic diagram of the structure of a communication device or a sensing device 130 provided in an embodiment of the present application, wherein the device 130 includes a processor 1301 and a transceiver 1302. The device 130 may be a receiving device, or a chip or a chip system therein. Fig.13 Only the main components of the device 130 are shown. In addition to the processor 1301 and the transceiver 1302, the device may further include a memory 1303 and an input and output device (not shown in the figure).

[0260] Optionally, the processor 1301 is mainly used to process the communication protocol and communication data, and to control the entire communication device or sensing device, execute the software program, and process the data of the software program. The memory 1303 is mainly used to store the software program and data. The transceiver 1302 may include a radio frequency circuit and an antenna. The radio frequency circuit is mainly used for converting baseband signals and radio frequency signals and processing radio frequency signals. The antenna is mainly used to transmit and receive radio frequency signals in the form of electromagnetic waves. Input and output devices, such as touch screens, display screens, keyboards, etc., are mainly used to receive data input by users and output data to users.

[0261] Optionally, the processor 1301, the transceiver 1302, and the memory 1303 may be connected via a communication bus.

[0262] When the communication device or the sensing device is turned on, the processor 1301 can read the software program in the memory 1303, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be sent wirelessly, the processor 1301 performs baseband processing on the data to be sent, and outputs the baseband signal to the RF circuit. The RF circuit performs RF processing on the baseband signal and then sends the RF signal outward in the form of electromagnetic waves through the antenna. When data is sent to the communication device or the sensing device, the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor 1301. The processor 1301 converts the baseband signal into data and processes the data.

[0263] In another implementation, the RF circuit and antenna may be arranged independently of the processor performing baseband processing. For example, in a distributed scenario, the RF circuit and antenna may be arranged remotely from the communication device or the sensing device.

[0264] In some embodiments, in terms of hardware implementation, those skilled in the art may understand that the above-mentioned device 110 may adopt Fig.13 The form of the device 130 is shown.

[0265] As an example, Fig.11 The function / implementation process of the processing module 1101 in Fig.13 The processor 1301 in the illustrated device 130 calls the computer execution instructions stored in the memory 1303 to implement. Fig.11 The function / implementation process of the transceiver module 1102 can be Fig.13 The transceiver 1302 in the device 130 shown is implemented.

[0266] As another possible product form, the receiving device in this application can adopt Fig.14 The structure shown, or including Fig.14Parts shown. Fig.14 A schematic diagram of the composition of a communication device or a sensing device 1400 provided in the present application. The device 1400 may be a receiving device or a chip or a system on a chip in a receiving device.

[0267] like Fig.14 As shown, the device 1400 includes at least one processor 1401 and at least one communication interface ( Fig.14 The device 1400 is merely illustrative and is described by taking a communication interface 1404 and a processor 1401 as an example. Optionally, the device 1400 may further include a communication bus 1402 and a memory 1403.

[0268] The processor 1401 may be a general-purpose central processing unit (CPU), a general-purpose processor, a network processor (NP), a digital signal processor (DSP), a microprocessor, a microcontroller, a programmable logic device (PLD), or any combination thereof. The processor 1401 may also be other devices with processing functions, such as circuits, devices, or software modules, without limitation.

[0269] The communication bus 1402 is used to connect different components in the communication device or the sensing device 1400 so that the different components can communicate. The communication bus 1402 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.14 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0270] The communication interface 1404 is used to communicate with other devices or communication networks. Exemplarily, the communication interface 1404 can be a module, a circuit, a transceiver, or any device capable of implementing communication. Optionally, the communication interface 1404 can also be an input / output interface located in the processor 1401 to implement signal input and signal output of the processor.

[0271] The memory 1403 may be a device with a storage function, used to store instructions and / or data, wherein the instructions may be computer programs.

[0272] Exemplarily, the memory 1403 may be a read-only memory (ROM) or other types of static storage devices that can store static information and / or instructions, or a random access memory (RAM) or other types of dynamic storage devices that can store information and / or instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, etc., without limitation.

[0273] It should be noted that the memory 1403 can exist independently of the processor 1401, or can be integrated with the processor 1401. The memory 1403 can be located in the communication device or the sensing device 1400, or can be located outside the communication device or the sensing device 1400, without limitation. The processor 1401 can be used to execute the instructions stored in the memory 1403 to implement the method provided in the following embodiments of the present application.

[0274] As an optional implementation, the communication device or perception device 1400 may also include an output device 1405 and an input device 1406. The output device 1405 communicates with the processor 1401 and can display information in a variety of ways. For example, the output device 1405 may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device 1406 communicates with the processor 1401 and can receive user input in a variety of ways. For example, the input device 1406 may be a mouse, a keyboard, a touch screen device, or a sensor device.

[0275] In some embodiments, in terms of hardware implementation, those skilled in the art may think of the above Fig.11 The device 110 shown may be used Fig.14 The form of the device 1400 is shown.

[0276] As an example, Fig.11 The function / implementation process of the processing module 1101 in Fig.14The processor 1401 in the illustrated device 1400 calls the computer execution instructions stored in the memory 1403 to implement. Fig.11 The function / implementation process of the transceiver module 1102 can be Fig.14 The communication interface 1404 in the device 1400 is shown to be implemented.

[0277] It should be noted that Fig.14 The structure shown does not constitute a specific limitation on the receiving device. For example, in other embodiments of the present application, the receiving device may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0278] In some embodiments, the embodiments of the present application also provide a communication device or a perception device, which includes a processor for implementing the method in any of the above method embodiments.

[0279] As a possible implementation, the communication device or perception device further includes a memory. The memory is used to store necessary computer programs and data. The computer program may include instructions, and the processor may call the instructions in the computer program stored in the memory to instruct the communication device or perception device to execute the method in any of the above method embodiments. Of course, the memory may not be in the communication device or perception device.

[0280] As another possible implementation, the communication device or perception device also includes an interface circuit, which is a code / data read / write interface circuit, which is used to receive computer execution instructions (computer execution instructions are stored in a memory, may be read directly from the memory, or may pass through other devices) and transmit them to the processor.

[0281] As another possible implementation, the communication device or the perception device further includes a communication interface, and the communication interface is used to communicate with a module outside the communication device or the perception device.

[0282] It can be understood that the communication device or the sensing device can be a chip or a chip system. When the communication device or the sensing device is a chip system, it can be composed of chips, or it can include chips and other discrete devices. The embodiments of the present application do not specifically limit this.

[0283] The present application also provides a computer-readable storage medium on which a computer program or instruction is stored. When the computer program or instruction is executed by a computer, the functions of any of the above method embodiments are implemented.

[0284] The present application also provides a computer program product, which implements the functions of any of the above method embodiments when executed by a computer.

[0285] Those skilled in the art will appreciate that, for the sake of convenience and brevity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0286] It is understood that the systems, devices and methods described in the present application can also be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0287] The units described as separate components may or may not be physically separated, i.e., they may be located in one place, or they may be distributed over multiple network units. The components shown as units may or may not be physical units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0288] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0289] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or may include one or more servers, data centers and other data storage devices that can be integrated with the medium. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state drive (SSD)), etc. In the embodiment of the present application, the computer may include the aforementioned device.

[0290] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in a claim. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0291] Although the present application has been described in conjunction with specific features and embodiments thereof, it is obvious that various modifications and combinations may be made thereto without departing from the spirit and scope of the present application. Accordingly, this specification and the drawings are merely exemplary illustrations of the present application as defined by the appended claims, and are deemed to have covered any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, those skilled in the art may make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A signal receiving method, characterized in that: The method comprises: Receive a first signal, where the first signal includes a target signal, where the target signal occupies one subcarrier in every M consecutive subcarriers, where M is a positive integer greater than 1; Down-converting the first signal to obtain a second signal; A third signal is determined according to the second signal, wherein the third signal comprises a superposition of K delayed signals of the second signal, and the delay time associated with the kth delayed signal among the K delayed signals is Wherein, T is the time length of the first signal, k=1, 2, ..., k, δ is greater than or equal to 0, and K is a positive integer greater than or equal to M; The third signal is sampled to determine the target signal.

2. The method according to claim 1, characterized in that The frequency of the down-conversion is related to the carrier frequency of the first signal and / or the position of the target signal.

3. The method according to claim 1 or 2, characterized in that: Determining a third signal according to the second signal includes: The second signal is delayed K times to obtain K delayed signals of the second signal, wherein the delay time associated with the kth delayed signal is The K delayed signals are superimposed to obtain the third signal.

4. The method according to claim 1 or 2, characterized in that: Determining a third signal according to the second signal includes: determining the third signal by an X-level circuit, wherein: The output signal of the i-th stage circuit is: a signal obtained by superimposing the input signal of the i-th stage circuit and a delayed signal of the input signal of the i-th stage circuit, i=1, 2, ..., X, where X is a positive integer greater than 1; Among them, when i=1, the input signal of the i-th stage circuit is the signal after the second signal is delayed by δ, when i>1, the input signal of the i-th stage circuit is the output signal of the i-1-th stage circuit, the third signal is the output signal of the X-th stage circuit, and the output signal of the X-th stage circuit includes the superposition of K delayed signals of the second signal.

5. The method according to claim 4, characterized in that K＝2 X ； The output signal of the i-th stage circuit is: the input signal of the i-th stage circuit and the input signal of the i-th stage circuit are delayed The signal after superposition of the signals.

6. The method according to claim 4, characterized in that The output signal of the i-th stage circuit is: the input signal of the i-th stage circuit and the input signal of the i-th stage circuit are delayed respectively. The signal after the superposition of the signals, Π represents the cumulative multiplication, K i Is a positive integer.

7. The method according to any one of claims 1 to 6, characterized in that: K=M, sampling the third signal, including: In time range The third signal is sampled within a time range, and the reference point of the time range is the starting time of the first signal.

8. The method according to any one of claims 1 to 6, characterized in that: K=M, sampling the third signal, including: The third signal is delayed A times to obtain A delayed signals of the third signal, where A is a positive integer, and the delay time associated with the a-th delayed signal is δ a Greater than or equal to 0, a=1,2,…,A; In time range The ath delayed signal of the third signal is sampled within the time range, and the reference point of the time range is the starting time of the first signal.

9. The method according to claim 8, characterized in that The sampling frequency used when sampling the ath delayed signal of the third signal is greater than or equal to NΔf C / A, wherein N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, N is a positive integer, Δf C is the bandwidth of the subcarrier.

10. The method according to claim 8 or 9, characterized in that: Among the A delayed signals of the third signal, sampling positions of any two delayed signals are different.

11. The method according to any one of claims 1 to 6, characterized in that: K=M-1+C, where C is a positive integer.

12. The method according to claim 11, characterized in that Sampling the third signal includes: Performing C-segment sampling on the third signal; The c-th sampling corresponds to a signal in which the third signal is within a time range c, c=1, 2, ..., C, and the time range c is: The reference point of the time range c is the start time of the first signal.

13. The method according to claim 12, characterized in that The sampling frequency used when performing C-segment sampling on the third signal is greater than or equal to NΔf C / C, N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, N is a positive integer, Δf C is the bandwidth of the subcarrier.

14. The method according to claim 12 or 13, characterized in that In the C-segment sampling of the third signal, the sampling positions in any two segments are different.

15. The method according to any one of claims 1 to 14, characterized in that: Sampling the third signal to determine the target signal includes: The third signal is sampled to obtain a first time domain sequence, and an N / M-point discrete Fourier transform DFT is performed on the first time domain sequence to obtain a frequency domain signal corresponding to the target signal; wherein N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer.

16. A device, characterized in that: The device comprises: a first circuit; The first circuit is used to determine a third signal according to the second signal, wherein the third signal includes a superposition of K delayed signals of the second signal, and the delay time associated with the kth delayed signal among the K delayed signals is Among them, the second signal is a signal after down-converting the first signal, the first signal includes a target signal, the target signal occupies one subcarrier in every M consecutive subcarriers, M is a positive integer greater than 1, T is the time length of the first signal, k=1,2,…,k, δ is greater than or equal to 0, and K is a positive integer greater than or equal to M; the third signal is the input signal of the analog-to-digital converter.

17. The device according to claim 16, characterized in that The first circuit includes K delays and an adder; The kth delay device among the K delay devices is used to delay the second signal Obtaining a kth delayed signal of the second signal; The adder is used to superimpose K delayed signals of the second signal to obtain the third signal.

18. The device according to claim 16, characterized in that The first circuit includes an X-level circuit, wherein: The output signal of the i-th stage circuit is: a signal obtained by superimposing the input signal of the i-th stage circuit and a delayed signal of the input signal of the i-th stage circuit, i=1, 2, ..., X, where X is a positive integer greater than 1; Among them, when i=1, the input signal of the i-th stage circuit is the signal after the second signal is delayed by δ, when i>1, the input signal of the i-th stage circuit is the output signal of the i-1-th stage circuit, the third signal is the output signal of the X-th stage circuit, and the output signal of the X-th stage circuit includes the superposition of K delayed signals of the second signal.

19. The device according to claim 18, characterized in that K=2 X ; The i-th stage circuit includes a delay device and an adder; The delay device is used to delay the input signal of the i-th stage circuit The adder is used to superimpose the input signal of the i-th stage circuit and the output signal of the delay device in the i-th stage circuit.

20. The device according to claim 18, characterized in that The i-th stage circuit includes K i -1 delay and one adder; The K i - 1 delay device, used to delay the input signal of the i-th circuit The adder is used to superimpose the input signal of the i-th circuit and the K in the i-th circuit. i -1 delay output signal.

21. The device according to any one of claims 16 to 20, characterized in that: K=M; the device also includes an analog-to-digital converter; The analog-to-digital converter is used in the time range The third signal is sampled within a time range, and the reference point of the time range is the starting time of the first signal.

22. The device according to any one of claims 16 to 20, characterized in that K=M; the device also includes an analog-to-digital converter and a second circuit; The second circuit is used to delay the third signal A times to obtain A delayed signals of the third signal, where A is a positive integer, and the delay time associated with the a-th delayed signal is δ a Greater than or equal to 0, a=1,2,…,A; The analog-to-digital converter is used in the time range The ath delayed signal of the third signal is sampled within the time range, and the reference point of the time range is the starting time of the first signal.

23. The device according to claim 22, characterized in that The sampling frequency used when sampling the ath delayed signal of the third signal is greater than or equal to NΔf C / A, wherein N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, N is a positive integer, Δf C is the bandwidth of the subcarrier.

24. The device according to claim 22 or 23, characterized in that Among the A delayed signals of the third signal, sampling positions of any two delayed signals are different.

25. The device according to any one of claims 16 to 20, characterized in that K=M-1+C, where C is a positive integer.

26. The device according to claim 25, characterized in that The device also includes an analog-to-digital converter; The analog-to-digital converter is used to perform C-segment sampling on the third signal; wherein the c-segment sampling corresponds to a signal of the third signal within a time range c, c=1, 2, ..., C, and the time range c is: The reference point of the time range c is the start time of the first signal.

27. The device according to any one of claims 16 to 26, characterized in that The device also includes: a discrete Fourier transform module; The discrete Fourier transform module is used to perform an N / M-point discrete Fourier transform DFT on the first time domain sequence to obtain a frequency domain signal corresponding to the target signal; wherein N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, N is a positive integer, and the first time domain sequence is a sampling result corresponding to the third signal.

28. A chip, characterized in that: The chip comprises: a first circuit; The first circuit is used to determine a third signal according to the second signal, wherein the third signal includes a superposition of K delayed signals of the second signal, and the delay time associated with the kth delayed signal among the K delayed signals is Among them, the second signal is a signal after down-converting the first signal, the first signal includes a target signal, the target signal occupies one subcarrier in every M consecutive subcarriers, M is a positive integer greater than 1, T is the time length of the first signal, k=1,2,…,K, δ is greater than or equal to 0, K is a positive integer greater than or equal to M; the third signal is the input signal of the analog-to-digital converter.

29. The chip according to claim 28, characterized in that The chip also includes the analog-to-digital converter; The analog-to-digital converter is used to sample the third signal.

30. The chip according to claim 28 or 29, characterized in that: The chip also includes a discrete Fourier transform module; The discrete Fourier transform module is used to perform an N / M-point discrete Fourier transform DFT on the first time domain sequence to obtain a frequency domain signal corresponding to the target signal; wherein the first time domain sequence is a sampling result corresponding to the third signal, N is greater than or equal to the number of subcarriers included in the bandwidth of the first signal, and N is a positive integer.

31. A device, characterized in that: The device comprises a processor; the processor is used to run a computer program or instruction so that the device executes the method according to any one of claims 1-15.

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