Solar cell and photovoltaic module

Abstract

The invention discloses a solar cell and a photovoltaic module. Wherein the semiconductor substrate comprises a first surface and a second surface which are opposite to each other, and a side surface connected with the first surface and the second surface; in the direction from the first face to the second face, the side face comprises a first area and a second area which are sequentially arranged, the first area is provided with a first texture structure, and the second area is provided with a second texture structure. The first texture structure and the second texture structure can enable light incident to the side face to be reflected and refracted for multiple times, the advancing direction of the incident light on the side face of the semiconductor substrate is changed, the optical path is prolonged, the light trapping effect is generated, and generation of photon-generated carriers is increased, so that when the side face of the semiconductor substrate is provided with the first texture structure and the second texture structure, the light trapping effect is improved. More light rays can be absorbed and utilized by the side surface of the semiconductor substrate, and the photoelectric conversion efficiency of the solar cell can be improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic power generation technology, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] Solar cells are now being used more and more widely as a new energy alternative. Among them, photovoltaic solar cells are devices that convert sunlight into electrical energy. Specifically, solar cells use the photovoltaic principle to generate carriers, and then use electrodes to lead the carriers out, thereby facilitating the effective use of electrical energy.

[0003] However, the optical loss of the solar cell in the prior art is high and the photoelectric conversion efficiency is low; moreover, the edges and sides of the solar cell are seriously compounded, which easily causes edge leakage. Summary of the invention

[0004] The purpose of the present application is to provide a solar cell and a photovoltaic module to reduce lateral recombination while improving photoelectric conversion efficiency.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A solar cell, comprising:

[0007] A semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other, and a side surface connecting the first surface and the second surface;

[0008] Along the direction from the first surface to the second surface, the side surface includes a first area and a second area which are arranged in sequence, the first area has a first texture structure, and the second area has a second texture structure.

[0009] In the solar cell provided in the present application, a first texture structure is provided in a first area on the side surface, and a second texture structure is provided in a second area on the side surface, wherein the first texture structure and the second texture structure can cause the light incident to the side surface to be reflected and refracted multiple times, thereby changing the advancing direction of the incident light on the side surface of the semiconductor substrate, extending the optical path, generating a light trapping effect, and increasing the generation of photogenerated carriers. Therefore, when the side surface of the semiconductor substrate has the first texture structure and the second texture structure, it is beneficial for more light to be absorbed and utilized by the side surface of the semiconductor substrate, thereby improving the photoelectric conversion efficiency of the solar cell.

[0010] In one implementation, the first surface has a first texture structure, and the first texture structure of the first region is continuously arranged with the first texture structure of the first surface. In this way, the first texture structure is arranged in the vicinity of the position where the side surface and the first surface meet. The surface area of ​​the first texture structure is larger, which is conducive to dispersing the stress of the edge of the solar cell, thereby reducing the edge defects of the solar cell and improving the yield of the solar cell. And / or,

[0011] The second surface has a second texture structure, and the second texture structure of the second region is continuously arranged with the second texture structure of the second surface. In this way, the second texture structure is arranged in the vicinity of the position where the side surface and the second surface meet, and the surface area of ​​the second texture structure is larger, which is conducive to dispersing the stress of the edge of the solar cell, thereby reducing the edge defects of the solar cell and improving the yield of the solar cell.

[0012] In one implementation, the first texture structure and the second texture structure are both non-polished surfaces, and the velvet structure can be a positive pyramid velvet structure, an inverted pyramid velvet structure, a pyramid velvet with a flat top, or a wormhole velvet structure. With this technical solution, the surface of the first texture structure has a stronger degree of concavity and convexity, and a better light trapping effect, so that more light can be absorbed and utilized by the side of the semiconductor substrate. And / or,

[0013] The first texture structure includes a velvet structure, so that the size of the first pyramid is set within a reasonable range. During the preparation of the battery, the light trapping effect of the velvet of the first pyramid can be taken into account, and the quality of the film layer subsequently deposited on the velvet of the first pyramid can be improved, and the density and coating of the film layer can be improved. And / or,

[0014] The second texture structure includes a pyramid-like velvet structure, and at least part of the pyramid-like side edges are curved. With this technical solution, part or all of the pyramid-like side edges are curved. Compared with straight side edges, on the one hand, it can more effectively disperse the stress on the side of the solar cell, effectively reduce stress concentration, and thus improve the yield of the solar cell; on the other hand, it increases the surface area of ​​the second texture structure, and the contact area with the subsequent deposited film layer is larger, thereby improving the passivation effect on the edge of the semiconductor substrate.

[0015] In one implementation, the first texture structure is a first pyramid velvet structure; the height of the first pyramid is 1μm to 5μm, and the side length of the base of the first pyramid is 1μm to 3μm. It can be understood that when the height of the first pyramid is too low, the light trapping effect of the first pyramid velvet will be reduced; when the height of the first pyramid is too high, the quality of the film layer will be reduced when the film layer is subsequently deposited on the first pyramid velvet. In this way, the size of the first pyramid is set within a reasonable range. During the preparation process of the battery, it can take into account the light trapping effect of the first pyramid velvet, and can also make the quality of the film layer subsequently deposited on the first pyramid velvet better, and the density and coating of the film layer are better.

[0016] In one implementation, the second texture structure includes a pyramid-like velvet structure, and at least a portion of the side edges of the pyramid-like structure are curved.

[0017] The height of the pyramid is 0.1μm to 5μm, and the side length of the pyramid base is 1μm to 3μm. It can be understood that when the height of the pyramid is too low, the light trapping effect of the pyramid velvet surface will be reduced; when the height of the pyramid is too high, the quality of the film layer will be reduced when the film layer is subsequently deposited on the pyramid velvet surface. In this way, the size of the pyramid is set within a reasonable range. During the preparation process of the battery, the light trapping effect of the pyramid can be taken into account, and the quality of the film layer subsequently deposited on the pyramid velvet surface can be better, and the density and coating of the film layer can be better.

[0018] And / or, the side edge of the pyramid-like is an inwardly concave curve; and / or, at least the bottom of the side edge of the pyramid-like is a curve, and the curvature radius of the bottom of the side edge of the pyramid-like is 0.1μm to 10μm; and / or, each pyramid-like includes 3 to 6 side edges. The multiple side faces of the pyramid-like face in different directions, so that light incident on the pyramid-like from different angles can be reflected and refracted through different side faces of the pyramid-like, further improving the absorption and utilization rate of the side of the semiconductor substrate for light; in addition, the surface area of ​​the pyramid-like is larger, which is conducive to increasing the contact area of ​​the subsequent deposited film layer and improving the passivation effect.

[0019] In one implementation, along the direction of the semiconductor thickness, the ratio of the extension distance of the first region to the entire extension distance of the side surface is greater than or equal to 50%; and / or,

[0020] Along the direction of the semiconductor thickness, the ratio of the extension distance of the second region to the overall extension distance of the side surface is less than or equal to 50%. Since light is generally irradiated downward from the top or obliquely above the solar cell, the first region closer to the first surface can receive more light than the second region farther from the first surface, so the ratio of the extension distance of the first region to the overall extension distance of the side surface can be made greater than the ratio of the extension distance of the second region to the overall extension distance of the side surface, so that the first texture structure in the first region absorbs and utilizes more light.

[0021] In one implementation, the average height of the first texture structure is greater than the average height of the second texture structure, so that the light trapping effect of the first texture structure is better than that of the second texture structure, and the light is generally irradiated downward from the top or obliquely above the solar cell, and the first area closer to the first surface can receive more light than the second area farther from the first surface, thereby improving the absorption rate of the light in the first area. And / or,

[0022] The first texture structure and the second texture structure have a height difference along a direction perpendicular to the side surface, and the height difference ranges from greater than 0 μm to less than or equal to 3 μm; and / or,

[0023] The reflectivity of the first texture structure is lower than that of the second texture structure. In this way, the second texture structure can reflect long-wave light and improve the light absorption efficiency.

[0024] In one implementation, the first surface is a light-receiving surface and the second surface is a backlight surface.

[0025] In one implementation, the side surface further includes a third region, the third region is located between the first region and the first surface, and the third region has a third texture structure;

[0026] The reflectivity of the third texture structure is greater than that of the first texture structure. Thus, the light irradiated to the third texture structure can be reabsorbed by the semiconductor substrate after reflection, thereby increasing the light absorption utilization rate of the semiconductor substrate.

[0027] In one implementation, the third texture structure includes a suede structure or a polished surface or a flattened tower base structure; and / or,

[0028] The first surface has a first texture structure, and the third texture structure of the third region is continuously arranged with the first texture structure of the first surface. In this way, the first surface and the first region are transitionally connected through the third region and its third texture structure, which can reduce defects in the vicinity of the side surface and the first surface, further reduce edge and side recombination, and prevent edge leakage. And / or,

[0029] The third texture structure has the same shape as the first texture structure and the average one-dimensional size of the third texture structure is smaller than the average one-dimensional size of the first texture structure, so as to prevent the third texture structure from being too large to block the first texture structure and affect the light absorption efficiency of the first texture structure. And / or,

[0030] Along the direction of the semiconductor thickness, the extension distance of the third region accounts for a proportion of the overall extension distance of the side surface that is greater than or equal to 5%. If the extension distance of the third region accounts for too large a proportion of the overall extension distance of the side surface, the larger the area of ​​the third region, the smaller the area of ​​the first region and the second region will inevitably be, thereby affecting the effect of dispersing stress in the first region and the second region. Therefore, in this embodiment, the extension distance of the third region along the direction of the semiconductor thickness is set within a reasonable range to ensure a reasonable distribution of the areas of the first region and the second region, thereby preventing the hidden danger of stress concentration on the side surface of the solar cell.

[0031] In one implementation, a passivation anti-reflection layer is also included, the passivation anti-reflection layer covers the first region and the third region, and the passivation anti-reflection layer does not cover the second region; there is also a second doped semiconductor layer between the third region and the passivation anti-reflection layer. In this embodiment, the first region and the third region are covered by the passivation anti-reflection layer, and the first region is close to the first surface of the solar cell. When the first surface is the light-facing surface, the passivation effect is better, and it has a hydrogen passivation effect, thereby reducing the risk of recombination and leakage. The passivation anti-reflection layer can protect the first region and the third region, isolate the invasion of water vapor, and extend the service life of the battery.

[0032] In one implementation, a passivation anti-reflection layer is further included, the passivation anti-reflection layer covers the first region, and the passivation anti-reflection layer does not cover the second region. With such a configuration, the passivation effect is better, and the hydrogen passivation effect is achieved, thereby reducing the risk of recombination and leakage.

[0033] In one implementation, a first doped semiconductor layer is further included, the first doped semiconductor layer covers the second region and at least partially covers the passivation anti-reflection layer located on the side surface. This arrangement increases the area of ​​the first doped semiconductor layer for collecting carriers, thereby improving power generation efficiency.

[0034] In one implementation, the first doped semiconductor layer is amorphous silicon or microcrystalline silicon, and the second doped semiconductor layer is polycrystalline silicon; the first doped semiconductor layer and the second doped semiconductor layer have opposite doping types. When the second doped semiconductor layer is a polycrystalline silicon layer, the carrier transmission efficiency is higher, which is conducive to improving the photoelectric conversion efficiency of the solar cell; when the first doped semiconductor layer is amorphous silicon or microcrystalline silicon, the passivation effect on the side edge is good, further reducing recombination.

[0035] In one implementation, the first doped semiconductor layer is also disposed on the second surface, and the first doped semiconductor layer extends from the second surface to the second region, thereby increasing the area of ​​the first doped semiconductor layer and thereby increasing the efficiency of the first doped semiconductor layer in collecting carriers.

[0036] In one implementation, the passivation anti-reflection layer is also disposed on the first surface, and the passivation anti-reflection layer extends from the first surface to the first region, thereby further improving the passivation effect of the first surface and reducing the recombination of the first surface; at the same time, the passivation anti-reflection layer on the first surface and the side surface can be formed in the same step, thereby simplifying the processing technology and improving production efficiency.

[0037] In one implementation, a second doped semiconductor layer is further included between the first surface and the passivation anti-reflection layer. In this way, the second doped semiconductor layer located on the first surface can collect carriers, thereby improving the power generation efficiency of the entire solar cell.

[0038] In one implementation, it also includes an interface layer between the first surface and the second doped semiconductor layer; the interface layer on the first surface and the second doped semiconductor layer are distributed in a finger shape. In this way, the interface layer can further enhance the passivation effect of the semiconductor substrate, and form a passivation contact structure in combination with the second doped semiconductor layer, which is more conducive to the collection of carriers; the interface layer on the first surface and the second doped semiconductor layer are distributed in a finger shape, and in this way, the interface layer on the first surface and the second doped semiconductor layer form a Poly-finger structure, which can reduce the parasitic absorption of the second doped semiconductor layer and improve the Jsc of the battery.

[0039] In one implementation, there is an interface layer between the third region and the second doped semiconductor layer, and the interface layer is silicon oxide. In this way, the passivation effect in the third region is better, and the interface layer and the second doped semiconductor layer can also collect carriers when receiving light, thereby improving the carrier collection efficiency and the photoelectric conversion efficiency.

[0040] In one implementation, it further includes an intrinsic amorphous silicon layer located under the first doped semiconductor layer, covering the second region and at least partially covering the passivation anti-reflection layer located on the side.

[0041] In one implementation, in the second region, the intrinsic amorphous silicon layer is in direct contact with the surface of the semiconductor substrate. The intrinsic amorphous silicon layer has a good passivation effect and can further reduce recombination.

[0042] In one implementation, along the direction from the second surface to the first surface, the thickness of the first doped semiconductor layer on the side surface gradually decreases, which is beneficial to improve the protective effect of the film layer on the side surface close to the second surface.

[0043] In one implementation, the passivation anti-reflection layer is in direct contact with the first region on the side of the semiconductor substrate, thereby further improving the passivation effect on the first region.

[0044] In an implementation, the passivation anti-reflection layer is a single layer or a stacked structure of at least two layers, and the stacked structure includes a passivation layer and an anti-reflection layer sequentially arranged in a direction away from the side surface.

[0045] In one implementation, the thickness of the passivation anti-reflection layer on the side surface gradually decreases along the direction from the first surface to the second surface, which is beneficial to improving the insulation protection effect of the passivation anti-reflection layer on the side surface close to the first surface, and further improving the reliability of the battery side structure.

[0046] A photovoltaic module, such as any of the solar cells described above.

[0047] Compared with the prior art, the beneficial effects of the photovoltaic module provided in the embodiment of the present application are the same as the beneficial effects of the above-mentioned solar cell, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0049] Figure 1 A SEM image of a side portion of a solar cell provided in an embodiment of the present application;

[0050] Figure 2 A partial SEM image of the side of a solar cell at another angle provided in an embodiment of the present application;

[0051] Figure 3 A partial cross-sectional view of a solar cell provided in an embodiment of the present application;

[0052] Figure 4 A cross-sectional view of a position where a first area and a second area of ​​a side surface of a solar cell provided in an embodiment of the present application are connected;

[0053] Figure 5 A schematic diagram of a pyramid-like structure provided in an embodiment of the present application;

[0054] Figure 6 A schematic diagram of a side view of a solar cell provided by another embodiment of the present application;

[0055] Figure 7 Schematic diagram of the method for manufacturing a solar cell provided in an embodiment of the present application Figure 1 ;

[0056] Figure 8 Schematic diagram of the method for manufacturing a solar cell provided in an embodiment of the present application Figure 2 ;

[0057] Fig. 9 Schematic diagram of the method for manufacturing a solar cell provided in an embodiment of the present application Figure 3 ;

[0058] Fig.10 Schematic diagram of the method for manufacturing a solar cell provided in an embodiment of the present application Figure 4 ;

[0059] Fig.11 Schematic diagram of the method for manufacturing a solar cell provided in an embodiment of the present application Figure 5 ;

[0060] Fig.12 Schematic diagram of the method for manufacturing a solar cell provided in an embodiment of the present application Figure 6 ;

[0061] Fig.13 Schematic diagram of the method for manufacturing a solar cell provided in an embodiment of the present application Figure 7 ;

[0062] Fig.14 Schematic diagram of the method for manufacturing a solar cell provided in an embodiment of the present application Figure 8 ;

[0063] Fig.15 Schematic diagram of the method for manufacturing a solar cell provided in an embodiment of the present application Figure 9 .

[0064] Reference numerals:

[0065] 1-semiconductor substrate, 1a-first region, 1b-second region, 1c-first texture structure, 1d-second texture structure, 1d1-pyramid-like, 1e-third region, 2-intrinsic amorphous silicon layer, 3-first doped semiconductor layer, 4-transparent conductive layer, 5-first electrode, 6-anti-reflection layer, 7-passivation layer, 8-second doped semiconductor layer, 9-interface layer, 10-second electrode, 11-PSG layer, 12-through hole. DETAILED DESCRIPTION

[0066] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0067] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0068] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0069] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", etc., indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0070] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0071] See also Figure 1-Figure 4 The solar cell provided in the embodiment of the present application includes a semiconductor substrate 1, and the semiconductor substrate 1 has a first surface, a second surface and a side surface. The first surface and the second surface are arranged opposite to each other, and the side surface connects the first surface and the second surface. The first surface of the semiconductor substrate 1 can correspond to the light-facing surface of the solar cell, and the second surface of the semiconductor substrate 1 can correspond to the backlight surface of the solar cell; or, the first surface of the semiconductor substrate 1 corresponds to the backlight surface of the solar cell, and the second surface of the semiconductor substrate 1 corresponds to the light-facing surface of the solar cell.

[0072] Among them, the material of the semiconductor substrate 1 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs). Obviously, in terms of conductivity type, the semiconductor substrate 1 can be an intrinsic conductive substrate, an n-type conductive substrate or a p-type conductive substrate. Optionally, the semiconductor substrate 1 is a p-type conductive substrate or an n-type conductive substrate. Compared with the intrinsic conductive substrate, the p-type conductive substrate or the n-type conductive substrate has better conductivity, so that the final solar cell has a lower body resistivity, thereby improving the efficiency of the solar cell.

[0073] Along the direction from the first surface to the second surface, the side surface includes a first area 1a and a second area 1b arranged in sequence. That is, the first area 1a is closer to the first surface than the second area 1b, and the second area 1b is closer to the second surface than the first area 1a. Figure 1 As shown, the left side of the red dotted line is the first area 1a, and the right side of the red dotted line is the second area 1b. The first area 1a has a first texture structure 1c, and the second area 1b has a second texture structure 1d.

[0074] In the solar cell provided in the present application, a first texture structure 1c is provided in a first area 1a on the side, and a second texture structure 1d is provided in a second area 1b on the side, wherein the first texture structure 1c and the second texture structure 1d can cause the light incident to the side to be reflected and refracted multiple times, thereby changing the advancing direction of the incident light on the side of the semiconductor substrate 1, extending the optical path, generating a light trapping effect, and increasing the generation of photogenerated carriers. Therefore, when the side of the semiconductor substrate 1 has the first texture structure 1c and the second texture structure 1d, it is beneficial for more light to be absorbed and utilized by the side of the semiconductor substrate 1, thereby improving the photoelectric conversion efficiency of the solar cell.

[0075] In some embodiments, the first surface of the solar cell has a first texture structure 1c, and the first texture structure 1c of the first region 1a is continuously arranged with the first texture structure 1c of the first surface. Specifically, the first surface and the first region 1a of the side of the solar cell both have the first texture structure 1c, and the first surface and the first region 1a of the side are continuously arranged, so that the first texture structure 1c of the first region 1a is also continuously arranged with the first texture structure 1c of the first surface. That is, the first texture structure 1c is continuously and uninterruptedly arranged from the first surface to the first region 1a. In this arrangement, the first texture structure 1c is arranged in the vicinity of the position where the side and the first surface meet, and the surface area of ​​the first texture structure 1c is larger, which is conducive to dispersing the stress at the edge of the solar cell, thereby reducing the edge defects of the solar cell and improving the yield of the solar cell.

[0076] In some embodiments, the second surface of the solar cell has a second texture structure 1d, and the second texture structure 1d of the second region 1b is continuously arranged with the second texture structure 1d of the second surface. Specifically, the second surface and the second region 1b of the side of the solar cell both have the second texture structure 1d, and the second surface and the second region 1b of the side are continuously arranged, so that the second texture structure 1d of the second region 1b is also continuously arranged with the second texture structure 1d of the second surface. That is, the second texture structure 1d is continuously and uninterruptedly arranged from the second surface to the second region 1b. In this arrangement, the second texture structure 1d is arranged in the vicinity of the position where the side and the second surface meet, and the surface area of ​​the second texture structure 1d is larger, which is conducive to dispersing the stress at the edge of the solar cell, thereby reducing the edge defects of the solar cell and improving the yield of the solar cell.

[0077] In view of the fact that the surface concavity of the polished surface structure is weak and the light trapping effect is poor, in this embodiment, the first texture structure 1c is a non-polished surface; the second texture structure 1d is a non-polished surface. The first texture structure 1c can be a velvet structure, specifically, the velvet structure can be a positive pyramid velvet structure, an inverted pyramid velvet structure, a pyramid velvet with a flat top, or a wormhole velvet structure. With this technical solution, the surface concavity of the first texture structure 1c is stronger and the light trapping effect is better, so that more light is further absorbed and utilized by the side of the semiconductor substrate 1.

[0078] In the above embodiment, the first texture structure 1c is the first pyramid velvet surface. The height of the first pyramid is 1μm to 5μm, and the side length of the base of the first pyramid is 1μm to 3μm. It can be understood that when the height of the first pyramid is too low, the light trapping effect of the first pyramid velvet surface will be reduced; when the height of the first pyramid is too high, the quality of the film layer formation will be reduced when the film layer is subsequently deposited on the first pyramid velvet surface. In this way, the size of the first pyramid is set within a reasonable range. During the preparation process of the battery, both the light trapping effect of the first pyramid velvet surface and the quality of the film layer subsequently deposited on the first pyramid velvet surface can be taken into account, and the density and coating of the film layer can be better.

[0079] Exemplarily, the height of the first pyramid is 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm or 5 μm, and the side length of the base of the first pyramid is 1 μm, 1.5 μm, 2 μm, 2.5 μm or 3 μm.

[0080] In addition, if Figure 5 As shown, the second texture structure 1d includes a pyramid-like velvet structure, and at least part of the side edges of the pyramid-like 1d1 are curved. In this technical solution, the second texture structure 1d is a smooth pyramid-like velvet structure. Figure 1 and Figure 2 As shown, part or all of the side edges of the pyramid-like 1d1 are curves, for example, the part of the side edges of the pyramid-like 1d1 close to the pyramid-like tower base is a curve, or the part of the side edges of the pyramid-like 1d1 close to the pyramid-like tower top is a curve, or the side edges of the pyramid-like 1d1 extend along the curve as a whole. With this technical solution, part or all of the side edges of the pyramid-like 1d1 are curves, which can more effectively disperse the stress on the side of the solar cell and effectively reduce stress concentration, thereby improving the yield of the solar cell compared to the straight side edges; on the other hand, the surface area of ​​the second texture structure 1d is increased, and the contact area with the subsequent deposited film layer is larger, thereby improving the passivation effect on the edge of the semiconductor substrate 1.

[0081] In the above embodiment, the height of the pyramid-like 1d1 is 0.1μm to 5μm, and the side length of the base of the pyramid-like 1d1 is 1μm to 3μm. It can be understood that when the height of the pyramid-like 1d1 is too low, the light-trapping effect of the pyramid-like velvet surface will be reduced; when the height of the pyramid-like 1d1 is too high, the quality of the film layer will be reduced when the film layer is subsequently deposited on the pyramid-like velvet surface. In this way, the size of the pyramid-like 1d1 is set within a reasonable range. During the preparation process of the battery, the light-trapping effect of the pyramid-like 1d1 can be taken into account, and the quality of the film layer subsequently deposited on the pyramid-like velvet surface can be better, and the density and coating of the film layer can be better.

[0082] Exemplarily, the height of the quasi-pyramid 1 d 1 is 0.1 μm, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm or 5 μm.

[0083] Among them, the side edges of the pyramid-like 1d1 are inwardly concave curves, so that the side surfaces of the pyramid-like 1d1 are inwardly concave curved surfaces, and the inner surfaces of the pits formed between adjacent pyramid-like 1d1 are all inwardly concave curved surfaces, which is more conducive to the multiple reflection and refraction of light incident on the velvet structure of the pyramid-like 1d1 on the inner surface of the pit, further improving the absorption and utilization of light, and is beneficial to improving the photoelectric conversion efficiency of solar cells.

[0084] In some embodiments, Figure 5 As shown, at least the bottom of the side edge of the pyramid-like 1d1 is a curve, and the curvature radius R of the bottom of the side edge of the pyramid-like 1d1 is 0.1μm to 10μm. In this embodiment, the curvature radius R of the bottom of the side edge of the pyramid-like 1d1 can be the curvature radius at the lowest point of any side edge of the pyramid-like 1d1, or in other words, the curvature radius R of the bottom of the side edge of the pyramid-like 1d1 is the curvature radius of the pyramid valley. If the curvature radius R of the bottom of the side edge of the pyramid-like 1d1 is too small, the quality of the film layer will be reduced when the film layer is subsequently deposited on the pyramid-like velvet surface; if the curvature radius R of the bottom of the side edge of the pyramid-like 1d1 is too large, the light trapping effect of the velvet structure of the pyramid-like 1d1 will be reduced. Therefore, setting the curvature radius R of the bottom of the side edge of the pyramid-like 1d1 within a reasonable range can not only take into account the light trapping effect of the pyramid-like 1d1, but also make the quality of the film layer subsequently deposited on the pyramid-like velvet surface better, and the density and coating of the film layer are better.

[0085] Exemplarily, the radius of curvature R of the bottom of the side edge of the pyramid-like 1d1 is 0.1μm, 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 7.5μm, 8μm, 8.5μm, 9μm, 9.5μm or 10μm.

[0086] In addition, each quasi-pyramid 1d1 includes 3 to 6 side edges. That is, the quasi-pyramid 1d1 has 3 to 6 side faces, and the multiple side faces of the quasi-pyramid 1d1 face different directions, so that light incident on the quasi-pyramid 1d1 from different angles can be reflected and refracted by different side faces of the quasi-pyramid 1d1, further improving the absorption and utilization rate of the side faces of the semiconductor substrate 1 for light; in addition, the surface area of ​​the quasi-pyramid 1d1 is larger, which is conducive to increasing the contact area of ​​the subsequent deposited film layer and improving the passivation effect. For example, the quasi-pyramid 1d1 can include 3, 4, 5 or 6 side edges.

[0087] It can be understood that, due to the difference in actual processing technology, in the pyramid-like 1d1 structure formed in the second region 1b, only the part of the side edge of the pyramid-like 1d1 close to the base of the pyramid-like 1d1 can be a curve, similar to the rounding of the base of an ordinary pyramid, and the rest of the side edge is a straight line, in which case the inner surface of the pit between the pyramid-like 1d1 is a curved surface with a shallow depth. Alternatively, in the pyramid-like 1d1 structure formed in the second region 1b, the side edge of the pyramid-like 1d1 is a concave curve as a whole, in which case the inner surface of the pit between the pyramid-like 1d1 is a curved surface with a deep depth.

[0088] In other embodiments, along the direction of the semiconductor thickness, the extension distance of the first region 1a accounts for a proportion of the overall extension distance of the side surface that is greater than or equal to 50%, and the extension distance of the second region 1b accounts for a proportion of the overall extension distance of the side surface that is less than or equal to 50%. Since light generally irradiates downward from the top or obliquely above the solar cell, the first region 1a closer to the first surface can receive more light than the second region 1b farther from the first surface, so that the extension distance of the first region 1a can account for a greater proportion of the overall extension distance of the side surface than the extension distance of the second region 1b, so as to facilitate the first texture structure 1c in the first region 1a to absorb and utilize more light.

[0089] For example, along the direction of the semiconductor thickness, the extension distance of the first region 1a accounts for 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90% or 95% of the extension distance of the entire side surface. Optionally, along the direction of the semiconductor thickness, the extension distance of the first region 1a accounts for 60%-95% of the extension distance of the entire side surface. It can be understood that the extension distance of the film layer covering the first region 1a is the same as the extension distance of the first region. Specifically, the extension distance of the passivation anti-reflection layer covering the first region is the same as the extension area of ​​the first region.

[0090] For example, along the direction of the semiconductor thickness, the extension distance of the first region 1a accounts for 50%, 45%, 40%, 35%, 30%, 25%, 20%, 15%, 10% or 5% of the overall extension distance of the side surface, etc. Optionally, along the direction of the semiconductor thickness, the extension distance of the first region 1a accounts for 5%-40% of the overall extension distance of the side surface.

[0091] like Figure 1-Figure 4 As shown, the average height of the first texture structure 1c is greater than the average height of the second texture structure 1d, so the light trapping effect of the first texture structure 1c is better than that of the second texture structure 1d, and the light generally irradiates downward from the top or obliquely above the solar cell, and the first area 1a closer to the first surface can receive more light than the second area 1b farther away from the first surface, thereby improving the absorption rate of light by the first area 1a.

[0092] In addition, the first texture structure 1c and the second texture structure 1d have a height difference along the direction perpendicular to the side, and the range of the height difference is greater than 0μm and less than or equal to 3μm, so as to prevent the first texture structure 1c from blocking the second texture structure 1d and affecting the absorption and utilization rate of light. Specifically, the height difference between the first texture structure 1c and the second texture structure 1d along the direction perpendicular to the side is 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm or 3μm.

[0093] Specifically, the height difference between the first texture structure 1c and the second texture structure 1d in the direction perpendicular to the side surface may be the height difference between the top of the first texture structure 1c and the top of the second texture structure 1d, or the height difference between the bottom of the second texture structure 1d and the bottom of the first texture structure 1c.

[0094] In one example, along the direction perpendicular to the side, the height difference between the vertex of the first texture structure 1c and the vertex of the second texture structure 1d is 0-3 μm, that is, the vertex of the first texture structure 1c is higher than the vertex of the second texture structure 1d. If the height difference between the vertex of the first texture structure 1c and the vertex of the second texture structure 1d is too large, the first texture structure 1c will block the second texture structure 1d; therefore, the height difference between the vertex of the first texture structure 1c and the vertex of the second texture structure 1d is set within a reasonable range of 0-3 μm to prevent the first texture structure 1c from blocking the second texture structure 1d and affecting the absorption and utilization rate of light.

[0095] Exemplarily, the height differences between the apex of the first texture structure 1 c and the apex of the second texture structure 1 d are 0, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, and 3 μm.

[0096] In another example, along the direction perpendicular to the side, the height difference between the bottom of the second texture structure 1d and the bottom of the first texture structure 1c is 0-3μm. In this way, the second texture structure 1d is set inwardly concave, which can reflect long-wave light and improve the absorption and utilization rate of light. Exemplarily, the distance that the bottom of the second texture structure 1d is concave inward relative to the bottom of the first texture structure 1c is 0, 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm.

[0097] In addition, the reflectivity of the first texture structure 1c is lower than the reflectivity of the second texture structure 1d. With this arrangement, the second texture structure 1d can reflect long-wave light and improve the light absorption utilization rate.

[0098] In other embodiments, Figure 6 As shown, the side surface also includes a third region 1e, which is located between the first region 1a and the first surface, and has a third texture structure. That is, the third region 1e is closer to the first surface than the first region 1a, and has a third texture structure in the third region 1e, and the third texture structure can be the same as or different from the second texture structure 1d.

[0099] Specifically, the third texture structure includes a suede structure or a polished surface or a flattened tower base structure. In this embodiment, the suede structure can be a positive pyramid suede structure, an inverted pyramid suede structure, or a wormhole suede structure.

[0100] In some possible implementations, the reflectivity of the third texture structure is greater than the reflectivity of the first texture structure 1c. In this way, the light irradiated to the third texture structure can be reabsorbed by the semiconductor substrate 1 after reflection, thereby increasing the absorption efficiency of the semiconductor substrate 1 for light.

[0101] In terms of the formation range, the third texture structure of the third region 1e is continuously arranged with the first texture structure 1c of the first surface. That is, the first region 1a and the third region 1e are continuously arranged, and the first texture structure 1c of the first region 1a and the third texture structure of the third region 1e are also continuously arranged. In this way, the first surface and the first region 1a are transitionally connected through the third region 1e and its third texture structure, which can reduce defects in the vicinity of the side surface and the first surface, further reduce edge and side recombination, and prevent edge leakage.

[0102] Along the direction of the semiconductor thickness, the extension distance of the third region 1e accounts for a proportion of the overall extension distance of the side surface that is greater than or equal to 5%. If the extension distance of the third region 1e accounts for too large a proportion of the overall extension distance of the side surface, the larger the area of ​​the third region 1e, the smaller the area of ​​the first region 1a and the second region 1b will inevitably be, thereby affecting the effect of dispersing stress in the first region 1a and the second region 1b. Therefore, in this embodiment, the extension distance of the third region 1e along the direction of the semiconductor thickness is set within a reasonable range to ensure a reasonable distribution of the areas of the first region 1a and the second region 1b, thereby preventing the hidden danger of stress concentration on the side surface of the solar cell.

[0103] Exemplarily, along the direction of the semiconductor thickness, the extension distance of the third region 1e accounts for 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55% or 60% of the extension distance of the entire side. Optionally, along the direction of the semiconductor thickness, the extension distance of the third region 1e accounts for 5% to 45% of the extension distance of the entire side. It can be understood that the extension distance of the film layer covering the third region 1e is the same as the extension distance of the third region 1e. Specifically, the extension distance of the interface layer and the second doped semiconductor layer covering the third region 1e is the same as the extension distance of the third region 1e.

[0104] In terms of shape and size, the third texture structure has the same shape as the first texture structure 1c, and the average one-dimensional size of the third texture structure is smaller than the average one-dimensional size of the first texture structure 1c, wherein the one-dimensional size includes height, side length, etc. This can prevent the third texture structure from being too large to block the first texture structure 1c and affect the light absorption efficiency of the first texture structure 1c.

[0105] It can be understood that in the process of observing the surface texture structure of the semiconductor substrate 1, if the observed area is too small, the size of the first texture structure, the second texture structure or the third area 1e cannot be accurately obtained by observing only the base area of ​​the texture structure. Therefore, the observed area should contain at least one texture structure. Preferably, the observed area should be greater than or equal to 5*5μm. 2 To prevent the inability to accurately obtain the precise average size of the texture structure by only observing the base area of ​​the texture structure. The one-dimensional size includes the height and side length of the texture structure.

[0106] like Figure 6As shown, the solar cell also includes a passivation anti-reflection layer, and the passivation anti-reflection layer covers the first region 1a and the third region 1e, and the passivation anti-reflection layer does not cover the second region 1b. There is also a second doped semiconductor layer 8 between the third region 1e and the passivation anti-reflection layer, that is, in the third region 1e, the second doped semiconductor layer 8 is located between the passivation anti-reflection layer and the surface of the semiconductor substrate 1. Since the current of the solar cell is collected at both ends, the edge of the cell needs to be passivated to reduce recombination; secondly, the side of the cell is easily invaded by water vapor, causing the cell to fail. In view of the above two situations, in this embodiment, the first region 1a and the third region 1e are covered by the passivation anti-reflection layer, and the first region 1a is close to the first surface of the solar cell. When the first surface is the light-facing surface, the passivation effect is better, and it has a hydrogen passivation effect, thereby reducing the risk of recombination and leakage. The passivation anti-reflection layer can protect the first region 1a and the third region 1e, isolate the invasion of water vapor, and extend the service life of the battery.

[0107] like Figure 4 As shown, when the solar cell does not include the third region 1e, the solar cell also includes a passivation anti-reflection layer, and the passivation anti-reflection layer covers the first region 1a, and the passivation anti-reflection layer does not cover the second region 1b. In this way, the passivation effect is better, and it has a hydrogen passivation effect, thereby reducing the risk of recombination and leakage. The passivation anti-reflection layer can at least protect the first region 1a, isolate the invasion of water vapor, and extend the service life of the battery.

[0108] In the above two technical solutions, the solar cell further includes a first doped semiconductor layer 3, which covers the second region 1b and at least partially covers the passivation anti-reflection layer located on the side. That is, the first doped semiconductor layer 3 extends to the side of the passivation anti-reflection layer away from the semiconductor substrate 1. Such an arrangement increases the area of ​​the first doped semiconductor layer 3 for collecting carriers, thereby improving the power generation efficiency.

[0109] In terms of material, the material of the first doped semiconductor layer 3 can be set according to the actual application scenario. Exemplarily, the material of the first doped semiconductor layer 3 can be an amorphous silicon layer or a microcrystalline silicon. When the first doped semiconductor layer is amorphous silicon or microcrystalline silicon, the passivation effect on the side edge is good, further reducing recombination. Of course, the embodiment of the present application does not specifically limit the material of the first doped semiconductor layer 3. The second doped semiconductor layer 8 can be polycrystalline silicon, which has higher carrier transport characteristics. Therefore, when the second doped semiconductor layer 8 is a polycrystalline silicon layer, the carrier transport efficiency is higher, which is beneficial to improve the photoelectric conversion efficiency of the solar cell.

[0110] In terms of conductivity type, the first doped semiconductor layer 3 and the second doped semiconductor layer 8 have opposite doping types, so as to collect and extract electrons and holes respectively, which is conducive to the formation of photocurrent. The conductivity type of the first doped semiconductor layer 3 and the semiconductor substrate 1 can be opposite. In addition, the first doped semiconductor layer 3 can be an n-type doped layer, and the second doped semiconductor layer 8 can be a p-type doped layer; or, the first doped semiconductor layer 3 can be a p-type doped layer, and the second doped semiconductor layer 8 can be an n-type doped layer.

[0111] In the above embodiment, the first doped semiconductor layer 3 is also arranged on the second surface, and the first doped semiconductor layer extends from the second surface to the second region 1b. In this technical solution, the second surface and the second region 1b of the side surface both cover the first doped semiconductor layer 3, and the first doped semiconductor layer 3 extends continuously from the second surface to the second region 1b without interruption. In this way, not only the area of ​​the first doped semiconductor layer 3 is increased, and thus the efficiency of the first doped semiconductor layer 3 in collecting carriers is increased, but also the first doped semiconductor layer on the second surface and the side surface can be processed and formed in the same step, which simplifies the processing technology and improves production efficiency.

[0112] In some embodiments, the passivation anti-reflection layer is also disposed on the first surface, and the passivation anti-reflection layer extends from the first surface to the first region 1a. Specifically, the passivation anti-reflection layer on the first surface and the passivation anti-reflection layer in the first region 1a are disposed in an integrated and continuous manner, which further improves the passivation effect of the first surface and reduces the recombination of the first surface; at the same time, the passivation anti-reflection layer on the first surface and the side surface can be processed and formed in the same step, which simplifies the processing technology and improves production efficiency.

[0113] In the above technical solution, the solar cell further includes a second doped semiconductor layer 8 located between the first surface and the passivation anti-reflection layer. Specifically, on the first surface, the second doped semiconductor layer 8 is located between the passivation anti-reflection layer and the semiconductor substrate 1, and the second doped semiconductor layer 8 located on the first surface and the second doped semiconductor layer 8 located on the side are intermittently arranged. In this way, the second doped semiconductor layer 8 located on the first surface can collect carriers, thereby improving the power generation efficiency of the entire solar cell.

[0114] Furthermore, the solar cell also includes an interface layer 9 between the first surface and the second doped semiconductor layer 8. The interface layer 9 is located on the side of the second doped semiconductor layer 8 close to the semiconductor substrate 1. In this way, the interface layer can further enhance the passivation effect of the semiconductor substrate, and form a passivation contact structure in combination with the second doped semiconductor layer, which is more conducive to the collection of carriers. In addition, the interface layer 9 on the first surface and the second doped semiconductor layer 8 are distributed in a finger shape, so that the interface layer 9 on the first surface and the second doped semiconductor layer 8 form a Poly-finger structure to reduce the parasitic absorption of the second doped semiconductor layer and improve the Jsc of the battery.

[0115] like Figure 6 As shown, when the side also includes the third region 1e, the third region 1e is located between the first region 1a and the first surface, and the third region 1e has a third texture structure. In this embodiment, the passivation anti-reflection layer covers both the first region 1a and the third region 1e. In the solar cell, there is also an interface layer 9 between the third region 1e and the second doped semiconductor layer 8, and the stacked interface layer 9 and the second doped semiconductor layer 8 are located between the passivation anti-reflection layer and the semiconductor substrate 1, and the interface layer 9 is located on the side of the second doped semiconductor layer 8 close to the semiconductor substrate 1. That is to say, in the third region 1e, the interface layer 9, the second doped semiconductor layer 8, and the passivation anti-reflection layer are stacked in sequence along the direction away from the semiconductor substrate 1. In this way, the passivation effect in the third region 1e is better, and the interface layer 9 and the second doped semiconductor layer 8 will also collect carriers when receiving light, thereby improving the carrier collection efficiency and the photoelectric conversion efficiency. Among them, the interface layer 9 may include silicon oxide.

[0116] In other embodiments, the solar cell further comprises an intrinsic amorphous silicon layer 2 located under the first doped semiconductor layer 3, the intrinsic amorphous silicon layer 2 covers the second region 1b, and at least partially covers the passivation anti-reflection layer located on the side. Wherein, in the first region 1a, the intrinsic amorphous silicon layer 2 covers at least part of the side of the passivation anti-reflection layer away from the semiconductor substrate 1 and is in direct contact with the passivation anti-reflection layer. That is, in the first region 1a, the passivation anti-reflection layer, the intrinsic amorphous silicon layer 2 and the first doped semiconductor layer 3 are sequentially stacked in a direction away from the semiconductor substrate 1. No other film layer is arranged between the passivation anti-reflection layer and the intrinsic amorphous silicon layer 2, and they are in direct contact.

[0117] In the second region 1b, the intrinsic amorphous silicon layer 2 is in direct contact with the surface of the semiconductor substrate 1, and no other film layer is disposed between the intrinsic amorphous silicon layer 2 and the semiconductor substrate 1. The intrinsic amorphous silicon layer 2 has a good passivation effect and can further reduce lateral recombination.

[0118] In some embodiments, in the first region 1a, the passivation anti-reflection layer is in direct contact with the surface of the semiconductor substrate 1, that is, there is no other film layer between the passivation anti-reflection layer and the semiconductor substrate 1, but they are in direct contact and stacked together, which further improves the passivation effect on the first region 1a.

[0119] Wherein, the passivation anti-reflection layer can be a single-layer structure or a laminated structure of at least two layers. Wherein, the laminated structure includes a passivation layer and an anti-reflection layer arranged in sequence along a direction away from the side, and the passivation layer 7 is located between the anti-reflection layer 6 and the semiconductor substrate 1. As for the material of the passivation layer 7 and the anti-reflection layer 6, the material of the passivation layer 7 can include at least one of SiOx (x can be any value), POx (x can be any value), AlOx (x can be any value) and PSG (phospho silicate Glass) or a composite film stacked therefrom. The material of the anti-reflection layer 6 includes at least one of SiNx (x can be any value), SiCx (x can be any value) and TiOx (x can be any value) or a composite film stacked therefrom. The above-mentioned various materials have low costs and are suitable for use in the passivation layer 7 and the anti-reflection layer 6.

[0120] As for the thickness of the passivation layer 7 and the anti-reflection layer 6, the thickness of the passivation layer 7 and the anti-reflection layer 6 can be set according to the actual application scenario of the solar cell. Exemplarily, the thickness of the passivation layer 7 is 3nm to 10nm, for example, it can be 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm or 10nm. The thickness of the anti-reflection layer 6 is 50nm to 120nm, for example, it can be 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm or 120nm.

[0121] In other embodiments, in the process of preparing solar cells, in the process of forming the intrinsic amorphous silicon layer 2 and / or the first doped semiconductor layer 3 by deposition, the farther away from the material evaporation mechanism, the smaller the thickness of the formed intrinsic amorphous silicon layer 2 and / or the first doped semiconductor layer 3, so along the direction from the first surface to the second surface, the thickness of the intrinsic amorphous silicon layer 2 and the first doped semiconductor layer 3 on the side surface gradually decreases. This is beneficial to improving the protective effect of the film layer on the side surface close to the second surface. Similarly, in the process of forming the passivation anti-reflection layer by deposition, the farther away from the material evaporation mechanism, the smaller the thickness of the formed passivation anti-reflection layer, so along the direction from the first surface to the second surface, the thickness of the passivation anti-reflection layer on the side surface gradually decreases, which is beneficial to improving the insulating protective effect of the passivation anti-reflection layer on the side surface close to the first surface, and further improving the reliability of the battery side structure.

[0122] The passivation anti-reflection layer is at least located in the first region 1a, that is, the stacked passivation layer 7 and the anti-reflection layer 6 at least cover the first region 1a. The intrinsic amorphous silicon layer 2 and the first doped semiconductor layer 3 are stacked and at least located in the first region 1a and the second region 1b, that is, the stacked intrinsic amorphous silicon layer 2 and the first doped semiconductor layer 3 cover the first region 1a and the second region 1b, and the intrinsic amorphous silicon layer 2 is located on the side of the first doped semiconductor layer 3 close to the semiconductor substrate 1.

[0123] In addition, the intrinsic amorphous silicon layer 2 and the first doped semiconductor layer 3 are stacked and located at least in the first region 1a and the second region 1b. The intrinsic amorphous silicon layer 2 has a good passivation effect, which can further reduce recombination. The stacked intrinsic amorphous silicon layer 2 and the passivation anti-reflection layer also help to improve the overall passivation effect, reduce carrier recombination on the side of the semiconductor substrate, and play a role in waterproofing.

[0124] In another embodiment, in the direction perpendicular to the thickness direction of the semiconductor substrate 1, at least one area (at least the first area 1a) on its side is stacked with a passivation anti-reflection layer, an intrinsic amorphous silicon layer 2, and a first doped semiconductor layer 3 in sequence; in the direction close to the first surface, a passivation anti-reflection layer is stacked in part of the side area; in the direction close to the second surface, a part of the surface of the semiconductor substrate 1 is in direct contact with the intrinsic amorphous silicon layer 2. A composite film layer of a passivation anti-reflection layer, an intrinsic amorphous silicon layer 2, and a first doped semiconductor layer 3 is sequentially arranged in at least one area of ​​the side surface, which helps to improve the passivation effect of the overall side surface and prevent external water vapor from entering the battery from the side surface to affect the battery efficiency; a passivation anti-reflection layer is stacked in a partial area close to the first surface, which can effectively reduce light reflection and increase light absorption when the first surface is a light-facing surface, thereby ensuring the utilization of front light; a partial semiconductor substrate 1 surface close to the second surface is in direct contact with the intrinsic amorphous silicon layer 2, so that the edge passivation effect of the semiconductor substrate 1 is better, which is conducive to reducing the recombination of carriers. Combined with the first doped semiconductor layer 3 arranged above the intrinsic amorphous silicon layer 2, it can further improve the collection of carriers, thereby improving the battery efficiency. The different settings of the film layers close to the first surface and the second surface not only maximize the utilization of front light, but also ensure the passivation effect of the back edge.

[0125] In addition, the first region 1a has a first texture structure 1c, which has a light trapping effect. The surface of the first texture structure 1c is covered with an anti-reflection layer 6, which can further improve the light absorption utilization rate, thereby improving the photoelectric conversion efficiency. The second region 1b has a second texture structure 1d, which increases the surface area of ​​the second texture structure 1d, and is more conducive to the uniform deposition of the intrinsic amorphous silicon layer 2 in the second region 1b, thereby facilitating the passivation effect in the second region 1b.

[0126] In addition, along the thickness direction of the semiconductor substrate 1, the extension distance of the passivation anti-reflection layer on the side accounts for a proportion of greater than or equal to 50% of the overall extension distance of the side. If the extension distance of the passivation anti-reflection layer along the thickness direction of the semiconductor substrate 1 is too small, the passivation effect and light absorption utilization rate of the side of the solar cell will be reduced. Therefore, in this embodiment, the extension distance of the passivation anti-reflection layer on the side accounts for a proportion of greater than or equal to 50% of the overall extension distance of the side, so as to ensure the passivation effect and light absorption utilization rate of the side of the solar cell.

[0127] Exemplarily, the extension distance of the passivation anti-reflection layer on the side accounts for 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90% or 95% of the overall extension distance of the side. Optionally, the extension distance of the passivation anti-reflection layer on the side accounts for 50% to 95% of the overall extension distance of the side.

[0128] In some embodiments, a portion of the passivation anti-reflection layer is in direct contact with the surface of the semiconductor substrate 1, and another portion of the passivation anti-reflection layer and the semiconductor substrate 1 further have a stacked interface layer 9 and a second doped semiconductor layer 8, and the interface layer 9 is located on the side of the second doped semiconductor layer 8 close to the semiconductor substrate 1. In this embodiment, the side of the solar cell may also include a third region 1e, and the third region 1e is located between the first region 1a and the first surface. In the third region 1e, there is a stacked interface layer 9 and a second doped semiconductor layer 8 between the passivation anti-reflection layer and the semiconductor substrate 1; in the first region 1a, the passivation anti-reflection layer is in direct contact with the surface of the semiconductor substrate 1, and the passivation anti-reflection layer is continuously and uninterruptedly arranged from the first region 1a to the third region 1e. With such an arrangement, it can be understood that the closer to the surface of the semiconductor substrate 1, the greater the impact on the current. Since the passivation effect of the stacked interface layer 9 and the second doped semiconductor layer 8 is better than that of the stacked passivation anti-reflection layer, the interface layer 9 and the second doped semiconductor layer 8 are arranged closer to the first surface of the semiconductor substrate 1, thereby improving the passivation effect of the position closer to the first surface of the semiconductor substrate 1. In addition, the stacked interface layer 9 and the second doped semiconductor layer 8 located on the side can collect carriers, thereby improving the power generation efficiency of the entire solar cell.

[0129] In the above technical solution, along the thickness direction of the semiconductor substrate 1, the ratio of the extension distance of the interface layer 9 and the second doped semiconductor layer 8 on the side to the overall extension distance of the side is greater than or equal to 5%, so as to balance the passivation effect and light absorption rate of the side, and prevent the parasitic absorption of the second doped semiconductor layer 8 from being too high and affecting the light absorption efficiency.

[0130] Exemplarily, along the thickness direction of the semiconductor substrate 1, the ratio of the extension distance of the interface layer 9 and the second doped semiconductor layer 8 on the side to the overall extension distance of the side is 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55% or 60%. Optionally, along the thickness direction of the semiconductor substrate 1, the ratio of the extension distance of the interface layer 9 and the second doped semiconductor layer 8 on the side to the overall extension distance of the side is 5% to 50%.

[0131] It should be noted that the solar cell can be a bifacial cell or a back contact cell. In the case where the solar cell can be a bifacial cell, an interface layer 9 and a second doped semiconductor layer 8 are stacked on the first surface, and an intrinsic amorphous silicon layer 2 and a first doped semiconductor layer 3 are stacked on the second surface. Specifically, the solar cell can be a bifacial hybrid cell, the semiconductor substrate 1 can be an N-type substrate, the first doped semiconductor layer 3 can be a P-type doped semiconductor layer, for example, a P-type doped amorphous silicon layer; the second doped semiconductor layer 8 can be an N-type doped semiconductor layer, for example, an N-type doped polycrystalline silicon layer.

[0132] In the case where the solar cell may be a back contact cell, the interface layer 9 and the second doped semiconductor layer 8 stacked together, and the intrinsic amorphous silicon layer 2 and the first doped semiconductor layer 3 stacked together may be arranged on the first surface or the second surface.

[0133] In some embodiments, an interface layer 9 and a second doped semiconductor layer 8 are stacked on the first surface. In this case, the passivation contact structure composed of the interface layer 9 and the second doped semiconductor layer 8 has an excellent interface passivation effect, and can realize the selective collection of carriers, reduce the carrier recombination rate in the area where the first doped semiconductor layer 3 is formed on the first surface of the semiconductor substrate 1, and further improve the photoelectric conversion efficiency of the solar cell. The interface layer 9 is located on the side of the second doped semiconductor layer 8 close to the semiconductor substrate 1. The interface layer 9 and the second doped semiconductor layer 8 located on the side are intermittently arranged with the interface layer 9 and the second doped semiconductor layer 8 located on the first surface. That is, the interface layer 9 and the second doped semiconductor layer 8 on the first surface and the interface layer 9 and the second doped semiconductor layer 8 on the side are not continuous with each other, but are intermittently arranged, so that the interface layer 9 and the second doped semiconductor layer 8 on the first surface and the side surface can be formed separately without affecting each other.

[0134] As for the materials of the interface layer 9 and the second doped semiconductor layer 8, the materials of the interface layer 9 and the second doped semiconductor layer 8 can be set according to the actual application scenario. For example, when the material of the second doped semiconductor layer 8 is a doped polysilicon layer, the interface layer 9 is a tunneling oxide layer. Of course, the embodiment of the present application does not specifically limit the materials of the interface layer 9 and the second doped semiconductor layer 8.

[0135] As for the thickness of the interface layer 9 and the second doped semiconductor layer 8, the thickness of the interface layer 9 will affect its own transmission resistance and passivation effect, so the thickness of the interface layer 9 and the second doped semiconductor layer 8 can be set according to the actual application scenario. Exemplarily, the thickness of the interface layer 9 is 1nm to 2nm, for example, it can be 1nm, 1.1nm, 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm or 2nm. The thickness of the second doped semiconductor layer 8 is 50nm to 180nm, for example, it can be 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm or 180nm. In this technical solution, the appropriate film thickness can ensure the passivation effect, and the stacked interface layer 9 and the second doped semiconductor layer 8 can prevent the invasion of water vapor.

[0136] In other embodiments, when the solar cell is a bifacial cell, an intrinsic amorphous silicon layer 2 and a first doped semiconductor layer 3 are stacked on the second surface, and the intrinsic amorphous silicon layer 2 is located on the side of the first doped semiconductor layer 3 close to the semiconductor substrate 1. In this case, the passivation contact structure composed of the intrinsic amorphous silicon layer 2 and the first doped semiconductor layer 3 can realize the selective collection of carriers and reduce the carrier recombination rate in the region where the first doped semiconductor layer 3 is formed on the second surface of the semiconductor substrate 1. The intrinsic amorphous silicon layer 2 and the first doped semiconductor layer 3 located on the side are continuously extended as a whole with the intrinsic amorphous silicon layer 2 and the first doped semiconductor layer 3 located on the second surface, that is, the intrinsic amorphous silicon layer 2 and the first doped semiconductor layer 3 on the second surface and the intrinsic amorphous silicon layer 2 and the first doped semiconductor layer 3 on the side are an integral continuous structure, so that they can be formed in the same step, simplifying the processing steps and improving the processing technology.

[0137] As for the thickness of the intrinsic amorphous silicon layer 2 and the first doped semiconductor layer 3, the thickness of the intrinsic amorphous silicon layer 2 will affect its own transmission resistance and passivation effect, so the thickness of the intrinsic amorphous silicon layer 2 and the first doped semiconductor layer 3 can be set according to the actual application scenario. Exemplarily, the thickness of the intrinsic amorphous silicon layer 2 is 3nm to 20nm, for example, it can be 3nm, 5nm, 8nm, 10nm, 12nm, 15nm, 18nm or 20nm. The thickness of the first doped semiconductor layer 3 is 8nm to 45nm, for example, it can be 8nm, 10nm, 12nm, 15nm, 18nm, 20nm, 22nm, 25nm, 28nm, 30nm, 32nm, 35nm, 38nm, 40nm, 42nm or 45nm.

[0138] See also Figure 7-Figure 15 As shown, a method for manufacturing a solar cell is provided below, comprising the steps of:

[0139] S100: providing a semiconductor substrate 1, and performing texturing or polishing on the semiconductor substrate 1.

[0140] The resistivity of the semiconductor substrate 1 may be 0.1-10Ω.cm, and the thickness may be 50-200μm. Figure 7 As shown, texturing or polishing can be performed using an alkali solution and a mixture of a texturing additive or a polishing additive to form a third texture structure on the first surface, the second surface and the side surface of the semiconductor substrate 1 .

[0141] S200: forming an interface layer 9 and a second doped semiconductor layer 8 on the surface of the semiconductor substrate 1;

[0142] Next, if Figure 8 As shown, the interface layer 9 and the second doped semiconductor layer 8 can be formed by LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PVD (Physical Vapor Deposition), PEALD (Plasma Enhanced Atomic Layer Deposition), etc. In this step, a PSG layer 11 is formed on the surface.

[0143] S300: performing patterning on the PSG layer 11 on the first surface;

[0144] Next, if Fig. 9 As shown, a laser process can be used to remove the PSG layer 11 in a local area on the first surface. Specifically, the laser spot used can be circular, with a spot diameter of 50 μm to 150 μm, a laser power of 1 w to 1000 w, a laser wavelength of 100 nm to 1200 nm, a pulse width of 1 ps to 500 ns, a laser frequency of 100 kHz to 100 MHz, and a laser scanning speed of 5 m / s to 70 m / s.

[0145] S400: removing the PSG layer 11 on the second surface and the side surface;

[0146] Next, if Fig.10 As shown, this step can remove all the PSG layer 11 on the second surface and the side surface. Specifically, in this step, the etching liquid can be brought into contact with the PSG layer 11 on the second surface and the side surface by floating on water or rolling with liquid, so as to remove the PSG layer 11 on the second surface and the side surface. The etching liquid can be HF solution.

[0147] S500: removing the interface layer 9 and the second doped semiconductor layer 8 not covered by the PSG layer 11, and performing texturing, and then removing the remaining PSG layer 11 on the first surface;

[0148] Next, if Fig.11 As shown, in this step, the interface layer 9 and the second doped semiconductor layer 8 on the side and second surface are removed by texturing or wet etching, and the interface layer 9 and the second doped semiconductor layer 8 on the first surface not covered by the PSG layer 11 are removed; as the etching time increases, after the film layer is removed, a first texture structure 1c is formed on the side and second surface of the semiconductor substrate 1, as well as the area on the first surface not covered by the PSG layer 11. The first texture structure 1c on the first surface forms a height difference of 2-9 microns with the third texture structure in the area covered by the PSG layer 11. Then, the remaining PSG layer 11 on the first surface is removed by wet etching.

[0149] S600: forming a passivation anti-reflection layer at least on the first surface and the side surface;

[0150] Next, if Fig.12 As shown, a passivation layer 7 may be deposited on the surface first, and then an anti-reflection layer 6 may be formed. As for the material and thickness of the passivation layer 7 and the anti-reflection layer 6, reference may be made to the above contents, and no further description is given here.

[0151] S700: forming a through hole 12 in the area where the passivation anti-reflection layer and the interface layer 9 are stacked;

[0152] Next, if Fig.13 As shown, a laser process can be used to form a through hole 12 in the area where the passivation anti-reflection layer and the interface layer 9 overlap, and the through hole 12 is used to form an electrode. The laser used can be one of green nanosecond, green picosecond, ultraviolet nanosecond or ultraviolet picosecond lasers.

[0153] S800: removing the second side region 1b and the passivation anti-reflection layer on the second surface;

[0154] Next, if Fig.14 As shown, in this step, the passivation anti-reflection layer on the second area 1b of the side and the second surface can be removed by wet etching. At the same time, the morphology of the second area 1b and the second surface is modified by etching liquid to form a second texture structure 1d on the second area 1b of the side and the second surface. S900: At least an intrinsic amorphous silicon layer 2 and a first doped semiconductor layer 3 are sequentially formed on the side and the second surface;

[0155] Next, if Fig.15As shown, in this step, the intrinsic amorphous silicon layer 2 and the first doped semiconductor layer 3 can be formed by magnetron sputtering, reactive plasma deposition, vacuum evaporation, etc. Wherein, in the first region 1a, the intrinsic amorphous silicon layer 2 covers the side of the passivation anti-reflection layer away from the semiconductor substrate 1 and is in direct contact with the passivation anti-reflection layer. That is, in the first region 1a, the passivation anti-reflection layer, the intrinsic amorphous silicon layer 2 and the first doped semiconductor layer 3 are stacked in sequence along the direction away from the semiconductor substrate 1. No other film layer is set between the passivation anti-reflection layer and the intrinsic amorphous silicon layer 2 and they are in direct contact.

[0156] In some embodiments, the intrinsic amorphous silicon layer 2 and the first doped semiconductor layer 3 formed in this step may extend to the edge region of the first surface. In addition, this step may also form a transparent conductive layer 4 on the side of the first doped semiconductor layer 3 away from the intrinsic amorphous silicon layer 2, and the transparent conductive layer 4 has a high conductivity, which can timely guide the collected carriers and reduce the carrier recombination rate.

[0157] Next, the first electrode 5 is formed on the transparent conductive layer 4, and the second electrode 10 is formed in the through hole 12 of the first surface. Specifically, the first electrode 5 and the second electrode 10 can be formed by combining one or more methods of screen printing, laser transfer printing, plating, and evaporation. The first electrode 5 and the second electrode 10 can be made of silver, copper, aluminum, and alloys thereof. The first electrode 5 and the second electrode 10 can be the same or different.

[0158] In addition, the embodiment of the present application further provides a photovoltaic module, which includes the solar cell provided by any of the above embodiments. Compared with the prior art, the beneficial effects of the photovoltaic module provided by the embodiment of the present application are the same as the beneficial effects of the above solar cell, which will not be repeated here.

[0159] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0160] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other, and a side surface connecting the first surface and the second surface; Along the direction from the first surface to the second surface, the side surface includes a first area and a second area arranged in sequence, the first area has a first texture structure, and the second area has a second texture structure.

2. The solar cell according to claim 1, characterized in that The first surface has the first texture structure, and the first texture structure of the first region is arranged continuously with the first texture structure of the first surface; and / or, The second surface has the second texture structure, and the second texture structure of the second region is continuously arranged with the second texture structure of the second surface.

3. The solar cell according to claim 1, characterized in that The first texture structure and the second texture structure are both non-polished surfaces; and / or, The first texture structure comprises a suede structure; and / or, The second texture structure includes a pyramid-like velvet structure, and at least a portion of the side edges of the pyramid-like structure are curved.

4. The solar cell according to claim 3, characterized in that: The first texture structure is a first pyramid velvet structure; the height of the first pyramid is 1 μm to 5 μm, and the side length of the base of the first pyramid is 1 μm to 3 μm.

5. The solar cell according to claim 3, characterized in that: The second texture structure comprises a pyramid-like velvet structure, and at least a part of the side edges of the pyramid-like structure is a curve; The height of the quasi-pyramid is 0.1 μm to 5 μm, and the side length of the base of the quasi-pyramid is 1 μm to 3 μm; and / or, the side edges of the quasi-pyramid are inwardly concave curves; and / or, at least the bottom of the side edges of the quasi-pyramid is a curve, and the curvature radius of the bottom of the side edges of the quasi-pyramid is 0.1 μm to 10 μm; and / or, each of the quasi-pyramids includes 3 to 6 side edges.

6. The solar cell according to claim 1, characterized in that Along the thickness direction of the semiconductor substrate, the ratio of the extension distance of the first region to the entire extension distance of the side surface is greater than or equal to 50%; and / or, Along the direction of the semiconductor thickness, a ratio of an extension distance of the second region to an extension distance of the entire side surface is less than or equal to 50%.

7. The solar cell according to claim 1, characterized in that The average height of the first texture structure is greater than the average height of the second texture structure; and / or, The first texture structure and the second texture structure have a height difference along a direction perpendicular to the side surface, and the height difference ranges from greater than 0 μm to less than or equal to 3 μm; and / or, The reflectivity of the first texture structure is lower than the reflectivity of the second texture structure.

8. The solar cell according to any one of claims 1 to 7, characterized in that: The first surface is a light-receiving surface, and the second surface is a backlight surface.

9. The solar cell according to claim 1, characterized in that: The side surface further includes a third area, the third area is located between the first area and the first surface, and the third area has a third texture structure; The reflectivity of the third texture structure is greater than the reflectivity of the first texture structure.

10. The solar cell according to claim 9, characterized in that: The third texture structure includes a velvet structure or a polished surface or a flattened tower base structure; and / or, The first surface has the first texture structure, and the third texture structure of the third region is continuously arranged with the first texture structure of the first surface; and / or, The third texture structure has the same shape as the first texture structure, and the average one-dimensional size of the third texture structure is smaller than the average one-dimensional size of the first texture structure; and / or, Along the direction of the semiconductor thickness, a ratio of the extension distance of the third region to the entire extension distance of the side surface is greater than or equal to 5%.

11. The solar cell according to claim 9, characterized in that: It also includes a passivation anti-reflection layer, which covers the first region and the third region, but does not cover the second region; and a second doped semiconductor layer is provided between the third region and the passivation anti-reflection layer.

12. The solar cell according to claim 1, characterized in that The invention also includes a passivation anti-reflection layer, wherein the passivation anti-reflection layer covers the first region, and the passivation anti-reflection layer does not cover the second region.

13. The solar cell according to claim 11 or 12, characterized in that: The invention also includes a first doped semiconductor layer, wherein the first doped semiconductor layer covers the second region and at least partially covers the passivation anti-reflection layer located on the side.

14. The solar cell according to claim 13, characterized in that: The first doped semiconductor layer is amorphous silicon or microcrystalline silicon, and the second doped semiconductor layer is polycrystalline silicon; the first doped semiconductor layer and the second doped semiconductor layer have opposite doping types.

15. The solar cell according to claim 13, characterized in that: The first doped semiconductor layer is also disposed on the second surface, and the first doped semiconductor layer extends from the second surface to the second region.

16. The solar cell according to claim 11 or 12, characterized in that: The passivation anti-reflection layer is also disposed on the first surface, and the passivation anti-reflection layer extends from the first surface to the first region.

17. The solar cell according to claim 16, characterized in that: The invention also includes a second doped semiconductor layer located between the first surface and the passivation anti-reflection layer.

18. The solar cell according to claim 17, characterized in that: It also includes an interface layer between the first surface and the second doped semiconductor layer; the interface layer on the first surface and the second doped semiconductor layer are distributed in a finger shape.

19. The solar cell according to claim 11, characterized in that: An interface layer is also provided between the third region and the second doped semiconductor layer, and the interface layer is silicon oxide.

20. The solar cell according to claim 13, characterized in that The invention also includes an intrinsic amorphous silicon layer located under the first doped semiconductor layer, covering the second region and at least partially covering the passivation anti-reflection layer located on the side.

21. The solar cell according to claim 20, characterized in that In the second region, the intrinsic amorphous silicon layer is in direct contact with a surface of the semiconductor substrate.

22. The solar cell according to claim 13, characterized in that Along the direction from the second surface to the first surface, the thickness of the first doped semiconductor layer on the side surface gradually decreases.

23. The solar cell according to claim 11 or 12, characterized in that: The passivation anti-reflection layer is in direct contact with the first region on the side surface of the semiconductor substrate.

24. The solar cell according to claim 11 or 12, characterized in that: The passivation anti-reflection layer is a single layer or a stacked structure of at least two layers, and the stacked structure includes a passivation layer and an anti-reflection layer arranged in sequence along a direction away from the side surface.

25. The solar cell according to claim 11 or 12, characterized in that: Along the direction from the first surface to the second surface, the thickness of the passivation anti-reflection layer on the side surface gradually decreases.

26. A photovoltaic module, characterized in that: A solar cell as claimed in any one of claims 1 to 25.

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