Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a plurality of circuit units, a first power supply connection line (68), a second power supply connection line (69), a first power supply line (51) and a second power supply line (52), the circuit unit comprises a pixel driving circuit, the first power supply line (51) is connected with the pixel driving circuit, the first power supply line (51) is connected with the first power supply connection line (68), and the second power supply line (52) is connected with the second power supply connection line (69); the pixel driving circuit comprises a first shielding electrode and at least one double-gate structure transistor, the orthographic projection of the first shielding electrode on a base at least partially overlaps with the orthographic projection of a node between two gate electrodes of the double-gate structure transistor on the base; and the first shielding electrode is connected with the first power supply connection line (68) or the second power supply connection line (69).

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, this disclosure provides a display substrate, the display substrate including a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on the driving circuit layer away from the substrate. The driving circuit layer includes at least a plurality of circuit units, at least one first power connection line and at least one second power connection line extending along a first direction, at least one first power line and at least one second power line extending along a second direction, at least one circuit unit including a pixel driving circuit, the first power line being connected to the pixel driving circuit and configured to continuously provide a high-level signal to the pixel driving circuit, the light-emitting structure layer including at least a plurality of light-emitting units, at least one light-emitting unit including a cathode, the second power line being connected to the cathode and configured to continuously provide a low-level signal to the cathode; the first power line being connected to the first power connection line to form a mesh structure for transmitting a first power signal, the second power line being connected to the second power connection line to form a mesh structure for transmitting a second power signal, and the first direction intersecting the second direction.

[0005] The pixel driving circuit includes a first shielding electrode and at least one dual-gate transistor, wherein the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the dual-gate transistor on the substrate; the first shielding electrode is connected to the first power connection line; or, the first shielding electrode is connected to the second power connection line.

[0006] In some exemplary embodiments, the at least one dual-gate transistor includes a first initialization transistor and a compensation transistor. The first terminal of the first initialization transistor is connected to a first initial signal line, and the first terminal of the compensation transistor is connected to a second terminal of the first initialization transistor. The orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor on the substrate, and the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the compensation transistor on the substrate.

[0007] In some exemplary embodiments, the first shielding electrode and the second power connection line are an integral structure that is interconnected.

[0008] In some exemplary embodiments, the second power connection line is located on the side of the first power connection line closer to the first initialization transistor and the compensation transistor.

[0009] In some exemplary embodiments, the first shielding electrode includes at least a first sub-electrode and a second sub-electrode. A first end of the first sub-electrode is connected to the second power connection line, and a second end of the first sub-electrode extends toward the first power connection line. The orthographic projection of the second end of the first sub-electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor on the substrate. The first end of the second sub-electrode is connected to the second power connection line, and a second end of the second sub-electrode extends toward the first power connection line. The orthographic projection of the second end of the second sub-electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the compensation transistor on the substrate.

[0010] In some exemplary embodiments, the first shielding electrode and the first power connection line are an integral structure that are interconnected.

[0011] In some exemplary embodiments, the first power connection line is located on the side of the second power connection line closer to the first initialization transistor and the compensation transistor.

[0012] In some exemplary embodiments, the first shielding electrode includes at least a third sub-electrode and a fourth sub-electrode. A first end of the third sub-electrode is connected to the first power connection line, and a second end of the third sub-electrode extends toward the second power connection line. The orthographic projection of the second end of the third sub-electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor on the substrate. A first end of the fourth sub-electrode is connected to the first power connection line, and a second end of the fourth sub-electrode extends toward the second power connection line. The orthographic projection of the second end of the fourth sub-electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the compensation transistor on the substrate.

[0013] In some exemplary embodiments, the pixel driving circuit further includes a first storage capacitor and a second storage capacitor. The first storage capacitor includes at least a first electrode plate and a third electrode plate, and the orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the third electrode plate on the substrate. The second storage capacitor includes at least a second electrode plate and a fourth electrode plate, and the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate on the substrate. The second electrode plate is connected to the third electrode plate, the fourth electrode plate is connected to the first power connection line, and the first shielding electrode is connected to the fourth electrode plate.

[0014] In some exemplary embodiments, the first shielding electrode and the fourth electrode plate are an integral structure that is interconnected.

[0015] In some exemplary embodiments, the first shielding electrode includes a first extension segment and a first shielding segment; the first extension segment is a strip shape extending along the second direction, and the first shielding segment is a strip shape extending along the first direction; a first end of the first extension segment is connected to the fourth electrode plate, and a second end of the first extension segment is connected to the first shielding segment; the first shielding segment includes a first shielding end and a second shielding end, the orthographic projection of the first shielding end on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor in the circuit unit on the substrate, and the orthographic projection of the second shielding end on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the compensation transistor in the adjacent circuit unit on the substrate.

[0016] In some exemplary embodiments, the at least one dual-gate transistor further includes a data writing transistor and a first reference transistor, wherein the first terminal of the data writing transistor is connected to a data signal line, the first terminal of the first reference transistor is connected to a first reference signal line, and the second terminal of the data writing transistor is connected to the second terminal of the first reference transistor.

[0017] The pixel driving circuit further includes a second shielding electrode, which is disposed between the first electrode of the data writing transistor and the second electrode of the data writing transistor.

[0018] In some exemplary embodiments, the at least one dual-gate transistor further includes a data writing transistor and a first reference transistor, wherein the first terminal of the data writing transistor is connected to a data signal line, the first terminal of the first reference transistor is connected to a first reference signal line, and the second terminal of the data writing transistor is connected to the second terminal of the first reference transistor.

[0019] The pixel driving circuit further includes a third shielding electrode and a fourth shielding electrode. The orthographic projection of the third shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the data writing transistor on the substrate. The orthographic projection of the fourth shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first reference transistor on the substrate.

[0020] In some exemplary embodiments, the orthographic projection of the second power connection line on the substrate at least partially overlaps with the orthographic projection of the first initial signal line on the substrate.

[0021] In some exemplary embodiments, the driving circuit layer includes multiple conductive layers on a plane perpendicular to the display substrate; the first power line and the first power connection line are disposed in different conductive layers, and the first power line and the first power connection line are connected through vias; the second power line and the second power connection line are disposed in different conductive layers, and the second power line and the second power connection line are connected through vias.

[0022] In some exemplary embodiments, the first power connection line and the second power connection line are disposed on the same layer, and the first power line and the second power line are disposed on the same layer.

[0023] In some exemplary embodiments, the plurality of conductive layers includes at least a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed sequentially along a direction away from the substrate; the first power connection line and the second power connection line are disposed in the third conductive layer, and the first power line and the second power line are disposed in the fourth conductive layer.

[0024] In some exemplary embodiments, the driving circuit layer includes a plurality of conductive layers on a plane perpendicular to the display substrate; the plurality of conductive layers include at least a first conductive layer, a second conductive layer, and a third conductive layer disposed sequentially along a direction away from the substrate; the first shielding electrode is disposed in the second conductive layer, or the first shielding electrode is disposed in the third conductive layer.

[0025] In some exemplary embodiments, the pixel driving circuit further includes a first storage capacitor and a second storage capacitor. The first storage capacitor includes at least a first electrode plate and a third electrode plate, and the orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the third electrode plate on the substrate. The second storage capacitor includes at least a second electrode plate and a fourth electrode plate, and the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate on the substrate. The first electrode plate and the second electrode plate are disposed in the first conductive layer, and the third electrode plate and the fourth electrode plate are disposed in the second conductive layer.

[0026] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0027] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0028] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0029] Figure 1 This is a schematic diagram of the structure of a display device;

[0030] Figure 2 This is a schematic diagram of a planar structure of a display substrate;

[0031] Figure 3 This is a schematic diagram of a cross-sectional structure of a display substrate;

[0032] Figure 4 An equivalent circuit diagram of a pixel driving circuit is provided as an exemplary embodiment of this disclosure.

[0033] Figure 5 This is a schematic diagram of a planar structure of a display substrate, which is an exemplary embodiment of the present disclosure.

[0034] Figure 6 for Figure 5 Enlarged view of the first and second storage capacitor regions in the middle;

[0035] Figure 7This is a schematic diagram of a display substrate after a semiconductor layer pattern has been formed.

[0036] Figure 8A and Figure 8B This is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to the present disclosure;

[0037] Figure 9A and Figure 9B This is a schematic diagram of a display substrate after the formation of a second conductive layer pattern according to the present disclosure;

[0038] Figure 10 This is a schematic diagram of a display substrate after the formation of a fourth insulating layer pattern according to the present disclosure;

[0039] Figure 11A and Figure 11B This is a schematic diagram of a display substrate after the formation of a third conductive layer pattern according to the present disclosure;

[0040] Figure 12 This is a schematic diagram of a display substrate after the formation of a fifth insulating layer pattern according to the present disclosure;

[0041] Figure 13A and 13B This is a schematic diagram of a display substrate after the formation of a fourth conductive layer pattern according to the present disclosure;

[0042] Figure 14 This is a schematic diagram of another planar structure of a display substrate, as an exemplary embodiment of the present disclosure;

[0043] Figure 15 for Figure 14 Enlarged view of the first and second storage capacitor regions in the middle;

[0044] Figure 16A and Figure 16B This is a schematic diagram of another display substrate after the formation of the third conductive layer pattern according to the present disclosure;

[0045] Figure 17 This is a schematic diagram of another planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0046] Figure 18 for Figure 17 Enlarged view of the first and second storage capacitor regions in the middle;

[0047] Figure 19A and Figure 19B This is a schematic diagram of a display substrate after the formation of a third conductive layer pattern according to another embodiment of the present disclosure;

[0048] Figure 20 This is a schematic diagram of a display substrate after the formation of a fifth insulating layer pattern according to another embodiment of the present disclosure;

[0049] Figure 21Aand 21B This is a schematic diagram of a display substrate after the fourth conductive layer pattern has been formed.

[0050] Figure Labels

[0051] 10—First active connection; 11—First active layer; 12—Second active layer;

[0052] 13—Third active layer; 14—Fourth active layer; 15—Fifth active layer;

[0053] 16—Sixth active layer; 17—Seventh active layer; 18—Eighth active layer;

[0054] 19—Ninth active layer; 20—Second active interconnect; 21—First gate electrode;

[0055] 22—Second gate electrode; 24—Fourth gate electrode; 25—Fifth gate electrode;

[0056] 26—Sixth gate electrode; 29—Ninth gate electrode; 31—First light-emitting signal line;

[0057] 32—Second light-emitting signal line; 33—Repair line; 36—First shielding electrode;

[0058] 37—Second shielding electrode; 38—Third shielding electrode; 39—Fourth shielding electrode;

[0059] 41—First connecting electrode; 42—Second connecting electrode; 43—Third connecting electrode;

[0060] 44—Fourth connecting electrode; 45—Fifth connecting electrode; 46—Sixth connecting electrode;

[0061] 47—Seventh connecting electrode; 48—Eighth connecting electrode; 49—Ninth connecting electrode;

[0062] 50—Tenth connecting electrode; 51—First power supply line; 52—Second power supply line;

[0063] 53—Data signal line; 54—Reference signal connection line; 55—Anode connection electrode;

[0064] 61—First scan signal line; 62—Second scan signal line; 63—Third scan signal line;

[0065] 64—Fourth scan signal line; 65—Fifth scan signal line; 68—First power supply connection line;

[0066] 69—Second power supply connection wire; 71—First electrode plate; 72—Second electrode plate;

[0067] 73—Third plate; 74—Fourth plate; 75—First opening;

[0068] 76—Second opening; 81—First initial signal line; 82—Second initial signal line;

[0069] 91—First reference signal line; 92—Second reference signal line; 101—Substrate;

[0070] 102—Driver circuit layer; 103—Light-emitting structure layer; 104—Packaging structure layer. Detailed Implementation

[0071] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0072] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0073] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0074] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0075] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0076] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0077] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0078] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0079] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0080] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0081] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0082] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0083] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, clock signals, scan start signals, etc., of specifications suitable for the scan driver to the scan driver, and clock signals, transmit stop signals, etc., of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0084] Figure 2This is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a display area and a border area surrounding the display area. Figure 2 As shown, the display area of ​​the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include at least a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0085] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 can be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular manner, etc., which is not limited herein.

[0086] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0087] Figure 3 This is a cross-sectional structural diagram of a display substrate, illustrating the structure of three sub-pixels within the substrate. Figure 3 As shown, on a plane perpendicular to the display substrate, the display area of ​​the display substrate may include a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0088] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0089] In an exemplary embodiment, the driving circuit layer 102 may include multiple circuit units, each of which may include at least a pixel driving circuit. The pixel driving circuit may include multiple transistors and a storage capacitor. The light-emitting structure layer 103 may include multiple light-emitting units, each of which may include at least a light-emitting device. The light-emitting device may include an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and the cathode.

[0090] In an exemplary embodiment, the encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0091] In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0092] An exemplary embodiment of this disclosure provides a display substrate, which includes a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on the driving circuit layer on a side away from the substrate. The driving circuit layer includes at least a plurality of circuit units, at least one first power connection line and at least one second power connection line extending along a first direction, and at least one first power line and at least one second power line extending along a second direction. At least one circuit unit includes a pixel driving circuit. The first power line is connected to the pixel driving circuit and is configured to continuously provide a high-level signal to the pixel driving circuit. The light-emitting structure layer includes at least a plurality of light-emitting units, at least one light-emitting unit including a cathode. The second power line is connected to the cathode and is configured to continuously provide a low-level signal to the cathode. The first power line is connected to the first power connection line to form a mesh structure for transmitting a first power signal, and the second power line is connected to the second power connection line to form a mesh structure for transmitting a second power signal. The first direction and the second direction intersect.

[0093] The pixel driving circuit includes a first shielding electrode and at least one dual-gate transistor, wherein the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the dual-gate transistor on the substrate; the first shielding electrode is connected to the first power connection line; or, the first shielding electrode is connected to the second power connection line.

[0094] In an exemplary embodiment, the at least one dual-gate transistor includes a first initialization transistor and a compensation transistor. The first terminal of the first initialization transistor is connected to a first initial signal line, and the first terminal of the compensation transistor is connected to the second terminal of the first initialization transistor. The orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first initialization transistor on the substrate, and the orthographic projection of the first shielding electrode on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the compensation transistor on the substrate.

[0095] In an exemplary embodiment, the first shielding electrode and the first power connection line are an integral structure that are interconnected.

[0096] In an exemplary embodiment, the first shielding electrode and the second power connection line are an integral structure that are interconnected.

[0097] In an exemplary embodiment, the pixel driving circuit further includes a first storage capacitor and a second storage capacitor. The first storage capacitor includes at least a first electrode plate and a third electrode plate, and the orthographic projection of the first electrode plate on the substrate at least partially overlaps with the orthographic projection of the third electrode plate on the substrate. The second storage capacitor includes at least a second electrode plate and a fourth electrode plate, and the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate on the substrate. The second electrode plate is connected to the third electrode plate, the fourth electrode plate is connected to the first power connection line, and the first shielding electrode is connected to the fourth electrode plate.

[0098] In an exemplary embodiment, the first shielding electrode and the fourth electrode plate are an integral structure.

[0099] The display substrate of this disclosure will be illustrated by some exemplary embodiments below.

[0100] Figure 4 This is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, or 9T2C structure. Figure 4 As shown, the pixel driving circuit of the exemplary embodiment of this disclosure can be a 9T2C structure, which may include 9 transistors (first transistor T1 to ninth transistor T9) and 2 storage capacitors (first storage capacitor C1 and second storage capacitor C2). The pixel driving circuit is connected to 12 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, first light emission signal line EM1, second light emission signal line EM2, first initial signal line INIT1, second initial signal line INIT2, first reference signal line REF1, second reference signal line REF2, data signal line DATA and first power supply line VDD).

[0101] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 is connected to the second terminal of a first transistor, the first terminal of a second transistor T2, the gate electrode of a third transistor T3, and the first terminal of a first storage capacitor C1. The second node N2 is connected to the first terminal of a third transistor T3, the second terminal of an eighth transistor T8, and the second terminal of a fifth transistor T5. The third node N3 is connected to the second terminals of a second transistor T2, a third transistor T3, and a sixth transistor T6. The fourth node N4 is connected to the second terminals of a sixth transistor T6 and a seventh transistor T7. The fifth node N5 is connected to the second terminal of a fourth transistor T4, the second terminal of a ninth transistor T9, the second terminal of the first storage capacitor C1, and the second terminal of the second storage capacitor C2.

[0102] In an exemplary embodiment, the first terminal (lower plate) of the first storage capacitor C1 is connected to the first node N1, and the second terminal (upper plate) of the first storage capacitor C1 is connected to the fifth node N5. The first terminal (upper plate) of the second storage capacitor C2 is connected to the first power line VDD, and the second terminal (lower plate) of the second storage capacitor C2 is connected to the fifth node N5.

[0103] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the fourth scan signal line S4, the first terminal of the first transistor T1 is connected to the first initial signal line INIT1, and the second terminal of the first transistor is connected to the first node N1. When a conduction signal is applied to the fourth scan signal line S4, the first transistor T1 transmits the first initial voltage to the gate electrode of the third transistor T3 and the first terminal of the first storage capacitor C1, thereby releasing the charge accumulated in the first storage capacitor C1 and achieving initialization.

[0104] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the second scan signal line S2, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction signal is applied to the second scan signal line S2, the second transistor T2 connects the gate electrode of the third transistor T3 to the second electrode.

[0105] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first terminal of the first storage capacitor C1. The first terminal of the third transistor T3 is connected to the second node N2, and the second terminal of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor, and the magnitude of the driving current is determined by the potential difference between its gate electrode and its first terminal.

[0106] In an exemplary embodiment, the gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the fifth node N5. When a conduction signal is applied to the third scan signal line S3, the fourth transistor T4 causes the data voltage of the data signal line DATA to be input to the second terminal of the first storage capacitor C1 and the second terminal of the second storage capacitor C2.

[0107] In an exemplary embodiment, the gate electrode of the fifth transistor T5 is connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4. When a conduction signal is applied to the first light-emitting signal line EM1 and the second light-emitting signal line EM2, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting device EL to emit light.

[0108] In an exemplary embodiment, the gate electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4. When a conduction signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the second initial voltage to the first electrode of the light-emitting device EL, releasing the charge accumulated in the first electrode of the light-emitting device EL and achieving initialization.

[0109] In an exemplary embodiment, the gate electrode of the eighth transistor T8 is connected to the first scan signal line S1, the first electrode of the eighth transistor T8 is connected to the second reference signal line REF2, and the second electrode of the eighth transistor T8 is connected to the second node N2. When a conduction signal is applied to the first scan signal line S1, the eighth transistor T8 transmits the second reference signal to the second node N2.

[0110] In an exemplary embodiment, the gate electrode of the ninth transistor T9 is connected to the second scan signal line S2, the first electrode of the ninth transistor T9 is connected to the first reference signal line REF1, and the second electrode of the ninth transistor T9 is connected to the fifth node N5. When a conduction signal is applied to the second scan signal line S2, the ninth transistor T9 transmits the first reference signal to the fifth node N5.

[0111] In an exemplary embodiment of this disclosure, the first transistor T1 can be referred to as the first initialization transistor, the second transistor T2 can be referred to as the compensation transistor, the third transistor T3 can be referred to as the driving transistor, the fourth transistor T4 can be referred to as the data writing transistor, the fifth transistor T5 can be referred to as the first light-emitting transistor, the sixth transistor T6 can be referred to as the second light-emitting transistor, the seventh transistor T7 can be referred to as the second initialization transistor, the eighth transistor T8 can be referred to as the second reference transistor, and the ninth transistor T9 can be referred to as the first reference transistor.

[0112] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode). The first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The signal of the second power line VSS is a continuously provided low-level signal, and the signal of the first power line VDD is a continuously provided high-level signal.

[0113] In an exemplary embodiment, the first transistor T1 to the ninth transistor T9 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the ninth transistor T9 may include both P-type and N-type transistors.

[0114] In an exemplary embodiment, the first transistor T1 to the ninth transistor T9 can be a low-temperature polysilicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS thin-film transistor is made of low-temperature polysilicon (LTPS), while the active layer of the oxide thin-film transistor is made of oxide. LTPS thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0115] In an exemplary embodiment, Figure 4 The operation of the pixel driving circuit shown can include stages one through five.

[0116] Phase 1. Phase 1 may include multiple sub-phases that are executed repeatedly, and each sub-phase may include a first sub-phase and a second sub-phase that are executed sequentially.

[0117] In the first sub-stage, the signals of the fourth scan signal line S4 and the first light-emitting signal line EM1 are on, while the signals of other signal lines are off. The on signal of the fourth scan signal line S4 enables the first transistor T1 to conduct, and the first initial signal of the first initial signal line INIT1 can be provided to the first node N1 to initialize it. When the third transistor T3 is a P-type transistor, it conducts. The on signal of the first light-emitting signal line EM1 enables the fifth transistor T5 to conduct, and the first power signal of the first power line VDD can be provided to the second node N2.

[0118] In the second sub-stage, the signals of the second scan signal line S2 and the first light-emitting signal line EM1 are on, while the signals of other signal lines are off. The on signal of the second scan signal line S2 enables the second transistor T2 to conduct, connecting the first node N1 and the third node N3, and the threshold voltage of the third transistor T3 is written to the first node N1. The on signal of the second scan signal line S2 also enables the ninth transistor T9 to conduct, and the first reference signal of the first reference signal line REF1 is provided to the fifth node N5 to initialize it. The on signal of the first light-emitting signal line EM1 enables the fifth transistor T5 to conduct, and the first power signal of the first power line VDD can be provided to the second node N2.

[0119] Second stage. The signal on the third scan signal line S3 is the on signal, while the signals on the other signal lines are the off signals. The on signal on the third scan signal line S3 enables the fourth transistor T4 to conduct, and the data voltage provided by the data signal line DATA is written to the fifth node N5.

[0120] Phase 3. The signal on the first scan signal line S1 is turned on, while the signals on the other signal lines are turned off. The turn-on signal on the first scan signal line S1 turns on the seventh transistor T7, and the second initial signal on the second initial signal line INIT2 can be written to the fourth node N4 to initialize it, preventing residual signals from the previous frame from affecting the display of this frame. The turn-on signal on the first scan signal line S1 turns on the eighth transistor T8, and the second reference signal on the second reference signal line REF2 can be written to the second node N2.

[0121] Phase 4. The signal on the second light-emitting signal line EM2 is turned on, while the signals on the other signal lines are turned off. The turn-on signal of the second light-emitting signal line EM2 turns on the sixth transistor T6, connecting the third node N3 and the fourth node N4, making the potentials of the third node N3 and the fourth node N4 the same.

[0122] Fifth stage. The signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are turned on, while the signals of the other signal lines are turned off. The turn-on signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2 turn on the fifth transistor T5 and the sixth transistor T6. The first power supply signal of the first power supply line VDD can provide a driving signal to the light-emitting device EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting device EL to emit light.

[0123] In an exemplary embodiment, when the driving transistor (i.e., the third transistor T3) remains in one state for an extended period, electrons are trapped, causing hysteresis. Therefore, in the first stage, by performing the initialization and threshold voltage writing process of the first node N1 multiple times (e.g., three times), not only can the hysteresis of the driving transistor be reduced, but the potential stability of the first node N1 can also be ensured. In the third stage, the second reference signal is written to the second node N2. By changing the potential of the second node N2, the hysteresis of the driving transistor can be reduced. In the fourth stage, by connecting the third node N3 and the fourth node N4, the potential of the fourth node N4 can be increased, which helps to reduce the time required to reach the turn-on voltage of the light-emitting device.

[0124] The pixel driving circuit provided in this disclosure can effectively improve the hysteresis of the driving transistor, which is beneficial to improving the display effect.

[0125] Figure 5This is a schematic diagram of a planar structure of a display substrate, illustrating the structure of pixel driving circuits in three circuit units (first circuit unit, second circuit unit, and third circuit unit) of the display substrate, as an exemplary embodiment of the present disclosure. In an exemplary embodiment, the display substrate may include a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate. The driving circuit layer may include at least a plurality of circuit units, and the light-emitting structure layer may include at least a plurality of light-emitting units. At least one circuit unit includes a pixel driving circuit, and at least one light-emitting unit includes a light-emitting device. The light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode. The anode in the light-emitting unit is connected to the pixel driving circuit in the corresponding circuit unit. In an exemplary embodiment, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In an exemplary embodiment, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or they may not correspond.

[0126] In an exemplary embodiment, a plurality of circuit units arranged sequentially along a first direction X can be referred to as a unit row, and a plurality of circuit units arranged sequentially along a second direction Y can be referred to as a unit column. The plurality of unit rows and the plurality of unit columns constitute an array of circuit units arranged in an array, and the first direction X intersects with the second direction Y.

[0127] like Figure 5 As shown, in an exemplary embodiment, the driving circuit layer may further include at least one first power line 51 extending along the second direction Y, at least one second power line 52 extending along the second direction Y, at least one first power connection line 68 extending along the first direction X, and at least one second power connection line 69 extending along the first direction X. In an exemplary embodiment, the first power line 51 is connected to the pixel driving circuit in a plurality of circuit units, and the first power line 51 is configured to continuously provide a high-level signal to the pixel driving circuit. The second power line 52 is connected to the cathode of a plurality of light-emitting units, and the second power line 52 is configured to continuously provide a low-level signal to the cathode. In an exemplary embodiment, the first power line 51 extending along the second direction Y and the first power connection line 68 extending along the first direction X are interconnected to form a mesh structure for transmitting a first power signal, and the second power line 52 extending along the second direction Y and the second power connection line 69 extending along the first direction X are interconnected to form a mesh structure for transmitting a second power signal.

[0128] In this disclosure, A extending along the direction of B means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip shape. The main part extends along the direction of B, and the length of the main part extending along the direction of B is greater than the length of the secondary part extending in other directions.

[0129] In an exemplary embodiment, the driving circuit layer may further include a reference signal connection line 54 and a first reference signal line 91. The first reference signal line 91 may be a line extending along a first direction X, and the reference signal connection line 54 may be a line extending along a second direction Y. The reference signal connection line 54 and the first reference signal line 91 are interconnected to form a mesh structure for transmitting the first reference signal.

[0130] In an exemplary embodiment, on a plane perpendicular to the display substrate, the driving circuit layer may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate. The first power line 51 and the first power connection line 68 may be disposed in different conductive layers, and the first power line 51 and the first power connection line 68 may be connected via vias. The second power line 52 and the second power connection line 69 may be disposed in different conductive layers, and the second power line 52 and the second power connection line 69 may be connected via vias.

[0131] In an exemplary embodiment, the first power line 51 and the second power line 52 can be arranged on the same layer and formed synchronously through the same patterning process, and the first power connection line 68 and the second power connection line 69 can be arranged on the same layer and formed synchronously through the same patterning process.

[0132] In an exemplary embodiment, the first power connection line 68 and the second power connection line 69 may be disposed in the third conductive layer, and the first power line 51 and the second power line 52 may be disposed in the fourth conductive layer.

[0133] In an exemplary embodiment, the reference signal connection line 54 and the first reference signal line 91 can be disposed in different conductive layers, and the reference signal connection line 54 and the first reference signal line 91 can be connected by vias.

[0134] In an exemplary embodiment, the first reference signal line 91 may be disposed in the third conductive layer, and the reference signal connection line 54 may be disposed in the fourth conductive layer.

[0135] In an exemplary embodiment, at least one circuit unit may include a plurality of transistors, and the semiconductor layer may include at least an active layer of a plurality of transistors.

[0136] In an exemplary embodiment, at least one pixel driving circuit may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting transistor, a sixth transistor T6 as a second light-emitting transistor, a seventh transistor T7 as a second initialization transistor, an eighth transistor T8 as a second reference transistor, a ninth transistor T9 as a first reference transistor, a first storage capacitor, and a second storage capacitor.

[0137] Figure 6 for Figure 5 An enlarged view of the first and second storage capacitor regions. (See image below.) Figure 6 As shown, in an exemplary embodiment, the first storage capacitor may include at least a first electrode 71 and a third electrode 73, wherein the orthographic projection of the third electrode 73 onto the substrate at least partially overlaps with the orthographic projection of the first electrode 71 onto the substrate. The second storage capacitor may include at least a second electrode 72 and a fourth electrode 74, wherein the orthographic projection of the fourth electrode 74 onto the substrate at least partially overlaps with the orthographic projection of the second electrode 72 onto the substrate.

[0138] In an exemplary embodiment, the first electrode 71 and the second electrode 72 can be disposed in the first conductive layer, the third electrode 73 and the fourth electrode 74 can be disposed in the second conductive layer, the first electrode 71 can serve as the gate electrode of the third transistor T3, the second electrode 72 is connected to the third electrode 73, and the fourth electrode 74 is connected to the first power line 51.

[0139] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the fourth scan signal line 64, the first terminal of the first transistor T1 is connected to the first initial signal line 81, and the second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2 and the first plate 71 of the first storage capacitor, respectively. The gate electrode of the second transistor T2 is connected to the second scan signal line 62, and the second terminal of the second transistor T2 is connected to the second terminal of the third transistor T3 and the first terminal of the sixth transistor T6, respectively. The gate electrode of the third transistor T3 serves as the first plate 71 of the first storage capacitor, and the first terminal of the third transistor T3 is connected to the second terminal of the fifth transistor T5 and the second terminal of the eighth transistor T8, respectively. The gate electrode of the fourth transistor T4 is connected to the third scan signal line 63, the first terminal of the fourth transistor T4 is connected to the data signal line 53, and the second terminal of the fourth transistor T4 is connected to the second terminal of the ninth transistor T9, the third plate 73 of the first storage capacitor, and the second plate 72 of the second storage capacitor, respectively. The gate electrode of the fifth transistor T5 is connected to the first light-emitting signal line 31, and the first terminal of the fifth transistor T5 is connected to the first power supply line 51. The gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line 32, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the first scan signal line 61, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 82. The gate electrode of the eighth transistor T8 is connected to the first scan signal line 61, and the first electrode of the eighth transistor T8 is connected to the second reference signal line 92. The gate electrode of the ninth transistor T9 is connected to the second scan signal line 62, and the first electrode of the ninth transistor T9 is connected to the first reference signal line 91.

[0140] In an exemplary embodiment, the second scan signal line 62 and the fifth scan signal line 65 transmit the same scan signal.

[0141] In an exemplary embodiment, the shapes of the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first light emission signal line 31, the second light emission signal line 32, the first initial signal line 81, the second initial signal line 82, the first reference signal line 91, and the second reference signal line 92 can be line shapes extending along the first direction X of the main body, and the shapes of the first power line 51 and the data signal line 53 can be line shapes extending along the second direction Y of the main body.

[0142] In an exemplary embodiment, at least one circuit unit may further include an anode connection electrode 55, which is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 respectively, and is also connected to the anode of the light-emitting unit.

[0143] In an exemplary embodiment, the driving circuit layer may further include a repair line 33, which may be a strip shape in which the main body extends along the first direction X, and the orthographic projection of the repair line 33 on the substrate at least partially overlaps with the orthographic projection of the anode connection electrode 55 on the substrate.

[0144] like Figure 5 and Figure 6 As shown, in an exemplary embodiment, at least one circuit unit may further include a first connection electrode 41, which is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first plate 71 of the first storage capacitor, respectively. The first connection electrode 41 may serve as the first node of the pixel driving circuit.

[0145] In an exemplary embodiment, at least one circuit unit may further include a power shielding block 51-1, which is connected to the first power line 51. The orthographic projection of the power shielding block 51-1 on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode 41 on the substrate, so as to shield the influence of other signals in the pixel driving circuit on the first node.

[0146] In an exemplary embodiment, at least one circuit unit may further include a second connection electrode 42, which is connected to the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third electrode plate 73 of the first storage capacitor, and the second electrode plate 72 of the second storage capacitor, respectively. The second connection electrode 42 may serve as the fifth node N5 in the pixel driving circuit.

[0147] In an exemplary embodiment, the orthographic projection of the first power line 51 on the substrate at least partially overlaps with the orthographic projection of the second connection electrode 42 on the substrate, so as to shield the influence of other signals in the pixel driving circuit on the fifth node.

[0148] In an exemplary embodiment, at least one circuit unit may further include a first shielding electrode 36, which is connected to a fourth electrode plate 74. The orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first transistor T1 on the substrate, and the orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the second transistor T2 on the substrate. In an exemplary embodiment, the first shielding electrode 36 is configured to shield the effects of data voltage transitions on the first transistor T1 and the second transistor T2, preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0149] In an exemplary embodiment, at least one circuit unit may further include a second shielding electrode 37, which is connected to the fourth electrode plate 74 and disposed between the first and second electrodes of the fourth transistor T4. In an exemplary embodiment, the second shielding electrode 37 is configured to shield the influence of data voltage transitions on the fifth node, preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0150] In an exemplary embodiment, the fourth electrode 74, the first shielding electrode 36, and the second shielding electrode 37 can be an integral structure that is interconnected.

[0151] In an exemplary embodiment, at least one circuit unit may further include a third shielding electrode 38, which is connected to the second reference signal line 92. The orthographic projection of the third shielding electrode 38 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the fourth transistor T4 on the substrate. In an exemplary embodiment, the third shielding electrode 38 is configured to shield the effect of data voltage transitions on the fourth transistor T4, thereby preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0152] In an exemplary embodiment, at least one circuit unit may further include a fourth shielding electrode 39, which is connected to the second reference signal line 92. The orthographic projection of the fourth shielding electrode 39 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the ninth transistor T9 on the substrate. In an exemplary embodiment, the fourth shielding electrode 39 is configured to shield the influence of data voltage transitions on the ninth transistor T9, thereby preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0153] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0154] In an exemplary embodiment, taking three circuit units in the nth unit row as an example, the fabrication process of the display substrate may include the following operations.

[0155] (11) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film using a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, such as... Figure 7 As shown.

[0156] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit in the display substrate may include at least the first active layer 11 of the first transistor T1, the second active layer 12 of the second transistor T2, the third active layer 13 of the third transistor T3, the fourth active layer 14 of the fourth transistor T4, the fifth active layer 15 of the fifth transistor T5, the sixth active layer 16 of the sixth transistor T6, the seventh active layer 17 of the seventh transistor T7, the eighth active layer 18 of the eighth transistor T8, and the ninth active layer 19 of the ninth transistor T9. The first active layer 11 to the third active layer 13 and the fifth active layer 15 to the eighth active layer 18 may be an integral structure interconnected with each other, and the fourth active layer 14 and the ninth active layer 19 may be an integral structure interconnected with each other.

[0157] In an exemplary embodiment, the fourth active layer 14 and the ninth active layer 19 of the nth unit row can be located on the side of the third active layer 13 near the (n-1)th unit row, that is, the fourth active layer 14 and the ninth active layer 19 can be located on the side opposite to the second direction Y of the third active layer 13 of this circuit unit. The first active layer 11, the second active layer 12, and the fifth active layer 15 to the eighth active layer 18 of the nth unit row can be located on the side of the third active layer 13 near the (n+1)th unit row, that is, the first active layer 11, the second active layer 12, and the fifth active layer 15 to the eighth active layer 18 can be located on the side of the third active layer 13 of this circuit unit in the second direction Y.

[0158] In an exemplary embodiment, the first active layer 11 may be located on one side of the third active layer 13 in the second direction Y of this circuit unit, the fifth active layer 15 may be located on one side of the first active layer 11 in the second direction Y of this circuit unit, and the eighth active layer 18 may be located on one side of the fifth active layer 15 in the second direction Y of this circuit unit. The second active layer 12 may be located on one side of the third active layer 13 in the second direction Y of this circuit unit, the sixth active layer 16 may be located on one side of the second active layer 12 in the second direction Y of this circuit unit, and the seventh active layer 17 may be located on one side of the sixth active layer 16 in the second direction Y of this circuit unit.

[0159] In an exemplary embodiment, the first active layer 11, the fourth active layer 14, the fifth active layer 15 and the eighth active layer 18 may be located on one side of the first direction X of this circuit unit (such as the opposite side of the first direction X), and the second active layer 12, the sixth active layer 16, the seventh active layer 17 and the ninth active layer 19 may be located on the other side of the first direction X of this circuit unit (such as one side of the first direction X).

[0160] In an exemplary embodiment, the first active layer 11 and the second active layer 12 can be in the shape of an "L", the third active layer 13 can be in the shape of a "C", the fourth active layer 14 and the ninth active layer 19 can be in the shape of an "n", and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17 and the eighth active layer 18 can be in the shape of an "I".

[0161] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer can be interconnected, and the second region 11-2 of the first active layer can serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 15-2 of the fifth active layer, and the second region 18-2 of the eighth active layer can be interconnected, and the first region 13-1 of the third active layer can simultaneously serve as both the second region 15-2 of the fifth active layer and the second region 18-2 of the eighth active layer, constituting the second node N2 of the pixel driving circuit. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer can be interconnected, and the second region 13-2 of the third active layer can simultaneously serve as both the second region 12-2 of the second active layer and the first region 16-1 of the sixth active layer, constituting the third node N3 of the pixel driving circuit. The second region 14-2 of the fourth active layer and the second region 19-2 of the ninth active layer can be interconnected, and the second region 14-2 of the fourth active layer can serve as the second region 19-2 of the ninth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer can be interconnected, and the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer, forming the fourth node N4 of the pixel driving circuit. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the first region 19-1 of the ninth active layer can be set individually. The first region 14-1 of the fourth active layer can be located on the side of the channel region of the fourth active layer near the third active layer 13, and the first region 19-1 of the ninth active layer can be located on the side of the channel region of the ninth active layer near the third active layer 13.

[0162] In an exemplary embodiment, in at least one cell row, the semiconductor layers in adjacent circuit cells in the first direction X are interconnected, that is, the semiconductor layer of the first circuit cell in the nth cell row is connected to the semiconductor layer of the second circuit cell in the nth cell row, and the semiconductor layer of the second circuit cell in the nth cell row is connected to the semiconductor layer of the third circuit cell in the nth cell row.

[0163] In an exemplary embodiment, the display substrate may further include a first active connection line 10 and a second active connection line 20. The first active connection line 10 may be located on one side of the ninth active layer 19 in the second direction Y and connected to the first region 19-1 of the ninth active layer of each circuit unit. The second active connection line 20 may be located on one side of the seventh active layer 17 in the second direction Y and connected to the first region 17-1 of the seventh active layer of each circuit unit.

[0164] In an exemplary embodiment, the shape of the first active connection line 10 can be a zigzag line extending along the first direction X of the main body. The first active connection line 10 and the ninth active layer of the plurality of circuit units can be an integral structure interconnected. Since the first region of the ninth active layer is connected to the subsequently formed first reference signal line, the first active connection line 10 can be multiplexed as a first reference signal line extending along the first direction X. This not only ensures that the first regions of the plurality of ninth active layers in a unit row have the same potential, but also reduces the voltage drop of the first reference signal, which is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0165] In an exemplary embodiment, the shape of the second active connection line 20 can be a straight line extending along the first direction X of the main body. The second active connection line 20 and the seventh active layer of the multiple circuit units can be an integral structure interconnected. Since the first region of the seventh active layer is connected to the subsequently formed second initial signal line, the second active connection line 20 can be multiplexed as a second initial signal line extending along the first direction X. This not only ensures that the first regions of the multiple seventh active layers in a unit row have the same potential, but also reduces the voltage drop of the second initial signal, which is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0166] In an exemplary embodiment, in at least one cell column, the semiconductor layers in adjacent circuit cells in the second direction Y are spaced apart from each other, that is, the semiconductor layer of the first circuit cell in the (n-1)th cell row is not connected to the semiconductor layer of the first circuit cell in the nth cell row, and the semiconductor layer of the first circuit cell in the nth cell row is not connected to the semiconductor layer of the first circuit cell in the (n+1)th cell row.

[0167] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, such as... Figure 8A and Figure 8B As shown, Figure 8B for Figure 8A A schematic diagram of the first conductive layer. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0168] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate includes at least: a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a fifth gate electrode 25, a sixth gate electrode 26, a ninth gate electrode 29, a first scan signal line 61, a first electrode plate 71 of a first storage capacitor, and a second electrode plate 72 of a second storage capacitor.

[0169] In an exemplary embodiment, the first gate electrode 21 may be in the shape of an "L" and may be located on one side of the first electrode plate 71 in the second direction Y. The area where the first gate electrode 21 overlaps with the first active layer may serve as the gate electrode of the first transistor T1 in the dual-gate structure.

[0170] In an exemplary embodiment, the second gate electrode 22 may be in the shape of a "T" and may be located on one side of the first electrode plate 71 in the second direction Y. The area where the second gate electrode 22 overlaps with the second active layer may serve as the gate electrode of the second transistor T2 in the dual-gate structure.

[0171] In an exemplary embodiment, the fourth gate electrode 24 may be in the shape of an "L" and may be located on the side opposite to the second direction Y of the second electrode plate 72. The area where the fourth gate electrode 24 overlaps with the fourth active layer may serve as the gate electrode of the fourth transistor T4 in a dual-gate structure.

[0172] In an exemplary embodiment, the fifth gate electrode 25 may be a strip shape extending along the second direction Y, and may be located on one side of the first gate electrode 21 in the second direction Y. The region where the fifth gate electrode 25 overlaps with the fifth active layer may serve as the gate electrode of the fifth transistor T5.

[0173] In an exemplary embodiment, the shape of the sixth gate electrode 26 may be a strip shape extending along the first direction X, and may be located on one side of the second gate electrode 22 in the second direction Y. The region where the sixth gate electrode 26 overlaps with the sixth active layer may serve as the gate electrode of the sixth transistor T6.

[0174] In an exemplary embodiment, the shape of the ninth gate electrode 29 can be a strip shape extending along the first direction X, and it can be located on the side opposite to the second direction Y of the second electrode plate 72. The area where the ninth gate electrode 29 overlaps with the ninth active layer can serve as the gate electrode of the ninth transistor T9 in a dual-gate structure.

[0175] In an exemplary embodiment, the shape of the first scan signal line 61 can be a line shape extending along the first direction X of the main body portion, and can be located on one side of the fifth gate electrode 25 and the sixth gate electrode 26 in the second direction Y. The area where the first scan signal line 61 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7, and the area where the first scan signal line 61 overlaps with the eighth active layer can serve as the gate electrode of the eighth transistor T8.

[0176] In an exemplary embodiment, the first electrode 71 of the first storage capacitor can be rectangular in shape, and the corners of the rectangle can be chamfered. The orthographic projection of the first electrode 71 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. The first electrode 71 can simultaneously serve as the lower electrode of the first storage capacitor and the gate electrode of the third transistor T3.

[0177] In an exemplary embodiment, the second electrode 72 of the second storage capacitor can be rectangular in shape, with chamfered corners. It can be located on the side opposite to the second direction Y of the first electrode 71, and on the side of the fourth gate electrode 24 and the ninth gate electrode 29 in the second direction Y. That is, in the second direction Y, the second electrode 72 is located between the first electrode 71 and the fourth gate electrode 24 (ninth gate electrode 29), and the orthographic projection of the second electrode 72 onto the substrate does not overlap with the orthographic projection of the semiconductor layer onto the substrate. In an exemplary embodiment, the second electrode 72 can serve as the lower electrode of the second storage capacitor.

[0178] In an exemplary embodiment, the areas of the first electrode plate 71 and the second electrode plate 72 projected onto the substrate may be the same or different.

[0179] In an exemplary embodiment, the region where the first active connection line 10 connects to the first region of the ninth active layer is bent toward the ninth active layer, forming a recess on the side of the first active connection line 10 away from the ninth active layer. A protrusion 72-1 is provided on the side of the second electrode plate 72 near the first active connection line 10. The protrusion 72-1 can be rectangular in shape. The first end of the protrusion 72-1 is connected to the second electrode plate 72, and the second end of the protrusion 72-1 extends into the recess of the first active connection line 10.

[0180] In an exemplary embodiment, the second electrode plate 72 and the protrusion 72-1 can be an integral structure connected to each other. By providing the recess of the first active connection line 10 and the protrusion 72-1 of the second electrode plate 72, this disclosure can effectively increase the area of ​​the second electrode plate 72 and effectively increase the capacitance of the second storage capacitor.

[0181] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first transistor T1 to the ninth transistor T9. The semiconductor layer in the region not shielded by the first conductive layer is conducted, that is, the first region and the second region of the first active layer to the ninth active layer are both conducted.

[0182] (13) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer, such as... Figure 9A and Figure 9B As shown, Figure 9B for Figure 9A A schematic diagram of the second conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0183] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: a first light-emitting signal line 31, a second light-emitting signal line 32, a repair line 33, a first shielding electrode 36, a second shielding electrode 37, a third shielding electrode 38, a fourth shielding electrode 39, a third electrode plate 73 of a first storage capacitor, a fourth electrode plate 74 of a second storage capacitor, a first initial signal line 81, and a second reference signal line 92.

[0184] In an exemplary embodiment, the shapes of the first light-emitting signal line 31, the second light-emitting signal line 32, the repair line 33, the first initial signal line 81, and the second reference signal line 92 can be the line shapes that extend along the first direction X of the main body. The first light-emitting signal line 31, the second light-emitting signal line 32, the repair line 33, and the first initial signal line 81 can be located between the first gate electrode 21 and the first scan signal line 61, and the second reference signal line 92 can be located on the side opposite to the second direction Y of the fourth gate electrode 24.

[0185] In an exemplary embodiment, the first light-emitting signal line 31 may be located on one side of the first gate electrode 21 in the second direction Y of this circuit unit, the first initial signal line 81 may be located on one side of the first light-emitting signal line 31 in the second direction Y of this circuit unit, the second light-emitting signal line 32 may be located on one side of the first initial signal line 81 in the second direction Y of this circuit unit, and the repair line 33 may be located on one side of the second light-emitting signal line 32 in the second direction Y of this circuit unit. That is, the second light-emitting signal line 32 may be located between the first light-emitting signal line 31 and the repair line 33, the first initial signal line 81 may be located between the first light-emitting signal line 31 and the second light-emitting signal line 32, and the second reference signal line 92 may be located on the side opposite to the second direction Y of the first light-emitting signal line 31.

[0186] In an exemplary embodiment, a first light-emitting connector 31-1 is provided on the side of the first light-emitting signal line 31 near the second light-emitting signal line 32. The first light-emitting connector 31-1 can be disposed in each circuit unit. The first end of the first light-emitting connector 31-1 is connected to the first light-emitting signal line 31, and the second end of the first light-emitting connector 31-1 extends toward the second light-emitting signal line 32. The first light-emitting connector 31-1 is configured to be connected to the fifth gate electrode 25 through a subsequently formed seventh connection electrode. In an exemplary embodiment, the first light-emitting signal line 31 and the plurality of first light-emitting connectors 31-1 can be an integral structure interconnected with each other.

[0187] In an exemplary embodiment, a second light-emitting connector 32-1 is provided on the side of the second light-emitting signal line 32 near the first light-emitting signal line 31. The second light-emitting connector 32-1 can be disposed in each circuit unit. The first end of the second light-emitting connector 32-1 is connected to the second light-emitting signal line 32, and the second end of the second light-emitting connector 32-1 extends toward the first light-emitting signal line 31. The second light-emitting connector 32-1 is configured to be connected to the sixth gate electrode 26 through a subsequently formed eighth connection electrode. In an exemplary embodiment, the second light-emitting signal line 32 and the plurality of second light-emitting connectors 32-1 can be an integral structure interconnected with each other.

[0188] In an exemplary embodiment, a first initial connection block 81-1 is provided on the side of the first initial signal line 81 near the first light-emitting signal line 31. The first initial connection block 81-1 can be disposed in each circuit unit. The first end of the first initial connection block 81-1 is connected to the first initial signal line 81, and the second end of the first initial connection block 81-1 extends toward the first light-emitting signal line 31. The first initial connection block 81-1 is configured to be connected to the first region of the first active layer through a subsequently formed ninth connection electrode, thereby realizing the connection of the first initial signal line 81 to the first electrode of the first transistor T1. The first initial signal line 81 can write the first initial signal into the first electrode of the first transistor T1. In an exemplary embodiment, the first initial signal line 81 and the plurality of first initial connection blocks 81-1 can be an integral structure interconnected with each other.

[0189] In an exemplary embodiment, a second reference connection block 92-1 is provided on the side of the second reference signal line 92 in the (n+1)th unit row away from the fourth electrode plate 74 of the (n+1)th unit row. The second reference connection block 92-1 can be disposed in each circuit unit. The first end of the second reference connection block 92-1 is connected to the second reference signal line 92, and the second end of the second reference connection block 92-1 extends away from the fourth electrode plate 74, i.e., extends towards the nth unit row. In an exemplary embodiment, the second reference connection block 92-1 of the second reference signal line 92 in the (n+1)th unit row is configured to connect to the first region of the eighth active layer in the nth unit row via a subsequently formed sixth connection electrode, providing a second reference signal to the first electrode of the eighth transistor T8 in the nth unit row. In an exemplary embodiment, the second reference signal line 92 and the plurality of second reference connection blocks 92-1 can be an interconnected integral structure.

[0190] In an exemplary embodiment, the outline shape of the third electrode 73 of the first storage capacitor can be rectangular, and the corners of the rectangle can be chamfered. It can be located between the first light-emitting signal line 31 and the second reference signal line 92 of this circuit unit. The orthographic projection of the third electrode 73 on the substrate at least partially overlaps with the orthographic projection of the first electrode 71 on the substrate. The third electrode 73 can serve as the upper electrode of the first storage capacitor. The first electrode 71 and the third electrode 73 constitute the first storage capacitor C1 of the pixel driving circuit.

[0191] In an exemplary embodiment, the outline shape of the fourth plate 74 of the second storage capacitor can be rectangular, and the corners of the rectangle can be chamfered. It can be located between the second reference signal line 92 and the third plate 73 of this circuit unit. The orthographic projection of the fourth plate 74 on the substrate at least partially overlaps with the orthographic projection of the second plate 72 on the substrate. The fourth plate 74 can serve as the upper plate of the second storage capacitor. The second plate 72 and the fourth plate 74 constitute the second storage capacitor C2 of the pixel driving circuit.

[0192] In an exemplary embodiment, the areas of the third electrode 73 and the fourth electrode 74 projected onto the substrate may be the same or different. For example, the area of ​​the fourth electrode 74 projected onto the substrate may be larger than the area of ​​the third electrode 73 projected onto the substrate.

[0193] In an exemplary embodiment, each circuit unit has a first opening 75 on its third electrode plate 73. The first opening 75 may be located in the middle of the third electrode plate 73 and may be rectangular, thus forming a ring structure with the third electrode plate 73. The first opening 75 exposes a third insulating layer covering the first electrode plate 71, and the orthographic projection of the first electrode plate 71 onto the substrate includes the orthographic projection of the first opening 75 onto the substrate. In an exemplary embodiment, the first opening 75 is configured to accommodate a subsequently formed tenth via, which is located within the first opening 75 and exposes the first electrode plate 71, allowing a subsequently formed first connection electrode to be connected to the first electrode plate 71.

[0194] In an exemplary embodiment, each circuit unit has a second opening 76 on its fourth electrode plate 74. The second opening 76 may be located in the middle of the fourth electrode plate 74 and may be rectangular, thus forming a ring structure with the fourth electrode plate 74. The second opening 76 exposes a third insulating layer covering the second electrode plate 72, and the orthographic projection of the second electrode plate 72 onto the substrate includes the orthographic projection of the second opening 76 onto the substrate. In an exemplary embodiment, the second opening 76 is configured to accommodate a subsequently formed eleventh via, which is located within the second opening 76 and exposes the second electrode plate 72, allowing a subsequently formed second connection electrode to be connected to the second electrode plate 72.

[0195] In an exemplary embodiment, the first shielding electrode 36 may be T-shaped and located on the side of the fourth electrode plate 74 near the first light-emitting signal line 31. The first shielding electrode 36 may be disposed in each circuit unit. The T-shaped first shielding electrode 36 may include a first extension 36-1 and a first shielding section 36-2. The first end of the first extension 36-1 is connected to the fourth electrode plate 74, and the second end of the first extension 36-1 extends toward the first light-emitting signal line 31 and connects to the first shielding section 36-2. The first shielding section 36-2 may be a strip shape extending along the first direction X. For the first shielding end of the first shielding section 36-2 located on the first direction X side of the first extension 36-1 and the second shielding end located on the opposite side of the first direction X of the first extension 36-1, the orthogonal projection of the first shielding end on the substrate at least partially overlaps with the orthogonal projection of the semiconductor layer between the two gate electrodes of the first transistor T1 in this circuit unit on the substrate. The orthogonal projection of the second shielding end on the substrate at least partially overlaps with the orthogonal projection of the semiconductor layer between the two gate electrodes of the second transistor T2 in the adjacent circuit unit on the substrate. In an exemplary embodiment, the first shielding electrode 36 is configured to shield the effects of data voltage jumps on the first transistor T1 and the second transistor T2, thereby preventing data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0196] In an exemplary embodiment, the second shielding electrode 37 may be I-shaped and located on the side of the fourth electrode plate 74 near the second reference signal line 92. The second shielding electrode 37 may be disposed in each circuit unit. The first end of the second shielding electrode 37 is connected to the fourth electrode plate 74, and the second end of the second shielding electrode 37 extends towards the second reference signal line 92. The second end of the second shielding electrode 37 may be located between the first and second electrodes of the fourth transistor T4. In an exemplary embodiment, the second shielding electrode 37 is configured to shield the influence of data voltage transitions on the fifth node N5, preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0197] In an exemplary embodiment, the fourth electrode 74, the first shielding electrode 36, and the second shielding electrode 37 can be an integral structure that is interconnected.

[0198] In an exemplary embodiment, the third shielding electrode 38 and the fourth shielding electrode 39 may be rectangular in shape and may be located on the side of the second reference signal line 92 near the fourth electrode plate 74. The third shielding electrode 38 and the fourth shielding electrode 39 may be disposed in each circuit unit. The first end of the third shielding electrode 38 is connected to the second reference signal line 92, and the second end of the third shielding electrode 38 extends toward the fourth electrode plate 74. The first end of the fourth shielding electrode 39 is connected to the second reference signal line 92, and the second end of the fourth shielding electrode 39 extends toward the fourth electrode plate 74. The orthographic projection of the third shielding electrode 38 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the fourth transistor T4 in this circuit unit on the substrate. The orthographic projection of the fourth shielding electrode 39 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the ninth transistor T9 in this circuit unit on the substrate. In an exemplary embodiment, the third shielding electrode 38 is configured to shield the effect of data voltage transitions on the fourth transistor T4, and the fourth shielding electrode 39 is configured to shield the effect of data voltage transitions on the ninth transistor T9, thereby preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0199] In an exemplary embodiment, the repair line 33, as a pre-set repair line, is configured to repair the failed anode by soldering. The repair line 33 is configured to input a signal to the anode of the sub-pixel with the bright spot defect when a bright spot defect occurs on the display substrate, thereby repairing it into a dark spot.

[0200] (14) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein each circuit unit is provided with multiple vias, such as... Figure 10 As shown.

[0201] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0202] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the first region of the first active layer onto the substrate. The fourth, third, and second insulating layers within the first via V1 are etched away, exposing the surface of the first region of the first active layer. The first via V1 is configured to allow a subsequently formed ninth connection electrode to be connected to the first region of the first active layer through the via.

[0203] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is located within the range of the orthographic projection of the second region of the first active layer (which is also the first region of the second active layer) onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the second via V2 are etched away, exposing the surface of the second region of the first active layer (which is also the first region of the second active layer). The second via V2 is configured to allow a subsequently formed first connection electrode to be connected to the second region of the first active layer (which is also the first region of the second active layer) through the via.

[0204] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the first region of the fourth active layer onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are etched away, exposing the surface of the first region of the fourth active layer. The third via V3 is configured to allow a subsequently formed third connection electrode to be connected to the first region of the fourth active layer through the via.

[0205] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the orthographic projection of the second region of the fourth active layer (which is also the second region of the ninth active layer) onto the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away, exposing the surface of the second region of the fourth active layer (which is also the second region of the ninth active layer). The fourth via V4 is configured to allow a subsequently formed second connection electrode to be connected to the second region of the fourth active layer (which is also the second region of the ninth active layer) through the via.

[0206] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is within the range of the orthographic projection of the first region of the fifth active layer onto the substrate. The fourth, third, and second insulating layers within the fifth via V5 are etched away, exposing the surface of the first region of the fifth active layer. The fifth via V5 is configured to allow a subsequently formed fourth connection electrode to be connected to the first region of the fifth active layer through the via.

[0207] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is located within the orthographic projection of the second region of the sixth active layer (which is also the second region of the seventh active layer) onto the substrate. The fourth, third, and second insulating layers within the sixth via V6 are etched away, exposing the surface of the second region of the sixth active layer (which is also the second region of the seventh active layer). The sixth via V6 is configured to allow the subsequently formed fifth connection electrode to be connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the via.

[0208] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the range of the orthographic projection of the first region of the seventh active layer onto the substrate. The fourth, third, and second insulating layers within the seventh via V7 are etched away, exposing the surface of the first region of the seventh active layer. The seventh via V7 is configured to allow a subsequently formed second initial signal line to be connected to the first region of the seventh active layer through the via.

[0209] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the range of the orthographic projection of the first region of the eighth active layer onto the substrate. The fourth, third, and second insulating layers within the eighth via V8 are etched away, exposing the surface of the first region of the eighth active layer. The eighth via V8 is configured to allow a subsequently formed sixth connection electrode to be connected to the first region of the eighth active layer through the via.

[0210] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate is within the range of the orthographic projection of the first region of the ninth active layer onto the substrate. The fourth, third, and second insulating layers within the ninth via V9 are etched away, exposing the surface of the first region of the ninth active layer. The ninth via V9 is configured to allow a subsequently formed first reference signal line to be connected to the first region of the ninth active layer through the via.

[0211] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate is within the range of the orthographic projection of the first opening 75 of the third electrode plate 73 onto the substrate. The fourth and third insulating layers within the tenth via V10 are etched away, exposing the surface of the first electrode plate 71. The tenth via V10 is configured to allow the subsequently formed first connection electrode to be connected to the first electrode plate 71 through the via.

[0212] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the second opening 76 of the fourth electrode plate 74 onto the substrate. The fourth and third insulating layers within the eleventh via V11 are etched away, exposing the surface of the second electrode plate 72. The eleventh via V11 is configured to allow a subsequently formed second connection electrode to be connected to the second electrode plate 72 through the via.

[0213] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is within the range of the orthographic projection of the third electrode plate 73 on the substrate. The fourth insulating layer within the twelfth via V12 is etched away, exposing the surface of the third electrode plate 73. The twelfth via V12 is configured to allow a subsequently formed second connection electrode to be connected to the third electrode plate 73 through the via.

[0214] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is within the range of the orthographic projection of the fourth electrode plate 74 on the substrate. The fourth insulating layer within the thirteenth via V13 is etched away, exposing the surface of the fourth electrode plate 74. The thirteenth via V13 is configured to allow the subsequently formed first power connection line to be connected to the fourth electrode plate 74 through the via.

[0215] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is within the range of the orthographic projection of the first gate electrode 21 on the substrate. The fourth insulating layer and the third insulating layer in the fourteenth via V14 are etched away to expose the surface of the first gate electrode 21. The fourteenth via V14 is configured to allow the subsequently formed fourth scan signal line to be connected to the first gate electrode 21 through the via.

[0216] In an exemplary embodiment, the orthogonal projection of the fifteenth via V15 onto the substrate is within the range of the orthogonal projection of the second gate electrode 22 onto the substrate. The fourth and third insulating layers within the fifteenth via V15 are etched away, exposing the surface of the second gate electrode 22. The fifteenth via V15 is configured to allow the subsequently formed fifth scan signal line to be connected to the second gate electrode 22 through the via.

[0217] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is within the range of the orthographic projection of the fourth gate electrode 24 on the substrate. The fourth insulating layer and the third insulating layer within the sixteenth via V16 are etched away, exposing the surface of the fourth gate electrode 24. The sixteenth via V16 is configured to allow the subsequently formed third scan signal line to be connected to the fourth gate electrode 24 through the via.

[0218] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 onto the substrate is within the range of the orthographic projection of the fifth gate electrode 25 onto the substrate. The fourth and third insulating layers within the seventeenth via V17 are etched away, exposing the surface of the fifth gate electrode 25. The seventeenth via V17 is configured to allow a subsequently formed seventh connection electrode to be connected to the fifth gate electrode 25 through the via.

[0219] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate is within the range of the orthographic projection of the sixth gate electrode 26 on the substrate. The fourth and third insulating layers within the eighteenth via V18 are etched away, exposing the surface of the sixth gate electrode 26. The eighteenth via V18 is configured to allow the subsequently formed eighth connection electrode to be connected to the sixth gate electrode 26 through the via.

[0220] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate is within the range of the orthographic projection of the ninth gate electrode 29 on the substrate. The fourth and third insulating layers within the nineteenth via V19 are etched away, exposing the surface of the ninth gate electrode 29. The nineteenth via V19 is configured to allow the subsequently formed second scan signal line to be connected to the ninth gate electrode 29 through the via.

[0221] In an exemplary embodiment, the orthographic projection of the twentieth via V20 onto the substrate is within the range of the orthographic projection of the first light-emitting connecting block 31-1 of the first light-emitting signal line 31 onto the substrate. The fourth insulating layer within the twentieth via V20 is etched away, exposing the surface of the first light-emitting connecting block 31-1. The twentieth via V20 is configured to allow the subsequently formed seventh connecting electrode to be connected to the first light-emitting connecting block 31-1 through the via.

[0222] In an exemplary embodiment, the orthographic projection of the 21st via V21 on the substrate is within the range of the orthographic projection of the second light-emitting connector 32-1 of the second light-emitting signal line 32 on the substrate. The fourth insulating layer inside the 21st via V21 is etched away, exposing the surface of the second light-emitting connector 32-1. The 21st via V21 is configured to allow the subsequently formed eighth connection electrode to be connected to the second light-emitting connector 32-1 through the via.

[0223] In an exemplary embodiment, the orthographic projection of the 22nd via V22 onto the substrate is within the range of the orthographic projection of the second reference connection block 92-1 onto the substrate of the second reference signal line 92. The fourth insulating layer within the 22nd via V22 is etched away, exposing the surface of the second reference connection block 92-1. The 22nd via V22 is configured to allow the subsequently formed sixth connection electrode to be connected to the second reference connection block 92-1 through the via.

[0224] In an exemplary embodiment, the orthographic projection of the 23rd via V23 onto the substrate is within the range of the orthographic projection of the first initial connection block 81-1 onto the substrate of the first initial signal line 81. The fourth insulating layer within the 23rd via V23 is etched away, exposing the surface of the first initial connection block 81-1. The 23rd via V23 is configured to allow the subsequently formed ninth connection electrode to be connected to the first initial connection block 81-1 through the via.

[0225] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on a fourth insulating layer, such as... Figure 11A and Figure 11B As shown, Figure 11B for Figure 11A A schematic diagram of the third conductive layer. In an exemplary embodiment, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0226] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display substrate may include: a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a sixth connecting electrode 46, a seventh connecting electrode 47, an eighth connecting electrode 48, a ninth connecting electrode 49, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a fifth scan signal line 65, a first power connection line 68, a second power connection line 69, a second initial signal line 82, and a first reference signal line 91.

[0227] In an exemplary embodiment, the shapes of the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the fifth scan signal line 65, the first power connection line 68, the second power connection line 69, the second initial signal line 82, and the first reference signal line 91 can be lines extending along the first direction X of the main body. The second scan signal line 62, the third scan signal line 63, and the first reference signal line 91 can be located on the side opposite to the second direction Y of the fourth electrode plate 74. The fourth scan signal line 64, the fifth scan signal line 65, and the second initial signal line 82 can be located on the side of the third electrode plate 73 in the second direction Y. The first power connection line 68 can be located in the area where the third electrode plate 73 is located. The second power connection line 69 can be located between the fifth scan signal line 65 and the second initial signal line 82. The second power connection line 69 can be located on the side of the first power connection line 68 in the second direction Y.

[0228] In an exemplary embodiment, the orthographic projection of the second power connection line 69 onto the substrate at least partially overlaps with the orthographic projection of the first initial signal line 81 onto the substrate. The second power connection line 69 is configured to connect to a subsequently formed second power line, forming a low-voltage power grid structure with a mesh-like interconnection structure on the display substrate. In an exemplary embodiment, the first reference signal line 91 may be located on the side of the fourth electrode plate 74 opposite to the second direction Y, the second scan signal line 62 may be located on the side of the first reference signal line 91 opposite to the second direction Y, and the third scan signal line 63 may be located on the side of the second scan signal line 62 opposite to the second direction Y.

[0229] In an exemplary embodiment, the fourth scan signal line 64 may be located on one side of the third electrode plate 73 in the second direction Y, the fifth scan signal line 65 may be located on one side of the fourth scan signal line 64 in the second direction Y, the second power connection line 69 may be located on one side of the fifth scan signal line 65 in the second direction Y, and the second initial signal line 82 may be located on one side of the second power connection line 69 in the second direction Y.

[0230] In an exemplary embodiment, the second scan signal line 62 is connected to the ninth gate electrode 29 in each circuit unit through the nineteenth via V19, thereby enabling the second scan signal line 62 to connect to the ninth gate electrode 29 of the ninth transistor T9, and the second scan signal line 62 can control the conduction and disconnection of the ninth transistor T9.

[0231] In an exemplary embodiment, the second scan signal line 62 may be provided with a second scan connection block 62-1, which may be rectangular. The middle portion of the second scan connection block 62-1 is connected to the second scan signal line 62, the first end of the second scan connection block 62-1 extends toward the first reference signal line 91, and the second end of the second scan connection block 62-1 extends toward the third scan signal line 63. In an exemplary embodiment, the second scan connection block 62-1 is configured to be connected to the ninth gate electrode 29 in each circuit unit through the nineteenth via V19, thereby realizing the connection of the second scan signal line 62 to the ninth gate electrode 29 of the ninth transistor T9, and the second scan signal line 62 can control the conduction and disconnection of the ninth transistor T9.

[0232] In an exemplary embodiment, the fifth scan signal line 65 is connected to the second gate electrode 22 in each circuit unit through the fifteenth via V15, thereby realizing the connection of the fifth scan signal line 65 to the second gate electrode 22 of the second transistor T2. The fifth scan signal line 65 can control the conduction and disconnection of the second transistor T2.

[0233] In an exemplary embodiment, the fifth scan signal line 65 may be provided with a fifth scan connection block 65-1, which may be rectangular. The middle portion of the fifth scan connection block 65-1 is connected to the fifth scan signal line 65, the first end of the fifth scan connection block 65-1 extends toward the second initial signal line 82, and the second end of the fifth scan connection block 65-1 extends toward the first reference signal line 91. In an exemplary embodiment, the fifth scan connection block 65-1 is configured to be connected to the second gate electrode 22 in each circuit unit through the fifteenth via V15, thereby realizing the connection of the fifth scan signal line 65 to the second gate electrode 22 of the second transistor T2, and the fifth scan signal line 65 can control the conduction and disconnection of the second transistor T2.

[0234] In an exemplary embodiment, the second scan signal line 62 and the fifth scan signal line 65 can extend to the frame area and be connected to the same gate drive circuit to achieve the same scan signal output, that is, the second scan signal line 62 and the fifth scan signal line 65 output the same second scan signal.

[0235] In an exemplary embodiment, the third scan signal line 63 is connected to the fourth gate electrode 24 in each circuit unit through the sixteenth via V16, thereby realizing the connection of the third scan signal line 63 to the fourth gate electrode 24 of the fourth transistor T4, and the third scan signal line 63 can control the conduction and disconnection of the fourth transistor T4.

[0236] In an exemplary embodiment, a third scan connection block 63-1 is provided on the side of the third scan signal line 63 near the first reference signal line 91. The first end of the third scan connection block 63-1 is connected to the third scan signal line 63, and the second end of the third scan connection block 63-1 extends toward the first reference signal line 91. In an exemplary embodiment, the third scan connection block 63-1 is configured to be connected to the fourth gate electrode 24 in each circuit unit through the sixteenth via V16, thereby realizing the connection of the third scan signal line 63 to the fourth gate electrode 24 of the fourth transistor T4. The third scan signal line 63 can control the conduction and disconnection of the fourth transistor T4.

[0237] In an exemplary embodiment, the fourth scan signal line 64 is connected to the first gate electrode 21 in each circuit unit through the fourteenth via V14, thereby realizing that the fourth scan signal line 64 is connected to the first gate electrode 21 of the first transistor T1, and the fourth scan signal line 64 can control the conduction and disconnection of the first transistor T1.

[0238] In an exemplary embodiment, the fourth scan signal line 64 may be provided with a fourth scan connection block 64-1, which may be rectangular. The middle portion of the fourth scan connection block 64-1 is connected to the fourth scan signal line 64, the first end of the fourth scan connection block 64-1 extends toward the second initial signal line 82, and the second end of the fourth scan connection block 64-1 extends toward the first reference signal line 91. In an exemplary embodiment, the fourth scan connection block 64-1 is configured to be connected to the first gate electrode 21 in each circuit unit through the fourteenth via V14, thereby realizing the connection of the fourth scan signal line 64 to the first gate electrode 21 of the first transistor T1, and the fourth scan signal line 64 can control the conduction and disconnection of the first transistor T1.

[0239] In an exemplary embodiment, the second initial signal line 82 is connected to the first region of the seventh active layer in each circuit unit through the seventh via V7, thereby enabling the second initial signal line 82 to connect to the first terminal of the seventh transistor T7, and the second initial signal line 82 can write the second initial signal to the first terminal of the seventh transistor T7.

[0240] In an exemplary embodiment, a second initial connection block 82-1 is provided on the side of the second initial signal line 82 near the fifth scan signal line 65. The first end of the second initial connection block 82-1 is connected to the second initial signal line 82, and the second end of the second initial connection block 82-1 extends toward the fifth scan signal line 65. In an exemplary embodiment, the second initial connection block 82-1 is configured to connect to the first region of the seventh active layer in each circuit unit through the seventh via V7, thereby enabling the second initial signal line 82 to connect to the first electrode of the seventh transistor T7, and the second initial signal line 82 can write the second initial signal to the first electrode of the seventh transistor T7. In an exemplary embodiment, since the second active connection line 20 of the semiconductor layer is directly connected to the first region of the seventh active layer of multiple circuit units in a unit row, and the second initial signal line 82 of the third conductive layer is connected to the first region of the seventh active layer of multiple circuit units in a unit row through a via, the second active connection line 20 and the second initial signal line 82 constitute a double-layer signal line structure. This not only ensures that the first regions of multiple seventh active layers in a unit row have the same potential, but also reduces the resistance of the signal line and the voltage drop of the second initial signal. This is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0241] In an exemplary embodiment, the first reference signal line 91 is connected to the first region of the ninth active layer in each circuit unit through the ninth via V9, thereby enabling the first reference signal line 91 to connect to the first terminal of the ninth transistor T9, and the first reference signal line 91 can write the first reference signal into the first terminal of the ninth transistor T9.

[0242] In an exemplary embodiment, a first reference connection block 91-1 is provided on the side of the first reference signal line 91 near the first power connection line 68. The first end of the first reference connection block 91-1 is connected to the first reference signal line 91, and the second end of the first reference connection block 91-1 extends toward the first power connection line 68. The first reference connection block 91-1 is configured to connect to the first region of the ninth active layer through the ninth via V9, and is also configured to connect to the reference signal connection line formed subsequently.

[0243] In an exemplary embodiment, the shape of the first active connection line 10 can be a zigzag line extending along the first direction X of the main body. The first active connection line 10 and the ninth active layer of the plurality of circuit units can be an integral structure interconnected. Since the first region of the ninth active layer is connected to the subsequently formed first reference signal line, the first active connection line 10 can be multiplexed as a first reference signal line extending along the first direction X. This not only ensures that the first regions of the plurality of ninth active layers in a unit row have the same potential, but also reduces the voltage drop of the first reference signal, which is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0244] In an exemplary embodiment, the first power connection line 68 is connected to the fourth electrode plate 74 in each circuit unit through the thirteenth via V13, thus realizing the connection of the first power connection line 68 to the fourth electrode plate 74. Since the first power connection line 68 is connected to the subsequently formed first power line, the first power connection line 68 can write the first power signal to the upper electrode plate of the second storage capacitor.

[0245] In an exemplary embodiment, a first power connection block 68-1 is provided on the side of the first power connection line 68 away from the second power connection line 69. The first end of the first power connection block 68-1 is connected to the first power connection line 68, and the second end of the first power connection block 68-1 extends away from the second power connection line 69. In this exemplary embodiment, the first power connection block 68-1 is configured to connect to the fourth electrode plate 74 through the thirteenth via V13, and is also configured to connect to the subsequently formed first power line.

[0246] In an exemplary embodiment, the orthographic projection of the first power connection line 68 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 73 on the substrate. The first power connection line 68 is configured to connect to the subsequently formed first power line, forming a high-voltage power grid structure with a mesh-like interconnection structure on the display substrate.

[0247] In an exemplary embodiment, in at least one circuit unit, a second power connection block 69-1 is provided on the side of the second power connection line 69 away from the first power connection line 68. A first end of the second power connection block 69-1 is connected to the second power connection line 69, and a second end of the second power connection block 69-1 extends in a direction away from the first power connection line 68. The second power connection block 69-1 is configured to connect to a subsequently formed second power line. In an exemplary embodiment, the second power connection block 69-1 may be disposed between the first circuit unit and the second circuit unit.

[0248] In an exemplary embodiment, the orthographic projection of the second power connection line 69 onto the substrate at least partially overlaps with the orthographic projection of the first initial signal line 81 onto the substrate. The second power connection line 69 is configured to connect to a subsequently formed second power line, forming a low-voltage power grid structure with a mesh-like interconnection structure on the display substrate.

[0249] In an exemplary embodiment, the first connecting electrode 41 can be a strip shape extending along the second direction Y, and can be located between the fourth scan signal line 64 and the first power connection line 68. The first end of the first connecting electrode 41 is connected to the second region of the first active layer (which is also the first region of the second active layer) through the second via V2, and the second end of the first connecting electrode 41 is connected to the first electrode plate 71 through the tenth via V10. In an exemplary embodiment, the first connecting electrode 41 makes the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 71 of the first storage capacitor (i.e., the first end of the first storage capacitor) have the same potential. The first connecting electrode 41 can serve as the first node N1 of the pixel driving circuit.

[0250] In an exemplary embodiment, the second connection electrode 42 can be shaped like a broken line extending along the second direction Y, and can be located between the first reference signal line 91 and the first power connection line 68. The first end of the second connection electrode 42 is connected to the second region of the fourth active layer (which is also the second region of the ninth active layer) through the fourth via V4, and the second end of the second connection electrode 42 is connected to the third electrode plate 73 through the twelfth via V12. The third end between the first end and the second end is connected to the second electrode plate 72 through the eleventh via V11. In an exemplary embodiment, the second connection electrode 42 makes the second electrode of the fourth transistor T4, the second electrode of the ninth transistor T9, the third electrode plate 73 of the first storage capacitor (i.e., the second end of the first storage capacitor), and the second electrode plate 72 of the second storage capacitor (i.e., the second end of the second storage capacitor) have the same potential. The second connection electrode 42 can serve as the fifth node N5 of the pixel driving circuit.

[0251] In an exemplary embodiment, the third connection electrode 43 may be rectangular in shape and may be located between the first reference signal line 91 and the first power connection line 68. The third connection electrode 43 is connected to the first region of the fourth active layer through the third via V3. In an exemplary embodiment, the third connection electrode 43 may serve as the first electrode of the fourth transistor T4 and may be configured to connect to the subsequently formed data signal line.

[0252] In an exemplary embodiment, the fourth connection electrode 44 may be rectangular in shape and may be located between the fifth scan signal line 65 and the second initial signal line 82. The fourth connection electrode 44 is connected to the first region of the fifth active layer through the fifth via V5. In an exemplary embodiment, the fourth connection electrode 44 may serve as the first electrode of the fifth transistor T5 and may be configured to connect to the subsequently formed first power line.

[0253] In an exemplary embodiment, the fifth connection electrode 45 can be L-shaped and located between the fifth scan signal line 65 and the second initial signal line 82. The fifth connection electrode 45 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the sixth via V6. In an exemplary embodiment, the fifth connection electrode 45 can serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and is configured to be connected to the subsequently formed anode connection electrode.

[0254] In an exemplary embodiment, the sixth connection electrode 46 can be a strip shape extending along the first direction X of the main body, and can be located between the fifth scan signal line 65 and the second initial signal line 82. The first end of the sixth connection electrode 46 is connected to the first region of the eighth active layer through the eighth via V8, and the second end of the sixth connection electrode 46 is connected to the second reference connection block 92-1 through the twenty-second via V22. In an exemplary embodiment, the sixth connection electrode 46 can serve as the first electrode of the eighth transistor T8. Since the second reference connection block 92-1 is connected to the second reference signal line 92, the second reference signal line 92 is connected to the first electrode of the eighth transistor T8, and the second reference signal line 92 in the nth unit row can write the second reference signal into the first electrode of the eighth transistor T8 in the (n-1)th unit row.

[0255] In an exemplary embodiment, the seventh connecting electrode 47 can be a strip shape extending along the first direction X, and can be located between the fifth scan signal line 65 and the second initial signal line 82. The first end of the seventh connecting electrode 47 is connected to the fifth gate electrode 25 through the seventeenth via V17, and the second end of the seventh connecting electrode 47 is connected to the first light-emitting connecting block 31-1 through the twentieth via V20. Since the first light-emitting connecting block 31-1 is connected to the first light-emitting signal line 31, the first light-emitting signal line 31 is connected to the fifth gate electrode 25 of the fifth transistor T5, and the first light-emitting signal line 31 can control the conduction and disconnection of the fifth transistor T5.

[0256] In an exemplary embodiment, the eighth connecting electrode 48 can be a strip shape with its main body extending along the first direction X, and can be located between the fifth scan signal line 65 and the second initial signal line 82. The first end of the eighth connecting electrode 48 is connected to the sixth gate electrode 26 through the eighteenth via V18, and the second end of the eighth connecting electrode 48 is connected to the second light-emitting connecting block 32-1 through the twenty-first via V21. Since the second light-emitting connecting block 32-1 is connected to the second light-emitting signal line 32, the second light-emitting signal line 32 is connected to the sixth gate electrode 26 of the sixth transistor T6, and the second light-emitting signal line 32 can control the conduction and disconnection of the sixth transistor T6.

[0257] In an exemplary embodiment, the ninth connecting electrode 49 can be a strip shape extending along the first direction X of the main body, and can be located between the fifth scan signal line 65 and the second initial signal line 82. The first end of the ninth connecting electrode 49 is connected to the first region of the first active layer through the first via V1, and the second end of the ninth connecting electrode 49 is connected to the first initial connecting block 81-1 through the twenty-third via V23. Since the first initial connecting block 81-1 is connected to the first initial signal line 81, the first initial signal line 81 is connected to the first electrode of the first transistor T1, and the first initial signal line 81 can write the first initial signal to the first electrode of the first transistor T1.

[0258] (16) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer, wherein each circuit unit is provided with multiple vias, such as... Figure 12 As shown.

[0259] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate includes at least: a thirty-first via V31, a thirty-second via V32, a thirty-third via V33, a thirty-fourth via V34, and a thirty-fifth via V35.

[0260] In an exemplary embodiment, the orthographic projection of the 31st via V31 on the substrate is within the range of the orthographic projection of the third connecting electrode 43 on the substrate. The fifth insulating layer inside the 31st via V31 is removed, exposing the surface of the third connecting electrode 43. The 31st via V31 is configured to allow subsequently formed data signal lines to be connected to the third connecting electrode 43 through the via.

[0261] In an exemplary embodiment, the orthographic projection of the 32nd via V32 on the substrate is within the range of the orthographic projection of the fourth connecting electrode 44 on the substrate. The fifth insulating layer within the 32nd via V32 is removed, exposing the surface of the fourth connecting electrode 44. The 32nd via V32 is configured to allow a subsequently formed first power line to be connected to the fourth connecting electrode 44 through the via.

[0262] In an exemplary embodiment, the orthographic projection of the 33rd via V33 onto the substrate is within the range of the orthographic projection of the fifth connecting electrode 45 onto the substrate. The fifth insulating layer within the 33rd via V33 is removed, exposing the surface of the fifth connecting electrode 45. The 33rd via V33 is configured to allow the subsequently formed anode connecting electrode to be connected to the fifth connecting electrode 45 through the via.

[0263] In an exemplary embodiment, the orthographic projection of the 34th via V34 onto the substrate is within the range of the orthographic projection of the first reference connection block 91-1 onto the substrate of the first reference signal line 91. The fifth insulating layer within the 34th via V34 is removed, exposing the surface of the first reference connection block 91-1. The 34th via V34 is configured to allow subsequently formed reference signal connection lines to be connected to the first reference connection block 91-1 through the via.

[0264] In an exemplary embodiment, the orthographic projection of the 35th via V35 on the substrate is within the range of the orthographic projection of the first power connection block 68-1 of the first power connection line 68 on the substrate. The fifth insulating layer in the 35th via V35 is removed, exposing the surface of the first power connection block 68-1. The 35th via V35 is configured to allow the subsequently formed first power line to be connected to the first power connection block 68-1 through the via.

[0265] In an exemplary embodiment, at least one circuit unit may further include a thirty-sixth via V36. The orthographic projection of the thirty-sixth via V36 onto the substrate lies within the orthographic projection of the second power connection block 69-1 of the second power connection line 69 onto the substrate. The fifth insulating layer within the thirty-sixth via V36 is removed, exposing the surface of the second power connection block 69-1. The thirty-sixth via V36 is configured to allow a subsequently formed second power line to connect to the second power connection block 69-1 through this via. In an exemplary embodiment, the thirty-sixth via V36 may be located between the first circuit unit and the second circuit unit.

[0266] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on a fifth insulating layer, such as... Figure 13A and13B As shown, Figure 13B for Figure 13A A schematic diagram of the fourth conductive layer. In an exemplary embodiment, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0267] In an exemplary embodiment, the fourth conductive layer pattern of each circuit unit in the display substrate may include: a first power line 51, a data signal line 53, a reference signal connection line 54, and an anode connection electrode 55.

[0268] In an exemplary embodiment, the first power line 51, the data signal line 53, and the reference signal connection line 54 can be strip-shaped with the main body extending along the second direction Y. The first power line 51 can be located on one side of the data signal line 53 in the first direction X, and the reference signal connection line 54 can be located on one side of the first power line 51 in the first direction X, that is, the first power line 51 can be located between the data signal line 53 and the reference signal connection line 54.

[0269] In an exemplary embodiment, the first power line 51 can be shaped as a broken line extending along the second direction Y of the main body. The first power line 51 is connected to the fourth connecting electrode 44 via the thirty-second via V32, and to the first power connection block 68-1 via the thirty-fifth via V35. Since the fourth connecting electrode 44 is connected to the first region of the fifth active layer via the via, the first power line 51 writes the first power signal to the first electrode of the fifth transistor T5. Since the first power connection block 68-1 is connected to the first power connection line 68, the first power connection line 68 extending along the first direction X of the main body and the first power line 51 extending along the second direction Y of the main body are interconnected. This forms a mesh structure on the display substrate, effectively reducing the resistance of the first power line 51 and decreasing the voltage drop of the first power signal. Furthermore, it effectively improves the uniformity of the first power signal in the display substrate, thereby enhancing display uniformity and improving display quality.

[0270] In an exemplary embodiment, a power shielding block 51-1 is provided on the side of the first power line 51 near the reference signal connection line 54. The first end of the power shielding block 51-1 is connected to the first power line 51, and the second end of the power shielding block 51-1 extends towards the reference signal connection line 54. The power shielding block 51-1 can be rectangular in shape, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode 41 on the substrate. Since the first connecting electrode 41 serves as the first node N1 in the pixel driving circuit, the constant-voltage power shielding block 51-1 can effectively shield the first node N1 from the influence of other signals in the pixel driving circuit, preventing other signals (such as data voltage jumps) from affecting the potential of the first node N1 in the pixel driving circuit, thus improving the display effect.

[0271] In an exemplary embodiment, the first power line 51 and the power shield block 51-1 can be an integral structure that is interconnected.

[0272] In an exemplary embodiment, the orthographic projection of the power shield block 51-1 onto the substrate may include the orthographic projection of the first connection electrode 41 onto the substrate.

[0273] In an exemplary embodiment, a third power connector 51-2 is provided on the side of the first power line 51 near the reference signal connection line 54. The third power connector 51-2 can be a strip shape extending along the first direction X. The first end of the third power connector 51-2 is connected to the first power line 51, and the second end of the third power connector 51-2 extends toward the reference signal connection line 54 and is connected to the first power connector 68-1 through the thirty-fifth via V35.

[0274] In an exemplary embodiment, the first power line 51 and the third power connection block 51-2 can be an integral structure that is interconnected.

[0275] In an exemplary embodiment, the orthographic projection of the first power line 51 on the substrate at least partially overlaps with the orthographic projection of the second connecting electrode 42 on the substrate. Since the second connecting electrode 42 serves as the fifth node N5 in the pixel driving circuit, the constant voltage of the first power line 51 can effectively shield the influence of other signals in the pixel driving circuit on the fifth node N5, preventing other signals from affecting the potential of the fifth node N5 in the pixel driving circuit and improving the display effect.

[0276] In an exemplary embodiment, the first power line 51 can be designed with non-uniform width. The non-uniform width design of the first power line 51 not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the first power line and the data signal line.

[0277] In an exemplary embodiment, the data signal line 53 can be a straight line extending along the second direction Y, and the data signal line 53 is connected to the third connection electrode 43 through the thirty-first via V31. Since the third connection electrode 43 is connected to the first region of the fourth active layer through the via, the data signal line 53 writes the data signal to the first electrode of the fourth transistor T4.

[0278] In an exemplary embodiment, a data signal connector 53-1 is provided on the side of the data signal line 53 near the first power line 51. The first end of the data signal connector 53-1 is connected to the data signal line 53, and the second end of the data signal connector 53-1 extends towards the first power line 51. The data signal connector 53-1 can be rectangular in shape. The data signal connector 53-1 is configured to connect to the third connection electrode 43 through a thirty-first via V31.

[0279] In an exemplary embodiment, the reference signal connection line 54 can be a straight line extending along the second direction Y of the main body. The reference signal connection line 54 is connected to the first reference connection block 91-1 through the thirty-fourth via V34. Since the first reference connection block 91-1 is connected to the first reference signal line 91, the first reference signal line 91 extending along the first direction X of the main body and the reference signal connection line 54 extending along the second direction Y of the main body are interconnected. This allows the first reference signal line 91 and the reference signal connection line 54 to form a mesh structure on the display substrate for transmitting the first reference signal. This not only effectively reduces the resistance of the first reference signal line and the voltage drop of the first reference signal, but also effectively improves the uniformity of the first reference signal in the display substrate, thereby improving display uniformity and display quality.

[0280] In an exemplary embodiment, a reference signal connection block 54-1 is provided on the side of the reference signal connection line 54 near the data signal line 53. A first end of the reference signal connection block 54-1 is connected to the reference signal connection line 54, and a second end of the reference signal connection block 54-1 extends toward the data signal line 53. The reference signal connection block 54-1 can be rectangular in shape. The reference signal connection block 54-1 is configured to connect to the first reference connection block 91-1 through a thirty-fourth via V34.

[0281] In an exemplary embodiment, the anode connection electrode 55 can be rectangular in shape, and it is connected to the fifth connection electrode 45 through a thirty-third via V33. Since the fifth connection electrode 45 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through a via, the anode connection electrode 55 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. In this exemplary embodiment, the anode connection electrode 55 is configured to connect to a subsequently formed anode, thus enabling the pixel driving circuit to drive the light-emitting device.

[0282] In an exemplary embodiment, the orthographic projection of the anode connection electrode 55 on the substrate at least partially overlaps with the orthographic projection of the repair line 33 on the substrate.

[0283] In an exemplary embodiment, at least one circuit unit may further include a second power line 52. The shape of the second power line 52 may be a straight line extending along the second direction Y of the main body portion. The second power line 52 is connected to the second power connection block 69-1 through the thirty-sixth via V36. Since the second power connection block 69-1 is connected to the second power connection line 69, the interconnection between the second power connection line 69 extending along the first direction X of the main body portion and the second power line 52 extending along the second direction Y of the main body portion is realized. This allows the second power line 52 and the second power connection line 69 to form a mesh structure on the display substrate for transmitting the second power signal. This not only effectively reduces the resistance of the second power line 52 and reduces the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, effectively improving display uniformity, display quality, and display performance.

[0284] In an exemplary embodiment, the second power line 52 may be located between the reference signal connection line 54 of the first circuit unit and the data signal line 53 of the second circuit unit.

[0285] In an exemplary embodiment, the second power line 52 is provided with a fourth power connector 52-1. The middle portion of the fourth power connector 52-1 is connected to the second power line 52. The first end of the fourth power connector 52-1 extends toward the reference signal connection line 54 of the first circuit unit, and the second end of the fourth power connector 52-1 extends toward the data signal line 53 of the second circuit unit. The fourth power connector 52-1 can be rectangular. In an exemplary embodiment, the fourth power connector 52-1 is configured to connect to the second power connector 69-1 through a thirty-sixth via V36.

[0286] In an exemplary embodiment, the first power connection line 68 of the third conductive layer can be disposed in each cell row, and the first power line 51 of the fourth conductive layer can be disposed in each cell column. Multiple first power lines 51 are respectively connected to multiple first power connection lines 68 to form a mesh structure for transmitting the first power signal.

[0287] In an exemplary embodiment, the first reference signal line 91 of the third conductive layer can be disposed in each cell row, and the reference signal connection line 54 of the fourth conductive layer can be disposed in each cell column. Multiple first reference signal lines 91 are respectively connected to multiple reference signal connection lines 54 to form a mesh structure for transmitting the first reference signal.

[0288] In an exemplary embodiment, the second power connection line 69 of the third conductive layer can be disposed in each cell row, and the second power line 52 of the fourth conductive layer can be disposed every two cell columns. The multiple second power lines 52 are respectively connected to the multiple second power connection lines 69 to form a mesh structure for transmitting the second power signal.

[0289] Subsequent fabrication processes may include forming a first planarization layer pattern, on which a plurality of anode vias are provided. The orthographic projection of the anode vias onto the substrate is within the range of the orthographic projection of the anode connecting electrode onto the substrate. The first planarization layer within the anode vias is removed to expose the surface of the anode connecting electrode. The anode vias are configured to allow the subsequently formed anode to be connected to the anode connecting electrode through the vias.

[0290] Thus, the driving circuit layer of this embodiment is fabricated on the substrate. In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer and an encapsulation structure layer can be fabricated sequentially on the driving circuit layer, which will not be described in detail here.

[0291] Figure 14 This is a schematic diagram of another planar structure of a display substrate, illustrating the structure of the pixel driving circuit in three circuit units (first circuit unit, second circuit unit, and third circuit unit) of the display substrate, as an exemplary embodiment of the present disclosure. Figure 14 As shown, the main structure of the pixel driving circuit in this exemplary embodiment is basically the same as that in the previous embodiment. The difference is that in this embodiment, the second power connection line 69 is located between the first power connection line 68 and the fourth scan signal line 64, and the first shielding electrode 36 and the second power connection line 69 are an integral structure that are interconnected.

[0292] Figure 15 for Figure 14 An enlarged view of the first and second storage capacitor regions. (See image below.) Figure 15As shown, at least one circuit unit may further include a first shielding electrode 36, which is connected to a second power supply connection line 69. The orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first transistor T1 on the substrate, and the orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the second transistor T2 on the substrate. In an exemplary embodiment, the first shielding electrode 36 is configured to shield the influence of data voltage transitions on the first transistor T1 and the second transistor T2, preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0293] In an exemplary embodiment, the first shielding electrode 36 may include a first sub-electrode 36-3 and a second sub-electrode 36-4. A first end of the first sub-electrode 36-3 is connected to a second power connection line 69, and a second end of the first sub-electrode 36-3 extends in a direction away from the second power connection line 69, i.e., extends in the opposite direction of the second direction Y. The orthographic projection of the second end of the first sub-electrode 36-3 onto the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first transistor T1 in this circuit unit onto the substrate. A first end of the second sub-electrode 36-4 is connected to the second power connection line 69, and a second end of the second sub-electrode 36-4 extends in a direction away from the second power connection line 69. The orthographic projection of the second end of the second sub-electrode 36-4 onto the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the second transistor T2 in this circuit unit onto the substrate.

[0294] In some possible exemplary embodiments, the middle portion of the first sub-electrode 36-3 is connected to the second power supply connection line 69, the first end of the first sub-electrode 36-3 extends in the opposite direction of the second direction Y, and the second end of the first sub-electrode 36-3 extends in the second direction Y. The orthographic projections of the first end and the second end of the first sub-electrode 36-3 on the substrate at least partially overlap with the orthographic projections of the node between the two gate electrodes of the first transistor T1 in this circuit unit on the substrate.

[0295] In some possible exemplary embodiments, the middle portion of the second sub-electrode 36-4 is connected to the second power supply connection line 69, the first end of the second sub-electrode 36-4 extends in the opposite direction of the second direction Y, and the second end of the second sub-electrode 36-4 extends in the second direction Y. The orthographic projections of the first and second ends of the second sub-electrode 36-4 onto the substrate at least partially overlap with the orthographic projections of the node between the two gate electrodes of the second transistor T2 in this circuit unit onto the substrate.

[0296] In an exemplary embodiment, the first shielding electrode 36 and the second power connection line 69 are an integral structure that is interconnected.

[0297] In an exemplary embodiment, at least one circuit unit may further include a second shielding electrode 37, a third shielding electrode 38, and a fourth shielding electrode 39, the shape, position, and connection structure of which are substantially the same as those in the foregoing embodiments.

[0298] The following is an exemplary description of the fabrication process of the display substrate. In an exemplary embodiment, taking three circuit units in the nth unit row as an example, the fabrication process of the display substrate in this embodiment may include the following operations.

[0299] (21) A pattern of a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, and a fourth insulating layer is formed sequentially. The semiconductor layer pattern may include at least a first active connection line 10, a second active connection line 20, and a first active layer 11 to a ninth active layer 19. The first conductive layer pattern may include at least a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a fifth gate electrode 25, a sixth gate electrode 26, a ninth gate electrode 29, a first scan signal line 61, a first electrode plate 71 of a first storage capacitor, and a second electrode plate 72 of a second storage capacitor. The second conductive layer pattern may include at least a first light-emitting signal line 31, a second light-emitting signal line 32, a repair line 33, a second shielding electrode 37, a third shielding electrode 38, a fourth shielding electrode 39, a third electrode plate 73 of a first storage capacitor, a fourth electrode plate 74 of a second storage capacitor, a first initial signal line 81, and a second reference signal line 92. The plurality of vias on the fourth insulating layer may include at least a first via V1 to a twenty-third via V23. The position, structure and connection relationship of the above pattern are basically the same as those of the previous embodiment. The difference is that the second conductive layer of this embodiment does not have a first shielding electrode.

[0300] (22) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on a fourth insulating layer, such as... Figure 16A and Figure 16B As shown, Figure 16B for Figure 16A A schematic diagram of the third conductive layer.

[0301] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display substrate may include: a first connection electrode 41 to a ninth connection electrode 49, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a fifth scan signal line 65, a first power connection line 68, a second power connection line 69, a second initial signal line 82, and a first reference signal line 91. The structure of the third conductive layer in this exemplary embodiment is basically the same as that in the previous embodiment, except that in this embodiment, the second power connection line 69 is located between the first power connection line 68 and the fourth scan signal line 64, and the third conductive layer is provided with a first shielding electrode 36, which is an integral structure interconnected with the second power connection line 69.

[0302] In an exemplary embodiment, the second power connection line 69 may be located on one side of the third electrode plate 73 in the second direction Y, and between the first power connection line 68 and the fourth scan signal line 64. A second power connection block 69-1 is provided on the side of the second power connection line 69 near the first power connection line 68. The first end of the second power connection block 69-1 is connected to the second power connection line 69, and the second end of the second power connection block 69-1 extends towards the first power connection line 68. The second power connection block 69-1 is configured to connect to a subsequently formed second power line. In an exemplary embodiment, the second power connection block 69-1 may be disposed between the first circuit unit and the second circuit unit.

[0303] In an exemplary embodiment, the third conductive layer of at least one circuit unit may further include a first shielding electrode 36. The first shielding electrode 36 is connected to the second power connection line 69. The orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor T1 on the substrate, and the orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor T2 on the substrate. In an exemplary embodiment, the first shielding electrode 36 is configured to shield the influence of data voltage transitions on the first transistor T1 and the second transistor T2, preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0304] In an exemplary embodiment, the first shielding electrode 36 may include a first sub-electrode 36-3 and a second sub-electrode 36-4, both of which may be rectangular in shape. The first end of the first sub-electrode 36-3 is connected to the second power connection line 69, and the second end of the first sub-electrode 36-3 extends in a direction away from the second power connection line 69, i.e., extends in the opposite direction of the second direction Y. The orthographic projection of the second end of the first sub-electrode 36-3 onto the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor T1 in this circuit unit onto the substrate. The first end of the second sub-electrode 36-4 is connected to the second power connection line 69, and the second end of the second sub-electrode 36-4 extends in a direction away from the second power connection line 69. The orthographic projection of the second end of the second sub-electrode 36-4 onto the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor T2 in this circuit unit onto the substrate.

[0305] In some possible exemplary embodiments, the middle portion of the first sub-electrode 36-3 is connected to the second power connection line 69, the first end of the first sub-electrode 36-3 extends in the opposite direction of the second direction Y, and the second end of the first sub-electrode 36-3 extends in the second direction Y. The orthographic projections of the first end and the second end of the first sub-electrode 36-3 on the substrate at least partially overlap with the orthographic projections of the semiconductor layer between the two gate electrodes of the first transistor T1 in this circuit unit on the substrate.

[0306] In some possible exemplary embodiments, the middle portion of the second sub-electrode 36-4 is connected to the second power supply connection line 69, the first end of the second sub-electrode 36-4 extends in the opposite direction of the second direction Y, and the second end of the second sub-electrode 36-4 extends in the second direction Y. The orthographic projections of the first and second ends of the second sub-electrode 36-4 on the substrate at least partially overlap with the orthographic projections of the semiconductor layer between the two gate electrodes of the second transistor T2 in this circuit unit on the substrate.

[0307] In an exemplary embodiment, the first shielding electrode 36 and the second power connection line 69 are an integral structure that is interconnected.

[0308] (23) Form the pattern of the fifth insulating layer and the fourth conductive layer, such as Figure 14 As shown. The position, structure, and connection relationship of the above patterns are basically the same as those in the previous embodiments, and will not be repeated here.

[0309] Subsequent fabrication processes may include forming a first planarization layer pattern, on which a plurality of anode vias are provided. The orthographic projection of the anode vias onto the substrate is within the range of the orthographic projection of the anode connecting electrode onto the substrate. The first planarization layer within the anode vias is removed to expose the surface of the anode connecting electrode. The anode vias are configured to allow the subsequently formed anode to be connected to the anode connecting electrode through the vias.

[0310] Thus, the driving circuit layer of this embodiment is fabricated on the substrate. In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer and an encapsulation structure layer can be fabricated sequentially on the driving circuit layer, which will not be described in detail here.

[0311] Figure 17 This is a schematic diagram of another planar structure of a display substrate, illustrating the structure of the pixel driving circuit in three circuit units (first circuit unit, second circuit unit, and third circuit unit) of the display substrate, as an exemplary embodiment of the present disclosure. Figure 17 As shown, the main structure of the pixel driving circuit in this exemplary embodiment is basically the same as that in the previous embodiment. The difference is that in this embodiment, the first power connection line 68 is located between the second power connection line 69 and the fourth scan signal line 64, and the first shielding electrode 36 and the first power connection line 68 are an integral structure that are interconnected.

[0312] Figure 18 for Figure 17 An enlarged view of the first and second storage capacitor regions. (See image below.) Figure 18 As shown, at least one circuit unit may further include a first shielding electrode 36, which is connected to a first power supply connection line 68. The orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first transistor T1 on the substrate, and the orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the second transistor T2 on the substrate. In an exemplary embodiment, the first shielding electrode 36 is configured to shield the influence of data voltage transitions on the first transistor T1 and the second transistor T2, preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0313] In an exemplary embodiment, the first shielding electrode 36 includes a third sub-electrode 36-5 and a fourth sub-electrode 36-6. The first end of the third sub-electrode 36-5 is connected to the first power connection line 68, and the second end of the third sub-electrode 36-5 extends in a direction away from the first power connection line 68, i.e., extends in the opposite direction of the second direction Y. The orthographic projection of the second end of the third sub-electrode 36-5 onto the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the first transistor T1 in this circuit unit onto the substrate. The first end of the fourth sub-electrode 36-6 is connected to the first power connection line 68, and the second end of the fourth sub-electrode 36-6 extends in a direction away from the first power connection line 68. The orthographic projection of the second end of the fourth sub-electrode 36-6 onto the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the second transistor T2 in this circuit unit onto the substrate.

[0314] In some possible exemplary embodiments, the middle portion of the third sub-electrode 36-5 is connected to the first power supply connection line 68, the first end of the third sub-electrode 36-5 extends in the opposite direction of the second direction Y, and the second end of the third sub-electrode 36-5 extends in the second direction Y. The orthographic projections of the first and second ends of the third sub-electrode 36-5 on the substrate at least partially overlap with the orthographic projections of the node between the two gate electrodes of the first transistor T1 in this circuit unit on the substrate.

[0315] In some possible exemplary embodiments, the middle portion of the fourth sub-electrode 36-6 is connected to the first power supply connection line 68, the first end of the fourth sub-electrode 36-6 extends in the opposite direction of the second direction Y, and the second end of the fourth sub-electrode 36-6 extends in the second direction Y. The orthographic projections of the first and second ends of the fourth sub-electrode 36-6 onto the substrate at least partially overlap with the orthographic projections of the node between the two gate electrodes of the second transistor T2 in this circuit unit onto the substrate.

[0316] In an exemplary embodiment, the first shielding electrode 36 and the first power connection line 68 are an integral structure that are interconnected.

[0317] In an exemplary embodiment, at least one circuit unit may further include a second shielding electrode 37, a third shielding electrode 38, and a fourth shielding electrode 39, the shape, position, and connection structure of which are substantially the same as those in the foregoing embodiments.

[0318] The following is an exemplary description of the fabrication process of the display substrate. In an exemplary embodiment, taking three circuit units in the nth unit row as an example, the fabrication process of the display substrate in this embodiment may include the following operations.

[0319] (31) A pattern of a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, and a fourth insulating layer is formed sequentially. The semiconductor layer pattern may include at least a first active connection line 10, a second active connection line 20, and a first active layer 11 to a ninth active layer 19. The first conductive layer pattern may include at least a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a fifth gate electrode 25, a sixth gate electrode 26, a ninth gate electrode 29, a first scan signal line 61, a first electrode plate 71 of a first storage capacitor, and a second electrode plate 72 of a second storage capacitor. The second conductive layer pattern may include at least a first light-emitting signal line 31, a second light-emitting signal line 32, a repair line 33, a second shielding electrode 37, a third shielding electrode 38, a fourth shielding electrode 39, a third electrode plate 73 of a first storage capacitor, a fourth electrode plate 74 of a second storage capacitor, a first initial signal line 81, and a second reference signal line 92. The plurality of vias on the fourth insulating layer may include at least a first via V1 to a twenty-third via V23. The position, structure and connection relationship of the above pattern are basically the same as those of the previous embodiment. The difference is that the second conductive layer of this embodiment does not have a first shielding electrode, and the thirteenth via V13 is configured to allow the subsequently formed connection electrode to be connected to the fourth electrode plate 74 through the via.

[0320] (32) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on a fourth insulating layer, such as... Figure 19A and Figure 19B As shown, Figure 19B for Figure 19A A schematic diagram of the third conductive layer.

[0321] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display substrate may include: a first connecting electrode 41 to a tenth connecting electrode 50, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a fifth scan signal line 65, a first power connection line 68, a second power connection line 69, a second initial signal line 82, and a first reference signal line 91. Except for the tenth connecting electrode 50, the first power connection line 68, and the second power connection line 69, the shape, position, and connection structure relationship of the above structure are basically the same as those in the previous embodiment, and will not be repeated here.

[0322] In an exemplary embodiment, the first power connection line 68 is located between the second power connection line 69 and the fourth scan signal line 64, and the first shielding electrode 36 and the first power connection line 68 are an integral structure that are interconnected.

[0323] In an exemplary embodiment, the first power connection line 68 may be located on one side of the third electrode plate 73 in the second direction Y. The second power connection line 69 may be located between the first power connection line 68 and the first reference signal line 91.

[0324] In an exemplary embodiment, each circuit unit may further include a first shielding electrode 36, which is connected to a first power supply connection line 68. The orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor T1 on the substrate, and the orthographic projection of the first shielding electrode 36 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor T2 on the substrate. In this exemplary embodiment, the first shielding electrode 36 is configured to shield the impact of data voltage transitions on the first transistor T1 and the second transistor T2, preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0325] In an exemplary embodiment, the first shielding electrode 36 includes a third sub-electrode 36-5 and a fourth sub-electrode 36-6, which may be rectangular in shape. The first end of the third sub-electrode 36-5 is connected to the first power connection line 68, and the second end of the third sub-electrode 36-5 extends in a direction away from the first power connection line 68, i.e., extends in the opposite direction of the second direction Y. The orthographic projection of the second end of the third sub-electrode 36-5 onto the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the first transistor T1 in this circuit unit onto the substrate. The first end of the fourth sub-electrode 36-6 is connected to the first power connection line 68, and the second end of the fourth sub-electrode 36-6 extends in a direction away from the first power connection line 68. The orthographic projection of the second end of the fourth sub-electrode 36-6 onto the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor T2 in this circuit unit onto the substrate.

[0326] In some possible exemplary embodiments, the middle portion of the third sub-electrode 36-5 is connected to the first power connection line 68, the first end of the third sub-electrode 36-5 extends in the opposite direction of the second direction Y, and the second end of the third sub-electrode 36-5 extends in the second direction Y. The orthographic projections of the first and second ends of the third sub-electrode 36-5 on the substrate at least partially overlap with the orthographic projections of the semiconductor layer between the two gate electrodes of the first transistor T1 in this circuit unit on the substrate.

[0327] In some possible exemplary embodiments, the middle portion of the fourth sub-electrode 36-6 is connected to the first power connection line 68, the first end of the fourth sub-electrode 36-6 extends in the opposite direction of the second direction Y, and the second end of the fourth sub-electrode 36-6 extends in the second direction Y. The orthographic projections of the first and second ends of the fourth sub-electrode 36-6 onto the substrate at least partially overlap with the orthographic projections of the semiconductor layer between the two gate electrodes of the second transistor T2 in this circuit unit onto the substrate.

[0328] In an exemplary embodiment, the first shielding electrode 36 and the first power connection line 68 are an integral structure that are interconnected.

[0329] In an exemplary embodiment, the tenth connection electrode 50 may be rectangular in shape and may be located between the first reference signal line 91 and the second power connection line 69. The tenth connection electrode 50 is connected to the fourth electrode plate 74 through a thirteenth via V13. In an exemplary embodiment, the tenth connection electrode 50 is configured to connect to the subsequently formed first power line.

[0330] (33) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer, wherein each circuit unit is provided with multiple vias, such as... Figure 20 As shown.

[0331] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate include at least: vias V31 to V35 and via V37. The positions, structures and connections of vias V31 to V34 are basically the same as those in the foregoing embodiments, and will not be repeated here.

[0332] In an exemplary embodiment, the orthographic projection of the 35th via V35 on the substrate is within the range of the orthographic projection of the 10th connecting electrode 50 on the substrate. The fifth insulating layer within the 35th via V35 is removed, exposing the surface of the 10th connecting electrode 50. The 35th via V35 is configured to allow a subsequently formed first power line to be connected to the 10th connecting electrode 50 through the via.

[0333] In an exemplary embodiment, the orthographic projection of the 37th via V37 onto the substrate can be located within the range of the orthographic projection of the third sub-electrode 36-5 onto the substrate. The fifth insulating layer within the 37th via V37 is removed, exposing the surface of the third sub-electrode 36-5. The 37th via V37 is configured to allow the subsequently formed first power line to connect to the first power connection line 68 through the via. Since the third sub-electrode 36-5 is connected to the first power connection line 68, the interconnection of the first power connection line 68 extending along the first direction X of the main body portion and the first power line 51 extending along the second direction Y of the main body portion is realized. This allows the first power line 51 and the first power connection line 68 to form a mesh structure on the display substrate for transmitting the first power signal. This not only effectively reduces the resistance of the first power line 51 and reduces the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improving display uniformity and enhancing display quality.

[0334] In an exemplary embodiment, at least one circuit unit may further include a thirty-sixth via V36. The orthographic projection of the thirty-sixth via V36 onto the substrate lies within the orthographic projection of the second power connection block 69-1 of the second power connection line 69 onto the substrate. The fifth insulating layer within the thirty-sixth via V36 is removed, exposing the surface of the second power connection block 69-1. The thirty-sixth via V36 is configured to allow a subsequently formed second power line to connect to the second power connection block 69-1 through this via. In an exemplary embodiment, the thirty-sixth via V36 may be located between the first circuit unit and the second circuit unit.

[0335] (34) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on a fifth insulating layer, such as... Figure 21A and 21B As shown, Figure 21B for Figure 21A A schematic diagram of the fourth conductive layer.

[0336] In an exemplary embodiment, the fourth conductive layer pattern of each circuit unit in the display substrate may include: a first power line 51, a data signal line 53, a reference signal connection line 54, and an anode connection electrode 55. The positions, structures, and connection relationships of the data signal line 53, the reference signal connection line 54, and the anode connection electrode 55 are substantially the same as in the aforementioned embodiments, and will not be described again here.

[0337] In an exemplary embodiment, a power shielding block 51-1 is provided on the side of the first power line 51 near the reference signal connection line 54. The first end of the power shielding block 51-1 is connected to the first power line 51, and the second end of the power shielding block 51-1 extends towards the reference signal connection line 54. The power shielding block 51-1 can be rectangular in shape, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first connecting electrode 41 on the substrate. Since the first connecting electrode 41 serves as the first node N1 in the pixel driving circuit, the constant-voltage power shielding block 51-1 can effectively shield the first node N1 from the influence of other signals in the pixel driving circuit, preventing other signals (such as data voltage jumps) from affecting the potential of the first node N1 in the pixel driving circuit, thus improving the display effect.

[0338] In an exemplary embodiment, the first power line 51 and the power shield block 51-1 can be an integral structure that is interconnected.

[0339] In an exemplary embodiment, the orthographic projection of the power shield block 51-1 onto the substrate may include the orthographic projection of the first connection electrode 41 onto the substrate.

[0340] In an exemplary embodiment, a third power connection block 51-2 is provided on the side of the first power line 51 near the reference signal connection line 54. The third power connection block 51-2 can be a strip shape extending along the first direction X. The first end of the third power connection block 51-2 is connected to the first power line 51, and the second end of the third power connection block 51-2 extends towards the reference signal connection line 54 and is connected to the tenth connection electrode 50 through the thirty-fifth via V35.

[0341] In an exemplary embodiment, the first power line 51 and the third power connection block 51-2 can be an integral structure that is interconnected.

[0342] In an exemplary embodiment, the fourth conductive layer pattern of each circuit unit in the display substrate may further include a fifth power connection block 51-3. The first end of the fifth power connection block 51-3 is connected to the first power line 51, and the second end of the fifth power connection block 51-3 extends towards the data signal line 53 within the circuit unit. The shape of the fifth power connection block 51-3 may be rectangular. The fifth power connection block 51-3 is connected to the first power connection line 68 through a thirty-seventh via V37. Since the fifth power connection block 51-3 is connected to the first power line 51, the first power connection line 68 extending along the first direction X of the main body and the first power line 51 extending along the second direction Y of the main body are interconnected. This allows the first power line 51 and the first power connection line 68 to form a mesh structure on the display substrate for transmitting the first power signal. This not only effectively reduces the resistance of the first power line 51 and decreases the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0343] Subsequent fabrication processes may include forming a first planarization layer pattern, on which a plurality of anode vias are provided. The orthographic projection of the anode vias onto the substrate is within the range of the orthographic projection of the anode connecting electrode onto the substrate. The first planarization layer within the anode vias is removed to expose the surface of the anode connecting electrode. The anode vias are configured to allow the subsequently formed anode to be connected to the anode connecting electrode through the vias.

[0344] Thus, the driving circuit layer of this embodiment is fabricated on the substrate. In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer and an encapsulation structure layer can be fabricated sequentially on the driving circuit layer, which will not be described in detail here.

[0345] As can be seen from the structure and fabrication process of the display substrate described above, this embodiment of the present disclosure, by setting a first power connection line, a second power connection line, a first power line, and a second power line, with the first power line and the first power connection line interconnected, forms a mesh structure on the display substrate for transmitting the first power signal. Similarly, the second power line and the second power connection line are interconnected, forming a mesh structure on the display substrate for transmitting the second power signal. This not only effectively reduces the resistance of the first and second power lines and decreases the voltage drop of the first and second power signals, but also effectively improves the uniformity of the first and second power signals in the display substrate, thereby enhancing display quality. Furthermore, by setting a shielding electrode connected to the first or second power connection line with a constant potential, this embodiment of the present disclosure can effectively shield the nodes between the two gate electrodes of the dual-gate transistor, ensuring the normal operation of the pixel driving circuit and improving the display effect.

[0346] This embodiment of the disclosure sets up a first reference signal line and a reference signal connection line, and the first reference signal line and the reference signal connection line are interconnected, so that the first reference signal line and the reference signal connection line form a mesh structure on the display substrate to transmit the first reference signal. This can not only effectively reduce the resistance of the first reference signal line and reduce the voltage drop of the first reference signal, but also effectively improve the uniformity of the first reference signal in the display substrate, effectively improve display uniformity, and improve display quality.

[0347] The embodiments disclosed herein construct a double-layer signal line by setting a first active connection line of the semiconductor layer and a first reference signal line of the third conductive layer. This can effectively reduce the voltage drop of the reference signal, improve the uniformity of the panel, avoid display defects in the display substrate, and ensure the display effect of the display substrate.

[0348] This embodiment of the present disclosure, by setting a first shielding electrode, a second shielding electrode, a third shielding electrode, and a fourth shielding electrode, can shield the effects of data voltage jumps on the first transistor T1, the second transistor T2, the fourth transistor T4, the ninth transistor T9, and critical nodes, thereby preventing data voltage jumps from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0349] This embodiment of the present disclosure effectively avoids other signals affecting the potential of the first node N1 and the fifth node N5 of the pixel driving circuit by setting a first power line and a power shielding block to shield the first node N1 and the fifth node N5 of the pixel driving circuit, thereby improving the display effect.

[0350] The embodiments disclosed herein achieve a more reasonable wiring layout by overlapping the second power connection line with the first initial signal line.

[0351] The preparation process disclosed herein is well compatible with existing preparation processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0352] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz, while the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0353] In an exemplary embodiment, the first, second, third, and fourth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first, second, third, fourth, and fifth insulating layers can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers. The first insulating layer is called a buffer layer, the second and third insulating layers are called gate insulating (GI) layers, the fourth insulating layer is called an interlayer insulating (ILD) layer, and the fifth insulating layer is called a passivation (PVX) layer. The first planarization layer can be made of organic materials, such as resin. The active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc. That is, this disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, or organic technology. The structure and fabrication process described above are merely illustrative examples. In exemplary embodiments, the corresponding structure and patterning processes can be modified and added or reduced according to actual needs, and this disclosure does not limit the scope of the invention.

[0354] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0355] This disclosure also provides a display device, which includes the display substrate of any of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0356] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit the invention. Any person skilled in the art may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope of this disclosure; however, the scope of patent protection for this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising a driving circuit layer disposed on a base and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base, the driving circuit layer comprising at least a plurality of circuit units, at least one first power connection line and at least one second power connection line extending along a first direction, at least one first power line and at least one second power line extending along a second direction, at least one circuit unit comprising a pixel driving circuit, the first power line being connected to the pixel driving circuit and configured to continuously supply a high-level signal to the pixel driving circuit, the light-emitting structure layer comprising at least a plurality of light-emitting units, at least one light-emitting unit comprising a cathode, the second power line being connected to the cathode and configured to continuously supply a low-level signal to the cathode; the first power line being connected to the first power connection line to form a mesh structure for transmitting a first power signal, and the second power line being connected to the second power connection line to form a mesh structure for transmitting a second power signal, the first direction intersecting the second direction. The pixel driving circuit comprises a first shielding electrode and at least one double-gate transistor, a projection of the first shielding electrode on the base at least partially overlapping a node between two gate electrodes of the double-gate transistor on the base; the first shielding electrode being connected to the first power connection line; or the first shielding electrode being connected to the second power connection line. 2.The display substrate of claim 1, wherein, The at least one double-gate transistor comprises a first initialization transistor and a compensation transistor, a first electrode of the first initialization transistor being connected to a first initialization signal line, a first electrode of the compensation transistor being connected to a second electrode of the first initialization transistor, a projection of the first shielding electrode on the base at least partially overlapping a node between two gate electrodes of the first initialization transistor on the base, and a projection of the first shielding electrode on the base at least partially overlapping a node between two gate electrodes of the compensation transistor on the base. 3.The display substrate of claim 2, wherein, The first shielding electrode and the second power connection line are an integrated structure connected to each other. 4.The display substrate of claim 3, wherein, The second power connection line is located on a side of the first power connection line close to the first initialization transistor and the compensation transistor. 5.The display substrate of claim 4, wherein, The first shielding electrode comprises at least a first sub-electrode and a second sub-electrode, a first end of the first sub-electrode being connected to the second power connection line, a second end of the first sub-electrode extending towards a direction close to the first power connection line, a projection of the second end of the first sub-electrode on the base at least partially overlapping the node between the two gate electrodes of the first initialization transistor on the base; a first end of the second sub-electrode being connected to the second power connection line, a second end of the second sub-electrode extending towards a direction close to the first power connection line, a projection of the second end of the second sub-electrode on the base at least partially overlapping the node between the two gate electrodes of the compensation transistor on the base. 6.The display substrate of claim 2, wherein, The first shielding electrode and the first power supply connecting line are an integral structure connected with each other. 7.The display substrate of claim 6, wherein, The first power supply connecting line is located on the side of the second power supply connecting line close to the first initialization transistor and the compensation transistor. 8.The display substrate of claim 7, wherein, The first shielding electrode comprises at least a third sub-electrode and a fourth sub-electrode, a first end of the third sub-electrode is connected with the first power supply connecting line, a second end of the third sub-electrode extends towards the direction close to the second power supply connecting line, and a normal projection of the second end of the third sub-electrode on the substrate at least partially overlaps with a normal projection of a node between two gate electrodes of the first initialization transistor on the substrate. A first end of the fourth sub-electrode is connected with the first power supply connecting line, a second end of the fourth sub-electrode extends towards the direction close to the second power supply connecting line, and a normal projection of the second end of the fourth sub-electrode on the substrate at least partially overlaps with a normal projection of a node between two gate electrodes of the compensation transistor on the substrate. 9.The display substrate of claim 2, wherein, The pixel driving circuit further comprises a first storage capacitor and a second storage capacitor, the first storage capacitor comprises at least a first plate and a third plate, and a normal projection of the first plate on the substrate at least partially overlaps with a normal projection of the third plate on the substrate. The second storage capacitor comprises at least a second plate and a fourth plate, and a normal projection of the second plate on the substrate at least partially overlaps with a normal projection of the fourth plate on the substrate. The second plate is connected with the third plate, the fourth plate is connected with the first power supply connecting line, and the first shielding electrode is connected with the fourth plate. 10.The display substrate of claim 9, wherein, The first shielding electrode and the fourth plate are an integral structure connected with each other. 11.The display substrate of claim 9, wherein, The first shielding electrode comprises a first extension segment and a first shielding segment, the first extension segment has a shape of a strip extending along the second direction, the first shielding segment has a shape of a strip extending along the first direction, a first end of the first extension segment is connected with the fourth plate, and a second end of the first extension segment is connected with the first shielding segment; the first shielding segment comprises a first shielding end and a second shielding end, a normal projection of the first shielding end on the substrate at least partially overlaps with a normal projection of a node between two gate electrodes of the first initialization transistor in the circuit unit on the substrate, and a normal projection of the second shielding end on the substrate at least partially overlaps with a normal projection of a node between two gate electrodes of the compensation transistor in the adjacent circuit unit on the substrate. 12.The display substrate of claim 1, wherein, The transistor of the at least one double-gate structure further comprises a data writing transistor and a first reference transistor, a first electrode of the data writing transistor is connected with a data signal line, a first electrode of the first reference transistor is connected with a first reference signal line, and a second electrode of the data writing transistor and a second electrode of the first reference transistor are connected. The pixel driving circuit further comprises a second shielding electrode, which is arranged between the first electrode of the data writing transistor and the second electrode of the data writing transistor. 13.The display substrate of claim 1, wherein, The transistor of the at least one double-gate structure further comprises a data write transistor and a first reference transistor, a first electrode of the data write transistor is connected with a data signal line, a first electrode of the first reference transistor is connected with a first reference signal line, a second electrode of the data write transistor and a second electrode of the first reference transistor are connected; The pixel driving circuit further comprises a third shielding electrode and a fourth shielding electrode, a projection of the third shielding electrode on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the data write transistor on the substrate, and a projection of the fourth shielding electrode on the substrate at least partially overlaps with a projection of a node between two gate electrodes of the first reference transistor on the substrate. 14.The display substrate of claim 2, wherein, The second power supply connection line at least partially overlaps with a projection of the first initial signal line on the substrate.

15. The display substrate of any of claims 1 to 14, wherein, In a plane perpendicular to the display substrate, the driving circuit layer comprises a plurality of conductive layers; the first power supply line and the first power supply connection line are arranged in different conductive layers, and the first power supply line and the first power supply connection line are connected through a via hole; the second power supply line and the second power supply connection line are arranged in different conductive layers, and the second power supply line and the second power supply connection line are connected through a via hole. 16.The display substrate of claim 15, wherein, The first power supply connection line and the second power supply connection line are arranged in the same layer, and the first power supply line and the second power supply line are arranged in the same layer.

17. The display substrate of claim 15, wherein, The plurality of conductive layers at least comprise a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence along a direction away from the substrate; the first power supply connection line and the second power supply connection line are arranged in the third conductive layer, and the first power supply line and the second power supply line are arranged in the fourth conductive layer.

18. The display substrate of any of claims 1 to 14, wherein, In a plane perpendicular to the display substrate, the driving circuit layer comprises a plurality of conductive layers; the plurality of conductive layers at least comprise a first conductive layer, a second conductive layer and a third conductive layer arranged in sequence along a direction away from the substrate; the first shielding electrode is arranged in the second conductive layer, or the first shielding electrode is arranged in the third conductive layer.

19. The display substrate of claim 18, wherein, The pixel driving circuit further comprises a first storage capacitor and a second storage capacitor, the first storage capacitor at least comprises a first plate and a third plate, and a projection of the first plate on the substrate at least partially overlaps with a projection of the third plate on the substrate; The second storage capacitor at least comprises a second plate and a fourth plate, a projection of the second plate on the substrate at least partially overlaps with a projection of the fourth plate on the substrate; the first plate and the second plate are arranged in the first conductive layer, and the third plate and the fourth plate are arranged in the second conductive layer.

20. A display device comprising: The display substrate comprises any one of the display substrates as claimed in any one of claims 1 to 19.

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