Temperature sensor and control method

Abstract

The invention discloses a temperature sensor and a control method, and the method comprises the steps: outputting a clock pulse signal to a pulse extractor and a non-overlapping clock and phase generator through a voltage-controlled ring oscillator, and then outputting a fractional pulse signal and a work control signal; a temperature sensing front end outputs a delay voltage signal according to the working control signal; carrying out linear transformation and chopping on the delay voltage signal through a time domain amplifier according to the working control signal, and outputting a delay pulse signal; outputting a pulse control signal according to the delay pulse signal through a phase frequency detector; performing voltage regulation on the notch filter through the charge pump according to the pulse control signal; outputting a control voltage signal according to the working control signal through a notch filter; by adopting a fractional type charge discharge scheme and introducing a time domain amplifier with a chopping function, compact design, low power consumption and high resolution of the sensor are realized under low voltage, and the temperature sensor can be widely applied to the technical field of temperature sensor design.

Description

Technical Field

[0001] The invention relates to the field of temperature sensor design, in particular to a temperature sensor and a control method thereof. Background Art

[0002] Resistor-based temperature sensors have a compact footprint and offer high accuracy and an excellent resolution figure of merit (R-FoM) (<100fJ·K 2 ). Compared with sensing elements based on active devices that require biasing (such as bipolar transistors BJT and field effect transistors MOSFET), the resistor type has no restrictions on the power supply voltage VDD. This feature helps to design resistor-based temperature sensors in advanced processes with an operating voltage VDD<1V (for example, 0.9V in the selected 28nm process) to achieve an integrated temperature sensing solution. However, in the traditional temperature sensor design, there are problems such as high power consumption, large area and difficulty in maintaining accuracy due to the non-ideal characteristics of transistors (gate tunneling, leakage current, short channel effect, etc.). Summary of the invention

[0003] The purpose of the present invention is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0004] To this end, an object of an embodiment of the present invention is to provide a temperature sensor and a control method, which achieves compact design, low power consumption and high resolution of the sensor at low voltage by adopting a fractional charge discharge scheme and introducing a time domain amplifier with a chopping function.

[0005] The first technical solution adopted by the present invention is:

[0006] A temperature sensor comprises a temperature sensing front end, a time domain amplifier, a frequency detector, a charge pump, a notch filter, a voltage-controlled ring oscillator, a pulse extractor, and a non-overlapping clock and phase generator, wherein the temperature sensing front end and the frequency detector are both connected to the time domain amplifier, the frequency detector and the notch filter are both connected to the charge pump, the notch filter and the pulse extractor are both connected to the voltage-controlled ring oscillator, the temperature sensing front end, the time domain amplifier, the notch filter, the voltage-controlled ring oscillator, and the pulse extractor are all connected to the non-overlapping clock and phase generator, the voltage-controlled ring oscillator is used to output a clock pulse signal to the pulse extractor and the non-overlapping clock and phase generator, and the pulse extractor is used to generate a pulse signal based on the pulse signal. A fractional pulse signal is output according to the clock pulse signal, the non-overlapping clock and phase generator is used to output a working control signal according to the clock pulse signal and the fractional pulse signal, the temperature sensor front end is used to output a delayed voltage signal according to the working control signal, the time domain amplifier is used to perform linear transformation and chopping on the delayed voltage signal according to the working control signal, and output a delayed pulse signal, the frequency detector and phase detector is used to output a pulse control signal according to the delayed pulse signal, the charge pump is used to perform voltage regulation on the notch filter according to the pulse control signal, the notch filter is used to output a control voltage signal according to the working control signal, and the voltage-controlled ring oscillator is also used to adjust the frequency of the clock pulse signal according to the control voltage signal.

[0007] Further, the voltage-controlled ring oscillator includes a control voltage signal input terminal, a ring inverter chain, a level converter array, and a bias reference current input terminal. The bias reference current input terminal, the ring inverter chain, the control voltage signal input terminal, and the level converter are all connected to the ring inverter chain. The ring inverter chain includes multiple inverters. The control voltage input terminal is used to input the control voltage signal into the ring inverter chain. The bias reference current input terminal is used to provide a bias reference current for the ring inverter chain. The ring inverter chain is used to determine the delay between the multiple inverters according to the bias reference current. The ring inverter chain is also used to adjust the delay between the multiple inverters according to the control voltage signal. The ring inverter chain is also used to output a delayed oscillation signal according to the delay between the multiple inverters. The level converter array is used to convert the delayed oscillation signal into the clock pulse signal.

[0008] Furthermore, the pulse extractor includes a plurality of logic gates, and the plurality of logic gates are used to output fractional pulse signals according to the clock pulse signal.

[0009] Furthermore, the working control signal specifically includes a reset control signal, a discharge control signal, an amplification control signal, a chopping control signal, a holding control signal and a sampling control signal.

[0010] Further, the temperature extraction front end includes a first discharge switch, a second discharge switch, a first reset switch, a second reset switch, a first capacitor, a second capacitor, a first temperature-sensitive resistor and a second temperature-sensitive resistor. The first temperature-sensitive resistor, the first reset switch and the time domain amplifier are all connected to the upper plate of the first capacitor, the second temperature-sensitive resistor, the second reset switch and the time domain amplifier are all connected to the lower plate of the second capacitor, the first temperature-sensitive resistor is connected to the first discharge switch, the second temperature-sensitive resistor is connected to the second discharge switch, the first discharge switch, the second reset switch, the lower plate of the first capacitor and the upper plate of the second capacitor are all grounded, the second discharge switch and the first reset switch are both connected to a power supply, the first reset switch and the second reset switch are used to control the charging time of the first capacitor and the second capacitor according to the working control signal, the first discharge switch and the second discharge switch are used to control the discharge time of the first capacitor and the second capacitor according to the working control signal, and the first capacitor and the second capacitor are used to output the delayed voltage signal.

[0011] Furthermore, the first temperature-sensitive resistor includes 5 layers of stacked metal resistors, an upper shielding layer and a lower shielding layer, and the structure of the second temperature-sensitive resistor is the same as that of the first temperature-sensitive resistor.

[0012] Further, the time domain amplifier includes a first field effect tube, a second field effect tube, a third field effect tube, a fourth field effect tube, a fifth field effect tube, a sixth field effect tube, a first amplifying switch, a second amplifying switch, a third amplifying switch, a fourth amplifying switch, a third capacitor, a fourth capacitor, a bias voltage input terminal, an amplified signal input terminal, a first differential voltage input terminal, a second differential voltage input terminal, a first common mode voltage input terminal, a second common mode voltage input terminal, a first differential pulse output terminal, a second differential pulse output terminal, a first chopper and a second chopper, the gate of the sixth field effect tube is connected to the bias voltage input terminal, the source of the sixth field effect tube is grounded, the drain of the sixth field effect tube is connected to the source of the third field effect tube, the gate of the third field effect tube, the gate of the fourth field effect tube and the gate of the fifth field effect tube are all connected to the amplified signal input terminal, the source of the first field effect tube and the source of the second field effect tube are both connected to the third The drain of the first field effect transistor is connected, the drain of the first field effect transistor, the drain of the fourth field effect transistor and the first differential pulse output terminal are all connected to the upper plate of the third capacitor, the drain of the second field effect transistor, the drain of the fifth field effect transistor and the second differential pulse output terminal are all connected to the upper plate of the fourth capacitor, the fourth field effect transistor and the fifth field effect transistor are both connected to a power supply, the lower plate of the third capacitor and the lower plate of the fourth capacitor are both grounded, the first common-mode voltage input terminal is connected to the first amplifying switch, the first differential voltage input terminal is connected to the second amplifying switch, the first amplifying switch and the second amplifying switch are both connected to the gate of the first field effect transistor, the second common-mode voltage input terminal is connected to the third amplifying switch, the second differential voltage input terminal is connected to the fourth amplifying switch, and the third amplifying switch and the fourth amplifying switch are both connected to the gate of the second field effect transistor.

[0013] Further, the notch filter includes a sampling control switch, a holding control switch, a fifth capacitor, a sixth capacitor and a seventh capacitor, the fifth capacitor and the sixth capacitor are both connected to the sampling control switch, the sixth capacitor and the seventh capacitor are both connected to the holding control switch, the sampling control switch and the holding control switch are both used to open and close according to the working control signal, the fifth capacitor is used to output an integrated voltage signal, the sixth capacitor is used to sample the integrated voltage signal and output a sampled voltage signal, and the seventh capacitor is used to hold the sampled voltage signal and output a control voltage signal.

[0014] Further, the pulse control signal includes a pull-up pulse signal and a pull-down pulse signal, and the frequency detector and the charge pump are specifically used for:

[0015] Detecting the phase difference of the delayed pulse signal by the phase frequency detector;

[0016] When the phase difference is positive, the frequency detector and phase detector are used to output a pull-up pulse signal to the charge pump, and the charge pump is used to charge the fifth capacitor;

[0017] When the phase difference is negative, a pull-down pulse signal is outputted through the phase frequency detector, and the fifth capacitor is discharged through the charge pump.

[0018] The second technical solution adopted by the present invention is:

[0019] A method for controlling a temperature sensor, which is implemented by the temperature sensor as described above, is characterized by comprising the following steps:

[0020] Outputting a clock pulse signal to the pulse extractor and the non-overlapping clock and phase generator through the voltage-controlled ring oscillator;

[0021] Outputting a fractional pulse signal according to the clock pulse signal by the pulse extractor;

[0022] Outputting a working control signal according to the clock pulse signal and the fractional pulse signal through the non-overlapping clock and phase generator;

[0023] Outputting a delayed voltage signal according to the working control signal through the temperature sensing front end;

[0024] The time domain amplifier performs linear transformation and chopping on the delayed voltage signal according to the working control signal, and outputs a delayed pulse signal;

[0025] Outputting a pulse control signal according to the delayed pulse signal through the phase frequency detector;

[0026] Performing voltage regulation on the notch filter according to the pulse control signal by the charge pump;

[0027] Outputting a control voltage signal according to the working control signal through the notch filter;

[0028] The frequency of the clock pulse signal is adjusted according to the control voltage signal by the voltage-controlled ring oscillator.

[0029] The beneficial effects of the present invention are as follows: the present invention adopts a fractional charge discharge scheme to extract fractional pulses from a voltage-controlled ring oscillator, and uses only one fractional pulse for discharge in each amplification cycle, thereby greatly shortening the discharge time and reducing the demand for the sensor resistance area, thereby reducing the overall area of ​​the sensor while maintaining power consumption; at the same time, by introducing a time domain amplifier with a chopping function to process the input of the temperature sensor front end, the DC offset voltage and 1 / f noise are effectively eliminated, and the sensor personal factor is realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A system schematic diagram of a temperature sensor provided by an embodiment of the present invention;

[0031] Figure 2 A signal timing diagram of a temperature sensor provided by an embodiment of the present invention;

[0032] Figure 3 An area division diagram of a temperature sensor provided by an embodiment of the present invention;

[0033] Figure 4 A diagram showing the area distribution ratio of a temperature sensor provided by an embodiment of the present invention

[0034] Figure 5 A relationship diagram between temperature and output frequency of a temperature sensor provided by an embodiment of the present invention;

[0035] Figure 6 A relationship diagram between temperature and temperature error of a temperature sensor provided by an embodiment of the present invention;

[0036] Figure 7 A temperature error diagram of a temperature sensor provided by an embodiment of the present invention after fitting with a third-order polynomial;

[0037] Figure 8 A temperature error diagram of a temperature sensor provided by an embodiment of the present invention after single-point and two-point calibration;

[0038] Fig. 9 A diagram showing the relationship between power supply and power of a temperature sensor provided by an embodiment of the present invention;

[0039] Fig.10 A diagram showing the relationship between power supply and temperature error of a temperature sensor provided by an embodiment of the present invention;

[0040] Fig.11 A resolution comparison diagram of a temperature sensor provided by an embodiment of the present invention before and after using chopping technology;

[0041] Fig.12A schematic diagram of the structure of a voltage-controlled ring oscillator provided in an embodiment of the present invention;

[0042] Fig.13 A schematic diagram of the structure of a pulse extractor provided in an embodiment of the present invention;

[0043] Fig.14 A timing diagram of a fractional pulse signal and a multi-level clock cycle signal provided by an embodiment of the present invention;

[0044] Fig.15 A schematic diagram of the structure of a metal wire resistor provided by an embodiment of the present invention;

[0045] Fig.16 A schematic diagram of the structure of a time domain amplifier provided by an embodiment of the present invention;

[0046] Fig.17 A schematic diagram of the working principle of the time domain amplifier provided by an embodiment of the present invention;

[0047] Fig.18 A comparison diagram of the effects before and after using the chopping technology provided by an embodiment of the present invention; Fig.19 A schematic diagram of the steps of a temperature sensor control method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limitations of the present invention. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0049] In the description of the present invention, the meaning of "a plurality" is two or more than two. If there is a description of "a first" or "a second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features. In addition, unless otherwise defined, all technical and scientific terms used in this document have the same meaning as those commonly understood by those skilled in the art.

[0050] Reference Figure 1The embodiment of the present invention provides a temperature sensor, which is characterized by comprising a temperature sensing front end, a time domain amplifier, a frequency detector, a charge pump, a notch filter, a voltage-controlled ring oscillator, a pulse extractor, and a non-overlapping clock and phase generator. The temperature sensing front end and the frequency detector are both connected to the time domain amplifier, the frequency detector and the notch filter are both connected to the charge pump, the notch filter and the pulse extractor are both connected to the voltage-controlled ring oscillator, the temperature sensing front end, the time domain amplifier, the notch filter, the voltage-controlled ring oscillator, and the pulse extractor are all connected to the non-overlapping clock and phase generator, and the voltage-controlled ring oscillator is used to output a clock pulse signal to the pulse extractor and the non-overlapping clock and phase generator. The pulse extractor is used to output a fractional pulse signal according to the clock pulse signal, the non-overlapping clock and phase generator is used to output a working control signal according to the clock pulse signal and the fractional pulse signal, the temperature sensor front end is used to output a delayed voltage signal according to the working control signal, the time domain amplifier is used to perform linear transformation and chopping on the delayed voltage signal according to the working control signal, and output a delayed pulse signal, the frequency detector and phase detector is used to output a pulse control signal according to the delayed pulse signal, the charge pump is used to adjust the voltage of the notch filter according to the pulse control signal, the notch filter is used to output a control voltage signal according to the working control signal, and the voltage-controlled ring oscillator is also used to adjust the frequency of the clock pulse signal according to the control voltage signal.

[0051] Specifically, refer to Figure 1 The CMOS temperature sensor based on fractional charge discharge proposed in the embodiment of the present invention adopts a frequency locked loop (FLL) as a detection temperature sensing resistor (R M , 25kΩ) temperature readout circuit, including temperature sensing front end, time domain amplifier (TDA), phase frequency detector (PFD), charge pump (CP), notch filter, 5-level voltage controlled ring oscillator (VCRO), pulse extractor (PE) and non-overlapping clock and phase generator. The temperature sensing front end includes a pair of R M C filter, where C (1.4pF) is a MOM capacitor, and its temperature coefficient TC (~50ppm / ℃) is negligible. FLL can detect the temperature-dependent time constant of the filter (τ=R M C, or 35ns at 25°C), this is because it can output the frequency (F OUT ) is locked at a fixed ratio of τ by a one-time adjustment after the sensor is manufactured to adjust the bias current (I VCRO ) and adjust the center frequency F OUT Period (T OUT ), so that T OUT In the stable state, it is locked at 7τ, at which point F OUT =4MHz, where R M C filter output (VRC+ / - ) is equal to 0.5V DD , control voltage signal V C =0.5V DD The working process of this sensor is that in the reset phase (RST), the FLL precharges C to V DD / V SS In the discharge phase (DIS), R M The C filter will discharge C within 0.7τ and output a delayed voltage signal (V i+ / - ), in the initial state, R M The C filter can discharge C to 0.5V within 0.7τ DD , delayed voltage signal (V i+ / - ) has no difference. When the external temperature changes, τ will also change, resulting in R M The delayed voltage signal (V i+ / - ) to generate the difference. When DIS becomes low, the FLL enters the amplification stage (AMP), where TDA delays the voltage signal (V i+ / - ) is converted into a delayed pulse signal (V O+ / - );V O+ / - The differential delay between d ) and Vi + / - Then, the FLL generates a pair of pull-up or pull-down (UP / DN) pulses through the PFD, and CP controls the capacitor C according to UP / DN. INT Perform charge and discharge integration to generate an integrated voltage signal V INT The notch filter is based on the sampling control signal (Ф S )Hold control signal (Ф H ) respectively control capacitor C M and capacitor C H V INT Perform sampling and holding, and output the sampling voltage signal V M and control voltage signal V C . Control voltage signal V C Control VCRO and relock its period to a fixed ratio of τ, at which point the output frequency F of VCRO OUT It is the indication signal of temperature change information. At the same time, VCRO's five-level delay output (Φ 1-5 ) will be sent to the pulse extractor and non-overlapping clock and phase generator. The former extracts each level output of VCRO through the NAND gate and NOR gate to obtain 10 fractional pulse signals (D 1-10 ), the width of each pulse is T OUT Each pulse is used to control the discharge of C in the temperature sensing front end, which is based on the first stage output of VCRO (Φ 1) and D 1-10 , output a series of control signals, including reset control signal (RST), discharge control signal (DIS), amplification control signal (AMP), chopping control signal (CHP), hold control signal (Ф H ), sampling control signal (Ф S ), used to control the switching of different modules in each cycle. The timing of each signal is as follows Figure 2 shown.

[0052] In the design of the fractional charge discharge scheme, the embodiment of the present invention uses the 5-level delay output (Φ 1-5 ) in an F OUT 10 pulses are generated in one cycle (D 1-10 ), the width of each pulse is T OUT 10% of the original value, and use one of the pulses to discharge C and amplify and integrate. In the steady state, we can get T OUT =0.7τ·10. By shortening the discharge time, the power consumption of FLL is kept constant (which is similar to F OUT In the case of being proportional to R M The C value is reduced by 10 times, so that at the same F OUT The whole chip area is optimized by 2.6 times. In fact, due to the mismatch between the delay units inside the VCRO, if it is not properly handled, D 1-10 The pulse widths between them will be unequal, which will lead to inaccurate output of the temperature sensor. To solve this problem, the embodiment of the present invention selects D 1-10 The discharge of C occurs in 10 separate comparison cycles (CMP); 1-10 The sum of the widths is equal to T OUT , this feature ensures that the total duration of 10 consecutive discharges remains stable despite mismatch and process / voltage variations.

[0053] In terms of chopping, the embodiments of the present invention amplify the output of the sensor front end by using a TDA with a chopping function without the need to perform chopping at the comparator, thereby avoiding the problem that the chopping caused by the nonlinear quantization of the comparator cannot eliminate the 1 / f noise and DC offset of the comparator, and avoiding introducing noise and inaccuracy into the sensor output.

[0054] It can be recognized that the embodiment of the present invention adopts a fractional charge discharge scheme to extract fractional pulses from the voltage-controlled ring oscillator, and only uses one fractional pulse for discharge in each amplification cycle, which greatly shortens the discharge time and reduces the demand for the sensor resistance area, thereby reducing the overall area of ​​the sensor while maintaining power consumption; at the same time, by introducing a time domain amplifier with a chopping function to process the input of the temperature sensor front end, the DC offset voltage and 1 / f noise are effectively eliminated, and the sensor personal factor is achieved. Specifically, the embodiment of the present invention implements a temperature sensor in a 28nm CMOS process, and its structure is as follows Figure 3 As shown in the figure, the symbols represent: A: front end, E: bias reference source, B: time domain amplifier, F: voltage controlled ring oscillator, C: frequency detector, G: notch filter, D: charge pump, H: phase generation and pulse extractor, and its area is 4,100μm 2 , each component area occupies Figure 4 As shown, 44.6% is occupied by the notch filter. In the performance test, the frequency and temperature error is as follows Figure 5 As shown, the average F OUT The range is from 4.1MHz (-40℃) to 2.8MHz (125℃), corresponding to an average TC of 0.22% / ℃, which is similar to R M The TC of the sensor is very close. The nonlinear error of the sensor after the first-order fitting is as follows Figure 6 as shown; Figure 8 and Figure 7 The temperature errors after 1-point and 2-point calibration and third-order polynomial fitting are ±1.5℃ (1.8%) and ±0.2℃ (0.24%) respectively. Fig. 9 As shown, at room temperature, when V DD When the voltage is 0.8V, the power consumption is 10.5μW, of which VCRO accounts for 31% (from simulation verification). Fig.10 As shown in Figure 2, the sensor achieves an average power supply sensitivity of 0.34°C in the range of 0.7 to 0.9V. Fig.11 As shown, the chopping technique used by the TDA increases the resolution from 22.6 to 1.2 mK within a 3 ms conversion time. RMS , and finally achieved 45fJ·K 2 R-FoM.

[0055] As a further optional implementation, the voltage-controlled ring oscillator includes a control voltage signal input terminal, a ring inverter chain, a level converter array, and a bias reference current input terminal. The bias reference current input terminal, the ring inverter chain, the control voltage signal input terminal, and the level converter are all connected to the ring inverter chain. The ring inverter chain includes multiple inverters. The control voltage input terminal is used to input the control voltage signal into the ring inverter chain. The bias reference current input terminal is used to provide a bias reference current for the ring inverter chain. The ring inverter chain is used to determine the delay between multiple inverters according to the bias reference current. The ring inverter chain is also used to adjust the delay between multiple inverters according to the control voltage signal. The ring inverter chain is also used to output a delayed oscillation signal according to the delay between the multiple inverters. The level converter array is used to convert the delayed oscillation signal into a clock pulse signal.

[0056] Specifically, Fig.12 As shown in Figure 1, VCRO is a current hungry 5-stage ring oscillator. Each stage includes an inverter and a MOSCAP for frequency adjustment. After manufacturing, we perform a one-time trim to adjust the bias current (I VCRO ) and adjust the center frequency (when V C =0.5V DD ). C Control the delay of each level so that T OUT Locked at 7τ in steady state.

[0057] As a further optional implementation, the pulse extractor includes a plurality of logic gates, and the plurality of logic gates are used to output fractional pulse signals according to the clock pulse signal.

[0058] Specifically, in the embodiment of the present invention, in order to implement the proposed fractional discharge scheme, PE uses a logic gate to extract the fractional discharge from VCRO based on Φ 1-5 D 1-10 , thus ensuring the stability and accuracy of the temperature sensor. Fig.13 As shown, PE extracts the 5-stage delayed output (Φ) of VCRO through the NAND gate and NOR gate. 1-5 ), the connection of each logic gate is shown in the figure, in an F OUT 10 pulses are generated in one cycle (D 1-10 ), Φ 1-5 and D 1-10 The timing relationship is as follows Fig.14 shown.

[0059] As a further optional implementation, the working control signal specifically includes a reset control signal, a discharge control signal, an amplification control signal, a chopping control signal, a holding control signal and a sampling control signal.

[0060] Further as an optional embodiment, the temperature extraction front end includes a first discharge switch, a second discharge switch, a first reset switch, a second reset switch, a first capacitor, a second capacitor, a first thermistor and a second thermistor, the first thermistor, the first reset switch and the time domain amplifier are all connected to the upper plate of the first capacitor, the second thermistor, the second reset switch and the time domain amplifier are all connected to the lower plate of the second capacitor, the first thermistor is connected to the first discharge switch, the second thermistor is connected to the second discharge switch, the first discharge switch, the second reset switch, the lower plate of the first capacitor and the upper plate of the second capacitor are all grounded, the second discharge switch and the first reset switch are both connected to a power supply, the first reset switch and the second reset switch are used to control the charging time of the first capacitor and the second capacitor according to the working control signal, the first discharge switch and the second discharge switch are used to control the discharge time of the first capacitor and the second capacitor according to the working control signal, and the first capacitor and the second capacitor are used to output a delayed voltage signal.

[0061] As a further optional implementation, the first temperature-sensitive resistor includes 5 layers of stacked metal resistors, an upper shielding layer and a lower shielding layer, and the structure of the second temperature-sensitive resistor is the same as that of the first temperature-sensitive resistor.

[0062] Specifically, in this embodiment, it is best to select resistors with higher temperature coefficients (TC) for temperature sensing. In the 28nm process used in the present invention, there are two types of resistors with higher 1st-order TC (>0.1% / ℃), namely metal resistors with TC of about 0.2% / ℃ and metal silicide diffused resistors with TC of 0.15% / ℃. Although metal resistors have higher TC, their extremely low block resistance (0.5Ω / □) limits them from being used as temperature sensing front ends in mature processes (such as 180nm). However, as the spacing of metal interconnects in deep submicron processes decreases, coupled with the availability of multiple metal layers, it helps to reduce its overall area; the area of ​​the 25kΩ resistor implemented in this embodiment using 5 layers of metal is 12% smaller than the area constructed using metal silicide diffused resistors. Therefore, if Fig.15 As shown, this embodiment uses 5 layers of stacked metal resistors and two upper and lower shielding layers to implement the temperature sensing resistor (R M , 25kΩ). It is worth noting that metal interconnects are common in all CMOS processes. As the size of metal interconnects continues to shrink, metal interconnects can still be used as temperature sensors in more compact sizes in advanced processes.

[0063] As an optional implementation, the time domain amplifier includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a first amplifying switch, a second amplifying switch, a third amplifying switch, a fourth amplifying switch, a third capacitor, a fourth capacitor, a bias voltage input terminal, an amplified signal input terminal, a first differential voltage input terminal, a second differential voltage input terminal, a first common mode voltage input terminal, a second common mode voltage input terminal, a first differential pulse output terminal, a second differential pulse output terminal, a first chopper and a second chopper, the gate of the sixth field effect transistor is connected to the bias voltage input terminal, the source of the sixth field effect transistor is grounded, the drain of the sixth field effect transistor is connected to the source of the third field effect transistor, the gate of the third field effect transistor, the gate of the fourth field effect transistor and the gate of the fifth field effect transistor are all connected to the amplified signal input terminal, and the first field The source of the field effect tube and the source of the second field effect tube are both connected to the drain of the third field effect tube, the drain of the first field effect tube, the drain of the fourth field effect tube and the first differential pulse output end are all connected to the upper plate of the third capacitor, the drain of the second field effect tube, the drain of the fifth field effect tube and the second differential pulse output end are all connected to the upper plate of the fourth capacitor, the fourth field effect tube and the fifth field effect tube are both connected to the power supply, the lower plate of the third capacitor and the lower plate of the fourth capacitor are both grounded, the first common mode voltage input end is connected to the first amplifying switch, the first differential voltage input end is connected to the second amplifying switch, the first amplifying switch and the second amplifying switch are both connected to the gate of the first field effect tube, the second common mode voltage input end is connected to the third amplifying switch, the second differential voltage input end is connected to the fourth amplifying switch, and the third amplifying switch and the fourth amplifying switch are both connected to the gate of the second field effect tube.

[0064] Specifically, for V DD <1V deep submicron process, voltage mode amplifier with sufficient gain to support accurate comparison requires complex design. The comparator of digital FLL can operate at voltage as low as 0.4V. However, due to nonlinear quantization, the use of chopping technology on the comparator cannot eliminate the 1 / f noise and DC offset of the comparator, which will bring noise and inaccuracy to the sensor output. To this end, this embodiment uses TDA to convert the differential input voltage (ΔV i ) is converted to t d The structure of TDA is shown in 16, including a first field effect transistor M 1 , the second field effect tube M 2 , the third field effect tube M 3 , the fourth field effect tube M 4 、Fifth Field Effect Transistor M 5 、The sixth field effect tube M 0 , a first amplifying switch, a second amplifying switch, a third amplifying switch, a fourth amplifying switch, a third capacitor C L , the fourth capacitor CL , bias voltage input terminal V BN , amplified signal input terminal AMP, first differential voltage input terminal V i+ , the second differential voltage input terminal V i- , the first common mode voltage input terminal V CM , the second common mode voltage input terminal V CM , the first differential pulse output terminal V O+ , the second differential pulse output terminal V O- ,like Figure 1 As shown in FIG. 1 , the first chopper and the second chopper are located at both ends of the time domain amplifier. The changes of each signal in the TDA are shown in FIG. Fig.17 As shown, when AMP is low, the M 4 / 5 V L+ / - Charge to V DD , at this time V o+ / - All in V SS , when AMP becomes V DD When M 1 / 2 The discharge current I M1 / 2 V L+ / - Discharge to V SS , due to I M1 and I M2 The difference between ΔV i related, so V L+ / - The difference in discharge rate is also related to ΔV i Once V L+ / - falls below the inverter threshold, V o+ / - It will flip to V DD , where V o+ / - The delay between d ) is proportional to ΔVi. In this embodiment, t d / ΔVi is set to 3μs / V to ensure that the detection error caused by CP leakage is less than 0.1℃ at a high temperature of 125℃ and to suppress in-band noise. d Without quantization, chopping techniques can be applied to the TDA and the DC offset and 1 / f noise can be modulated to high frequencies. Fig.18 As shown, the simulated residual DC offset (1σ) of the TDA after chopping is 0.12mV, which is 20 times lower than the unchopped case (2.4mV).

[0065] Further as an optional implementation, the notch filter includes a sampling control switch, a holding control switch, a fifth capacitor, a sixth capacitor and a seventh capacitor, the fifth capacitor and the sixth capacitor are both connected to the sampling control switch, the sixth capacitor and the seventh capacitor are both connected to the holding control switch, the sampling control switch and the holding control switch are both used to open and close according to the working control signal, the fifth capacitor is used to output an integrated voltage signal, the sixth capacitor is used to sample the integrated voltage signal and output a sampled voltage signal, and the seventh capacitor is used to hold the sampled voltage signal and output a control voltage signal.

[0066] As an optional implementation, the pulse control signal includes a pull-up pulse signal and a pull-down pulse signal, and the frequency detector and the charge pump are specifically used for:

[0067] Specifically, the output of the TDA (at F OUT / 40 (the frequency is about 100kHz after chopping) to drive the PFD to output a pair of pull-up or pull-down UP / DN pulses. The polarity of the pulse is transmitted t d The notch filter receives the information from the control signal and controls the current sent to the notch filter. S ) and maintain (Ф H ) phase. In the case of the fractional discharge scheme and TDA chopping, the mismatch existing in VCRO and TDA will INT Therefore, the FLL samples the signal at a sampling frequency F every 10 cycles. OUT / 80(~50kHz) alternating Ф S and Φ H V INT Sampling and obtaining V C , thereby reducing the impact of such ripple on VCRO. The Ф generated by the non-overlapping clock module S and Φ H Unnecessary charge sharing between capacitors can be avoided.

[0068] The phase difference of the delayed pulse signal is detected by a phase frequency detector;

[0069] When the phase difference is positive, the pull-up pulse signal is output to the charge pump through the frequency detector and the fifth capacitor is charged through the charge pump;

[0070] When the phase difference is negative, a pull-down pulse signal is outputted through the frequency detector and the phase detector, and the fifth capacitor is discharged through the charge pump.

[0071] Reference Fig.19 The embodiment of the present invention provides a method for controlling a temperature sensor, which is implemented by the above-mentioned temperature sensor, and includes the following steps:

[0072] S101, outputting a clock pulse signal to a pulse extractor and a non-overlapping clock and phase generator through a voltage-controlled ring oscillator;

[0073] S102, outputting a fractional pulse signal according to the clock pulse signal through a pulse extractor;

[0074] S103, outputting a working control signal according to the clock pulse signal and the fractional pulse signal through a non-overlapping clock and phase generator;

[0075] S104, outputting a delayed voltage signal according to the working control signal through the temperature sensing front end;

[0076] S105, performing linear transformation and chopping on the delayed voltage signal according to the working control signal through a time domain amplifier, and outputting a delayed pulse signal;

[0077] S106, outputting a pulse control signal according to the delayed pulse signal through a frequency detector and a phase detector;

[0078] S107, regulating the voltage of the notch filter according to the pulse control signal through the charge pump;

[0079] S108, outputting a control voltage signal according to the working control signal through a notch filter;

[0080] S109 , adjusting the frequency of the clock pulse signal according to the control voltage signal through a voltage-controlled ring oscillator.

[0081] It can be understood that the contents of the above system embodiments are all applicable to the present method embodiments, the functions specifically implemented by the present method embodiments are the same as those of the above system embodiments, and the beneficial effects achieved are also the same as those achieved by the above system embodiments.

[0082] It should be appreciated that embodiments of the present invention may be implemented or enforced by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable memory. The above methods may be implemented in a computer program using standard programming techniques, including a non-transitory computer-readable storage medium configured with a computer program, wherein the storage medium so configured causes the computer to operate in a specific and predefined manner, according to the methods and drawings described in the specific embodiments. Each program may be implemented in a high-level procedural or object-oriented programming language to communicate with a computer system. However, if desired, the program may be implemented in an assembly or machine language. In any case, the language may be a compiled or interpreted language. In addition, the program may be run on a programmed dedicated integrated circuit for this purpose.

[0083] Furthermore, the operations of the processes described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The processes described herein (or variations and / or combinations thereof) may be performed under the control of one or more computer systems configured with executable instructions, and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that is executed collectively on one or more processors, by hardware, or a combination thereof. The computer programs described above include a plurality of instructions that may be executed by one or more processors.

[0084] Further, the above method can be implemented in any type of computing platform that is operably connected to a suitable computer, including but not limited to a personal computer, a minicomputer, a mainframe, a workstation, a network or distributed computing environment, a separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, etc. Various aspects of the present invention can be implemented in machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, an optical read and / or write storage medium, a RAM, a ROM, etc., so that it can be read by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the process described herein. In addition, the machine-readable code, or a portion thereof, can be transmitted via a wired or wireless network. When such media includes instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor, the invention described herein includes these and other different types of non-transitory computer-readable storage media. When programmed according to the methods and techniques described in the present invention, the present invention also includes the computer itself.

[0085] The computer program can be applied to input data to perform the functions described herein, thereby converting the input data to generate output data stored in a non-volatile memory. The output information can also be applied to one or more output devices such as a display. In a preferred embodiment of the present invention, the converted data represents physical and tangible objects, including specific visual depictions of physical and tangible objects produced on the display.

[0086] The above are only preferred embodiments of the present invention. The present invention is not limited to the above embodiments. As long as the technical effects of the present invention are achieved by the same means, any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of protection of the present invention. Within the scope of protection of the present invention, its technical solutions and / or implementation methods may have various modifications and changes.

Claims

1. A temperature sensor, characterized in that: The invention comprises a temperature sensing front end, a time domain amplifier, a frequency detector, a charge pump, a notch filter, a voltage-controlled ring oscillator, a pulse extractor and a non-overlapping clock and phase generator, wherein the temperature sensing front end and the frequency detector are both connected to the time domain amplifier, the frequency detector and the notch filter are both connected to the charge pump, the notch filter and the pulse extractor are both connected to the voltage-controlled ring oscillator, the temperature sensing front end, the time domain amplifier, the notch filter, the voltage-controlled ring oscillator and the pulse extractor are all connected to the non-overlapping clock and phase generator, the voltage-controlled ring oscillator is used to output a clock pulse signal to the pulse extractor and the non-overlapping clock and phase generator, and the pulse extractor is used to generate a clock pulse signal according to the time domain amplifier. The clock pulse signal outputs a fractional pulse signal, the non-overlapping clock and phase generator is used to output a working control signal according to the clock pulse signal and the fractional pulse signal, the temperature sensing front end is used to output a delayed voltage signal according to the working control signal, the time domain amplifier is used to perform linear transformation and chopping on the delayed voltage signal according to the working control signal, and output a delayed pulse signal, the frequency detector and phase detector is used to output a pulse control signal according to the delayed pulse signal, the charge pump is used to perform voltage regulation on the notch filter according to the pulse control signal, the notch filter is used to output a control voltage signal according to the working control signal, and the voltage-controlled ring oscillator is also used to adjust the frequency of the clock pulse signal according to the control voltage signal.

2. A temperature sensor according to claim 1, characterized in that: The voltage-controlled ring oscillator includes a control voltage signal input terminal, a ring inverter chain, a level converter array, and a bias reference current input terminal. The bias reference current input terminal, the ring inverter chain, the control voltage signal input terminal, and the level converter are all connected to the ring inverter chain. The ring inverter chain includes multiple inverters. The control voltage input terminal is used to input the control voltage signal into the ring inverter chain. The bias reference current input terminal is used to provide a bias reference current for the ring inverter chain. The ring inverter chain is used to determine the delay between the multiple inverters according to the bias reference current. The ring inverter chain is also used to adjust the delay between the multiple inverters according to the control voltage signal. The ring inverter chain is also used to output a delayed oscillation signal according to the delay between the multiple inverters. The level converter array is used to convert the delayed oscillation signal into the clock pulse signal.

3. A temperature sensor according to claim 1, characterized in that: The pulse extractor includes a plurality of logic gates configured to output fractional pulse signals according to the clock pulse signal.

4. A temperature sensor according to claim 1, characterized in that: The working control signal specifically includes a reset control signal, a discharge control signal, an amplification control signal, a chopping control signal, a holding control signal and a sampling control signal.

5. A temperature sensor according to claim 1, characterized in that: The temperature extraction front end includes a first discharge switch, a second discharge switch, a first reset switch, a second reset switch, a first capacitor, a second capacitor, a first temperature-sensitive resistor and a second temperature-sensitive resistor. The first temperature-sensitive resistor, the first reset switch and the time domain amplifier are all connected to the upper plate of the first capacitor, the second temperature-sensitive resistor, the second reset switch and the time domain amplifier are all connected to the lower plate of the second capacitor, the first temperature-sensitive resistor is connected to the first discharge switch, the second temperature-sensitive resistor is connected to the second discharge switch, the first discharge switch, the second reset switch, the lower plate of the first capacitor and the upper plate of the second capacitor are all grounded, the second discharge switch and the first reset switch are both connected to a power supply, the first reset switch and the second reset switch are used to control the charging time of the first capacitor and the second capacitor according to the working control signal, the first discharge switch and the second discharge switch are used to control the discharge time of the first capacitor and the second capacitor according to the working control signal, and the first capacitor and the second capacitor are used to output the delayed voltage signal.

6. A temperature sensor according to claim 5, characterized in that: The first temperature-sensitive resistor includes 5 layers of stacked metal resistors, an upper shielding layer and a lower shielding layer, and the structure of the second temperature-sensitive resistor is the same as that of the first temperature-sensitive resistor.

7. A temperature sensor according to claim 1, characterized in that: The time domain amplifier includes a first field effect tube, a second field effect tube, a third field effect tube, a fourth field effect tube, a fifth field effect tube, a sixth field effect tube, a first amplifying switch, a second amplifying switch, a third amplifying switch, a fourth amplifying switch, a third capacitor, a fourth capacitor, a bias voltage input terminal, an amplified signal input terminal, a first differential voltage input terminal, a second differential voltage input terminal, a first common mode voltage input terminal, a second common mode voltage input terminal, a first differential pulse output terminal, a second differential pulse output terminal, a first chopper and a second chopper. The gate of the sixth field effect tube is connected to the bias voltage input terminal, the source of the sixth field effect tube is grounded, the drain of the sixth field effect tube is connected to the source of the third field effect tube, the gate of the third field effect tube, the gate of the fourth field effect tube and the gate of the fifth field effect tube are all connected to the amplified signal input terminal, the source of the first field effect tube and the source of the second field effect tube are both connected to the third field effect tube. The drain of the first field effect transistor, the drain of the fourth field effect transistor and the first differential pulse output terminal are all connected to the upper plate of the third capacitor, the drain of the second field effect transistor, the drain of the fifth field effect transistor and the second differential pulse output terminal are all connected to the upper plate of the fourth capacitor, the fourth field effect transistor and the fifth field effect transistor are all connected to a power supply, the lower plate of the third capacitor and the lower plate of the fourth capacitor are all grounded, the first common-mode voltage input terminal is connected to the first amplifying switch, the first differential voltage input terminal is connected to the second amplifying switch, the first amplifying switch and the second amplifying switch are both connected to the gate of the first field effect transistor, the second common-mode voltage input terminal is connected to the third amplifying switch, the second differential voltage input terminal is connected to the fourth amplifying switch, and the third amplifying switch and the fourth amplifying switch are both connected to the gate of the second field effect transistor.

8. A temperature sensor according to claim 1, characterized in that: The notch filter includes a sampling control switch, a holding control switch, a fifth capacitor, a sixth capacitor and a seventh capacitor. The fifth capacitor and the sixth capacitor are both connected to the sampling control switch, the sixth capacitor and the seventh capacitor are both connected to the holding control switch, the sampling control switch and the holding control switch are both used to open and close according to the working control signal, the fifth capacitor is used to output an integrated voltage signal, the sixth capacitor is used to sample the integrated voltage signal and output a sampled voltage signal, and the seventh capacitor is used to hold the sampled voltage signal and output a control voltage signal.

9. A temperature sensor according to claim 8, characterized in that: The pulse control signal includes a pull-up pulse signal and a pull-down pulse signal, and the frequency detector and the charge pump are specifically used for: Detecting the phase difference of the delayed pulse signal by the phase frequency detector; When the phase difference is positive, the frequency detector and phase detector are used to output a pull-up pulse signal to the charge pump, and the charge pump is used to charge the fifth capacitor; When the phase difference is negative, a pull-down pulse signal is outputted through the phase frequency detector, and the fifth capacitor is discharged through the charge pump.

10. A method for controlling a temperature sensor, which is implemented by the temperature sensor according to any one of claims 1 to 9, characterized in that: The following steps are involved: Outputting a clock pulse signal to the pulse extractor and the non-overlapping clock and phase generator through the voltage-controlled ring oscillator; Outputting a fractional pulse signal according to the clock pulse signal by the pulse extractor; Outputting a working control signal according to the clock pulse signal and the fractional pulse signal through the non-overlapping clock and phase generator; Outputting a delayed voltage signal according to the working control signal through the temperature sensing front end; The time domain amplifier performs linear transformation and chopping on the delayed voltage signal according to the working control signal, and outputs a delayed pulse signal; Outputting a pulse control signal according to the delayed pulse signal through the phase frequency detector; Performing voltage regulation on the notch filter according to the pulse control signal by the charge pump; Outputting a control voltage signal according to the working control signal through the notch filter; The frequency of the clock pulse signal is adjusted according to the control voltage signal by the voltage-controlled ring oscillator.

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