Method and device for determining grid resistance of hybrid device and electronic equipment

Abstract

The embodiment of the invention discloses a grid resistance determination method and device of a hybrid device and electronic equipment, and the method comprises the steps: obtaining a parasitic parameter circuit model of the hybrid device according to a design model of the hybrid device; simulating the parasitic parameter circuit model to obtain a plurality of corresponding switch parameters under different gate resistors; fitting the plurality of switch parameters to obtain a fitness function and a screening condition function; performing iterative optimization on the fitness function according to the screening condition function to obtain a target gate resistance corresponding to each power device; according to the application, the influence of different gate resistors on the switching behavior of the power device is comprehensively considered, so that the obtained gate resistance value can realize the minimization of the switching loss of the hybrid device on the premise of ensuring that the hybrid device works safely.

Description

Technical Field

[0001] The present application relates to the field of parameter control technology; specifically, to a method, device and electronic device for determining the gate resistance of a hybrid device. Background Art

[0002] As the core device in power electronic converters, power semiconductor devices have been widely used in new energy system inverters, battery management, electric drive systems, frequency converters and other fields. Si IGBT-SiC MOSFET hybrid devices can combine the high current carrying capacity of IGBT and the high frequency and high efficiency characteristics of SiC MOSFET to achieve complementary advantages of the two devices. Compared with IGBT devices, the switching loss is lower, and compared with the full SiC solution, the cost is lower, which can achieve a compromise between performance and cost.

[0003] The gate resistor controls the charge and discharge rate of the gate capacitance by changing the gate drive current, thereby affecting the rate of change of the gate voltage and the switching speed of the power device. A larger gate resistor will reduce the switching speed and increase the switching loss. A gate resistance value that is too small will reduce the damping coefficient of the gate drive circuit and easily cause gate voltage oscillation and overshoot. Therefore, choosing a suitable gate resistor is crucial to optimizing the switching characteristics of power devices, improving efficiency and ensuring device reliability.

[0004] However, hybrid devices involve both IGBT and SiC MOSFET, and the gate resistance of both will affect the switching behavior of the hybrid device. The traditional method of determining the gate resistance through physical testing is not only time-consuming and labor-intensive, but also costly when applied to hybrid devices. It is also difficult to obtain a gate resistance value that can achieve minimum switching loss while ensuring the safe operation of the hybrid device.

[0005] Therefore, how to optimize the gate resistance while ensuring safe operation of the hybrid device is an urgent problem to be solved. Summary of the invention

[0006] In order to solve the above technical problems, the embodiments of the present application provide a method, device and electronic device for determining the gate resistance of a hybrid device. The present application comprehensively considers the influence of different gate resistances on the switching behavior of the power device, so that the obtained gate resistance value can ensure that the hybrid device can minimize the switching loss of the hybrid device under the premise of safe operation.

[0007] According to one aspect of an embodiment of the present application, a method for determining the gate resistance of a hybrid device, the hybrid device comprising at least one first power device and at least one second power device, the method comprising: obtaining a parasitic parameter circuit model of the hybrid device according to a design model of the hybrid device; simulating the parasitic parameter circuit model to obtain a plurality of switching parameters corresponding to different gate resistances; fitting the plurality of switching parameters to obtain a fitness function and a screening condition function; iteratively optimizing the fitness function according to the screening condition function to obtain a target gate resistance corresponding to each power device.

[0008] Optionally, a parasitic parameter circuit model of the hybrid device is obtained according to the design model of the hybrid device, including: performing three-dimensional layout design according to the circuit topology diagram of the hybrid device to obtain the design model of the hybrid device; importing the design model into simulation software, and setting the corresponding material properties of each device in the simulation software; performing grid division according to the positions of the power terminals and signal terminals of the hybrid device and the electrode positions of each power device to obtain multiple grids with different functions; setting the current flow direction in each grid according to the actual current direction of the drive circuit and the commutation circuit; running the simulation software to obtain a parasitic parameter matrix; and generating a parasitic parameter circuit model of the hybrid device according to the parasitic parameter matrix.

[0009] Optionally, simulation is performed based on the parasitic parameter circuit model to obtain multiple switching parameters corresponding to different gate resistances, including: importing the parasitic parameter circuit model and the power device model into circuit simulation software to build a dual-pulse simulation circuit; setting simulation parameters for the dual-pulse simulation circuit according to actual test conditions to simulate the switching process of the hybrid device under different gate resistances; and extracting multiple switching parameters corresponding to different gate resistances.

[0010] Optionally, fitting the multiple switch parameters to obtain a fitness function and a screening condition function includes: fitting the multiple switch parameters corresponding to different gate resistances to obtain a fitting function of each switch parameter, the specific expression of which is:

[0011] in, represents the gate resistance of the first power device, represents the gate resistance of the second power device, represents the fitting function of the kth switch parameter, k=1,2,…,K; K represents the total number of switch parameters; represents the coefficients of the polynomial, and Respectively represent the highest values ​​of i and j; the fitting function corresponding to the switching parameters of the total turn-on loss of the hybrid device, the total turn-off loss of the hybrid device or the total switching loss of the hybrid device is used as the fitness function; the fitting function corresponding to the switching parameters of the turn-on current peak of the first power device, the turn-on current peak of the second power device, the turn-off current peak of the first power device, the turn-off current peak of the second power device, and the turn-off voltage peak of the hybrid device is used as the screening condition function.

[0012] Optionally, when different gate resistances are used in the turn-on process and the turn-off process of the power device, the fitness function is iteratively optimized according to the screening condition function to obtain the target gate resistance corresponding to each power device, including: taking the fitting function corresponding to the total turn-on loss of the hybrid device as the first fitness function, and iteratively optimizing the first fitness function according to the screening condition function to obtain the turn-on gate resistances corresponding to the first power device and the second power device respectively; taking the fitting function corresponding to the total turn-off loss of the hybrid device as the second fitness function, and iteratively optimizing the second fitness function according to the screening condition function to obtain the turn-off gate resistances corresponding to the first power device and the second power device respectively.

[0013] Optionally, when the same gate resistance is used for the turn-on and turn-off processes of a power device, the fitness function is iteratively optimized according to the screening condition function to obtain a target gate resistance corresponding to each power device, including: using a fitting function corresponding to the total switching loss of the hybrid device as a third fitness function, and iteratively optimizing the third fitness function according to the screening condition function to obtain target gate resistances corresponding to the first power device and the second power device, respectively.

[0014] Optionally, the fitness function is iteratively optimized according to the screening condition function to obtain a target gate resistance corresponding to each power device, including: generating an individual population according to a first gate resistance and a second gate resistance; wherein the first gate resistance corresponds to the gate resistance of the first power device, and the second gate resistance corresponds to the gate resistance of the second power device; according to the screening condition function, calculating the screening condition function value corresponding to each individual in the individual population; judging whether the screening condition function value corresponding to each individual satisfies the constraint condition; taking the fitness function value corresponding to the individual that satisfies the constraint condition as the fitness value of the individual; if the current iteration meets the termination criterion, taking the first gate resistance and the second gate resistance corresponding to the minimum fitness function value as the target gate resistance of the first power device and the target gate resistance of the second power device respectively; wherein the termination criterion includes that the change value of the fitness value in N consecutive iterations is less than a preset function tolerance, or reaching the maximum number of iterations.

[0015] Optionally, the method also includes: setting the fitness value of individuals that do not meet the constraint conditions to a preset value; if the current iteration does not meet the termination criterion, selecting new individuals for the next iteration according to the fitness value corresponding to each individual; performing crossover and genetic mutation on the new individuals to generate a new individual population; and performing cyclic iteration on the new individual population until the termination criterion is met.

[0016] According to one aspect of an embodiment of the present application, a device for determining the gate resistance of a hybrid device is provided, the device comprising: a circuit model acquisition module, used to obtain a parasitic parameter circuit model of the hybrid device according to a design model of the hybrid device; a switch parameter acquisition module, used to simulate the parasitic parameter circuit model to obtain a plurality of switch parameters corresponding to different gate resistances; a parameter fitting module, used to fit the plurality of switch parameters to obtain a fitness function and a screening condition function; and an iterative optimization module, used to iteratively optimize the fitness function according to the screening condition function to obtain a target gate resistance corresponding to each power device.

[0017] According to one aspect of an embodiment of the present application, a computer-readable medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the method for determining the gate resistance of a hybrid device in the above technical solution is implemented.

[0018] According to one aspect of an embodiment of the present application, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the executable instructions so that the electronic device implements a method for determining the gate resistance of a hybrid device as in the above technical solution.

[0019] According to one aspect of an embodiment of the present application, a computer program product is provided, including a computer program, wherein when the computer program is executed by a processor, the method for determining the gate resistance of a hybrid device in the above technical solution is implemented.

[0020] The technical solution provided by this application includes at least the following beneficial effects: The present application obtains a parasitic parameter circuit model of the hybrid device based on the design model of the hybrid device; simulates the parasitic parameter circuit model to obtain multiple switching parameters corresponding to different gate resistances; then fits the multiple switching parameters to obtain a multi-objective optimization fitness function and a screening condition function to ensure safe operation of the hybrid device; finally, iteratively optimizes the fitness function according to the screening condition function to obtain a target gate resistance corresponding to each power device; therefore, the present application comprehensively considers the influence of different gate resistances on the switching behavior of the power device, so that the obtained gate resistance value can ensure that the hybrid device can minimize the switching loss of the hybrid device under the premise of safe operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings: Figure 1 FIG. 1 is a flow chart of a method for determining gate resistance of a hybrid device provided in an embodiment of the present application; Figure 2 The figure shows a circuit structure diagram of a hybrid device provided in an embodiment of the present application; Figure 3 Shown Figure 1 An exemplary flow chart of step S10 in FIG. Figure 4 Shown is a schematic diagram of a design model of a hybrid device provided in an embodiment of the present application; Figure 5 FIG. 1 is a schematic diagram of a parasitic parameter circuit model provided in an embodiment of the present application; Figure 6 Shown Figure 1 An exemplary flow chart of step S20 in FIG. Figure 7 Shown is a schematic diagram of a double pulse simulation circuit provided in an embodiment of the present application; Figure 8 Shown Figure 1 An exemplary flow chart of step S40 in FIG. Fig. 9 The figure shows a schematic diagram of a multi-objective optimization process provided by an embodiment of the present application; Fig.10 Shown is another multi-objective optimization process schematic diagram provided in an embodiment of the present application; Fig.11 The figure shows a circuit schematic diagram of a turn-on process and a turn-off process using different gate resistors provided by an embodiment of the present application; Fig.12 The figure shows a schematic diagram of the change of a fitness value with the number of iterations provided in an embodiment of the present application; Fig.13 Shown is a schematic diagram of simulated switching waveforms of a hybrid device provided by an embodiment of the present application under a target gate resistance; Fig.14 Shown is a schematic diagram of a measured switching waveform of a hybrid device under a target gate resistance provided by an embodiment of the present application; Fig.15Shown is a schematic structural diagram of a gate resistance determination device for a hybrid device provided in an embodiment of the present application; Fig.16 A schematic diagram of the structure of a computer system suitable for implementing an electronic device of an embodiment of the present application is shown. DETAILED DESCRIPTION

[0022] Here, exemplary embodiments will be described in detail, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.

[0023] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0024] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0025] It should also be noted that the "multiple" mentioned in this application refers to two or more than two. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship.

[0026] Figure 1 FIG. 1 is a flow chart of a method for determining the gate resistance of a hybrid device provided in an embodiment of the present application; Figure 1 As shown, the method specifically comprises the following steps: Step S10: Obtain a parasitic parameter circuit model of the hybrid device according to the design model of the hybrid device.

[0027] The hybrid device in this embodiment includes at least one first power device and at least one second power device. The first power device and the second power device have the same function but different characteristics, that is, the first power device and the second power device have the same switching function, but the device type, process material, process technology, etc. of the two are different. The first power device can be SiC-MOSFET (SiC-Metal-Oxide-Semiconductor Field-Effect Transistor), and the second power device can be Si-IGBT (Si-InsulatedGate Bipolar Transistor); in addition, the first power device and the second power device can also be transistors of other materials. There is no restriction on the specific type and quantity of the two power devices here. As long as the characteristics of the first power device and the second power device are different, they belong to the scope of the hybrid device of this application.

[0028] For example: Figure 2 A schematic diagram of the circuit structure of a hybrid device provided in an embodiment of the present application is a half-bridge structure, each bridge arm includes 1 Si IGBT chip, 1 SiC MOSFET chip and 1 Si FRD chip, wherein the SiCMOSFET has an anti-parallel parasitic diode due to its own structure; Figure 2 The hybrid device in the invention includes four power devices, among which T1 and T2 are Si-IGBT, M1 and M2 are SiC-MOSFET, M1 and M2 can be used as the first power device, and T1 and T2 can be used as the second power device; further, resistors R1, R2, R3 and R4 are the gate resistors of T1, T2, M1 and M2 respectively, and the main purpose of this application is to determine the resistance values ​​of resistors R1, R2, R3 and R4. It should be noted that the power device in this application does not include a diode, that is, in Figure 2 The two diodes connected in parallel with T1 and T2 do not belong to the scope of the power device of this application; in addition, Figure 2 The two diodes connected in parallel with M1 and M2 are integrated in M1 and M2. In this embodiment, Figure 2 The circuit topology diagram includes two first power devices and two second power devices, and the gate resistance can be determined by treating the four power devices as a hybrid device.

[0029] It should also be noted that, ideally, the characteristics of the T1 and T2 chips are the same, and the characteristics of the M1 and M2 chips are the same. However, due to the presence of parasitic parameters in actual circuits, the influence of the difference in parasitic parameters may cause differences in the switching parameters of T1 and T2 and the switching parameters of M1 and M2. In order to optimize the performance of the upper bridge arm (T1 and M1) and the lower bridge arm (T2 and M2) respectively, the resistance values ​​of R1 and R2 and the resistance values ​​of R3 and R4 are not necessarily the same; because one of the upper bridge arm devices T1 and M1 and the lower bridge arm devices T2 and M2 is always in the off state during the double pulse test, the gate resistance of the power device of this bridge arm will not affect the switching characteristics of the other bridge arm. In order to improve the evaluation efficiency of the gate resistance, the gate resistance of the power device of one of the bridge arms can be determined first, and then the gate resistance of the power device of the other bridge arm can be determined.

[0030] In the double pulse test, one of the upper and lower bridge arms of the half-bridge circuit is always in the off state, which is called the companion test device, while the other bridge arm performs a switching action, which is called the device under test. In one embodiment, if the upper bridge arm device (T1 and M1) is the companion test device and the lower bridge arm device is the device under test (T2 and M2), that is, this test determines the gate resistance of T2 and M2.

[0031] In one embodiment, if Figure 3 As shown, according to the design model of the hybrid device, a parasitic parameter circuit model of the hybrid device is obtained, which specifically includes the following steps: Step S11 , performing three-dimensional layout design according to the circuit topology diagram of the hybrid device to obtain a design model of the hybrid device.

[0032] It should be noted that Figure 2 It is a circuit topology diagram of a hybrid device. In practical applications, it is necessary to perform three-dimensional layout design on the circuit topology diagram, that is, to perform layout design based on the connection relationship between each component, and to optimize the performance from the aspects of electricity, heat, force, etc. Figure 4 The 3D design model shown.

[0033] Step S12: import the design model into the simulation software, and set the corresponding material properties of each device in the simulation software.

[0034] Specifically, the three-dimensional design model is imported into finite element simulation software, and the material properties corresponding to each device are set, and the material properties include but are not limited to conductivity, relative dielectric constant, etc.

[0035] Step S13: Grid division is performed according to the positions of the power terminals and signal terminals of the hybrid device and the electrode positions of each power device to obtain a plurality of grids with different functions.

[0036] It should be noted that the power terminals and signal terminals of this embodiment are different from the device electrodes. The power terminals and signal terminals refer to the input and output terminals of the entire hybrid device. Figure 2 The P, U, and N in Figure 4 The DC+, AC, and DC- in the device are the control terminals, input and output terminals of each power device, such as the gate, collector, and emitter of Si-IGBT devices, and the gate, drain, and source of MOSFET devices.

[0037] Specifically, meshing according to the positions of the power terminals and signal terminals of the hybrid device and the electrode positions of each power device is equivalent to meshing according to the connection relationships between conductors and between conductors and chips, so that different meshes are formed on the design model.

[0038] Step S14: setting the current flow direction in each grid according to the actual current direction of the drive circuit and the commutation circuit.

[0039] Specifically, a plurality of current inflow points and outflow points are set according to the required circuit interface and the actual current flow direction in the module in the double pulse test.

[0040] Step S15, running simulation software to obtain a parasitic parameter matrix.

[0041] Specifically, the parasitic parameter matrix includes parasitic parameter types and corresponding parasitic values. The parasitic parameter types include but are not limited to parasitic inductance, parasitic capacitance and parasitic resistance. The parasitic parameter matrix can be solved by running simulation software.

[0042] Step S16: Generate a parasitic parameter circuit model of the hybrid device according to the parasitic parameter matrix.

[0043] It should be noted that the parasitic parameter matrix can be output as an equivalent circuit model and imported into the circuit simulation software to obtain the parasitic parameter circuit model used for circuit simulation, such as Figure 5 shown.

[0044] Step S20: simulating the parasitic parameter circuit model to obtain a plurality of switch parameters corresponding to different gate resistances.

[0045] In one embodiment, if Figure 6 As shown, the parasitic parameter circuit model is simulated to obtain multiple switch parameters corresponding to different gate resistances, which specifically includes the following steps: Step S21: import the parasitic parameter circuit model and the power device model into the circuit simulation software to build a dual pulse simulation circuit.

[0046] Specifically, the parasitic parameter circuit model and the power device model are imported into the circuit simulation software to construct a double-pulse simulation circuit containing the parasitic parameter model, such as Figure 7 shown in Figure 7 In the figure, HPD_HyS (i.e. U7) is the extracted parasitic parameter circuit model, U1 and U2 are the SPICE models of SiC MOSFET chips, which contain junction temperature setting ports; U3 and U4 are the SPICE models of IGBT chips, and U5 and U6 are the SPICE models of FRD chips. In addition, Figure 7 The drive circuit and busbar model of SiC MOSFET and IGBT are also given, where: is the external gate resistance of the MOSFET, is the external gate resistor of the IGBT, L1, C1 and V1 are the load inductance, bus capacitance and DC power supply respectively. During simulation, as control variables, the time TD_ON when the SiC MOSFET is turned on earlier than the IGBT and the time TD_OFF when it is turned off later are set to 0.

[0047] The circuit simulation software of this embodiment includes but is not limited to LTSPICE software, Pspice software and Simplorer software.

[0048] Step S22: setting simulation parameters for the double pulse simulation circuit according to actual test conditions, and simulating the switching process of the hybrid device under different gate resistances.

[0049] Specifically, appropriate simulation parameters are set according to the actual test conditions, and the gate resistance of the IGBT and the gate resistance of the SiCMOSFET are set as variables and , and then simulate to obtain different gate resistances and Switching waveforms of the combined down-mixing device.

[0050] Step S23: extracting a plurality of switch parameters corresponding to different gate resistances.

[0051] In this embodiment, multiple switching parameters include the turn-on current peak of the first power device, the turn-on current peak of the second power device, the turn-off current peak of the first power device, the turn-off current peak of the second power device, the turn-off voltage peak of the hybrid device, the turn-on loss of the first power device, the turn-on loss of the second power device, the turn-off loss of the first power device, the turn-off loss of the second power device, the total turn-on loss of the hybrid device, the total turn-off loss of the hybrid device, and the total switching loss of the hybrid device.

[0052] Step S30: Fit multiple switch parameters to obtain a fitness function and a screening condition function.

[0053] It should be noted that, after extracting key parameters such as voltage and current peaks and switching losses of the hybrid device during the switching process and obtaining a sufficient amount of data, each switching parameter is fitted into a binary polynomial function of the gate resistances Rt and Rm through nonlinear fitting; specifically, the switching parameters of the hybrid device under different combinations of Rm and Rt are obtained through simulation, including SiCMOSFET turn-on current peak, Si IGBT turn-on current peak, SiC MOSFET turn-off current peak, Si IGBT turn-off current peak, module turn-off voltage peak, SiC MOSFET turn-on loss, Si IGBT turn-on loss, SiC MOSFET turn-off loss, Si IGBT turn-off loss and total switching loss of the hybrid device, and these switching parameters are fitted into a binary polynomial function with the gate resistance Rt of the IGBT and the gate resistance Rm of the SiC MOSFET as variables through nonlinear fitting.

[0054] In this embodiment, multiple switch parameters are fitted to obtain a fitness function and a screening condition function, including: multiple switch parameters corresponding to different gate resistances are fitted to obtain a fitting function of each switch parameter, and the specific expression is shown in formula (1): (1) in, represents the gate resistance of the first power device, represents the gate resistance of the second power device, represents the fitting function of the kth switch parameter, k=1,2,…,K; K represents the total number of switch parameters; Represents the coefficients of the polynomial, i and j represent and The power of i is from 0 to , j ranges from 0 to For the kth switch parameter, the coefficients of the corresponding bivariate polynomial fitting function are ( +1)( +1), and The value of is determined by evaluating the goodness of fit of the fitting function, and the value in the fitting function with the highest goodness of fit is selected. and The highest order of and The value of .

[0055] In one embodiment, the goodness of fit can be evaluated by the following indicators: (1) Variance and SSE (Sum of Squared Errors) or MSE (Mean Squared Error)

[0056]

[0057] In the formula, is the value extracted from the simulation, is the predicted value of the fitting function, and N is the number of data points. The smaller the value of SSE and MSE, the better the model fits the data.

[0058] (2) Root Mean Squared Error (RMSE)

[0059] The unit of RMSE is the same as that of the original data. The smaller the RMSE, the smaller the model prediction error and the better the fitting effect.

[0060] (3) R-squared

[0061] in, is the mean of the values ​​extracted from the simulation. The R-squared value ranges from 0 to 1. The closer it is to 1, the better the model fit.

[0062] (4) Adjusted R-squared

[0063] p is the number of independent variables in the model. In the present invention, p=2. The closer the value of adjusted R-squared is to 1, the better the model fits the data, and the complexity of the model is taken into account.

[0064] In this embodiment, the fitting function corresponding to each switch parameter is shown in Table 1: Table 1. Fitting function relationship table

[0065] For the fitting functions in Table 1, there are the following relationships:

[0066]

[0067]

[0068] It can be seen that the fitting function , and It can be obtained by calculating other fitting functions, so this application only needs to calculate the ~ A total of 9 switch parameters can be subjected to nonlinear fitting.

[0069] In one embodiment, a fitting function corresponding to a switching parameter that is a total turn-on loss of a hybrid device, a total turn-off loss of a hybrid device, or a total switching loss of a hybrid device may be used as a fitness function; wherein the fitness function represents a target optimization function.

[0070] In another embodiment, a fitting function corresponding to the switching parameters of the turn-on current peak of the first power device, the turn-on current peak of the second power device, the turn-off current peak of the first power device, the turn-off current peak of the second power device, and the turn-off voltage peak of the hybrid device can be used as a screening condition function.

[0071] Step S40: iteratively optimize the fitness function according to the screening condition function to obtain a target gate resistance corresponding to each power device.

[0072] It should be noted that the gate resistance of each switch parameter is and After the nonlinear fitting function is obtained, this embodiment proposes a multi-objective optimization method to obtain the target gate resistance corresponding to each power device; the specific process of the multi-objective optimization method is: (1) Initializing the population: Randomly generate an initial population consisting of a series of individuals. Each individual in the population is usually represented by binary coding, etc., representing a possible solution in the problem solution space.

[0073] (2) Calculate the screening condition function: Evaluate the fitness of each individual to determine its ability to solve the problem.

[0074] (3) Selection operation: individuals are selected based on their fitness. Individuals with better fitness are more likely to be selected to participate in crossover and reproduction, thereby passing their characteristics to the next generation. In this embodiment, the minimum value of the fitness function (i.e., loss) is sought, that is, individuals with smaller fitness values ​​are selected.

[0075] (4) Crossover operation: The selected individuals exchange part of their codes through the crossover operation to produce new offspring.

[0076] (5) Mutation operation: Randomly change certain genes of an individual so that a more diverse solution space can be generated during the iteration process.

[0077] (6) Generate a new population: Use new individuals generated by selection, crossover and mutation operations to replace individuals with poor fitness in the original population, thereby generating a new generation of population.

[0078] (7) Termination condition judgment: Repeat the above operations and continuously optimize the population through an iterative process until the maximum number of iterations is reached, a solution that meets the requirements is found, or the fitness change is less than a threshold.

[0079] Since the effectiveness of the multi-objective optimization method of this embodiment depends largely on the definition of the fitness function, the design of the selection strategy, and the setting of the termination condition, this embodiment takes the loss of the hybrid device during the switching process (i.e. and ,or ) is defined as the fitness function, and the termination condition is set as the change of the fitness function value in consecutive generations is less than the preset function tolerance to find the minimum value of the fitness function, that is, the minimum value of the switching loss of the hybrid device. In addition, in order to perform multi-objective optimization, the current peak of IGBT and SiC MOSFET during the switching process and the voltage peak during the shutdown process are added as screening conditions to the multi-objective optimization process to ensure the safe operation of the hybrid device, that is, before calculating the fitness of the individual, it is first substituted into the fitting function in Table 1 ~ In the process, determine whether the function value exceeds the safe operating area (SOA) of IGBT and SiC MOSFET. If any parameter exceeds the SOA of the device, the fitness value of the individual is set to infinity, and the individual is unlikely to be selected and participate in the subsequent iteration process. If the function value is within the SOA of the device, the switching loss value of the hybrid device is calculated as the fitness value of the individual. Then, through selection, crossover and mutation and multiple iterations, find the gate resistor that can achieve the minimum switching loss while ensuring the safe operation of IGBT and SiC MOSFET. and value.

[0080] In summary, the present application obtains a parasitic parameter circuit model of the hybrid device according to the design model of the hybrid device; performs simulation based on the parasitic parameter circuit model to obtain multiple switching parameters corresponding to different gate resistances; then fits the multiple switching parameters to obtain a multi-objective optimization fitness function and a screening condition function to ensure the safe operation of the hybrid device; finally, iteratively optimizes the fitness function according to the screening condition function to obtain the target gate resistance corresponding to each power device; therefore, the present application comprehensively considers the influence of different gate resistances on the switching behavior of the power device, so that the obtained gate resistance value can ensure that the hybrid device can minimize the switching loss of the hybrid device under the premise of safe operation.

[0081] In one embodiment, if Figure 8As shown, the fitness function is iteratively optimized according to the screening condition function to obtain the target gate resistance corresponding to each power device, which specifically includes the following steps: (1) Generate an individual population according to a first gate resistor and a second gate resistor; wherein the first gate resistor corresponds to the gate resistor of the first power device, and the second gate resistor corresponds to the gate resistor of the second power device; it should also be noted that when generating the initialized individual population, the individual population can be obtained by random generation.

[0082] (2) According to the screening condition function, the screening condition function value corresponding to each individual in the individual population is calculated; wherein, the number of screening condition functions can be multiple, and the screening condition function value corresponding to each individual can also be multiple. For example, in this embodiment, the fitting function in Table 1 is , , , and All are used as filter function.

[0083] (3) Determine whether the screening condition function value corresponding to each individual satisfies the constraint condition; wherein, in this embodiment, each screening condition function value may be compared with the corresponding safety threshold range. If all the screening condition function values ​​are within the corresponding safety threshold range, it is determined that the individual satisfies the constraint condition; if any of the screening condition function values ​​is not within the corresponding safety threshold range, it is determined that the individual does not satisfy the constraint condition.

[0084] (4) The fitness function value corresponding to the individual that meets the constraint conditions is used as the fitness value of the individual, and the fitness value of the individual that does not meet the constraint conditions is set to a preset value; wherein the preset value can be an infinite value or zero, and it mainly plays a filtering role.

[0085] (5) Determine whether the current iteration satisfies the termination criterion. In this embodiment, the termination criterion is satisfied when the change in the fitness value in N consecutive iterations is less than a preset function tolerance or when the maximum number of iterations is reached.

[0086] (6) If the current iteration satisfies the termination criterion, the first gate resistance and the second gate resistance corresponding to the minimum fitness function value are respectively used as the target gate resistance of the first power device and the target gate resistance of the second power device, and the obtained target gate resistances are simulated and verified.

[0087] (7) If the current iteration does not meet the termination criterion, a new individual for the next iteration is selected based on the fitness value corresponding to each individual.

[0088] (8) Perform crossover and genetic mutation on the new individuals to generate a new population of individuals.

[0089] (9) The new individual population is iterated repeatedly until the termination criterion is met.

[0090] In one embodiment, in a simulation experiment of a switching process of a hybrid device, the switching process is divided into cases of using the same gate resistor and different gate resistors according to actual needs; specifically, using the same gate means that the same gate resistor is used in both the turn-on simulation process and the turn-off simulation process of the power device, and using different gate resistors means that different gate resistors are used in the turn-on simulation process and the turn-off simulation process of the power device.

[0091] Optionally, if the process of iteratively optimizing the fitness function according to the screening condition function is used as a multi-objective optimization algorithm, when different gate resistances are used in the turn-on process and the turn-off process of the power device, the multi-objective optimization algorithm needs to be run twice to obtain the target gate resistance corresponding to each power device, specifically: the fitting function corresponding to the total turn-on loss of the hybrid device is used as the first fitness function, and the first fitness function is iteratively optimized according to the screening condition function to obtain the turn-on gate resistances corresponding to the first power device and the second power device respectively; the fitting function corresponding to the total turn-off loss of the hybrid device is used as the second fitness function, and the second fitness function is iteratively optimized according to the screening condition function to obtain the turn-off gate resistances corresponding to the first power device and the second power device respectively.

[0092] Optionally, when the same gate resistance is used in the turn-on and turn-off processes of a power device, the target gate resistance corresponding to each power device can be obtained by running the multi-objective optimization algorithm only once. Specifically, the fitting function corresponding to the total switching loss of the hybrid device is used as the third fitness function, and the third fitness function is iteratively optimized according to the screening condition function to obtain the target gate resistances corresponding to the first power device and the second power device respectively.

[0093] like Fig. 9 As shown, when the same driving resistance is used in the switching process, only one operation is required. Figure 8 The multi-objective optimization algorithm shown in the figure. The screening condition function includes the SiC MOSFET turn-on current peak fitting function. , Si IGBT turn-on current peak fitting function , SiC MOSFET turn-off current peak fitting function , Si IGBT turn-off current peak fitting function And the hybrid device off-state voltage peak fitting function , it is necessary to ensure that the above five function values ​​are all within the SOA of Si IGBT or SiCMOSFET chip. At the same time, the fitness function is set to the total switching loss of the hybrid device The optimization algorithm will continue to search for the minimum value of the fitness function until the change in the fitness function value in consecutive generations is less than the preset function tolerance. After selection, crossover and mutation and multiple iterations, the optimized IGBT gate resistance value is output. and SiCMOSFET gate resistance value , and the total switching loss fitting value Eloss_tot of the hybrid device under the optimized gate resistance. This solution can simplify the gate drive circuit, but the obtained total switching loss fitting value Eloss_tot is a local optimal solution.

[0094] like Fig.10 As shown, when different drive resistances are used in the switching process, two runs are required. Figure 8 The gate resistor optimization algorithm shown. When the algorithm is run for the first time, the filter function includes the SiC MOSFET turn-on current peak fitting function And SiIGBT turn-on current peak fitting function , it is necessary to ensure that the above two function values ​​are both within the SOA of the Si IGBT or SiC MOSFET chip. At the same time, the fitness function is set to the total turn-on loss of the hybrid device f10(Rm,Rt). The optimization algorithm will continuously search for the minimum value of the fitness function until the change in the fitness function value in consecutive generations is less than the preset function tolerance. After selection, crossover and mutation, and multiple iterations, the optimized IGBT turn-on gate resistance value Rt_on and SiCMOSFET turn-on gate resistance value Rm_on are output, as well as the total turn-on loss fitting value Eloss_on of the hybrid device under the optimized turn-on gate resistance. When running the algorithm for the second time, the screening condition function includes the SiC MOSFET turn-off current peak fitting function , Si IGBT turn-off current peak fitting function And the hybrid device off-state voltage peak fitting function , it is necessary to ensure that the above three function values ​​are all within the SOA of the Si IGBT or SiC MOSFET chip. At the same time, the fitness function is set to the total turn-off loss f11(Rm, Rt) of the hybrid device. The optimization algorithm will continuously search for the minimum value of the fitness function until the change in the fitness function value in consecutive generations is less than the preset function tolerance. After selection, crossover and mutation, and multiple iterations, the optimized IGBT turn-off gate resistance value Rt_off and SiC MOSFET turn-off gate resistance value Rm_off are output, as well as the total turn-off loss fitting value Eloss_off of the hybrid device under the optimized turn-off gate resistance. At the same time, the total switching loss fitting value Eloss_tot=Eloss_on+Eloss_off of the hybrid device can also be obtained. The total switching loss fitting value Eloss_tot obtained by this scheme is the global optimal solution, but the gate drive circuit is more complicated.

[0095] like Fig.11 As shown, taking the IGBT power device as an example, when different gate resistors are used in the turn-on process and the turn-off process, the target gate resistance obtained includes the turn-on gate resistance Rt_on and the turn-off gate resistance Rt_off; in the actual driving circuit, a turn-on diode Dt_on and a turn-off diode Dt_off need to be connected in series with the turn-on gate resistance Rt_on and the turn-off gate resistance Rt_off, respectively. Since the current flows into the gate of the device during the turn-on process, and the direction of the gate current during the turn-off process is opposite, that is, it flows out from the gate of the device, assuming that the current flows from left to right during the turn-on process, since the diode is unidirectionally conductive, the turn-on diode Dt_on is turned on and the turn-off diode Dt_off is turned off, thereby connecting the turn-on gate resistance Rt_on to the gate of the power device; on the contrary, for the turn-off process, the current flows from the right to the left, then the turn-off diode Dt_off is turned on and the turn-on diode Dt_on is turned off, thereby connecting the turn-off gate resistance Rt_off to the gate of the power device. The resistance values ​​of the on-gate resistor Rt_on and the off-gate resistor Rt_off in this embodiment are obtained by Fig.10 Obtained in the manner shown.

[0096] In order to simplify the driving circuit, this embodiment adopts Fig. 9 The switching process shown is experimentally verified using the same gate resistance method. Figure 8 The multi-objective optimization results of the gate resistance are as follows: Fig.12 As shown, in Fig.12In the experiment, when the number of iterations reaches about 90, the change of the fitness function value in consecutive generations is less than the preset function tolerance. The multi-objective optimization algorithm reaches the termination condition and outputs the result: the optimized SiC MOSFET gate resistance value is 17.9586 Ω, the IGBT gate resistance value is 1.5 Ω, and the total switching loss of the hybrid device is 16.414 mJ under this gate resistance.

[0097] Furthermore, the optimized target gate resistance value is substituted into the simulation circuit, and the switching waveform is as follows: Fig.13 As shown; among them, Fig.13 13a is the simulated turn-on waveform, and 13b is the simulated turn-off waveform. The key switching parameters are extracted. The peak values ​​of IGBT current IC and SiC MOSFET current ID during the turn-on process are 439.25591 A and 144.67885 A respectively. The peak values ​​of IC and ID during the turn-off process are 251.17457 A and 90.857289 A respectively. The turn-off voltage peak value is 737.07632 V. The above parameters are all within the chip safe operating area. The total loss simulation value of the switching process during the hybrid period is 14.217 mJ, which is lower than the fitting value. This is attributed to the accuracy difference of the fitting model under different gate resistances. However, the proposed optimization strategy can obviously control the voltage and current of the switching process within a safe range and reduce the switching loss.

[0098] Furthermore, under the optimized target gate resistance, the switching wave measurement results of the Si IGBT-SiC MOSFET hybrid device are as follows: Fig.14 As shown, Fig.14 14a is the measured turn-on waveform, and 14b is the measured turn-off waveform. During the turn-on process, the peak values ​​of the IGBT current IC and the SiC MOSFET current ID are 473 A and 191 A respectively, and the peak values ​​of the turn-off process IC and ID are 265A and 101A respectively, and the turn-off voltage peak value is 761V. The above parameters are all within the chip safe operating area. Under the optimized gate resistance, the total switching loss of the Si / SiC hybrid power device is 17.29 mJ. It can be seen that the measured results are similar to the simulation output results and have a high consistency. Therefore, the gate resistance determination method proposed in this application can effectively realize the multi-objective optimization of the gate resistance of the Si IGBT-SiC MOSFET hybrid device, shorten the development cycle, and save R&D costs.

[0099] in, Fig.13 and Fig.14 V F express Figure 2 The voltage between point U and point N, I HyS express Figure 2 The current that flows from point U through devices T2 and M2 and flows out from point N is the current IC and current I D sum.

[0100] In summary, the technical solution provided by this application has at least the following beneficial effects: 1. Multi-objective optimization of the gate resistance of Si IGBT-SiC MOSFET hybrid devices can be achieved: Si IGBT-SiCMOSFET hybrid devices involve both IGBT and SiC MOSFET, and the gate resistance of both will affect the switching behavior of the hybrid device. Inappropriate gate resistance will not only increase the switching loss of the hybrid device and reduce its cost performance, but may even cause the voltage and current peaks of the device to exceed the safe working area of ​​the IGBT and SiC MOSFET chips during the switching process, causing device failure. The traditional method of selecting the gate resistance value through physical testing often obtains a local optimal solution, and it is difficult to comprehensively consider the influence of the gate resistance on multiple parameters; however, the hybrid device gate resistance determination method proposed in this application comprehensively considers the influence of the IGBT gate resistance and the SiC MOSFET gate resistance on the device switching behavior. The obtained gate resistance value can minimize the switching loss of the hybrid device under the premise of ensuring that the voltage and current peaks of the hybrid device are within the safe working area of ​​the IGBT and SiC MOSFET chips.

[0101] 2. Lower cost and shorter cycle: When selecting the gate resistor through the traditional physical test method, the test volume is large and the time is long because the two variables of IGBT gate resistance and SiC MOSFET gate resistance need to be considered at the same time. In the actual dynamic test process, since the current overshoot that the power chip can withstand is certain, unreasonable gate resistance value will cause overcurrent failure of the power chip and increase the development cost. When the gate resistor needs to be integrated into the power module, once the physical test result is not suitable, the power module needs to be re-prepared. For power modules with longer production time and higher material cost, this method will cause a significant increase in development cycle and cost. The gate resistance determination method proposed in this application obtains the fitting function of the switching parameters about the gate resistance by building a simulation circuit considering the parasitic parameters of the hybrid device and performing multi-objective optimization through genetic algorithm, thereby obtaining the optimized gate resistance value. Compared with physical testing, the method of this application mainly relies on simulation, reduces a large number of physical preparation and testing links, and can even realize the evaluation of the gate resistance value in the hybrid device design stage, effectively shortening the development cycle and reducing R&D costs.

[0102] 3. Wide application scope: In addition to being applicable to Si IGBT-SiC MOSFET hybrid devices, the gate resistor selection method proposed in this application is also applicable to the parallel connection of Si IGBT and SiC MOSFET discrete devices, the full Si IGBT solution, and the full SiC MOSFET solution. For example, for Si IGBT modules, its parasitic parameter matrix can also be extracted and exported as a circuit model for electrical simulation, and the physical switch parameters under different gate resistances can be extracted and nonlinear fitting can be performed. Finally, multi-objective optimization is performed. Because it has only one variable, the simulation calculation amount is smaller and the time is shorter. At the same time, the fitting function complexity is lower, and the optimization algorithm calculation amount is reduced, so it is easier to determine the gate resistance.

[0103] Fig.15 FIG. 1 is a schematic diagram of a structure of a gate resistance determination device of a hybrid device provided in an embodiment of the present application; Fig.15 As shown, the device comprises: A circuit model acquisition module 111 is used to obtain a parasitic parameter circuit model of the hybrid device according to a design model of the hybrid device; A switch parameter acquisition module 112 is used to simulate the multi-port circuit model and obtain a plurality of switch parameters corresponding to different gate resistances; The parameter fitting module 113 fits a plurality of switch parameters to obtain a fitness function and a screening condition function; The iterative optimization module 114 is used to iteratively optimize the fitness function according to the screening condition function to obtain the target gate resistance corresponding to each power device.

[0104] In one embodiment, the gate resistance determination device also includes a verification module for performing double pulse simulation and testing on the target gate resistance value corresponding to each power device to verify whether the voltage and current peaks during the switching process of the hybrid device are within the safe operating area of ​​the IGBT and SiC MOSFET chips, and whether the switching loss meets the design requirements.

[0105] In one embodiment, the hardware control system architecture of the gate resistance determination device of the hybrid device may include but is not limited to: (1) Core control unit (CPU): As the core control unit, it handles parasitic parameter extraction, multi-objective optimization algorithm calculation, and data transmission control.

[0106] (2) Storage unit (ROM+RAM): ROM: stores fixed programs, such as optimization algorithms, control logic, and simulation verification models; RAM: is used to store dynamic data, including parasitic parameters collected in real time, optimization intermediate results, simulation data, etc.

[0107] (3) I / O interface: interacts with external modules and is used to input data (such as experimental measurement data) and output control signals.

[0108] (4) Input module: includes the measurement device interface, which is used to collect the parasitic parameters and switching characteristics of the device.

[0109] (5) Output module: used to control external experimental equipment or feedback optimization results, such as the gate resistance value after multi-objective optimization.

[0110] (6) Drive module: used to control the working status of Si IGBT and SiC MOSFET.

[0111] Fig.16 A schematic diagram of the structure of a computer system suitable for implementing an electronic device of an embodiment of the present application is shown.

[0112] It should be noted that Fig.16 The computer system 1000 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0113] like Fig.16 As shown, the computer system 1000 includes a central processing unit (CPU) 1001, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1002 or the program loaded from the storage part 1008 to the random access memory (RAM) 1003, such as executing the method described in the above embodiment. Various programs and data required for system operation are also stored in the RAM 1003. The CPU 1001, the ROM 1002 and the RAM 1003 are connected to each other through the bus 1004. The input / output (I / O) interface 1005 is also connected to the bus 1004.

[0114] The following components are connected to the I / O interface 1005: an input section 1006 including a keyboard, a mouse, etc.; an output section 1007 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to the I / O interface 1005 as needed. A removable medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1010 as needed, so that a computer program read therefrom is installed into the storage section 1008 as needed.

[0115] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through the communication part 1009, and / or installed from a removable medium 1011. When the computer program is executed by the central processing unit (CPU) 1001, various functions defined in the system of the present application are executed.

[0116] It should be noted that the computer-readable medium shown in the embodiment of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, device or device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable computer program. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which may send, propagate, or transmit programs for use by or in conjunction with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0117] The flowchart and block diagram in the accompanying drawings illustrate the possible architecture, functions and operations of the system, method and computer program product according to various embodiments of the present application. Wherein, each box in the flowchart or block diagram can represent a module, a program segment, or a part of the code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0118] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. The names of these units do not, in some cases, constitute limitations on the units themselves.

[0119] The above content is only a preferred exemplary embodiment of the present application and is not intended to limit the implementation scheme of the present application. A person skilled in the art can easily make corresponding changes or modifications based on the main concept and spirit of the present application. Therefore, the scope of protection of the present application shall be based on the scope of protection required by the claims.

Claims

1. A method for determining the gate resistance of a hybrid device, characterized in that: The hybrid device includes at least one first power device and at least one second power device, and the method includes: Obtaining a parasitic parameter circuit model of the hybrid device according to the design model of the hybrid device; Simulating the parasitic parameter circuit model to obtain a plurality of switch parameters corresponding to different gate resistances; Fitting the multiple switch parameters to obtain a fitness function and a screening condition function; The fitness function is iteratively optimized according to the screening condition function to obtain a target gate resistance corresponding to each power device.

2. The method according to claim 1, characterized in that: According to the design model of the hybrid device, a parasitic parameter circuit model of the hybrid device is obtained, including: Perform three-dimensional layout design according to the circuit topology diagram of the hybrid device to obtain a design model of the hybrid device; Importing the design model into simulation software, and setting the material properties corresponding to each device in the simulation software; Grid division is performed according to the positions of the power terminals and signal terminals of the hybrid device and the electrode positions of each power device to obtain a plurality of grids with different functions; According to the actual current direction of the drive circuit and the commutation circuit, the current flow direction in each grid is set; Running the simulation software to obtain a parasitic parameter matrix; A parasitic parameter circuit model of the hybrid device is generated according to the parasitic parameter matrix.

3. The method according to claim 1, characterized in that The parasitic parameter circuit model is simulated to obtain a plurality of switch parameters corresponding to different gate resistances, including: Importing the parasitic parameter circuit model and the power device model into circuit simulation software to build a double pulse simulation circuit; Setting simulation parameters for the double pulse simulation circuit according to actual test conditions to simulate the switching process of the hybrid device under different gate resistances; Extract multiple switching parameters corresponding to different gate resistances.

4. The method according to claim 1, characterized in that Fitting the multiple switch parameters to obtain a fitness function and a screening condition function includes: The multiple switch parameters corresponding to different gate resistances are fitted to obtain the fitting function of each switch parameter. The specific expression is: in, represents the gate resistance of the first power device, represents the gate resistance of the second power device, represents the fitting function of the kth switch parameter, k=1,2,…,K; K represents the total number of switch parameters; represents the coefficients of the polynomial, and Represent the highest values ​​of i and j respectively; The fitting function corresponding to the switch parameter being the total turn-on loss of the hybrid device, the total turn-off loss of the hybrid device, or the total switching loss of the hybrid device is used as the fitness function; The fitting function corresponding to the switch parameters of the turn-on current peak of the first power device, the turn-on current peak of the second power device, the turn-off current peak of the first power device, the turn-off current peak of the second power device, and the turn-off voltage peak of the hybrid device is used as the screening condition function.

5. The method according to claim 4, characterized in that When different gate resistances are used in the turn-on process and the turn-off process of the power device, the fitness function is iteratively optimized according to the screening condition function to obtain the target gate resistance corresponding to each power device, including: Taking the fitting function corresponding to the total turn-on loss of the hybrid device as the first fitness function, iteratively optimizing the first fitness function according to the screening condition function, and obtaining the turn-on gate resistances corresponding to the first power device and the second power device respectively; The fitting function corresponding to the total turn-off loss of the hybrid device is used as the second fitness function, and the second fitness function is iteratively optimized according to the screening condition function to obtain the turn-off gate resistances corresponding to the first power device and the second power device respectively.

6. The method according to claim 4, characterized in that When the same gate resistance is used in the turn-on process and the turn-off process of the power device, the fitness function is iteratively optimized according to the screening condition function to obtain the target gate resistance corresponding to each power device, including: The fitting function corresponding to the total switching loss of the hybrid device is used as the third fitness function, and the third fitness function is iteratively optimized according to the screening condition function to obtain the target gate resistances corresponding to the first power device and the second power device respectively.

7. The method according to claim 5 or 6, characterized in that: Iteratively optimizing the fitness function according to the screening condition function to obtain a target gate resistance corresponding to each power device includes: Generate an individual population according to a first gate resistor and a second gate resistor, wherein the first gate resistor corresponds to the gate resistor of the first power device, and the second gate resistor corresponds to the gate resistor of the second power device; According to the screening condition function, calculating the screening condition function value corresponding to each individual in the individual population; The screening condition function value corresponding to each individual is used to determine whether it satisfies the constraint condition; The fitness function value corresponding to the individual that meets the constraint conditions is taken as the fitness value of the individual; If the current iteration meets the termination criteria, the first gate resistance and the second gate resistance corresponding to the minimum fitness function value are respectively used as the target gate resistance of the first power device and the target gate resistance of the second power device; wherein the termination criteria include that the change value of the fitness value in N consecutive iterations is less than the preset function tolerance, or the maximum number of iterations is reached.

8. The method according to claim 5, characterized in that The method further comprises: Set the fitness values ​​of individuals that do not meet the constraints to the preset values; If the current iteration does not meet the termination criteria, a new individual for the next iteration is selected based on the fitness value corresponding to each individual; Performing crossover and genetic mutation on the new individuals to generate a new individual population; The new individual population is iterated in a loop until a termination criterion is met.

9. A device for determining gate resistance of a hybrid device, characterized in that: The device comprises: A circuit model acquisition module, used to obtain a parasitic parameter circuit model of the hybrid device according to the design model of the hybrid device; A switch parameter acquisition module, used to simulate the parasitic parameter circuit model to obtain a plurality of switch parameters corresponding to different gate resistances; A parameter fitting module, which fits the multiple switch parameters to obtain a fitness function and a screening condition function; The iterative optimization module is used to iteratively optimize the fitness function according to the screening condition function to obtain a target gate resistance corresponding to each power device.

10. An electronic device, characterized in that: include: processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the executable instructions to enable the electronic device to implement the gate resistance determination method of the hybrid device as described in any one of claims 1 to 8.

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