A superconducting quantum chip wiring and optimization method

Abstract

The present invention discloses a method for automatic wiring and optimization of superconducting quantum chips, belonging to the field of automated design of superconducting quantum chips. In the modeling phase, the method adopts a "combined wiring template" model under a fine-grained grid. The combined wiring template is used to discretize the problem, avoiding the complex geometric operations in the arc wiring problem solution process and significantly reducing the algorithm's search space. In the legal solution search phase, a one-sided wiring algorithm is adopted. Based on the wiring result characteristics of the algorithm, the line sequence search problem is extended and a line sequence tree search framework is designed. On this basis, the blocking relationship between lines is explored and a series of search optimization strategies are designed. An exchange winding action is adopted to meet the special line sequence requirements of the read line. In the wiring optimization phase, an iterative optimization wiring scheme based on space constraints is adopted. Based on the legal solution, the overall wiring result is optimized at multiple levels of objectives to ensure that the wiring result meets the design requirements.

Description

Technical Field

[0001] The present invention belongs to the field of automatic design of superconducting quantum chips, and more specifically, relates to a superconducting quantum chip wiring and optimization method. Background Art

[0002] In recent years, quantum computers have become one of the most intriguing research areas. Unlike traditional computers, quantum computers perform mathematical calculations according to the laws of quantum mechanics. Quantum computing has the potential to solve certain problems that are intractable for traditional computers and is of great significance in research fields such as cryptography, machine learning, and quantum measurement. Currently, quantum computer designs primarily include those based on superconducting qubits, photons, trapped ions, and silicon qubits. Superconducting quantum computers offer superior performance and controllability, with the superconducting qubit (qubit) as their core unit. Superconducting quantum computers are one of the mainstream quantum computer types and have become one of the most important candidates for scalable quantum processors. In 2019, Google's 53-qubit superconducting quantum computer, "Platanus," achieved quantum supremacy for the first time. Subsequently, "Zu Chongzhi," developed by a team from the University of Science and Technology of China, achieved quantum supremacy again with 66 qubits. IBM's Condor, released in 2023, boasts 1,121 qubits, bringing the qubit count of existing superconducting quantum computers to the thousands. The number of bits in superconducting quantum chips has exploded in recent years, significantly impacting the overall performance of quantum computers. Future commercially viable general-purpose quantum computers are expected to require millions of qubits. Integrating a large number of superconducting qubits onto a single quantum chip will make the design and manufacturing process unprecedentedly complex. However, the current layout design process for superconducting quantum chips still relies heavily on human decision-making, primarily through manual design supplemented by automated tools. This approach is unable to meet the time and quality requirements for chip design. Summary of the Invention

[0003] In response to the above-mentioned deficiencies or improvement needs of the prior art, the present invention provides a superconducting quantum chip wiring and optimization method, which can shorten the design cycle of superconducting quantum chips and improve the design quality and performance of the chip.

[0004] To achieve the above objectives, according to a first aspect of the present invention, a method for automatic wiring and optimization of a superconducting quantum chip is provided, comprising:

[0005] The wiring layout is gridded and, under preset constraints, the optimal wiring result for the superconducting quantum chip is obtained by minimizing the number of turns and the total length of the line.

[0006] The optimal wiring result includes the wiring solutions of n read lines and m control lines. Each wiring solution includes multiple wiring templates and the type value of each wiring template, the actual line length, the number of grids offset between the template end point and the starting point on the x-axis and y-axis, and the number of grids at d1, d2, and d b The relative coordinates of all grids passed through the range and the starting point, and the direction of rotation of the routing template relative to the forward direction;

[0007] The preset constraints include:

[0008] Route geometry constraints: Routes are constructed by sequentially stitching together multiple routing templates. These routing templates include a straight line template, a turn template, and an offset template. The turn template is a quarter-circle arc, and the offset template is a stitching together of arcs corresponding to the inner alternate angles at the diagonal of a parallelogram. The minimum length of a set of parallel sides of the parallelogram is r, the length of the diagonal is 2r, and the minimum radius of the arc is r. The type values ​​of the straight line template, turn template, and offset template are 0, 1, and 2, respectively. The type value is used to simultaneously characterize the type of routing template and the number of turns.

[0009] Wire connectivity constraints: The endpoints of the read and control wires correspond to a unique non-empty wire solution. In a wire solution, the starting point of the first routing template is the starting point of the wire, the end point of the last routing template is the end point of the wire, the starting point of the current routing template is the end point of the previous routing template, and the end point of the current routing template is the starting point of the next routing template.

[0010] Line spacing constraints: The minimum spacing between control lines or between control lines and read lines is d1, the minimum spacing between read lines is d2, and the minimum spacing between microwave transmission lines and wiring obstacles is d b .

[0011] According to a second aspect of the present invention, there is provided an electronic device comprising: a computer-readable storage medium and a processor;

[0012] The computer-readable storage medium is used to store executable instructions;

[0013] The processor is configured to read the executable instructions stored in the computer-readable storage medium and execute the method according to the first aspect.

[0014] According to a third aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to execute the method according to the first aspect.

[0015] According to a fourth aspect of the present invention, a computer program product is provided, comprising a computer program or instructions, which implement the method according to the first aspect when executed by a processor.

[0016] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0017] 1. Existing academic research and commercial tools are currently unable to solve the experimental examples used in this study, especially for large-scale layouts with a large number of bits and dense wiring, where even tool-assisted wiring is very difficult. The method provided by this invention establishes a "combined wiring template" based on the chip to solve the arc wiring and air bridge layout problems of superconducting quantum chips. Using a modeling scheme for the combined wiring template, a "combined wiring template" model is established on a fine-grained grid, which highly discretizes the problem. Discretizing the problem through the combined wiring template avoids the complex geometric operations in the arc wiring problem solution process and significantly reduces the algorithm's search space, making it possible to solve and optimize the wiring of highly integrated layouts.

[0018] 2. Considering computational efficiency, as a further optimization of the present invention, a complete wiring process from legal line sequence search to wiring optimization is designed to realize the automated wiring function of real superconducting chips. In the legal solution search stage, a one-sided wiring algorithm is adopted. Based on the wiring result characteristics of the algorithm, the line sequence search problem is extended and a line sequence tree search framework is designed, which effectively solves the wiring resource competition problem of superconducting quantum chips. The one-sided wiring algorithm has many interesting wiring characteristics, powerful search capabilities, flexible scalability and excellent wiring efficiency in the escape wiring problem. On this basis, the blocking relationship between lines is explored, and a series of search optimization strategies such as two-step backtracking and blocking table are proposed. In addition, an exchange winding action is proposed to further expand the one-sided wiring to meet the special line sequence requirements of the read line. In the wiring optimization stage, an iterative optimization wiring scheme based on space constraints is designed. Based on the legal solution, the overall wiring result is optimized at multiple levels of objectives, so that the final wiring result meets the design requirements.

[0019] 3. As a further preference of the present invention, a spatial restriction concept is introduced during wiring optimization to solve the multi-objective optimization problem in superconducting quantum chip wiring. When designing the exchange winding action and the iterative wiring optimization algorithm, the algorithm first marks the space near the legal solution of one or more lines as a local search area, and the new line is routed within the limited area. This method allows the new line to simply inherit the direction characteristics of the previous line, while limiting the scale of the search space, making it possible to use complex and inefficient wiring algorithms. Spatial restriction not only guarantees the search efficiency of iterative wiring optimization, but is also a prerequisite for the implementation of winding actions. In wiring problems with complex wiring rules and the need to consider the direction relationship between multiple lines, the spatially restricted wiring algorithm design concept has higher flexibility and controllability. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of each wiring template provided in an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of a single-sided wiring effect provided by an embodiment of the present invention. Figure 2 (a) to (d) are schematic diagrams of the wiring sequence of A, B, the wiring sequence of C, A, B, the wiring sequence of A, C, B, and the wiring sequence of C, B, A, respectively;

[0022] Figure 3 A schematic diagram of line sequence search under two-step backtracing provided by an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of the switching winding action provided by an embodiment of the present invention, Figure 4 (a) to (d) are schematic diagrams of unilateral routing in the order of B and C, marking the spaces of lines C and B, unilateral routing of spatially marked read line B, and unilateral routing of control line C;

[0024] Figure 5 A schematic diagram of a spatial iterative routing optimization process provided by an embodiment of the present invention. Figure 5 (a) to (d) are schematic diagrams of the first, second, and third routing iterations and the optimal routing result, respectively. DETAILED DESCRIPTION

[0025] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0026] The layout design process for a superconducting quantum chip, also known as the physical design phase of the chip, begins by placing a series of core components, such as bits and couplers, according to the chip's logic design. Microwave transmission lines are then installed to connect the qubits to external pins, and finally, other design requirements, such as solder joint and hole placement, are finalized. The completed layout undergoes physical rule verification and post-simulation validation to ensure that the design meets constraints and meets requirements. Layouts that do not meet design requirements are fed back into the corresponding design process, requiring re-design and verification. As chip size grows, the design process becomes increasingly complex, significantly increasing the difficulty and time required for each design step. Currently, the design phase of a large-scale layout can take several days in a single iteration. Furthermore, the results of manually drawn layouts are somewhat uncontrollable, making it difficult to verify the design results during the design process, prone to errors, and resulting in increased design iterations and significant time costs.

[0027] During the layout design phase, automatic routing is the most difficult, time-consuming, and yet one of the most important steps. Routing involves planning the specific microwave transmission lines from the read and control cavities under the quantum bits to the outside of the chip. Each quantum bit generally has corresponding read and control lines, so the number of lines is positively correlated with the number of quantum bits. In addition to the increased design time due to the number of lines, currently designed superconducting quantum computers are noisy quantum computers, and their performance is not as stable as the digital circuits used in traditional computers. The core of superconducting quantum computers uses microwave transmission lines to transmit signals. The noise and crosstalk generated during transmission directly affect the reliability and performance of the calculations. Designing a routing scheme for microwave transmission lines in the layout to achieve a balance between signal dissipation and noise is a major challenge.

[0028] The current bottleneck of quantum computers is not limited to breakthroughs in physical theory; it also tests the design and manufacturing process of quantum chips. Traditional quantum chip layout and routing processes rely on a large amount of manpower, and are no longer able to meet the development needs of superconducting quantum computers in terms of time cost, design quality, and reliability. The layout automation and routing capabilities of quantum electronic design automation (Q-EDA) tools are crucial to the development of superconducting quantum chips. Efficient automated routing can not only significantly shorten the design cycle of superconducting quantum chips, but also improve the chip's design quality and performance, making it an indispensable design tool for the future design and development of superconducting quantum chips.

[0029] Faced with the wiring problems of advanced, highly integrated, large-scale superconducting quantum chips, traditional physical design methodologies are still unable to adapt to their physical design requirements. The main problems are as follows:

[0030] 1) Due to the large differences in design requirements in different scenarios during circuit layout design, the algorithm designs of these studies are often highly targeted, making it difficult to find a unified solution to all wiring problems. Superconducting quantum chips use coplanar waveguide circuits, and to date, there has been no research on automatic wiring specifically targeting the characteristics of highly integrated superconducting quantum chips. The biggest difference from conventional circuits is that they use coplanar waveguides to transmit high-frequency microwave signals. When microwave transmission lines need to turn, they must use curved turns to ensure signal stability and reduce crosstalk. This is also the fundamental difference and difficulty between the automatic wiring problem of superconducting quantum chips and other automatic wiring research.

[0031] 2) The current state of routing functionality in currently released Q-EDA tools primarily expands upon traditional circuit automatic routing algorithms and layout tools. While these tools have taken shape, they are still immature. Their algorithms are less specific to the curved circuit characteristics of superconducting quantum chips, and solutions offered by different companies vary and are not directly compatible with each other. The tools also impose significant restrictions on design processes and parameters, resulting in very limited functionality.

[0032] 3) Existing Q-EDA tools that support routing have limited routing capabilities, cannot automatically route multiple routes simultaneously, and are unable to automatically route chip layouts with dense wiring. Publicly available Q-EDA tools have lowered the design threshold for superconducting quantum chip layouts to a certain extent, but due to limitations in their algorithm design and company commercial considerations, they cannot currently meet the design requirements of cutting-edge chips.

[0033] Based on this, an embodiment of the present invention provides a method for automatic wiring optimization of a superconducting quantum chip, comprising:

[0034] The wiring layout is gridded and, under preset constraints, the optimal wiring result for the superconducting quantum chip is obtained by minimizing the number of turns and the total length of the line.

[0035] The optimal wiring result includes the wiring solutions of n read lines and m control lines. Each wiring solution includes multiple wiring templates and the type value of each wiring template, the actual line length, the number of grids offset between the template end point and the starting point on the x-axis and y-axis, and the number of grids at d1, d2, and d b The relative coordinates of all grids passed through the range and the starting point, and the direction of rotation of the routing template relative to the forward direction;

[0036] The preset constraints include:

[0037] Route geometry constraints: Routes are constructed by sequentially stitching together multiple routing templates. These routing templates include a straight line template, a turn template, and an offset template. The turn template is a quarter-circle arc, and the offset template is a stitching together of arcs corresponding to the inner alternate angles at the diagonal of a parallelogram. The minimum length of a set of parallel sides of the parallelogram is r, the length of the diagonal is 2r, and the minimum radius of the arc is r. The type values ​​of the straight line template, turn template, and offset template are 0, 1, and 2, respectively. The type value is used to simultaneously characterize the type of routing template and the number of turns.

[0038] Wire connectivity constraints: The endpoints of the read line and the control line correspond to a unique non-empty wire solution. In a wire solution, the starting point of the first routing template is the starting point of the wire, the end point of the last routing template is the end point of the wire, and the end point is on the boundary of the layout to be routed that can be used as an end point. The starting point of the current routing template is the end point of the previous routing template, and the end point of the current routing template is the starting point of the next routing template.

[0039] Line spacing constraints: The minimum spacing between control lines or between control lines and read lines is d1, the minimum spacing between read lines is d2, and the minimum spacing between microwave transmission lines and wiring obstacles is d b .

[0040] The method provided by the present invention analyzes the constraints and optimization goals of the superconducting quantum wiring problem based on its physical characteristics, and establishes a wiring problem mathematical model that is highly correlated and easy to optimize.

[0041] The mathematical model of layout and routing problems mainly considers the following elements:

[0042] 1. Known Information

[0043] 1) Layout boundaries: represent the size of the chip and the area of ​​wiring

[0044] 2) Escape end point: The boundary representing the end point of the wiring.

[0045] 3) Obstacles: Wiring obstacles consisting of resonant cavities, substrates, and some other components, through which microwave transmission lines cannot pass.

[0046] 4) Line starting point: the starting point of the control line and the read line.

[0047] 2. Decision variables

[0048] 1) Route solution: The solution of all routes consisting of arcs and straight lines of a specific arc.

[0049] 3. Optimization goals

[0050] 1) Minimize the number of corners (CoC): Corners in microwave transmission lines cause signal loss and generate noise. Therefore, more turns in a line mean less stable transmission quality and higher chip error rates. Furthermore, a wiring design with fewer turns creates a more aesthetically pleasing and neat route, which aligns with manual wiring design practices.

[0051] The regular design also makes it easier for chip designers to make additional design changes and maintenance, while also leaving more effective space for adding other components in subsequent processes;

[0052] 2) Minimize the total wire length (TWL): The length of the line directly affects the signal transmission quality and loss. At the same time, a shorter total wire length also means less space occupied by wiring on the chip. Therefore, total wire length is also one of the key indicators for improving chip integration.

[0053] 4. Constraints

[0054] 1) Line geometry constraints: The line must consist of straight lines or circular arcs, and the radius of the arc must be greater than or equal to r. When a microwave transmission line needs to make a turn, a curved turn should be used. The main purpose is to reduce signal reflection and loss, which is also the biggest feature and difficulty of this wiring problem.

[0055] 2) Line connectivity constraint: All read lines and control line endpoints must correspond to a unique non-empty line solution. i ={s1, s2, ...s m The starting point of line segment s1 is the endpoint of the line, and line segment s m The end point is on the boundary of the chip that can be used as the end point. For any j∈[1,m-1], s j The end point and s j+1 The starting point must be the same. Connectivity constraints ensure that the results meet the basic logic requirements of routing, which is also the basic goal of all routing problems;

[0056] 3) Line spacing constraint: In a superconducting quantum chip, all lines cannot overlap with obstacles or other lines, and must maintain a certain distance from them. The distance between the line and the obstacle d b The requirement for line spacing, d1 and d2, depends primarily on the line width and manufacturing process. Microwave signals are susceptible to noise and crosstalk between lines, also known as signal coherence. The spacing between readout lines is typically larger than that between other lines because the readout signal is more sensitive to noise.

[0057] The main symbolic definitions of the mathematical model of the superconducting quantum chip wiring problem are shown in Table 1.

[0058] Table 1 Symbol definitions of the mathematical model for the superconducting quantum chip wiring problem

[0059]

[0060]

[0061] The method provided in the embodiment of the present invention adopts the "combined wiring template" as follows Figure 1 As shown in Figure 2, the starting and ending points of these routing templates can be perfectly placed on the vertices of the grid, and all routing solutions are defined, which are composed of several continuous routing templates. The contents of a combined routing template are shown in Table 2. Among them, the parameters in Table 1 that need to be known in advance for calculating the routing template include: the minimum spacing between all lines d1, the minimum spacing between read lines d2, and the minimum spacing between lines and obstacles d b , minimum turning radius r.

[0062] Table 2 Main information contained in a wiring template

[0063]

[0064] Under the "Combined Wiring Template", the decision variables for this solution are:

[0065] Rw={r1,r2……r n} (1)

[0066] R C ={r n ,r n+1 ....r n+m} (2)

[0067] r i ={t i1 ,t i2 ,....t io} (3)

[0068] Among them, t i1 ,t i2 ,t io They are the first, second and last wiring templates of the i-th line respectively. The parameters contained in each wiring template are shown in Table 2.

[0069] The optimization goal is:

[0070]

[0071]

[0072] In this modeling, the output of the problem can be supplemented as R w and R C , expressed as formula (1) and formula (2), respectively representing n read line solutions and m control line solutions. i It can be expressed as formula (3), which means that the solution of a line is composed of several routing templates. The first-level optimization goal of the problem is to minimize the total number of turns COC, which can be expressed as formula (4), which means R C and R W The sum of the type of all solution templates t in the second level optimization goal is to minimize the total length TWL, which is expressed as formula (5), representing R C and R W The sum of the len of the template t of all solutions in .

[0073] The method provided in the embodiment of the present invention generates a set of routing templates by combining arc segments and straight line segments according to the accuracy and constraint requirements of the layout. The templates include three types: straight line templates, turning templates, and offset templates. The templates can be screened according to the constraints to meet special requirements such as neat and symmetrical placement of air bridges. The combined routing template adopted by this method limits the use of arc lines and converts the routing problem from an irregular path planning problem in a continuous space to a template splicing problem in a grid. In the design of the combined routing template, the geometric shapes of all templates are fixed, and the geometric shape information can be abstracted in advance as relative coordinate position information in a fine-grained grid. In the process of solving routing using templates, it is only necessary to consider the state of the grid where the template is located, and there is no need to repeatedly perform geometric operations to determine whether constraints such as spacing are met.

[0074] The above mathematical model can be solved using existing methods, such as brute force solution. Considering the computational complexity, as a further preferred embodiment of the present invention, the following method is used to solve the optimal wiring result:

[0075] S1, using a single-side routing algorithm to obtain d1 and d2 that meet the line geometry constraints, the line connectivity constraints of a single line, and the line spacing constraints. b A solution for a single line with constraints is obtained; a tree search method is used to obtain the wiring order between the lines that meets the line connectivity constraints of multiple lines. Moreover, after the current read line is routed, if the d2 constraint in the line spacing constraint is violated and the previous line is a control line, the wiring order of the current read line and the control line is swapped so that the wiring order meets the d2 constraint in the line spacing constraint, thereby meeting all constraints in the line spacing constraint and obtaining a legal solution for the line.

[0076] Specifically, in S1, the legal line sequence and preliminary routing are solved to obtain a legal solution that meets the preset constraints. By leveraging the edge-fitting characteristics of the unilateral routing algorithm results, the line resource competition problem is transformed into a line escape sequence search problem. A tree search framework and pruning strategy are designed to optimize the efficiency of the tree search. The methods used include:

[0077] 1. One-sided wiring algorithm

[0078] like Figure 2 The figure shows the effects of using the unilateral routing algorithm in different sequences. The unilateral routing algorithm simulates how a person plans their walking path. In reality, when planning a walking route on complex city streets and under unknown road conditions, people first determine the general direction of their destination or use map navigation or other methods to obtain a rough route. While walking, to avoid collisions with vehicles and other pedestrians, they try to stay as close to the right as possible, while staying within their destination. While pedestrians only know the location and distance of their destination and not the specific route, they have a strong ability to correct errors while walking, allowing them to navigate complex scenarios. Furthermore, all vehicles and pedestrians adhere to the traffic rule of keeping to the right, ensuring traffic order and efficient use of road space.

[0079] The one-sided routing algorithm sets a virtual routing boundary. The algorithm uses the starting point information to set search restrictions or a specific space division method, so that the starting point is at the "edge of a certain space" from the beginning. This design ensures that pedestrians do not stray away from the target when walking or use navigation to obtain a rough path.

[0080] The unilateral routing algorithm dynamically searches for paths along one side of the edge, finding a path that best fits the edge of the space, allowing pedestrians to walk to the right. This avoids the need to use directional patterns to reach the space boundary, as well as the maintenance costs associated with curved boundaries. The main methods used by the unilateral routing algorithm to generate routes include:

[0081] By defining a virtual space, we set the boundaries for the algorithm to walk;

[0082] Set the boundaries of the algorithm's travel by distance or other reference values;

[0083] By simulating the way people walk, the circuit can walk along the edge of the space in complex scenarios to reach the chip boundary.

[0084] 2. Legal Line Sequence Tree Search

[0085] This method uses a tree search framework for line sequence search, which aligns with the characteristics of single-sided routing algorithms. The advantage of this tree search framework is that each time a new branch is searched or backtracked, wires are added or removed only at the end of the existing line sequence, which is consistent with the characteristics of single-sided routing algorithms. Adding or removing wires at the end of the line sequence does not affect the preceding wires, allowing the search process to maximize the use of each routing action and better reuse of existing routing results.

[0086] That is, based on the current routing algorithm, a wire sequence tree search framework is adopted, whose main contents include:

[0087] Convert the resource competition problem into a wiring order problem;

[0088] The legal line sequence is searched through tree search, and the pruning and backtracking strategies are optimized during the search process based on the blocking relationship between lines.

[0089] Figure 3 The figure shows the line-sequence tree search process designed in this solution. This solution leverages the blocking relationships of circuits within the chip, employing a two-step backtracking method and a blocking table approach. First, the blocking relationships between circuits are checked pairwise. During node search and search backtracking, the number of search nodes is reduced based on the blocking relationships.

[0090] 3. Exchange winding action

[0091] This solution uses a wire swapping technique to address the special wiring order requirements of superconducting quantum chips. Specifically, the minimum spacing between readout lines is d2, reducing signal crosstalk between critical lines. For example, in the wire order {C, B}, where B is the readout line and C is the control line, if the spacing between B and other legally routed readout lines is less than d2, the wires need to be swapped to adjust the order to {B, C}. Figure 4 This means that line B is bypassed by line C to realize the wiring process in line sequence {B, C}. Figure 4 In (a), use the one-side winding algorithm to lay out lines C and B in reverse order. Then, Figure 4 In (b), mark the routable space around lines B and C and the routable space around the starting point C, and delete lines B and C. Figure 4 In (c), line B is routed along the edge of the marked space. Finally, line C is routed again using the monotonic one-sided routing algorithm, resulting in Figure 4 The winding effect in (d).

[0092] S2, uses the A* algorithm to optimize the legal solutions according to the objective function to obtain the optimal solution.

[0093] Specifically, based on the space-constrained iterative routing optimization algorithm, the number of turns and total length of the route are further optimized based on the legal solution to obtain the optimal routing result. By replacing a single large-scale search with multiple small-scale optimal path searches, the impact of large-scale space on search efficiency is reduced. Specifically, the following are included:

[0094] 1. Wiring optimization for space constraints

[0095] This scheme adopts a routing optimization framework that iterates through space constraints. Figure 5 The following shows the general process of iterative optimization. When performing routing optimization, a routing optimization framework that iterates through space constraints is adopted, including:

[0096] By using existing legal routing, a specific routing space is defined to reduce the algorithm’s search space;

[0097] By setting specific routing priorities, the algorithm can optimize the number of turns in the route after multiple iterations;

[0098] Optimize the turns and length of multiple routes through multiple specific sequence optimizations.

[0099] In order to improve the computational efficiency, as a further optimization of the present invention, based on a legal line, the space near it (for example, an area of ​​N times the line width, the specific area range can be designed according to the actual computational complexity and accuracy requirements) is delineated as the iteration space. In the next round of iteration, the A* algorithm is used to find an optimal path in the iteration space. This process is repeated until the optimal path in the iteration space no longer changes. The design of spatial iteration directly limits the scope of the search, replacing a large-scale search with multiple small-scale iterative optimization searches. This design greatly reduces the search space of the algorithm, improves the efficiency of a single search, avoids the impact of the degradation of the A* algorithm when optimizing the number of turns, and enhances the stability of the search process.

[0100] Furthermore, due to the routing characteristics of the single-sided routing algorithm, all lines are tightly packed on one side, leaving only the last line with the most remaining routing space. Based on this, as a further optimization, the present invention optimizes each line in reverse order to free up remaining space, freeing up routing resources for lines at the beginning of the order.

[0101] In order to improve the computational efficiency, as a further optimization of the present invention, this solution adopts a multi-layer A* search algorithm, where the number of search layers represents the number of turns of the current search route, in order to solve the problem of optimizing the number of turns. The algorithm first attempts to search for a feasible shortest path with 0 turns. If unsuccessful, the number of search layers, that is, the number of turns of the route, is gradually increased until the end point can be reached. The candidate points in the open set of the A* algorithm can be represented from high to low according to three priorities: the route with the least number of turns, the length of the route traveled plus the length of the heuristic evaluation is the shortest, and the route traveled is the longest. The evaluation of the line length can directly use the Manhattan distance calculated by the coordinate difference, or the estimated distance of each grid to the escape edge can be calculated in advance by the Maze Routing method.

[0102] 2. Open Lazy Set

[0103] Because a combined routing template consists of at most two arcs, candidate points from at most two layers back will be generated in the current search layer. Furthermore, candidate points from the two layers back will not be used until all candidate points in the current layer are exhausted. This feature allows for the construction of a "lazy open set" to optimize the efficiency of maintaining the min-heap.

[0104] During the element insertion process, if the new candidate point does not increase the number of turns, it is directly inserted into the heap; otherwise, it is temporarily stored in a temporary list according to the type value of the template.

[0105] When the element with the minimum heuristic function value needs to be popped, if the heap is not empty, it is popped directly. Otherwise, it means that the next layer needs to be searched, and the heap is constructed again through a temporary list.

[0106] That is, when performing routing optimization, an open lazy set structure is used to optimize the routing speed of the line, including:

[0107] A multi-layer A* search algorithm is used, and the number of search layers represents the number of turns in the current search route;

[0108] A lazy open set design is adopted to delay the time for candidate line nodes to participate in heap maintenance, thereby reducing the heap size and maintenance cost.

[0109] Lazy open sets delay the inclusion of non-essential data in the open set in heap maintenance. This significantly reduces the size of the heap maintained during the search process. Furthermore, at the end of the algorithm, candidate points in the last two layers are not included in the heap construction but are instead cached directly in a list, reducing the number of nodes involved in the min-heap construction. Lazy open sets are well-suited to the structure of multi-level optimization routing problems and reduce the cost of min-heap maintenance. Through simple cache design and engineering optimizations, the lazy open set design can consistently and effectively improve the search efficiency of the A* algorithm during routing optimization.

[0110] An embodiment of the present invention provides an electronic device, comprising: a computer-readable storage medium and a processor;

[0111] The computer-readable storage medium is used to store executable instructions;

[0112] The processor is configured to read the executable instructions stored in the computer-readable storage medium and execute the method described in any one of the above embodiments.

[0113] An embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to execute the method described in any of the above embodiments.

[0114] An embodiment of the present invention provides a computer program product, including a computer program or instructions, which implements the method described in any of the above embodiments when executed by a processor.

[0115] It will be easily understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A superconducting quantum chip automatic wiring and optimization method, characterized in that: include: The wiring layout is gridded and, under preset constraints, the optimal wiring result for the superconducting quantum chip is obtained by minimizing the number of turns and the total length of the line. The optimal wiring result includes the wiring solutions of n read lines and m control lines. Each wiring solution includes multiple wiring templates and the type value of each wiring template, the actual line length, the number of grids offset between the template end point and the starting point on the x-axis and y-axis, and the number of grids at d1, d2, and d b The relative coordinates of all grids passed through the range and the starting point, and the direction of rotation of the routing template relative to the forward direction; The preset constraints include: Route geometry constraints: Routes are constructed by sequentially stitching together multiple routing templates. These routing templates include a straight line template, a turn template, and an offset template. The turn template is a quarter-circle arc, and the offset template is a stitching together of arcs corresponding to the inner alternate angles at the diagonal of a parallelogram. The minimum length of a set of parallel sides of the parallelogram is r, the length of the diagonal is 2r, and the minimum radius of the arc is r. The type values ​​of the straight line template, turn template, and offset template are 0, 1, and 2, respectively. The type value is used to simultaneously characterize the type of routing template and the number of turns. Wire connectivity constraints: The endpoints of the read and control wires correspond to a unique non-empty wire solution. In a wire solution, the starting point of the first routing template is the starting point of the wire, the end point of the last routing template is the end point of the wire, the starting point of the current routing template is the end point of the previous routing template, and the end point of the current routing template is the starting point of the next routing template. Line spacing constraints: The minimum spacing between control lines or between control lines and read lines is d1, the minimum spacing between read lines is d2, and the minimum spacing between microwave transmission lines and wiring obstacles is d b .

2. The method according to claim 1, wherein The following solution method is used to calculate and obtain the optimal wiring result: S1, using a single-side routing algorithm to obtain d1 and d2 that meet the line geometry constraints, line connectivity constraints, and line spacing constraints. b A solution for a single line with constraints; a tree search method is used to obtain the routing order between the lines that meet the line connectivity constraints. After the current read line is routed, if the d2 constraint in the line spacing constraint is violated and the previous routed line is a control line, the routing order of the current read line and the control line is swapped to obtain a legal solution for the line. S2, uses the A* algorithm to optimize the legal solutions according to the objective function to obtain the optimal solution.

3. The method according to claim 2, wherein In step S2, the preset area where any legal route in the legal solution is located is used as the iteration space. In the next round of iteration, the A* algorithm is used to find an optimal path in the iteration space. This process is repeated until the optimal path in the iteration space no longer changes.

4. The method according to claim 2 or 3, wherein: In step S2, the routes in the legal solution are optimized one by one in reverse order to release the remaining space.

5. The method according to claim 2 or 3, wherein the A* algorithm is a multi-layer A* algorithm; in, The search layer number represents the number of turns in the current search route; The candidate points in the open set of the multi-layer A* algorithm are ranked according to three priorities from high to low: the number of turns in the route traveled is the least, the length of the route traveled plus the length of the heuristic evaluation is the shortest, and the route traveled is the longest. In the current search level, at most two layers of candidate points are generated, and the candidate points in the next two layers will not be used until the candidate points in the current layer are exhausted. During the element insertion process, if the new candidate point does not increase the number of turns, it is directly inserted into the heap; otherwise, it is temporarily stored in a temporary list based on the template type. When the element with the minimum heuristic function value needs to be popped, if the heap is not empty, it is popped directly, otherwise the heap is built through a temporary list.

6. An electronic device, characterized in that: include: Computer-readable storage medium and processor; The computer-readable storage medium is used to store executable instructions; The processor is configured to read the executable instructions stored in the computer-readable storage medium and execute the method according to any one of claims 1 to 5.

7. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to execute the method according to any one of claims 1 to 5.

8. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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