Source driving circuit and display device

Abstract

The present invention provides a source driver circuit and a display device, wherein the source driver circuit includes a plurality of chip-on-chip films bonded side by side to a display panel, the chip-on-chip films including a source driver chip and a first signal line connecting the source driver chip and a data line of the display panel. Each source driver chip determines its own polarity switching mode, and when the polarity switching modes of the first signal lines of two adjacent chip-on-chip films are opposite, when the polarity of adjacent first signal lines is the same, one of the two adjacent first signal lines of the two adjacent chip-on-chip films is switched to dot flipping. The polarity of this first signal line is switched row by row, and the polarity is different from that of the adjacent first signal lines, thereby weakening dark lines and improving display effects.

Description

Technical Field

[0001] The present invention belongs to the technical field of display panels, and in particular relates to a source driving circuit and a display device. Background Art

[0002] A conventional display panel is bonded with multiple chip-on-films (COFs), each of which includes a source driver chip. The source driver chip outputs multiple data signals to multiple data lines of the display panel to drive the display panel.

[0003] With the development of display technology, display panels tend to develop towards larger size and higher resolution. Correspondingly, the number of chip-on-chip films in the display panel has increased relatively. There are differences between the data transmission and actual effects between different chip-on-chip films, resulting in adjacent output channels having the same polarity in the same frame. During the frame switching process, the pixel units between the two data lines connected to the adjacent output channels experience brightness changes, resulting in the existence of dark lines, which reduces the display effect of the display panel. Summary of the Invention

[0004] The object of the present invention is to provide a source driving circuit, aiming to solve the problem of dark lines of the same polarity appearing in adjacent output channels of a traditional source driving circuit in the same frame.

[0005] A first aspect of an embodiment of the present invention provides a source driver circuit, comprising:

[0006] A plurality of chip-on-films (COFs) bonded side by side to the display panel, each COF comprising a source driver chip and a plurality of first signal lines, the source driver chip outputting multiple data signals via the plurality of first signal lines, the plurality of first signal lines of each COF being connected to a group of data lines in the display panel, the plurality of data line groups being arranged side by side, each group of data lines comprising an even number of data lines;

[0007] When the polarity switching pattern of the plurality of first signal lines of the 2i-1th chip-on-film is opposite to the polarity switching pattern of the plurality of first signal lines of the 2ith chip-on-film, the polarity of one of the two adjacent first signal lines of the 2i-1th chip-on-film and the 2ith chip-on-film is switched row by row in a dot flipping mode when the display panel is driven row by row, wherein i is a positive integer;

[0008] The polarity switching mode is a first polarity switching mode or a second polarity switching mode. The first polarity switching mode is periodically switched in the order of the first polarity to the second polarity. The second polarity switching mode is periodically switched in the order of the second polarity to the first polarity. The first polarity and the second polarity are positive and negative polarities to each other.

[0009] Optionally, the (2i-1)th source driver chip of the chip-on-film sequentially switches the polarities of the plurality of first signal lines connected thereto according to a first polarity pattern in response to a first-level signal of the first polarity switching signal, or sequentially switches the polarities of the plurality of first signal lines connected thereto according to a second polarity pattern in response to a second-level signal of the first polarity switching signal, wherein the first-level signal and the second-level signal are signals of opposite levels;

[0010] The 2ith source driver chip of the flip chip film switches the signals of the multiple first signal lines connected thereto in sequence according to the first polarity mode in response to the third level signal of the second polarity switching signal, and switches the signals of the multiple first signal lines connected thereto in sequence according to the second polarity mode in response to the fourth level signal of the second polarity switching signal, wherein the third level signal and the fourth level signal are opposite level signals.

[0011] Optionally, the chip-on-film further comprises a film body, and the film body comprises multiple circuit layers;

[0012] The two adjacent first signal lines of the 2i-1th COF and the 2ith COF are located in different circuit layers of the film body.

[0013] Optionally, the two adjacent first signal lines of the 2i-1th COF and the 2ith COF are respectively located on the surface layer of the film body and the inner layer adjacent to the surface layer of the film body;

[0014] The non-adjacent first signal lines of the 2i-1th COF and the 2ith COF are located on the surface layer of the film body.

[0015] Optionally, the nth first signal line of the 2i-1th chip-on-chip film is located in the inner layer of the film body, or the first first signal line of the 2i-1th chip-on-chip film is located in the inner layer of the film body, and the nth first signal line of the 2i-1th chip-on-chip film is arranged adjacent to the first first signal line of the 2i-1th chip-on-chip film.

[0016] Optionally, the source driver chip is integrated into the thin film body;

[0017] The source driver chip is connected to the first signal line located in the inner layer of the film body through a via hole.

[0018] Optionally, the COF further includes a plurality of second signal lines, each of which is stacked on one of the first signal lines located on the inner layer and connected to the source driver chip of the same COF;

[0019] When the polarity switching mode of the multiple first signal lines of the 2i-1th flip chip film is the same as the polarity switching mode of the multiple first signal lines of the 2ith flip chip film, the source driver chip corresponding to the flip chip film outputs the data signal through the second signal line, and the polarity of the data signal of the second signal line is switched according to the frame inversion mode.

[0020] Optionally, the chip-on-film further includes a plurality of switches;

[0021] The first signal line and the second signal line are stacked and connected in series with one of the switches respectively;

[0022] The source driver chip is used for:

[0023] When the polarity switching pattern of the plurality of first signal lines of the 2i-1th chip on film is the same as the polarity switching pattern of the plurality of first signal lines of the 2ith chip on film, controlling the switch connected in series to the second signal line to be turned on;

[0024] When the polarity switching pattern of the multiple first signal lines of the 2i-1th chip-on-film is opposite to the polarity switching pattern of the multiple first signal lines of the 2ith chip-on-film, the switch connected in series to the first signal line located in the inner layer is controlled to be turned on.

[0025] Optionally, the source driver chip is further used to:

[0026] When the polarity switching pattern of the plurality of first signal lines of the 2i-1th chip on film is the same as the polarity switching pattern of the plurality of first signal lines of the 2ith chip on film, outputting the first data signal to the second signal line;

[0027] And when the polarity switching pattern of the multiple first signal lines of the 2i-1th flip chip film is opposite to the polarity switching pattern of the multiple first signal lines of the 2ith flip chip film, a second data signal is output to the first signal line located in the inner layer, and the second data signal is greater than the first data signal.

[0028] A second aspect of an embodiment of the present invention provides a display device, including a display panel and the source driving circuit as described above.

[0029] Compared with the prior art, the beneficial effects of the embodiments of the present invention are as follows: the above-mentioned source driver circuit includes multiple flip-chip films bonded side by side to the display panel, the flip-chip films include a source driver chip and a first signal line connecting the source driver chip and the data line of the display panel, each source driver chip determines its own polarity switching mode, and when the polarity switching modes of the first signal lines of two adjacent flip-chip films are opposite, when the polarity of the adjacent first signal lines is the same, one of the two adjacent first signal lines of the two adjacent flip-chip films is switched to dot flipping, and the polarity of the first signal line is switched row by row, and the polarity is different from that of the adjacent first signal line, thereby weakening the dark line and improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0031] Figure 1 A schematic structural diagram of a display panel provided in Embodiment 1 of the present invention;

[0032] Figure 2 A schematic diagram of a first waveform of adjacent data lines provided in the first embodiment of the present invention;

[0033] Figure 3 A schematic diagram of a second waveform of adjacent data lines provided in the first embodiment of the present invention;

[0034] Figure 4 A schematic diagram of a third waveform of adjacent data lines provided in the first embodiment of the present invention;

[0035] Figure 5 A schematic diagram of the first structure of the chip-on-film provided in the second embodiment of the present invention;

[0036] Figure 6 A schematic diagram of a second structure of a chip-on-film provided in the second embodiment of the present invention;

[0037] Figure 7 A schematic diagram of a third structure of a chip-on-film provided in the second embodiment of the present invention;

[0038] Figure 8 A schematic diagram of a fourth structure of a chip-on-film provided in the second embodiment of the present invention;

[0039] Figure 9 A schematic diagram of the first structure of the chip-on-film provided in the third embodiment of the present invention;

[0040] Figure 10 A schematic diagram of a second structure of a chip-on-film provided in the third embodiment of the present invention;

[0041] Figure 11 A schematic diagram of a third structure of a chip-on-film provided in the third embodiment of the present invention;

[0042] Figure 12 This is a schematic structural diagram of a display device provided in Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0043] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0044] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0045] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0047] A first aspect of an embodiment of the present invention provides a source driver circuit 100, comprising a plurality of chip-on-films (COFs) 110 bonded side by side to a display panel 200. The display panel 200 includes a display area 210 and a non-display area 220. The non-display area 220 includes a bonding area. The COFs 110 are bonded to the bonding area. The display area 210 includes a plurality of data lines, a plurality of scan lines, and pixel units 230. The pixel units 230 are respectively connected to a data line and a scan line. The plurality of data lines may be grouped according to the number of COFs 110. The plurality of data lines are arranged side by side in sequence. Each group of data lines includes an even number of data lines, for example, each group of data lines includes 996 data lines. The plurality of data lines in each group are respectively connected to the COF 110 and input multiple data signals. The scan lines are also connected to the gate driver circuit 300 and input row scan signals for row-by-row scanning and data signal writing. The data signals are written to the pixel units 230 so that the display panel 200 displays corresponding image information.

[0048] Among them, each flip chip 110 includes a source driver chip 111 and multiple first signal lines L1. The source driver chip 111 outputs multiple data signals through the multiple first signal lines L1. The multiple first signal lines L1 of each flip chip 110 are connected to a group of data lines in the display panel 200. Correspondingly, each flip chip 110 includes at least the same number of first signal lines L1 as a group of data lines. For example, each flip chip 110 includes 966 first signal lines L1.

[0049] Among them, the display panel 200's own structural design and product principles will have parasitic capacitance. For example, parasitic capacitance is generated between the pixel electrode of the pixel unit 230 and the adjacent data line. The parasitic capacitance will cause the original output voltage to be coupled with each other, resulting in a difference from the ideal value. This is one of the reasons why dark lines appear.

[0050] Secondly, in the screen display, different polarity switching signals are usually selected to control the signal polarity on the first signal line L1 of the odd-numbered flip chip films 110 and the even-numbered flip chip films 110 respectively, so as to switch the polarity of the data signal on each data line to avoid polarization problems, such as Figure 1As shown, when the two polarity switching signals are different, the polarity switching mode of the data signals output to the corresponding data lines by the odd-numbered source driver chips 111 is different from the polarity switching mode of the data signals output to the corresponding data lines by the even-numbered source driver chips 111, and the polarity of the two adjacent data lines corresponding to the two first signal lines L1 between the odd and even flip-chip films 110 becomes incoherent, which is manifested as the polarity of the two first signal lines L1 at the junction of the flip-chip films 110 is the same as the polarity of the two correspondingly connected data lines. For example, the first data line D1 correspondingly connected to the first source driver chip 111 and the nth data line Dn correspondingly connected to the second source driver chip 111 have the same polarity, resulting in a different degree of coupling of the data line to the pixel electrode at the junction than in other areas, ultimately presenting a problem of dark lines at the junction.

[0051] Taking a 64-grayscale image as an example, the coupling of the entire pixel electrode is divided into three periods for analysis: the display period, the first row analysis, when the first pixel unit 230 between the two data lines at the junction is charged, the row scan signal is input, and the first data line D1 corresponding to the first flip chip film 110 is charged to the negative polarity L64 (V_L64N). At this time, the nth data line Dn corresponding to the second flip chip film 110 is a negative polarity 0 grayscale voltage. After charging is completed, the first row scan signal is turned off, and the data signals of the two adjacent data lines corresponding to the two adjacent flip chip films 110 continue to be transmitted to charge the pixel units 230 of the subsequent rows. Figure 2 Shown and Figure 3 As shown, the data changes of two adjacent data lines corresponding to two adjacent COFs 110 are opposite, and during the display period, the coupling voltages on the pixel electrodes cancel each other out. Therefore, it can be seen that there is no coupling voltage during the actual period.

[0052] During the data processing period, no data signal is output and the pixel unit 230 does not display. At this time, the coupling direction of the two adjacent data lines corresponding to the two adjacent flip-chip films 110 to the pixel electrode is a single direction, and the coupling amount is ΔV, ΔV=V_L64N-0.

[0053] During the frame switching period, the polarity of each first signal line L1 and each first signal line L1 is switched, the positive polarity is switched to the negative polarity, and the negative polarity is switched to the positive polarity, wherein the positive polarity refers to the voltage polarity greater than the common electrode voltage Vcom, and the negative polarity refers to the voltage polarity less than the common electrode voltage Vcom. The common electrode voltage Vcom is the reference voltage. The two adjacent data lines corresponding to the two adjacent flip-chip films 110 change from the same polarity on the previous one to the same polarity on the next one, for example, from the "-" polarity to the "+" polarity. +" polarity, the data signal of the first row of pixel units 230 between two adjacent data lines corresponding to two adjacent flip-chip films 110 is refreshed and switched the fastest after the polarity is switched. The switched data signal is output to the pixel electrode of the first row of pixel units 230, and then the coupling situation of the display period is repeated. Correspondingly, the voltage and coupling amount waveform of the image cable electrode of the last row of pixel units 230 between two adjacent data lines corresponding to two adjacent flip-chip films 110 can be deduced. Because the scanning is line-by-line scanning, before the last row of pixel units 230 is turned on, the voltage of the pixel electrode of the last row of pixel units 230 maintains the data of the previous frame, and there is a large voltage difference with the voltage of the data signal on the data line of the current frame, resulting in greater coupling and smaller coupling voltage, so it is displayed as a dark line. The closer the pixel unit 230 is to the bottom, the more severe the coupling will be. Therefore, the dark line phenomenon is not a through line, and the phenomenon is milder as it approaches the top.

[0054] To this end, in this embodiment, when the polarity switching pattern of the plurality of first signal lines L1 of the 2i-1th chip-on-film 110 is opposite to the polarity switching pattern of the plurality of first signal lines L1 of the 2i-th chip-on-film 110, the polarity of one of the two adjacent first signal lines L1 of the 2i-1th chip-on-film 110 and the 2i-th chip-on-film 110 is switched row by row in a dot flipping mode when the display panel 200 is driven row by row, where i is a positive integer;

[0055] The polarity switching mode is a first polarity switching mode or a second polarity switching mode. The first polarity switching mode is periodically switched in the order of the first polarity to the second polarity. The second polarity switching mode is periodically switched in the order of the second polarity to the first polarity. The first polarity and the second polarity are positive and negative polarities to each other.

[0056] In this embodiment, the source driver chip 111 in each flip chip film 110 determines its own polarity switching mode based on the received polarity switching signal, and judges whether it is the first polarity switching mode or the second polarity switching mode, and whether the polarity switching mode is different from the source driver chip 111 of the adjacent flip chip film 110. In the first polarity switching mode, the polarities of the multiple first signal lines L1 and data lines corresponding to each source driver chip 111 are periodically switched in sequence according to the first polarity and the second polarity, for example, they are periodically switched in sequence of positive polarity, negative polarity, positive polarity, and negative polarity, and in the second polarity switching mode, the polarities of the multiple first signal lines L1 and data lines corresponding to each source driver chip 111 are periodically switched in sequence according to the second polarity and the first polarity, for example, they are periodically switched in sequence of negative polarity, positive polarity, negative polarity, and positive polarity.

[0057] When the polarity switching modes of the two are the same, the multiple first signal lines L1 connected to each flip chip film 110 are switched in sequence according to the same polarity switching method. For example, the multiple first signal lines L1 connected to the first flip chip film 110 are switched in sequence according to positive polarity, negative polarity, positive polarity, and negative polarity. Correspondingly, the multiple first signal lines L1 connected to the adjacent second flip chip film 110 are also switched in sequence according to positive polarity, negative polarity, positive polarity, and negative polarity. At this time, the polarities of the two adjacent data lines connected to the two adjacent flip chips 110 are opposite, and there is no different coupling effect on the pixel unit 230 between the two adjacent data lines, and no dark lines are generated.

[0058] On the contrary, when the polarity switching modes of the two are opposite, e.g. Figure 1 As shown, the first flip chip film 110 is connected to a plurality of first signal lines L1 that are switched in sequence according to positive polarity, negative polarity, positive polarity, and negative polarity. The second adjacent flip chip film 110 is connected to a plurality of first signal lines L1 that are switched in sequence according to negative polarity, positive polarity, negative polarity, and positive polarity. The polarities of the two adjacent data lines connected to the two adjacent flip chip films 110 are the same, both of which are negative polarity. Different coupling effects will occur on the pixel units 230 between the two adjacent data lines, resulting in the problem of dark lines at the junction. Therefore, when it is determined that the polarity switching modes of the two are opposite, one of the two adjacent data lines connected to the two adjacent flip chip films 110 is switched to point flipping, such as Figure 4As shown, during row-by-row scanning, the data lines in the row are periodically switched in sequence according to the first polarity and the second polarity. For example, the polarity switching mode on the nth data line Dn connected to the second chip-on-film 110 is switched to dot flipping, or the polarity switching mode on the first data line D1 connected to the first chip-on-film 110 is switched to dot flipping. The polarity switching directions of the other first signal lines L1 and data lines connected to the chip-on-film 110 remain unchanged, and only the polarity switching mode of one of the two adjacent data lines connected to the two adjacent chip-on-films 110 is changed. Since the signal polarity on this data line is no longer fixed and is different from the polarity of the adjacent data line corresponding to the adjacent chip-on-film 110, dark lines are weakened and the display effect is improved.

[0059] Among them, the source driver chip 111 of each flip chip 110 can be switched accordingly according to the received polarity switching signal. In an optional embodiment, the source driver chip 111 of the 2i-1th flip chip 110 switches the polarities of the multiple first signal lines L1 connected thereto in sequence according to the first polarity mode by the first level signal of the first polarity switching signal, or switches the polarities of the multiple first signal lines L1 connected thereto in sequence according to the second polarity mode by the second level signal of the first polarity switching signal. The first level signal and the second level signal are opposite level signals, for example, the first level signal is a high level, and the second level signal is a low level. Therefore, after receiving a high level, the polarities of the multiple first signal lines L1 connected to the odd number of source driver chips 111 are periodically changed in sequence according to the first polarity and the second polarity, and when receiving a low level, the polarities of the multiple first signal lines L1 connected to the odd number of source driver chips 111 are periodically changed in sequence according to the second polarity and the first polarity.

[0060] The source driver chip 111 of the 2i-th flip chip 110 switches the signals of the multiple first signal lines L1 connected thereto in sequence according to the first polarity mode by the third level signal of the second polarity switching signal, and switches the signals of the multiple first signal lines L1 connected thereto in sequence according to the second polarity mode by the fourth level signal of the second polarity switching signal. The third level signal and the fourth level signal are opposite level signals. For example, the third level signal is a high level, and the fourth level signal is a low level. Therefore, after receiving a high level, the polarities of the multiple first signal lines L1 connected to the even number of source driver chips 111 change periodically in sequence according to the first polarity and the second polarity, and when receiving a low level, the polarities of the multiple first signal lines L1 connected to the even number of source driver chips 111 change periodically in sequence according to the second polarity and the first polarity.

[0061] Assuming that the first level signal and the third level signal are high levels, and the second level signal and the fourth level signal are low levels, when the source driver chips 111 of the adjacent odd-numbered and even-numbered flip chips 110 receive the high level and the low level respectively, the source driver chips 111 of the two adjacent flip chips 110 switch the polarity of one of the two adjacent first signal lines L1 of the two flip chips 110 to point switching, thereby reducing parasitic voltage and improving dark lines.

[0062] When the source driver chips 111 of the adjacent odd-numbered and even-numbered flip chips 110 simultaneously receive a high level or a low level, the source driver chips 111 of the two adjacent flip chips 110 switch the two adjacent first signal lines L1 of the two flip chips 110 according to the normal frame switching mode, that is, the polarity direction is switched after each frame.

[0063] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned source driver circuit 100 includes a plurality of chip-on-films 110 bonded side by side to the display panel 200, the chip-on-film 110 includes a source driver chip 111 and a first signal line L1 connecting the source driver chip 111 and the data line of the display panel 200, each source driver chip 111 determines its own polarity switching mode, and when the polarity switching modes of the first signal lines L1 of two adjacent chip-on-films 110 are opposite, when the polarity of the adjacent first signal lines L1 is the same, one of the two adjacent first signal lines L1 of the two adjacent chip-on-films 110 is switched to dot flipping, and the polarity of the first signal line L1 is switched row by row, and the polarity of the first signal line L1 is different from that of the adjacent first signal line L1, thereby weakening dark lines and improving display effects.

[0064] Example 2

[0065] Among them, when the polarity switching modes of the source driver chips 111 of two adjacent flip-chip films 110 are opposite, when one of the two adjacent data lines corresponding to the two adjacent flip-chip films 110 is in dot flip mode, there is still a situation where the polarity of the data line switched in the adjacent frame is the same half of the time, and there is a problem of different parasitic voltages in some pixel units 230, and there are some dark lines. Therefore, in order to further improve the dark line problem, as shown in FIG. Figure 1 、 Figure 5 and Figure 6 As shown, the flip chip 110 further includes a film body 112 , on which the source driver chip 111 and the first signal line L1 are integrated, wherein the film body 112 includes a multi-layer circuit layer 1121 ;

[0066] The two adjacent first signal lines L1 of the 2i-1th chip on film 110 and the 2ith chip on film 110 are located in different circuit layers 1121 of the film body 112 .

[0067] In this embodiment, two adjacent first signal lines L1 corresponding to two adjacent flip-chip films 110 are routed in different layers, for example Figure 5 As shown, the first first signal line L1_1 corresponding to the first COF 110 is set on the layer of the film body 112, and the nth first signal line L1_n corresponding to the second COF 110 is set on the lower layer of the film body 112, or as shown in FIG. Figure 6 As shown, the first first signal line L1_1 corresponding to the first flip chip film 110 is set in the lower layer of the film body 112, and the nth first signal line L1_n corresponding to the second flip chip film 110 is set in the upper layer of the film body 112. The two adjacent first signal lines L1 corresponding to the two adjacent flip chip films 110 are routed on different layers, and there are no parallel routes and overlapping routes, which weakens the coupling of the two adjacent data lines corresponding to the two adjacent flip chip films 110, thereby eliminating dark lines.

[0068] In which, the film body 112 can be provided with a multi-layer circuit layer 1121, and the two adjacent first signal lines L1 of the 2i-1th chip-on-chip film 110 and the 2i-th chip-on-chip film 110 can be respectively provided in different layers. In an optional embodiment, the two adjacent first signal lines L1 of the 2i-1th chip-on-chip film 110 and the 2i-th chip-on-chip film 110 are respectively located on the surface layer of the film body 112 and the inner layer adjacent to the surface layer of the film body 112, and the non-adjacent first signal lines L1 of the 2i-1th chip-on-chip film 110 and the 2i-th chip-on-chip film 110 are located on the surface layer of the film body 112.

[0069] For example Figure 5 and Figure 6 As shown, the film body 112 has two layers, and the two adjacent first signal lines L1 corresponding to the two adjacent flip-chip films 110 are respectively set on the surface and bottom layers of the film body 112, and the remaining non-adjacent first signal lines L1 are normally arranged on the surface layer of the film body 112 and are normally routed on the surface layer through copper foil routing.

[0070] Among them, the cover chip film 110 includes multiple, i.e., two adjacent first signal lines L1 corresponding to multiple adjacent cover chip films 110, wherein the layered arrangement of the two adjacent first signal lines L1 corresponding to each adjacent cover chip film 110 may be the same or different, for example, the first first signal line L1_1 of the first cover chip film 110 is arranged on the surface layer of the film body 112, and the nth first signal line L1_n of the second cover chip film 110 is arranged on the bottom layer, the first first signal line L1_1 of the second cover chip film 110 can be arranged on the surface layer or the bottom layer of the film body 112, and the nth first signal line L1_n of the third cover chip film 110 can be arranged on the bottom layer or the surface layer, and the specific arrangement method is not limited.

[0071] In order to unify the wiring and simplify the wiring method, in an optional embodiment, the nth first signal line L1 of the 2i-1th chip-on-film 110 is located in the inner layer of the film body 112, or the first first signal line L1 of the 2i-1th chip-on-film 110 is located in the inner layer of the film body 112, and the nth first signal line L1 of the 2i-1th chip-on-film 110 is adjacent to the first first signal line L1 of the 2i-1th chip-on-film 110, that is, the wiring method of each chip-on-film 110 is the same, for example Figure 7 As shown, the n-th first signal line L1 in each COF 110 is located in the inner layer of the film body 112, or as shown in FIG. Figure 8 As shown, the first first signal line L1 in each COF 110 is located in the inner layer of the film body 112 .

[0072] Correspondingly, the source driver chip 111 is integrated into the surface layer of the thin film body 112. The source driver chip 111 is directly connected to the first signal line L1 located on the surface layer, and is connected to the first signal line L1 located on the inner layer of the thin film body 112 through a via. The corresponding signal end position of the source driver chip 111 can be drilled downward for routing.

[0073] Example 3

[0074] Furthermore, in order to simplify the wiring, Figure 9 and Figure 10 As shown, the COF 110 further includes a plurality of second signal lines L2 , each of which is stacked on a first signal line L1 located in the inner layer and connected to the source driver chip 111 of the same COF 110 ;

[0075] When the polarity switching mode of the multiple first signal lines L1 of the 2i-1th flip chip film 110 is the same as the polarity switching mode of the multiple first signal lines L1 of the 2ith flip chip film 110, the source driver chip 111 of the corresponding flip chip film 110 outputs the data signal through the second signal line L2, and the polarity of the data signal of the second signal line L2 is switched according to the frame inversion mode.

[0076] In this embodiment, when the polarity switching mode of an odd number of chip-on-chip films 110 and an even number of chip-on-chip films 110 is the same, each chip-on-chip film 110 is periodically switched in the corresponding first polarity and second polarity sequence or in the corresponding second polarity and first polarity sequence, and each adjacent first signal line L1 and the corresponding data line do not have the same polarity. At this time, the wiring can be normally performed according to the original structure, that is, two adjacent chip-on-chip films 110 normally output data signals corresponding to non-adjacent first signal lines L1, and the source driver chip 111 outputs data signals through the second signal line L2 located on the surface, and each first signal line L1 and data line switches polarity according to the frame flip mode.

[0077] When the polarity switching modes of the odd-numbered flip chip films 110 and the even-numbered flip chip films 110 are opposite, the two adjacent flip chip films 110 corresponding to the non-adjacent first signal lines L1 set on the film body 112 normally output data signals, and the source driver chip 111 outputs data signals through the first signal line L1 located at the bottom layer of the film body 112. The first signal line L1 located at the bottom layer of the film body 112 switches polarity according to the dot flip mode, weakening the coupling problem and eliminating the dark line problem.

[0078] Among them, the output ends of the second signal line L2 located on the surface of the film body 112 and the first signal line L1 located on the bottom layer of the film body 112 are connected in common, and their input ends can be connected in common to the same signal end of the source driver chip 111 or not connected in common to different signal ends of the source driver chip 111. In an optional embodiment, in order to ensure that the resources of the signal end of the source driver chip 111 are avoided from being increased, the input ends of the second signal line L2 located on the surface of the film body 112 and the first signal line L1 located on the bottom layer of the film body 112 are connected in common to the same signal end of the source driver chip 111. Therefore, in order to realize the output of data signals with different polarity switching modes, in an optional embodiment, as Figure 11 As shown, the chip-on-film 110 further includes a plurality of switches K1;

[0079] The stacked first signal line L1 and the second signal line L2 are respectively connected in series with a switch K1;

[0080] The source driver chip 111 is used for:

[0081] When the polarity switching pattern of the plurality of first signal lines L1 of the 2i-1th chip on film 110 is the same as the polarity switching pattern of the plurality of first signal lines L1 of the 2ith chip on film 110, the switch K1 connected in series to the second signal line L2 is controlled to be turned on;

[0082] When the polarity switching pattern of the multiple first signal lines L1 of the 2i-1th COF 110 is opposite to the polarity switching pattern of the multiple first signal lines L1 of the 2ith COF 110, the switch K1 connected in series to the first signal line L1 located in the inner layer is controlled to be turned on.

[0083] In this embodiment, the source driver chip 111 is also respectively connected to each switching switch K1 on the corresponding flip chip film 110. When the odd-numbered source driver chips 111 and the even-numbered source driver chips 111 all receive a high level or a low level, the polarity switching mode of the multiple first signal lines L1 of the odd-numbered flip chip films 110 is the same as the polarity switching mode of the multiple first signal lines L1 of the even-numbered flip chip films 110. At this time, there is no parasitic voltage, and the data signal with positive and negative polarity changes can be normally output through the first signal line L1 and the second signal line L2 located on the surface. At this time, the source driver chip 111 controls the switching switch K1 connected in series to the second signal line L2 to turn on, and the data signal in the frame flip mode is normally output through the first signal line L1 and the second signal line L2 located on the surface.

[0084] And when the odd-numbered source driver chips 111 and the even-numbered source driver chips 111 receive a high level and a low level respectively, the polarity switching mode of the multiple first signal lines L1 of the odd-numbered flip chip films 110 is opposite to the polarity switching mode of the multiple first signal lines L1 of the even-numbered flip chip films 110. At this time, there is a parasitic voltage that causes dark lines to be generated. At this time, the data signal with positive and negative polarity changes can be output through the first signal line L1 located on the surface and the first signal line L1 located on the bottom layer. At this time, the source driver chip 111 controls the switching switch K1 connected in series to the first signal line L1 located on the bottom layer of the film body 112 to turn on, and the data signal of the frame flip mode normally outputs the data signal with positive and negative polarity changes through the first signal line L1 located on the surface, and the data signal of the dot flip mode outputs the data signal with positive and negative polarity changes through the first signal line L1 located on the bottom layer.

[0085] Among them, each switching switch K1 can be connected to different signal terminals of the source driver chip 111 or to the same signal terminal. When each switching switch K1 is connected to the same signal terminal of the source driver chip 111, the switching switch K1 connected in series on the second signal line L2 and the switching switch K1 connected in series on the first signal line L1 of the bottom layer are of opposite types. For example, the switching switch K1 connected in series on the second signal line L2 is an NMOS transistor, and the switching switch K1 connected in series on the first signal line L1 of the bottom layer is a PMOS transistor. The control terminals of each switching switch K1 are connected. When the polarity switching mode of the multiple first signal lines L1 of the odd-numbered flip chip films 110 is the same as the polarity switching mode of the multiple first signal lines L1 of the even-numbered flip chip films 110, the source driver chip 111 outputs a high level to trigger the NMOS tube to turn on and the PMOS tube to turn off; and when the polarity switching mode of the multiple first signal lines L1 of the odd-numbered flip chip films 110 is opposite to the polarity switching mode of the multiple first signal lines L1 of the even-numbered flip chip films 110, the source driver chip 111 outputs a low level to trigger the NMOS tube to turn off and the PMOS tube to turn on.

[0086] Furthermore, the signal lines located in the inner layer are longer and have greater impedance than the signal lines located in the surface layer. When the source driver chip 111 outputs data signals of the same magnitude to the signal lines located in the inner layer and the signal lines located in the surface layer, there is a difference in the voltage magnitude of the data signals output to the data lines, resulting in bright and dark lines on the display panel 200. Therefore, in an optional embodiment, the source driver chip 111 is further configured to:

[0087] When the polarity switching pattern of the plurality of first signal lines L1 of the 2i-1th chip on film 110 is the same as the polarity switching pattern of the plurality of first signal lines L1 of the 2ith chip on film 110, the first data signal is output to the second signal line L2;

[0088] And when the polarity switching mode of the multiple first signal lines L1 of the 2i-1th flip chip film 110 is opposite to the polarity switching mode of the multiple first signal lines L1 of the 2ith flip chip film 110, a second data signal is output to the first signal line L1 located in the inner layer, and the second data signal is greater than the first data signal.

[0089] In this embodiment, when the second data signal of the dot flip mode is output through the first signal line L1 of the bottom layer, voltage compensation is performed on the second data signal to avoid grayscale deviation caused by the offset of the column data. The second data signal has a larger voltage than the first data signal output to the second signal line L2 of the surface layer, and the voltage difference can be designed according to the length and impedance of the stacked first signal and second signal lines L2. Alternatively, during the test process, the size of the first data signal and the second data signal are adjusted based on the same target brightness, and data is stored. In different polarity switching modes, the data signal of corresponding size is selected for output to ensure the stability of the display screen.

[0090] Example 4

[0091] The present invention also proposes a display device, which includes a source driver circuit 100. The specific structure of the source driver circuit 100 refers to the above embodiment. Since the display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0092] In this embodiment, the display device may further include a gate driving circuit 300 , which is configured to output a row scanning signal and cooperate with the row scanning signal output by the source driving circuit 100 to drive the display panel 200 to display corresponding image information.

[0093] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A source driver circuit, characterized in that: include: A plurality of chip-on-films (COFs) bonded side by side to the display panel, each COF comprising a source driver chip and a plurality of first signal lines, the source driver chip outputting multiple data signals via the plurality of first signal lines, the plurality of first signal lines of each COF being connected to a group of data lines in the display panel, the plurality of data line groups being arranged side by side, each group of data lines comprising an even number of data lines; The source driver chip in the COF is configured to determine its own polarity switching mode according to a received polarity switching signal, determine whether it is the first polarity switching mode or the second polarity switching mode, and determine whether the polarity switching mode is different from that of the source driver chip in an adjacent COF; Wherein, when the polarity switching pattern of the plurality of first signal lines of the 2i-1th chip-on-chip film is opposite to the polarity switching pattern of the plurality of first signal lines of the 2ith chip-on-chip film, the polarity of one of the two adjacent first signal lines of the 2i-1th chip-on-chip film and the 2ith chip-on-chip film is switched row by row in a dot flip mode when the display panel is driven row by row, and a data line corresponding to the one of the first signal lines is switched to dot flip mode, wherein the data line in the dot flip mode is periodically switched in sequence of the first polarity and the second polarity in row by row scanning, wherein i is a positive integer; The polarity switching mode is a first polarity switching mode or a second polarity switching mode, wherein the first polarity switching mode is periodically switched in the order of the first polarity to the second polarity, and the second polarity switching mode is periodically switched in the order of the second polarity to the first polarity, and the first polarity and the second polarity are positive and negative polarities to each other; The chip-on-film further comprises a film body, and the film body comprises a multi-layer circuit layer; The two adjacent first signal lines of the 2i-1th COF and the 2ith COF are located in different circuit layers of the film body.

2. The source driver circuit according to claim 1, wherein: the 2i-1th source driver chip of the chip-on-film sequentially switching the polarities of the plurality of first signal lines connected thereto according to a first polarity pattern after receiving a first-level signal of the first polarity switching signal, or sequentially switching the polarities of the plurality of first signal lines connected thereto according to a second polarity pattern after receiving a second-level signal of the first polarity switching signal, wherein the first-level signal and the second-level signal are signals of opposite levels; The 2ith source driver chip of the flip chip film switches the polarities of the multiple connected first signal lines in sequence according to the first polarity mode after receiving the third level signal of the second polarity switching signal, and switches the polarities of the multiple connected first signal lines in sequence according to the second polarity mode after receiving the fourth level signal of the second polarity switching signal, and the third level signal and the fourth level signal are opposite level signals.

3. The source driver circuit according to claim 2, wherein: The two adjacent first signal lines of the 2i-1th COF and the 2ith COF are respectively located on the surface layer of the film body and the inner layer adjacent to the surface layer of the film body; The non-adjacent first signal lines of the 2i-1th COF and the 2ith COF are located on the surface layer of the film body.

4. The source driver circuit according to claim 3, wherein: The nth first signal line of the 2i-1th chip-on-chip film is located in the inner layer of the film body, or the first first signal line of the 2i-1th chip-on-chip film is located in the inner layer of the film body, and the nth first signal line of the 2i-1th chip-on-chip film is arranged adjacent to the first first signal line of the 2i-1th chip-on-chip film.

5. The source driver circuit according to claim 3 or 4, wherein: The source driver chip is integrated into the thin film body; The source driver chip is connected to the first signal line located in the inner layer of the film body through a via hole.

6. The source driving circuit according to claim 5, wherein: The COF further includes a plurality of second signal lines, each of which is stacked on a first signal line located in an inner layer and connected to a source driver chip of the same COF; When the polarity switching mode of the multiple first signal lines of the 2i-1th flip chip film is the same as the polarity switching mode of the multiple first signal lines of the 2ith flip chip film, the source driver chip corresponding to the flip chip film outputs the data signal through the second signal line, and the polarity of the data signal of the second signal line is switched according to the frame inversion mode.

7. The source driving circuit according to claim 6, wherein: The chip-on-film further includes a plurality of switching switches; The first signal line and the second signal line are stacked and connected in series with one of the switches respectively; The source driver chip is used for: When the polarity switching pattern of the plurality of first signal lines of the 2i-1th chip on film is the same as the polarity switching pattern of the plurality of first signal lines of the 2ith chip on film, controlling the switch connected in series to the second signal line to be turned on; When the polarity switching pattern of the multiple first signal lines of the 2i-1th chip-on-film is opposite to the polarity switching pattern of the multiple first signal lines of the 2ith chip-on-film, the switch connected in series to the first signal line located in the inner layer is controlled to be turned on.

8. The source driving circuit according to claim 6, wherein: The source driver chip is further used for: When the polarity switching pattern of the plurality of first signal lines of the 2i-1th chip on film is the same as the polarity switching pattern of the plurality of first signal lines of the 2ith chip on film, outputting the first data signal to the second signal line; And when the polarity switching pattern of the multiple first signal lines of the 2i-1th flip chip film is opposite to the polarity switching pattern of the multiple first signal lines of the 2ith flip chip film, a second data signal is output to the first signal line located in the inner layer, and the second data signal is greater than the first data signal.

9. A display device, characterized in that: The device comprises a display panel and a source driving circuit according to any one of claims 1 to 8.

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