Trench isolation structure and preparation method thereof

Abstract

The invention provides a trench isolation structure and a preparation method thereof. The preparation method of the trench isolation structure comprises the following steps: providing a substrate; sequentially depositing an isolation oxide layer, a hard mask layer and a photoetching layer on the surface of the substrate from bottom to top; patterning the photoetching layer, etching the hard mask layer and the isolation oxide layer by taking the patterned photoetching layer as a mask, forming a plurality of oxide grooves on the substrate, and exposing the substrate from each oxide groove; and forming a silicon epitaxial layer in each oxide trench, wherein an isolation oxide layer for isolating the silicon epitaxial layer is of a trench isolation structure. According to the invention, the isolation oxidation layers are firstly formed on the substrate, so that each isolation oxidation layer is exposed out of the substrate to ensure that the depths of the formed oxide trenches are the same, and then the oxide trenches are filled with the silicon epitaxial layers, so that the depths of the trenches formed by etching are prevented from being different.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor preparation, and in particular to a trench isolation structure and a preparation method thereof. Background Art

[0002] As semiconductor manufacturing processes enter the 20-nanometer and below technology nodes, the requirements for isolation between devices become more stringent, and the importance of shallow trench isolation (Shallow Trench Isolation) technology becomes more prominent.

[0003] The existing STI process usually uses dry plasma etching of silicon wafers to form the required grooves. As the process becomes more refined and complicated, it is required that the grooves at different critical dimensions are kept at the same depth at some locations on the wafer surface. In the actual etching process, the effective components of the reactive ions are consumed quickly in the area with dense graphics, resulting in an imbalance in supply and a decrease in the etching rate, which causes the etching depth in the dense graphics area to be less than that in the sparse graphics area, thereby causing an uneven distribution of the overall etching depth of the sample. In addition, the etching depth of graphics of different sizes on the same substrate will also be different, with wide graphics being etched deeply and narrow graphics being etched shallowly.

[0004] The above-mentioned difference in pattern etching depth caused by different pattern densities and pattern aspect ratios is the etching load effect. Summary of the invention

[0005] The object of the present invention is to provide a trench isolation structure and a preparation method thereof, so as to solve the problem of different trench etching depths in a pattern-dense area and a pattern-sparse area caused by an etching load effect.

[0006] In order to solve the above technical problems, the present invention provides a trench isolation structure and a preparation method thereof, wherein the preparation method of the trench isolation structure comprises: providing a substrate; depositing an isolation oxide layer, a hard mask layer and a photolithography layer in sequence from bottom to top on the surface of the substrate; patterning the photolithography layer, and performing an etching process on the hard mask layer and the isolation oxide layer using the patterned photolithography layer as a mask to form a plurality of oxide trenches in the substrate, and each of the oxide trenches exposes the substrate; and forming a silicon epitaxial layer in each of the oxide trenches, and the isolation oxide layer isolating the silicon epitaxial layer is a trench isolation structure.

[0007] Preferably, in the method for preparing the trench isolation structure, the substrate has a device-dense area and a device-sparse area, and the method for forming a plurality of the oxide trenches on the substrate includes: controlling the etching time for etching the hard mask layer and the isolation oxide layer until the oxide trenches in the device-dense area expose the substrate.

[0008] Preferably, in the method for preparing the trench isolation structure, the etching process stops on the substrate during etching.

[0009] Preferably, in the method for preparing the trench isolation structure, the method for forming the silicon epitaxial layer in each of the oxide trenches includes: forming an initial silicon epitaxial layer protruding from the hard mask layer in each of the oxide trenches; and etching the initial silicon epitaxial layer to form the silicon epitaxial layer, so that the upper surface of the silicon epitaxial layer is lower than the upper surface of the trench isolation structure.

[0010] Preferably, in the preparation method of the trench isolation structure, before etching the initial silicon epitaxial layer, it also includes: depositing a polysilicon layer, wherein the polysilicon layer covers the upper surface of the hard mask layer and the initial silicon epitaxial layer; and performing a planarization process on the polysilicon layer and the initial silicon epitaxial layer until the hard mask layer is exposed.

[0011] Preferably, in the method for preparing the trench isolation structure, the method for performing the planarization process includes: grinding the polysilicon layer and the initial silicon epitaxial layer, and simultaneously detecting a grinding signal; and stopping grinding when a grinding endpoint signal appears, wherein the grinding endpoint signal includes a signal in which a component of the polysilicon layer disappears and / or a signal in which a component of the hard mask layer appears.

[0012] Preferably, in the method for preparing the trench isolation structure, after forming the silicon epitaxial layer, the method further comprises: removing the hard mask layer by using a phosphoric acid solution.

[0013] Preferably, in the method for preparing the trench isolation structure, the photolithography layer includes an advanced graphic film layer, an anti-reflection layer and a photoresist layer deposited sequentially from bottom to top.

[0014] Preferably, in the method for preparing the trench isolation structure, the sidewalls of the oxide trench are perpendicular to the surface of the substrate.

[0015] The present invention also provides a trench isolation structure, comprising: a trench isolation structure prepared by the method for preparing the trench isolation structure as described above.

[0016] In summary, the present invention provides a trench isolation structure and a method for preparing the same, wherein the method for preparing the trench isolation structure comprises: providing a substrate; depositing an isolation oxide layer, a hard mask layer and a photolithography layer on the surface of the substrate in order from bottom to top; patterning the photolithography layer, and performing an etching process on the hard mask layer and the isolation oxide layer using the patterned photolithography layer as a mask to form a plurality of oxide trenches on the substrate, and each oxide trench exposes the substrate; and forming a silicon epitaxial layer in each oxide trench, wherein the isolation oxide layer isolating the silicon epitaxial layer is a trench isolation structure. The present invention first forms the isolation oxide layer on the substrate, so that each isolation oxide layer exposes the substrate, to ensure that the depth of each oxide trench formed is the same, and then fills the silicon epitaxial layer in the oxide trench, thereby avoiding different trench depths formed by etching. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a flow chart of a method for preparing a shallow trench isolation structure according to an embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of a device structure corresponding to step 2 of an embodiment of the present invention;

[0019] Figure 3-4 is a schematic diagram of a device structure corresponding to step 3 of an embodiment of the present invention;

[0020] Figures 5 to 9 is a schematic diagram of a device structure corresponding to step 4 of an embodiment of the present invention;

[0021] Wherein, each figure is marked as:

[0022] 10-substrate; 20-isolation oxide layer; 30-hard mask layer; 40-photolithography layer; 50-trench isolation structure; 60-polysilicon layer;

[0023] 21- oxide trench; 22- initial silicon epitaxial layer; 23- silicon epitaxial layer;

[0024] 41 - advanced graphic film layer; 42 - anti-reflective layer; 43 - photoresist layer. DETAILED DESCRIPTION

[0025] The following is a further detailed description of a trench isolation structure and a method for preparing the same proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often a part of the actual structure. In particular, the emphasis that each drawing needs to show is different, and sometimes different proportions are used.

[0026] It should be understood that spatial relationship terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0027] See also Figure 1 , an embodiment of the present invention provides a method for preparing a trench isolation structure, comprising:

[0028] S1, providing a substrate;

[0029] S2, depositing an isolation oxide layer, a hard mask layer and a photolithography layer in sequence from bottom to top on the surface of the substrate;

[0030] S3, patterning the photoresist layer, and performing an etching process on the hard mask layer and the isolation oxide layer using the patterned photoresist layer as a mask to form a plurality of oxide trenches on the substrate, wherein each oxide trench exposes the silicon substrate; and,

[0031] S4, forming a silicon epitaxial layer in each of the oxide trenches, and the isolation oxide layer isolating the silicon epitaxial layer to form a trench isolation structure.

[0032] The present invention first forms the isolation oxide layer on the substrate so that each isolation oxide layer exposes the substrate to ensure that the depth of each oxide groove formed is the same, and then fills the isolation oxide layer with the silicon epitaxial layer to avoid different groove depths formed by etching.

[0033] The following combination Figure 2 to Figure 9 Steps S1 to S4 are described in further detail.

[0034] First, perform step S1 to provide a substrate 10. Optionally, the substrate 10 may include semiconductor elements, such as silicon or silicon germanium (SiGe) in a single crystal structure, or a mixed semiconductor structure, such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, an alloy semiconductor or a combination thereof; it may also be silicon on insulator (SOI). In addition, the substrate 10 may also include other materials, such as a multilayer structure of an epitaxial layer or a buried layer. Although several examples of materials that can form the substrate 10 are described herein, any material that can be used as a semiconductor substrate 10 falls within the scope of protection of the present invention.

[0035] Specifically, the substrate 10 includes a device dense area and a device sparse area, and a plurality of the trench isolation structures 50 are formed in both the device dense area and the device sparse area. The device dense area and the device sparse area are divided according to the distribution density of the device structure on the substrate 10.

[0036] Next, execute step S2, see Figure 2 An isolation oxide layer 20 , a hard mask layer 30 , and a photolithography layer 40 are sequentially deposited on the surface of the substrate 10 from bottom to top.

[0037] Optionally, the deposition method may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0038] Optionally, the hard mask layer 30 is silicon nitride.

[0039] In some embodiments, the photolithography layer 40 may be formed by stacking an advanced pattern film layer 41 , an anti-reflective coating (ARC) 42 , and a photoresist layer 43 in sequence.

[0040] Among them, the function of the anti-reflection layer 42 is to prevent the exposure reflection problem caused by the difference in optical properties between the photoresist layer 43 and its underlying layer during the photolithography exposure process. Optionally, when there is no exposure reflection problem, the anti-reflection layer 42 may be absent; the advanced patterning film layer 41 (APF, Advanced patterning film) is similar to a polymer, but has less hydrogen and more carbon. Optionally, the advanced patterning film layer 41 is deposited by chemical vapor deposition at a high temperature greater than 200°C, so that it has better etching resistance.

[0041] Then, execute step S3, see Figure 3-4, patterning the photoresist layer 40, and performing an etching process on the hard mask layer 30 and the isolation oxide layer 20 using the patterned photoresist layer 40 as a mask to form a plurality of oxide trenches 21 on the substrate 10, and each of the oxide trenches 21 exposes the silicon substrate 10.

[0042] For details, see Figure 3 , patterning the photoresist layer 40, and the patterned photoresist layer 40 defines the position of the oxide trench 21 to be formed in a subsequent process.

[0043] In a specific embodiment, a dry etching process is used in step S3 to form the oxide trench 21 , and the dry etching process includes but is not limited to: reactive ion etching, ion beam etching, plasma etching or laser cutting.

[0044] In step S3 , the method of etching a plurality of the oxide trenches 21 in the device dense area and the device sparse area includes: controlling the etching time of the hard mask layer 30 and the isolation oxide layer 20 until the oxide trenches 21 in the device dense area expose the substrate 10 .

[0045] Furthermore, when the etching process is being performed, the etching stops on the substrate 10 , that is, the etching material has no etching effect on the substrate 10 .

[0046] As an optional implementation, the etching selectivity ratio of the etching process to the isolation oxide layer 20 and the substrate 10 is adjusted so that the etching process only etches the isolation oxide layer 20 but has no etching effect on the substrate 10 .

[0047] The above etching selectivity refers to the ratio of the etching rate of the isolation oxide layer 20 to the etching rate of the substrate 10. Specifically, the etching selectivity is adjusted when the oxide trench 21 is formed by dry etching. For the etching gas, the material of the isolation oxide layer 20 has a higher etching selectivity than the material of the substrate 10. Therefore, even if the isolation oxide layer 20 is etched until the substrate 10 is etched, no structural loss will be caused to the substrate 10.

[0048] In the prior art, the substrate 10 is first etched to form a silicon groove, and then an isolation layer is filled in the silicon groove to form a trench isolation structure. When etching to form the silicon groove, the effective components of the reactive ions in the device dense area are consumed quickly, resulting in a supply imbalance and a decreased etching rate, causing the etching depth in the device dense area to be smaller than that in the device sparse area, thereby causing an uneven distribution of the overall etching depth of the sample. Moreover, the etching selectivity of the etching gas under one etching condition for the same material is the same, and therefore, a difference in trench depth is inevitably formed, i.e., an etching load effect.

[0049] In comparison, in the embodiment of the present invention, the isolation oxide layer 20 is formed on the substrate 10, and the isolation oxide layer 20 is first etched to form the initialized trench isolation structure. Since the substrate 10 and the isolation oxide layer 20 are made of different materials, when the etching process is performed, the etching process only etches the isolation oxide layer 20. Since the etching depth of the dense area is less than the etching depth of the sparse area under the same etching time, as long as the oxide trench 21 formed in the dense area of ​​the device exposes the substrate 10 under the etching process for the etching time, the oxide trench 21 in the sparse area of ​​the device can also expose the substrate 10.

[0050] Furthermore, since the etching material of the etching process has no etching effect on the substrate 10, that is, in the process of etching the sparse area of ​​the device to reach the substrate 10 and waiting for the etching of the dense area of ​​the device to reach the substrate 10, even if the etching material contacts the substrate 10, it will not cause damage to the structure of the substrate 10, so as to ensure that the depth of each oxide groove 21 formed is the same, thereby avoiding different depths of the grooves formed by etching, that is, ensuring that the depths of the trench isolation structure 50 formed in the dense area and the sparse area are the same.

[0051] Finally, execute step S4, see Figures 5 to 9 A silicon epitaxial layer 23 is formed in each of the oxide trenches 21 , and the isolation oxide layer 20 isolating the silicon epitaxial layer 23 to form a trench isolation structure 50 .

[0052] Among them, the trench isolation structure includes a shallow trench isolation structure or a deep trench isolation structure. As a preferred implementation, the shallow trench isolation structure is prepared using the trench isolation structure preparation method provided in this embodiment, which can better achieve morphological size control of the shallow trench isolation structure.

[0053] Unlike the silicon trench formed by etching in the existing process with a morphology of "wide at the top and narrow at the bottom", since the embodiment of the present invention first forms the oxide trench 21 and then epitaxially grows the silicon epitaxial layer 23 in the oxide trench 21, if the oxide trench 21 formed in the existing process is "wide at the top and narrow at the bottom", the silicon epitaxial layer 23 epitaxially grown in the oxide trench 21 is also "wide at the top and narrow at the bottom", which will cause the silicon epitaxial layer 23 to break and separate from the substrate 10 due to insufficient stress inside the silicon epitaxial layer 23 during subsequent processes such as high-temperature oxidation. Therefore, in order to ensure the strength of the silicon epitaxial layer 23, it is preferred that the sidewalls of the oxide trench 21 are perpendicular to the surface of the substrate 10, or the oxide trench 21 is in a morphology of "narrow at the top and wide at the bottom", so that the silicon epitaxial layer 23 formed in the oxide trench 21 has a sufficiently large contact area with the substrate 10. In this embodiment, Figure 8 or Fig. 9 As shown, the sidewall of the oxide trench 21 is perpendicular to the surface of the substrate 10 .

[0054] Specifically, the method for forming the silicon epitaxial layer 23 in each of the oxide trenches 21 includes: forming an initial silicon epitaxial layer 22 protruding from the hard mask layer 30 in each of the oxide trenches 21; and etching the initial silicon epitaxial layer 22 to form the silicon epitaxial layer 23, so that the upper surface of the silicon epitaxial layer 23 is lower than the upper surface of the trench isolation structure 50, and the distance difference is the step height difference H, such as Figure 8 or Fig. 9 shown.

[0055] The step height difference H has a significant impact on the performance of semiconductor devices. Controlling the step height difference H can add many process windows to subsequent processes (such as the focal depth of gate lithography, gate etching, etc.). Preferably, the values ​​of the step height differences H are consistent.

[0056] For further information, see Figure 6-7 Before etching to form the initial silicon epitaxial layer 22, the method further includes: depositing a polysilicon layer 60, wherein the polysilicon layer 60 covers the upper surface of the hard mask layer 30 and the initial silicon epitaxial layer 22; and performing a planarization process on the polysilicon layer 60 and the initial silicon epitaxial layer 22 until the hard mask layer 30 is exposed.

[0057] The purpose of depositing the polysilicon layer 60 is to facilitate detection of the end point of the planarization process during the planarization process, so as to make the initial silicon epitaxial layer 22 and the hard mask layer 30 level before etching the initial silicon epitaxial layer 22. Optionally, the hard mask layer 30 may be deposited by methods including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0058] Specifically, the method for performing the planarization process includes: grinding the polysilicon layer 60 and the initial silicon epitaxial layer 22, and simultaneously detecting a grinding signal; and stopping grinding when a grinding endpoint signal appears, wherein the grinding endpoint signal includes a signal indicating that a component of the polysilicon layer 60 disappears, and / or a signal indicating that a component of the hard mask layer 30 appears.

[0059] Optionally, the grinding signal is detected by monitoring the friction between the grinding pad (not shown) and the grinding surface. In this embodiment, the grinding surface is one of the surface of the polysilicon layer 60, the surface composed of the polysilicon layer 60 and the initial silicon epitaxial layer 22, or the surface composed of the initial silicon epitaxial layer 22 and the hard mask layer 30. Since different materials have different friction with the grinding pad under the same grinding conditions, when passing through two layers of film with different materials during the grinding process, for example, the components of the polysilicon layer 60 disappear and / or the components of the hard mask layer 30 appear, the friction between the grinding pad and the grinding surface will change significantly, thereby helping technicians to quickly confirm the grinding endpoint signal.

[0060] After executing step S4 , in the embodiment of the present invention, phosphoric acid solution is further used to remove the hard mask layer 30 .

[0061] The embodiment of the present invention further provides a trench isolation structure 50 , including: the trench isolation structure 50 prepared by the above-mentioned method for preparing the trench isolation structure.

[0062] In summary, an embodiment of the present invention provides a trench isolation structure and a method for preparing the same, wherein the method for preparing the trench isolation structure comprises: providing a substrate; depositing an isolation oxide layer, a hard mask layer, and a photolithography layer on the surface of the substrate in order from bottom to top; patterning the photolithography layer, and performing an etching process on the hard mask layer and the isolation oxide layer using the patterned photolithography layer as a mask to form a plurality of oxide trenches on the substrate, and each oxide trench exposes the substrate; and forming a silicon epitaxial layer in each oxide trench, and the isolation oxide layer isolating the silicon epitaxial layer is a trench isolation structure. The present invention first forms the isolation oxide layer on the substrate, so that each isolation oxide layer exposes the substrate, to ensure that the depth of each oxide trench formed is the same, and then fills the silicon epitaxial layer in the oxide trench, thereby avoiding different trench depths formed by etching.

[0063] In addition, it should be recognized that although the present invention application has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing a trench isolation structure, characterized in that: include: providing a substrate; Depositing an isolation oxide layer, a hard mask layer and a photolithography layer in sequence from bottom to top on the surface of the substrate; Patterning the photoresist layer, and performing an etching process on the hard mask layer and the isolation oxide layer using the patterned photoresist layer as a mask to form a plurality of oxide trenches on the substrate, wherein each of the oxide trenches exposes the substrate; as well as, A silicon epitaxial layer is formed in each of the oxide trenches, and the isolation oxide layer isolating the silicon epitaxial layer is a trench isolation structure.

2. The method for preparing a trench isolation structure according to claim 1, wherein: The substrate has a device-intensive area and a device-sparse area. The method for forming a plurality of oxide trenches on the substrate includes: controlling the etching time of the hard mask layer and the isolation oxide layer until the oxide trenches on the device-intensive area expose the substrate.

3. The method for preparing a trench isolation structure according to claim 1, wherein: The etching process stops on the substrate during etching.

4. The method for preparing a trench isolation structure according to claim 1, wherein: The method of forming the silicon epitaxial layer in each of the oxide trenches comprises: forming an initial silicon epitaxial layer protruding from the hard mask layer in each of the oxide trenches; and, The initial silicon epitaxial layer is etched to form the silicon epitaxial layer, so that an upper surface of the silicon epitaxial layer is lower than an upper surface of the trench isolation structure.

5. The method for preparing a trench isolation structure according to claim 4, characterized in that: Before etching the initial silicon epitaxial layer, the method further comprises: depositing a polysilicon layer, the polysilicon layer covering the upper surfaces of the hard mask layer and the initial silicon epitaxial layer; and, A planarization process is performed on the polysilicon layer and the initial silicon epitaxial layer until the hard mask layer is exposed.

6. The method for preparing a trench isolation structure according to claim 5, characterized in that: The method of performing the planarization process includes: grinding the polysilicon layer and the initial silicon epitaxial layer, and detecting grinding signals at the same time; and, The polishing is stopped when a polishing endpoint signal appears, wherein the polishing endpoint signal includes a signal indicating that a component of the polysilicon layer disappears and / or a signal indicating that a component of the hard mask layer appears.

7. The method for preparing a trench isolation structure according to claim 1, wherein: The photolithography layer includes an advanced graphic film layer, an anti-reflection layer and a photoresist layer which are deposited sequentially from bottom to top.

8. The method for preparing a trench isolation structure according to claim 1, wherein: After forming the silicon epitaxial layer, the method further includes: removing the hard mask layer by using a phosphoric acid solution.

9. The method for preparing a trench isolation structure according to claim 1, wherein: The sidewalls of the oxide trench are perpendicular to the surface of the substrate.

10. A trench isolation structure, characterized in that: include: A trench isolation structure manufactured by the method for manufacturing a trench isolation structure according to any one of claims 1 to 9.

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