SAR-ADC circuit and communication system

Abstract

The invention discloses an SAR-ADC circuit and a communication system, and belongs to the technical field of integrated circuits. The circuit comprises a time sequence control module, an output selection module and n asynchronous analog-to-digital conversion modules, n is greater than or equal to 2 and is a positive integer; the asynchronous analog-to-digital conversion module starts sampling and conversion of an input signal according to a signal accessed by a clock end of the asynchronous analog-to-digital conversion module; the time sequence control module converts a first clock signal with a first frequency into n second clock signals with second frequencies, delays the second clock signals in sequence at a preset time interval and outputs the second clock signals to the clock ends of the asynchronous analog-to-digital conversion modules respectively; the second frequency is 1 / n of the first frequency, and the preset time interval is a pulse period of the first clock signal; and the output selection module selectively outputs the conversion result of each asynchronous analog-to-digital conversion module. According to the invention, the design difficulty of the asynchronous analog-to-digital conversion module can be reduced, and the SAR-ADC circuit can maintain a high conversion speed.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a SAR-ADC circuit and a communication system. Background Art

[0002] With the rapid development of modern electronic technology, high-speed signal processing and data acquisition have become the core requirements of many fields. For example, communication systems such as ultra-wideband radio and broadband Ethernet transceivers require low-power, high-speed and medium-resolution analog-to-digital converters. Successive approximation register analog-to-digital converters (SAR-ADC) have become a powerful choice for these applications due to their low analog complexity and excellent power consumption performance. However, the 1bit / cycle serial conversion method of SAR-ADC greatly limits its conversion speed. Under the demand for high-speed signal processing, the higher the output frequency of SAR-ADC, the lower the pulse width of the connected clock signal, the higher the cost and the higher the processing difficulty. Summary of the invention

[0003] The present invention provides a SAR-ADC circuit and a communication system. By combining the time interleaving technology and the asynchronous analog-to-digital conversion technology, each asynchronous analog-to-digital conversion module can sample the input signal at a frequency lower than the output bit rate, thereby reducing the design difficulty of each asynchronous analog-to-digital conversion module and maintaining a relatively high conversion speed of the SAR-ADC circuit.

[0004] In a first aspect, an embodiment of the present invention provides a SAR-ADC circuit, including:

[0005] n asynchronous analog-to-digital conversion modules; the input end of each asynchronous analog-to-digital conversion module is connected to an input signal, and the asynchronous analog-to-digital conversion module is used to start sampling and converting the input signal according to the signal connected to the clock end of the asynchronous analog-to-digital conversion module; n≥2, and n is a positive integer;

[0006] A timing control module, connected to the clock end of each of the asynchronous analog-to-digital conversion modules, respectively, for converting a first clock signal having a first frequency into n second clock signals having a second frequency, and delaying each of the second clock signals in sequence at a preset time interval and outputting them to the clock end of each of the asynchronous analog-to-digital conversion modules respectively; wherein the second frequency is 1 / n of the first frequency, and the preset time interval is the pulse period of the first clock signal;

[0007] The output selection module is connected to the output ends of the asynchronous analog-to-digital conversion modules respectively, and is used for selecting and outputting the conversion results of the asynchronous analog-to-digital conversion modules.

[0008] Optionally, the asynchronous analog-to-digital conversion module includes: a sampling switch unit, a serial comparison unit and a digital-to-analog conversion unit;

[0009] The sampling switch unit is connected to the input end of the asynchronous analog-to-digital conversion module and the clock end of the asynchronous analog-to-digital conversion module respectively, and the sampling switch unit is used to be turned on when the asynchronous analog-to-digital conversion module receives a pulse of the corresponding second clock signal, so as to start sampling the input signal;

[0010] The serial comparison unit is connected to the sampling switch unit, the digital-to-analog conversion unit, and the clock end and the output end of the asynchronous analog-to-digital conversion module respectively; the serial comparison unit is used to cooperate with the digital-to-analog conversion unit to convert the sampling result output by the sampling switch unit between adjacent pulses of the second clock signal received by the asynchronous analog-to-digital conversion module to obtain a conversion result;

[0011] The output selection module is used to output the conversion result obtained by the asynchronous analog-to-digital conversion module in the previous pulse period of the second clock signal within any pulse time of the second clock signal corresponding to the asynchronous analog-to-digital conversion module;

[0012] The digital-to-analog conversion unit includes: a capacitive digital-to-analog converter.

[0013] Optionally, the input end of the asynchronous analog-to-digital conversion module includes a first differential input end and a second differential input end;

[0014] The first input end of the sampling switch unit is connected to the first differential input end, the second input end of the sampling switch unit is connected to the second differential input end, and the clock end of the sampling switch unit is connected to the clock end of the asynchronous analog-to-digital conversion module;

[0015] The first input end of the serial comparison unit is respectively connected to the first output end of the sampling switch unit and the first output end of the digital-to-analog conversion unit, the second input end of the serial comparison unit is respectively connected to the second output end of the sampling switch unit and the second output end of the digital-to-analog conversion unit, the clock end of the serial comparison unit is connected to the clock end of the asynchronous analog-to-digital conversion module, the first output end of the serial comparison unit is connected to the first input end of the digital-to-analog conversion unit, the second output end of the serial comparison unit is connected to the second input end of the digital-to-analog conversion unit, and the third output end of the serial comparison unit is connected to the output end of the asynchronous analog-to-digital conversion module.

[0016] Optionally, the serial comparison unit includes: m comparison subunits, the conversion result includes an m-bit quantization code; m≥2, and m is a positive integer; the first input end of the digital-to-analog conversion unit includes m-1 first sub-input ends, and the second input end of the digital-to-analog conversion unit includes m-1 second sub-input ends respectively corresponding to the m-1 first sub-input ends;

[0017] The first input end of each of the comparison subunits is connected to the first input end of the serial comparison unit, and the second input end of each of the comparison subunits is connected to the second input end of the serial comparison unit; the first output ends of the first m-1 comparison subunits are respectively connected to the m-1 first sub-input ends of the digital-to-analog conversion unit, and the second output ends of the first m-1 comparison subunits are respectively connected to the m-1 second sub-input ends of the digital-to-analog conversion unit; the third output end of each of the comparison subunits is connected to the output end of the asynchronous analog-to-digital conversion module; wherein the clock end of the first comparison subunit is connected to the clock end of the serial comparison unit; the clock end of each subsequent comparison subunit is connected to the identification signal output end of the previous comparison subunit;

[0018] The comparison subunit is used to start comparing the signals respectively input to the first input terminal and the second input terminal of the comparison subunit after receiving a pulse at the clock terminal of the comparison subunit; after completing the comparison, a pulse of the identification signal is output through the identification signal output terminal, the comparison result is fed back to the digital-to-analog conversion unit through the first output terminal and the second output terminal of the comparison subunit, and a one-bit quantization code in the conversion result is output through the third output terminal of the comparison subunit.

[0019] Optionally, the comparison subunit includes: a dynamic comparator and a D flip-flop;

[0020] The clock end of the dynamic comparator is connected to the clock end of the comparison subunit, the two input ends of the dynamic comparator are respectively connected to the first input end and the second input end of the comparison subunit, the two output ends of the dynamic comparator are respectively connected to the first output end and the second output end of the comparison subunit, the input end of the D flip-flop is connected to one of the output ends of the dynamic comparator, the output end of the D flip-flop is connected to the third output end of the comparison subunit, and the identification end of the dynamic comparator is respectively connected to the clock end of the D flip-flop and the identification signal output end of the comparison subunit;

[0021] Among them, when the D flip-flop in the last one of the comparison subunits is triggered, the m-bit quantization code outputted by the third output terminal of each of the comparison subunits in the asynchronous analog-to-digital conversion module is used as the conversion result of the asynchronous analog-to-digital conversion module.

[0022] Optionally, the dynamic comparator comprises: an operational amplifier circuit and a logic circuit;

[0023] The two input ends of the operational amplifier circuit are respectively connected to the two input ends of the dynamic comparator, the clock end of the operational amplifier circuit is connected to the clock end of the dynamic comparator, and the two output ends of the operational amplifier circuit are respectively connected to the two output ends of the dynamic comparator; the operational amplifier circuit is used to compare the signals respectively connected to the two input ends of the operational amplifier circuit;

[0024] The two output ends of the operational amplifier circuit are also connected to the two input ends of the logic circuit respectively, and the output end of the logic circuit is connected to the identification end of the dynamic comparator; the logic circuit is used to generate a pulse of the identification signal according to the comparison result of the operational amplifier circuit.

[0025] Optionally, the dynamic comparator also includes: a delay control circuit connected to the logic circuit; the delay control circuit is used to control the delay length from the moment when the operational amplifier circuit completes the comparison to the moment when the identification signal output terminal outputs the pulse of the identification signal.

[0026] Optionally, the SAR-ADC circuit further includes: a reset module, respectively connected to each of the dynamic comparators and each of the digital-to-analog conversion units; for any of the asynchronous analog-to-digital conversion modules, the reset module is used to reset each of the dynamic comparators and the digital-to-analog conversion units in the asynchronous analog-to-digital conversion module within any pulse period of the second clock signal connected to the asynchronous analog-to-digital conversion module, after the moment when the D flip-flop in the last comparison subunit in the asynchronous analog-to-digital conversion module is triggered.

[0027] Optionally, the timing control module includes: a frequency division unit and n-1 delay units;

[0028] The input end of the frequency division unit is connected to the first clock signal, and the output end of the frequency division unit is connected to the clock end of the first asynchronous analog-to-digital conversion module; the frequency division unit is used to divide the first clock signal into n frequencies;

[0029] The input end of the first delay unit is connected to the output end of the frequency division unit, and the input end of each subsequent delay unit is connected to the output end of the previous delay unit; the output end of each frequency division unit is respectively connected to the clock end of the second to nth asynchronous analog-to-digital conversion modules; the delay unit is used to delay the signal connected to its input end for the preset time interval and then output it.

[0030] In a second aspect, an embodiment of the present invention further provides a communication system, comprising: the SAR-ADC circuit provided by any embodiment of the present invention.

[0031] In the SAR-ADC circuit provided by the embodiment of the present invention, a timing control module, an output selection module and n asynchronous analog-to-digital conversion modules are provided. By adopting the asynchronous analog-to-digital conversion module, the conversion speed of the module can be improved to a certain extent compared with the synchronous analog-to-digital conversion; and the timing control module and the output selection module cooperate to implement the time interleaving technology, by controlling the n asynchronous analog-to-digital conversion modules to alternately sample and convert the input signal, and alternately output the conversion results of each asynchronous analog-to-digital conversion module, so that the conversion results output by the n asynchronous analog-to-digital conversion modules with low sampling frequencies are interleaved to obtain a digital output result with a high output frequency, thereby improving the conversion efficiency. Therefore, the embodiment of the present invention combines the time interleaving technology and the asynchronous analog-to-digital conversion technology, so that each asynchronous analog-to-digital conversion module can sample the input signal at a frequency lower than the output code rate, thereby reducing the design difficulty and cost of each asynchronous analog-to-digital conversion module on the basis of maintaining a high conversion speed of the SAR-ADC circuit.

[0032] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 is a structural schematic diagram of a SAR-ADC circuit provided by an embodiment of the present invention;

[0035] Figure 2 is a schematic structural diagram of another SAR-ADC circuit provided by an embodiment of the present invention;

[0036] Figure 3 is a structural schematic diagram of an asynchronous analog-to-digital conversion module provided by an embodiment of the present invention;

[0037] Figure 4 is a structural schematic diagram of a dynamic comparator provided by an embodiment of the present invention;

[0038] Figure 5 is a structural schematic diagram of another SAR-ADC circuit provided by an embodiment of the present invention;

[0039] Figure 6 is a structural schematic diagram of a capacitive digital-to-analog converter provided by an embodiment of the present invention;

[0040] Figure 7 This is a working timing diagram of a SAR-ADC circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0043] The embodiment of the present invention provides a SAR-ADC circuit, which can effectively improve the conversion speed of the SAR-ADC. Figure 1 is a schematic diagram of the structure of a SAR-ADC circuit provided by an embodiment of the present invention. Figure 1 The SAR-ADC circuit includes: a timing control module 20, an output selection module 30 and n asynchronous analog-to-digital conversion modules. n≥2; n is a positive integer. Figure 1 Two asynchronous analog-to-digital conversion modules are exemplarily given, namely a first asynchronous analog-to-digital conversion module 101 and a second asynchronous analog-to-digital conversion module 102.

[0044] Among them, the input end of each asynchronous analog-to-digital conversion module is connected to the input signal VIN, and the asynchronous analog-to-digital conversion module is used to start the sampling and conversion of the input signal VIN according to the signal connected to the clock end of the asynchronous analog-to-digital conversion module. The timing control module 20 is respectively connected to the clock end of each asynchronous analog-to-digital conversion module, and is used to convert the first clock signal Clk1 with a first frequency into n second clock signals with a second frequency, and delay each second clock signal in turn at a preset time interval and output it to the clock end of each asynchronous analog-to-digital conversion module respectively, so that each asynchronous analog-to-digital conversion module alternately starts the sampling and conversion of the input signal VIN. The second frequency is 1 / n of the first frequency, and the preset time interval is the pulse period of the first clock signal Clk1. The output selection module 30 is respectively connected to the output end of each asynchronous analog-to-digital conversion module, and is used to select and output the conversion result of each asynchronous analog-to-digital conversion module.

[0045] Exemplarily, the asynchronous analog-to-digital conversion module can be a sub-ADC module formed by any asynchronous SAR-ADC architecture. Compared with the synchronous SAR-ADC, the asynchronous analog-to-digital conversion module has a faster quantization speed. Specifically, in the synchronous SAR-ADC, the clock signal of the comparator is controlled by a separate high-frequency clock that is unrelated to its output signal, so the comparison interval of the synchronous SAR-ADC is the same, and the comparison interval is determined by the longest comparison time required by the comparator, which greatly limits the working speed of the synchronous SAR-ADC. However, in the asynchronous SAR-ADC, the control signal of the comparator is controlled by the output state of the previous comparator, and the comparison interval of each comparator may no longer be the same. There is no need to determine a unified comparison interval based on the longest comparison time required by the comparator, which can effectively speed up the quantization speed and greatly improve the working speed of the asynchronous analog-to-digital conversion module.

[0046] The timing control module 20 and the output selection module 30 work together to control each asynchronous analog-to-digital conversion module to alternately perform sampling, conversion (i.e., analog-to-digital conversion) and output, which is equivalent to using time interleaving technology to interleave the conversion results of multiple asynchronous analog-to-digital conversion modules, thereby obtaining a final output result with a high output rate. The timing control module 20 can control each asynchronous analog-to-digital conversion module to alternately perform sampling and conversion at a second frequency, and the output selection module 30 can select and alternately output the conversion results of each asynchronous analog-to-digital conversion module at a first frequency in a time-sharing manner.

[0047] Specifically, the working process of the SAR-ADC circuit may be:

[0048] The timing control module 20 performs a series of processing such as frequency division and delay on the first clock signal Clk1 to obtain n second clock signals whose initial pulses are sequentially delayed by a preset time interval; wherein the first second clock signal Clk21 is transmitted to the clock end of the first asynchronous analog-to-digital conversion module 101, the second second clock signal Clk22 is transmitted to the clock end of the second asynchronous analog-to-digital conversion module 102, and so on. Each asynchronous analog-to-digital conversion module samples and converts the input signal VIN once in each pulse cycle of the second clock signal connected thereto. In other words, whenever a pulse of the second clock signal arrives, the asynchronous analog-to-digital conversion module connected to the second clock signal starts sampling and converting the input signal VIN once.

[0049] Among them, the frequency of each second clock signal is 1 / n of the first clock signal Clk1, that is, the pulse period of each second clock signal is n times that of the first clock signal Clk1, and each second clock signal is delayed in turn by the duration of one pulse period of the first clock signal Clk1. Then, each second clock signal has the following timing relationship: the i-th pulse of the n second clock signals starts in turn, and the start time of the i-th pulse of the adjacent second clock signals is separated by one pulse period of the first clock signal Clk1; after the i-th pulse of the n-th second clock signal ends, the i+1-th pulse of the first second clock signal Clk21 will start, and the start time of the i-th pulse of the n-th second clock signal and the start time of the i+1-th pulse of the first second clock signal Clk21 are separated by one pulse period of the first clock signal Clk1; i is a positive integer. Therefore, under the control of each second clock signal, each asynchronous analog-to-digital conversion module performs multiple rounds of sampling and conversion on the input signal VIN in a cycle, and in each round, each asynchronous analog-to-digital conversion module samples and converts the input signal VIN in turn.

[0050] From the above analysis, it can be seen that the sampling frequency of each asynchronous analog-to-digital conversion module is the second frequency, that is, sampling and conversion are performed once in every n pulse periods of the first clock signal Clk1; but every pulse period of the first clock signal Clk1, there will be an asynchronous analog-to-digital conversion module for sampling and conversion. The output selection module 30 can output the conversion result after each asynchronous analog-to-digital conversion module completes one sampling and conversion. Then, the output selection module 30 can interweave each conversion result into a digital output result D with a first frequency by cyclically and alternately outputting the conversion results of each asynchronous analog-to-digital conversion module. Specifically, the conversion result of the first asynchronous analog-to-digital conversion module 101 is recorded as Dout1, the conversion result of the second asynchronous analog-to-digital conversion module 102 is recorded as Dout2, and so on. In each round, the digital output result D includes Dout1, Dout2, ..., Doutn in sequence.

[0051] In the SAR-ADC circuit provided by the embodiment of the present invention, a timing control module 20, an output selection module 30 and n asynchronous analog-to-digital conversion modules are provided. By adopting the asynchronous analog-to-digital conversion module, the conversion speed of the module can be improved to a certain extent compared with the synchronous analog-to-digital conversion; and the timing control module 20 and the output selection module 30 cooperate to implement the time interleaving technology, by controlling the n asynchronous analog-to-digital conversion modules to alternately sample and convert the input signal VIN, and alternately output the conversion results of each asynchronous analog-to-digital conversion module, so that the conversion results output by the n asynchronous analog-to-digital conversion modules with low sampling frequencies are interleaved to obtain a digital output result D with a high output frequency, thereby improving the conversion efficiency. Therefore, the embodiment of the present invention combines the time interleaving technology and the asynchronous analog-to-digital conversion technology, so that each asynchronous analog-to-digital conversion module can sample the input signal at a frequency lower than the output code rate, thereby reducing the design difficulty and cost of each asynchronous analog-to-digital conversion module on the basis of maintaining a high conversion speed of the SAR-ADC circuit.

[0052] The basic working principle of the SAR-ADC circuit is explained in the above-mentioned embodiments. The circuit structure that each module in the circuit may have is exemplarily described below, but it is not intended to limit the present invention.

[0053] Figure 2 is a schematic diagram of the structure of another SAR-ADC circuit provided by an embodiment of the present invention. Figure 2 In one implementation, optionally, the timing control module 20 includes: a frequency division unit 210 and n-1 delay units. Figure 2 Two delay units are exemplarily given, namely a first delay unit 221 and a second delay unit 222.

[0054] The input end of the frequency division unit 210 is connected to the first clock signal Clk1, and the output end of the frequency division unit 210 is connected to the clock end of the first asynchronous analog-to-digital conversion module 101; the frequency division unit 210 is used to divide the first clock signal Clk1 by n. Figure 2 For example, n=3, the frequency division unit 210 divides the first clock signal Clk1 by 3, and the second frequency is 1 / 3 of the first frequency. The input end of the first delay unit (i.e., the first delay unit 221) is connected to the output end of the frequency division unit 210, and the input end of each subsequent delay unit is connected to the output end of the previous delay unit. The output end of each frequency division unit is respectively connected to the clock end of the 2nd to nth asynchronous analog-to-digital conversion modules. Figure 2As shown, the output end of the first frequency dividing unit 221 is connected to the clock end of the second asynchronous analog-to-digital conversion module 102, and the output end of the second frequency dividing unit 222 is connected to the clock end of the third asynchronous analog-to-digital conversion module 103. Among them, the delay unit is used to delay the signal connected to its input end for a preset time interval and then output it. In this way, the timing control module 20 can output each second clock signal in sequence at a preset time interval.

[0055] Based on the above embodiments, n can be selected as any positive integer greater than 1, for example, an odd number or an even number. Preferably, n can be set to an integer power of 2 to make the structure of the frequency division unit 210 simple and easy to implement. For example, n can be set to 2 or 4.

[0056] On the basis of the above embodiments, each pulse in any second clock signal may be optionally aligned with a portion of pulses in the first clock signal. For example, the frequency division unit 210 may extract a pulse in the first clock signal Clk1 as a pulse in the first second clock signal at intervals of n-1 pulses; since the output delay between adjacent second clock signals is a pulse period of the first clock signal Clk1, each pulse of the remaining second clock signals also corresponds to a different pulse in the first clock signal Clk1.

[0057] On this basis, the output selection module 30 can be set to access the first clock signal Clk1, so that the output selection module 30 selects to alternately output the conversion results of each asynchronous analog-to-digital conversion module according to the first clock signal Clk1, so as to ensure that the output selection module 30 outputs at the first frequency.

[0058] Continue to see Figure 2 On the basis of the above embodiments, optionally, the asynchronous analog-to-digital conversion module includes: a sampling switch unit, a serial comparison unit and a digital-to-analog conversion unit. Figure 2 Exemplarily, the first asynchronous analog-to-digital conversion module 101 includes: a first sampling switch unit 1101, a first serial comparison unit 1201 and a first digital-to-analog conversion unit 1301; the second asynchronous analog-to-digital conversion module 102 includes: a second sampling switch unit 1102, a second serial comparison unit 1202 and a second digital-to-analog conversion unit 1302; the third asynchronous analog-to-digital conversion module 103 includes: a third sampling switch unit 1103, a third serial comparison unit 1203 and a third digital-to-analog conversion unit 1303.

[0059] Wherein, for any asynchronous analog-to-digital conversion module, the sampling switch unit is respectively connected to the input end of the asynchronous analog-to-digital conversion module and the clock end of the asynchronous analog-to-digital conversion module, and the sampling switch unit is used to be turned on when the asynchronous analog-to-digital conversion module receives a pulse of the corresponding second clock signal, and start sampling of the input signal. Wherein, the sampling switch unit, for example, performs sampling within the time provided by the pulse, and is turned off after the pulse ends to stop sampling. The serial comparison unit is respectively connected to the sampling switch unit, the digital-to-analog conversion unit, and the clock end and output end of the asynchronous analog-to-digital conversion module; the serial comparison unit is used to convert the sampling result output by the sampling switch unit in cooperation with the digital-to-analog conversion unit between adjacent pulses of the second clock signal received by the asynchronous analog-to-digital conversion module, that is, after any pulse ends and before the next pulse begins, to obtain a conversion result. Exemplarily, the conversion result is an m-bit quantization code. For example, after the serial comparison unit compares the sampling results, it forms a one-bit quantization code in the conversion result according to the comparison result, and feeds the comparison result back to the digital-to-analog conversion unit; the digital-to-analog conversion unit processes the comparison result and then feeds it back to the serial comparison unit for re-comparison to generate the next one-bit quantization code, and the comparison result of the re-comparison is fed back to the digital-to-analog conversion unit, and this cycle is repeated until an m-bit quantization code is formed.

[0060] Among them, for any asynchronous analog-to-digital conversion module, the output selection module 30 is used to output the conversion result obtained by the asynchronous analog-to-digital conversion module in the previous pulse period of the second clock signal within any pulse time of the second clock signal corresponding to the asynchronous analog-to-digital conversion module. In other words, the asynchronous analog-to-digital conversion module can perform sampling within the current pulse time, and perform conversion after the current pulse ends and before the next pulse arrives; within the next pulse time, the output selection module 30 outputs the conversion result obtained by the asynchronous analog-to-digital conversion module in the current cycle. For any asynchronous analog-to-digital conversion module, the output process of the conversion result obtained in the current pulse period can be performed simultaneously with the sampling process in the next pulse period. In this way, the signal output process does not take up extra time, further improving the output rate.

[0061] Based on the above embodiments, optionally, see Figure 2 , the input signal can be a group of differential signals; each asynchronous analog-to-digital conversion module samples and converts the differential signal. Specifically, the input end of the asynchronous analog-to-digital conversion module includes a first differential input end and a second differential input end; each first differential input end is connected to each other, and each second differential input end is connected to each other, so that each asynchronous analog-to-digital conversion module is connected to the input signal. Figure 2As shown, the first differential input terminal IN11 of the first asynchronous analog-to-digital conversion module 101, the first differential input terminal IN12 of the second asynchronous analog-to-digital conversion module 102, and the first differential input terminal IN13 of the third asynchronous analog-to-digital conversion module 103 are connected; the second differential input terminal IN21 of the first asynchronous analog-to-digital conversion module 101, the second differential input terminal IN22 of the second asynchronous analog-to-digital conversion module 102, and the second differential input terminal IN23 of the third asynchronous analog-to-digital conversion module 103 are connected.

[0062] In any asynchronous analog-to-digital conversion module: the first input end of the sampling switch unit is connected to the first differential input end, the second input end of the sampling switch unit is connected to the second differential input end, and the clock end of the sampling switch unit is connected to the clock end of the asynchronous analog-to-digital conversion module. The first input end of the serial comparison unit is respectively connected to the first output end of the sampling switch unit and the first output end of the digital-to-analog conversion unit, the second input end of the serial comparison unit is respectively connected to the second output end of the sampling switch unit and the second output end of the digital-to-analog conversion unit, the clock end of the serial comparison unit is connected to the clock end of the asynchronous analog-to-digital conversion module, the first output end of the serial comparison unit is connected to the first input end of the digital-to-analog conversion unit, the second output end of the serial comparison unit is connected to the second input end of the digital-to-analog conversion unit, and the third output end of the serial comparison unit is connected to the output end of the asynchronous analog-to-digital conversion module.

[0063] Figure 3 is a schematic diagram of the structure of an asynchronous analog-to-digital conversion module provided by an embodiment of the present invention. Figure 3 On the basis of the above embodiments, optionally, in the asynchronous analog-to-digital conversion module 10, the serial comparison unit 120 includes: m comparison subunits 121, and the conversion result includes an m-bit quantization code; m≥2, and m is a positive integer. The first input end of the digital-to-analog conversion unit 130 includes m-1 first sub-input ends, which are respectively the first first sub-input end N11, the second first sub-input end N12, ..., and the m-1th first sub-input end N1m-1; the second input end of the digital-to-analog conversion unit 130 includes m-1 second sub-input ends corresponding to the m-1 first sub-input ends, which are respectively the first second sub-input end N21, the second second sub-input end N22, ..., and the m-1th second sub-input end N2m-1.

[0064] Among them, the first input terminal P1 of each comparison subunit 121 is connected to the first input terminal of the serial comparison unit 120, and the second input terminal P2 of each comparison subunit 121 is connected to the second input terminal of the serial comparison unit 120; the first output terminals P5 of the first m-1 comparison subunits 121 are respectively connected to the m-1 first sub-input terminals of the digital-to-analog conversion unit 130, and the second output terminals P6 of the first m-1 comparison subunits 121 are respectively connected to the m-1 second sub-input terminals of the digital-to-analog conversion unit 130; the third output terminal P7 of each comparison subunit 121 is connected to the output terminal of the asynchronous analog-to-digital conversion module 10; among them, the clock terminal P3 of the first comparison subunit 121 is connected to the clock terminal of the serial comparison unit 120; the clock terminal P3 of each subsequent comparison subunit 121 is connected to the identification signal output terminal P4 of the previous comparison subunit 121. The comparison subunit 121 is used to start the comparison of the signals respectively inputted into the first input terminal P1 and the second input terminal P2 of the comparison subunit 121 after the clock terminal P3 of the comparison subunit 121 receives the pulse; after the comparison is completed, the pulse of the identification signal r is outputted through the identification signal output terminal P4, the comparison result is fed back to the digital-to-analog conversion unit 130 through the first output terminal P5 and the second output terminal P6 of the comparison subunit 121, and the one-bit quantization code in the conversion result is outputted through the third output terminal P7 of the comparison subunit 121. It can be understood that the clock terminal of the first comparison subunit 121 receives the second clock signal corresponding to the asynchronous analog-to-digital conversion module in which it is located, and the pulse received by it is the pulse in the second clock signal; the clock terminal of each subsequent comparison subunit 121 receives the identification signal r outputted by the previous comparison subunit 121, and the pulse received by it is the pulse in the identification signal r.

[0065] It can be understood that the conversion result of m bits can be expressed as Dout<m-1:0> , the first comparison subunit 121 outputs the first quantization code Dout <m-1>The second comparison subunit 121 outputs the second quantization code Dout <m-2>, ..., the m-1th comparison subunit 121 outputs the m-1th quantization code Dout <1> , the mth comparison subunit 121 outputs the mth quantization code Dout <0> Since there is no next comparing subunit 121 after the m-th comparing subunit 121, the identification signal output terminal P4 of the m-th comparing subunit 121 can be set to be vacant and not output; and the m-th comparing subunit 121 does not need to feed back the comparison result to the digital-to-analog conversion unit 130.

[0066] Furthermore, the comparison subunit 121 includes: a dynamic comparator U1 and a D flip-flop DFF. The clock terminal of the dynamic comparator U1 is connected to the clock terminal P3 of the comparison subunit 121; the two input terminals of the dynamic comparator U1 are respectively connected to the first input terminal P1 and the second input terminal P2 of the comparison subunit 121, for example, the positive input terminal of the dynamic comparator U1 is connected to the first input terminal P1, and the negative input terminal is connected to the second input terminal P2. The two output terminals of the dynamic comparator are respectively connected to the first output terminal P5 and the second output terminal P6 of the comparison subunit 121, for example, the positive output terminal of the dynamic comparator U1 is connected to the first output terminal P5, and the negative output terminal is connected to the second output terminal P6. The input terminal of the D flip-flop DFF is connected to one of the output terminals of the dynamic comparator U1, for example, to the negative output terminal; the output terminal of the D flip-flop DFF is connected to the third output terminal P7 of the comparison subunit 121. The identification terminal of the dynamic comparator U1 is respectively connected to the clock terminal of the D flip-flop DFF and the identification signal output terminal P4 of the comparison subunit 121.

[0067] Figure 4 is a schematic diagram of the structure of a dynamic comparator provided by an embodiment of the present invention. Figure 4 On the basis of the above embodiments, the dynamic comparator U1 optionally includes an operational amplifier circuit 1211 and a logic circuit 1212. The operational amplifier circuit 1211 is a part of the dynamic comparator U1 that implements the comparison function. Specifically, the two input terminals of the operational amplifier circuit 1211 are respectively connected to the two input terminals of the dynamic comparator U1, and further connected to the first input terminal P1 and the second input terminal P2 of the comparison subunit 121; the clock terminal of the operational amplifier circuit 1211 is connected to the clock terminal of the dynamic comparator U1, and further connected to the clock terminal P3 of the comparison subunit 121; the two output terminals of the operational amplifier circuit 1211 are respectively connected to the two output terminals of the dynamic comparator U1, and further connected to the first output terminal P5 and the second output terminal P6 of the comparison subunit 121. The operational amplifier circuit 1211 is used to compare the signals respectively connected to the two input terminals of the operational amplifier circuit 1211; for example, after the clock terminal of the operational amplifier circuit 1211 receives a pulse, the comparison of the signals respectively connected to the two input terminals of the operational amplifier circuit 1211 is started. Exemplarily, the operational amplifier circuit 1211 may be a differential operational amplifier. The logic circuit 1212 is used to generate a pulse of the identification signal r according to the comparison result of the operational amplifier circuit 1211. The two input terminals of the logic circuit 1212 are respectively connected to the two output terminals of the operational amplifier circuit 1211. The output terminal of the logic circuit 1212 is connected to the identification terminal of the dynamic comparator U1, and then connected to the identification signal output terminal P4 of the comparison subunit 121. The logic circuit 1212 may be formed by a logic gate circuit such as a NAND gate or an XOR gate. The logic circuit 1212 may determine whether the operational amplifier circuit 1211 has completed the comparison according to the voltage change of the two output terminals of the operational amplifier circuit 1211.

[0068] It can be understood that the time required for each comparison subunit 121 to complete the comparison is determined according to the performance of the operational amplifier circuit 1211 and the voltage difference of the signal connected to the two input terminals of the operational amplifier circuit 1211. For example, for the same dynamic comparator U1, the greater the voltage difference between the signals connected to the two input terminals of the current dynamic comparator U1, the shorter the recognition time required for the operational amplifier circuit 1211 to perform voltage comparison; and the logic circuit 1212 performs logic processing to output the pulse of the identification signal r after the operational amplifier circuit 1211 completes the comparison. Then, the shorter the recognition time required for the operational amplifier circuit 1211 to perform voltage comparison, the shorter the time required for the dynamic comparator U1 to output the pulse of the identification signal r. In this way, in the asynchronous analog-to-digital conversion module 10, the time required for each comparison subunit 121 to output the pulse of the identification signal r can be adaptively adjusted according to the change of the voltage output by the digital-to-analog conversion unit 130, thereby reducing the comparison time as much as possible and improving the conversion speed on the basis of ensuring the accuracy of the comparison result of the dynamic comparator U1. Exemplarily, when a voltage jump occurs at at least one output terminal of the current comparison subunit U1, if the jump is fed back to the digital-to-analog conversion unit 130 so that the voltage jump amount of the output signal of the digital-to-analog conversion unit 130 is larger, it indicates that the change is easier to be recognized by the next comparison subunit 121, then the recognition time required for the next comparison subunit 121 to complete the comparison is shorter, and the pulse time of the corresponding output identification signal r is shorter.

[0069] Among them, the D flip-flop DFF in each comparison subunit 121 can play the role of aligning the output signal, or marking the time node of the conversion completion. Specifically, in the serial comparison unit 120, when the D flip-flop DFF in the last comparison subunit 121 is triggered, it indicates that the last dynamic comparator U1 has completed the comparison. At this time, since the next pulse of the second clock signal has not yet arrived, the next pulse of each identification signal r has not yet been output, and each dynamic comparator U1 still maintains the output state after receiving the previous pulse, which is equivalent to latching the output state. Then, based on the time when the D flip-flop DFF in the last comparison subunit 121 is triggered, the output result of each dynamic comparator U1 at this time can represent the comparison result obtained in this conversion, and the m-bit quantization code output by the third output terminal of each comparison subunit in the asynchronous analog-to-digital conversion module at this moment can be used as the conversion result of the asynchronous analog-to-digital conversion module.

[0070] Figure 5 It is a structural schematic diagram of another SAR-ADC circuit provided by an embodiment of the present invention. Figure 5 The specific structure of the first asynchronous analog-to-digital conversion module 101 is given as an example, and the structure of the second asynchronous analog-to-digital conversion module 102 can refer to the first asynchronous analog-to-digital conversion module 101, which is not specifically shown. Figure 5 On the basis of the above embodiments, optionally, taking the structure of the first digital-to-analog conversion unit 1301 as an example, the digital-to-analog conversion unit includes: a capacitive digital-to-analog converter CDAC. Specifically, see Figure 6 , the capacitive digital-to-analog converter CDAC may include a binary capacitor array; in a corresponding set of first sub-input terminals and second sub-input terminals, the capacitance value of the capacitor connected between the first sub-input terminal and the first output terminal of the capacitive digital-to-analog converter CDAC is the same as the capacitance value of the capacitor connected between the second sub-input terminal and the second output terminal of the capacitive digital-to-analog converter CDAC. The capacitance values ​​of the capacitors connected between different first sub-input terminals and the first output terminal of the capacitive digital-to-analog converter CDAC may be different.

[0071] On this basis, the time required for each comparison subunit 121 to complete the process of comparing and outputting the pulse of the identification signal r can be determined based on the capacitance value of the capacitor between the first output terminal of the previous comparison subunit 121 and the first output terminal of the capacitive digital-to-analog converter CDAC. For example, the larger the capacitance value, the greater the voltage change coupled to the output terminal of the capacitive digital-to-analog converter CDAC, and the shorter the time required for the next comparison subunit 121 to complete the process of comparing and outputting the pulse of the identification signal r.

[0072] On the basis of the above-mentioned embodiments, optionally, for each comparison subunit 121, the dynamic comparator U1 can be set to output the pulse of the identification signal r after a delay after the comparison is completed, so as to provide a certain time margin for the comparison process of the operational amplifier circuit 1211, and ensure that the pulse of the identification signal r is output from the identification signal output terminal P4 after the comparison is completed. Among them, the delay time length of the pulse of the identification signal r output by the dynamic comparator U1 after the comparison is completed can be adjusted according to the demand.

[0073] Specifically, the dynamic comparator U1 may also include: a delay control circuit connected to the logic circuit 1212. The delay control circuit is used to control the delay time between the moment when the comparison is completed by the operational amplifier circuit 1211 and the moment when the identification signal output terminal P4 outputs the pulse of the identification signal r. Exemplarily, the delay control circuit can be connected between the operational amplifier circuit 1211 and the logic circuit 1212, for example, the two output terminals of the operational amplifier circuit 1211 and the two input terminals of the logic circuit 1212 are respectively connected, and the delay time between the moment when the comparison is completed by the operational amplifier circuit 1211 and the moment when the identification signal output terminal P4 outputs the pulse of the identification signal r is controlled by controlling the delay time of the output signal of the two output terminals of the operational amplifier circuit 1211 to be transmitted to the two input terminals of the logic circuit 1212. Alternatively, the delay control circuit can be connected between the output end of the logic circuit 1212 and the identification signal output end P4, and the signal output by the logic circuit 1212 is output after a certain delay, so as to control the delay time between the moment when the self-op-amp circuit 1211 completes the comparison and the moment when the identification signal output end P4 outputs the pulse of the identification signal r. The delay control circuit can be composed of any delay device with adjustable delay time. The specific setting method of the delay control circuit can be adjusted according to actual needs and is not specifically limited here.

[0074] Exemplarily, for the comparison subunit 121 with a shorter identification time required for comparison, the higher the credibility of its comparison result, the shorter the delay time provided by the delay control circuit therein can be set. Among them, the delay time of the pulse of the identification signal r output by the first comparison subunit 121 after completing the comparison can be set to the minimum value; the first comparison subunit 121 can start the comparison from the receipt of the pulse of the second clock signal, so even if its delay time is set shorter, the comparison time of the first comparison subunit 121 is still sufficient from the pulse start time, and does not affect the accuracy of its output result.

[0075] Continue to see Figure 5 On the basis of the above embodiments, optionally, taking the structure of the first sampling switch unit 1101 as an example, the sampling switch unit may include two switch sub-units whose switch states are controlled by the clock terminal signal of the sampling switch unit, which are respectively connected between the first input terminal and the first output terminal of the sampling switch unit, and between the second input terminal and the second output terminal of the sampling switch unit, so as to control whether the input signal is transmitted backward through the sampling switch unit.

[0076] On the basis of the above-mentioned embodiments, the SAR-ADC circuit may optionally further include: a reset module, which is respectively connected to each dynamic comparator U1 and each digital-to-analog conversion unit 130. For any asynchronous analog-to-digital conversion module 10, the reset module is used to reset each dynamic comparator U1 and the digital-to-analog conversion unit 130 in the asynchronous analog-to-digital conversion module 10 after the D flip-flop DFF in the last comparison subunit 121 in the asynchronous analog-to-digital conversion module 10 is triggered within any pulse cycle of the second clock signal Clk2 to which the asynchronous analog-to-digital conversion module 10 is connected, so as to perform sampling and conversion within the next pulse cycle. It is understandable that the time required for the digital-to-analog conversion unit 130 to perform the three steps of sampling, conversion and resetting within one pulse cycle of the second clock signal Clk2 can be allocated according to actual needs.

[0077] In summary, the embodiment of the present invention provides a high-speed time-interleaved asynchronous SAR-ADC circuit. By using the time interleaving technology, the conversion results of n asynchronous analog-to-digital conversion modules with low sampling rates are interleaved to obtain a quantization code with a high output rate, which can effectively improve the conversion efficiency, reduce the requirements such as circuit power consumption, and reduce the difficulty of circuit design.

[0078] Combine the following Figure 5-7 , taking n=2, m=8 as an example, in combination with a specific embodiment, the structure and working process of the time-interleaved asynchronous SAR-ADC circuit are described, but it is not intended to limit the present invention.

[0079] See also Figure 5 , illustratively, the conversion result of the first asynchronous analog-to-digital conversion module 101 includes Dout1<7:0>, the conversion result of the second asynchronous analog-to-digital conversion module 102 includes Dout2<7:0>, and the interleaved digital output result is D<7:0>. Taking the first asynchronous analog-to-digital conversion module 101 as an example, the comparison results of the first seven comparison subunits 121 in the first serial comparison unit 1201 include out_p<7:1> and out_n<7:1>; the signal output from the first output terminal of the first digital-to-analog conversion unit 1301 is Comp_in_p, and the signal output from the second output terminal is Comp_in_m. See Figure 7 , the blue period corresponds to the sampling period Ts, the green period corresponds to the conversion period Tc as a whole, and the red period corresponds to the reset period Tr. The dotted line indicates the working stage of the first asynchronous analog-to-digital conversion module 101 within a pulse cycle of the first second clock signal Clk2_1, and the dashed line indicates the working stage of the second asynchronous analog-to-digital conversion module 102 within a pulse cycle of the second second clock signal Clk22. Each green sub-stage in the green period represents a period of comparison performed by each comparison sub-unit 121, and it can be seen that the delay time corresponding to different comparison sub-units 121 may be different. See Figure 6 , Figure 6 The specific structure of the binary capacitor array of the capacitive digital-to-analog converter CDAC is given, wherein C represents the basic capacitance value, and kC represents the basic capacitance value connected k times. Specifically, the capacitance value connected between the first first sub-input terminal N11 and the first second sub-input terminal N21 and the first output terminal of the capacitive digital-to-analog converter CDAC is 32C, the first first sub-input terminal N11 is connected to the second output terminal of the capacitive digital-to-analog converter CDAC through an inverter (or digital circuit) and a capacitor (capacitance value is 32C), and the first second sub-input terminal N21 is connected to the second output terminal of the capacitive digital-to-analog converter CDAC through an inverter (or digital circuit) and a capacitor (capacitance value is 32C); the connection method between the 2nd to 5th first sub-input terminals and the two output terminals of the capacitive digital-to-analog converter CDAC is the same as that between the first first sub-input terminal N11 and the two output terminals of the capacitive digital-to-analog converter CDAC. The connection mode is similar, except that the capacitance value is halved successively; the connection mode of the 2nd to 5th second sub-input terminals and the two output terminals of the capacitive digital-to-analog converter CDAC is similar to the connection mode of the 1st second sub-input terminal N21 and the two output terminals of the capacitive digital-to-analog converter CDAC, except that the capacitance value is halved successively; the 6th first sub-input terminal N16 and the 7th first sub-input terminal N17 are both connected to the first output terminal of the capacitive digital-to-analog converter CDAC through an inverter (or digital circuit) and a capacitor (capacitance is C), and the 6th second sub-input terminal N26 and the 7th second sub-input terminal N27 are both connected to the second output terminal of the capacitive digital-to-analog converter CDAC through an inverter (or digital circuit) and a capacitor (capacitance is C). It can be understood that the structure of the above-mentioned capacitive digital-to-analog converter CDAC is not intended to limit the present invention. Exemplarily, during the operation of the circuit, each second sub-input terminal can be set to be connected to a fixed potential, for example, all grounded.

[0080] See also Figure 5-Figure 7 , taking the pulse as a high potential as an example, the working process of the SAR-ADC circuit includes:

[0081] The frequency division unit 210 divides the first clock signal Clk1 by two, adjusts the duty cycle to 25%, and obtains two second clock signals Clk2_1 and Clk2_2, which are respectively used as sampling clocks for the two asynchronous analog-to-digital conversion modules 101 and 102. When the falling edge of the first second clock signal Clk21 comes, the first asynchronous analog-to-digital conversion module 101 finishes sampling and starts conversion; at this time, the second second clock signal Clk22 is low, and the second asynchronous analog-to-digital conversion module 102 is in a reset state.

[0082] During the conversion process of the first asynchronous analog-to-digital conversion module 101, the first comparison subunit 121 starts to compare, obtains the first comparison results out_p<7> and out_n<7>, feedback controls the capacitive digital-to-analog converter CDAC, changes the input voltages Comp_in_p and Comp_in_n of all comparison subunits 121, and then latches the first quantization code Dout1 <7> , generate the identification signal r as the comparison clock of the second comparison subunit 121; the second comparison subunit 121 starts to compare, repeat the above steps to perform serial comparison until all comparison subunits 121 complete the comparison and latch the comparison results, and obtain the conversion result Dout1<7:0>.

[0083] Among them, the dynamic comparator U1 in the last comparison sub-unit 121 completes the comparison and generates an identification signal r. The comparison results of all dynamic comparators U1 are aligned and output through the D flip-flop DFF to obtain the conversion result Dout1<7:0> composed of the first 8-bit quantization code and latch it. Then, all dynamic comparators U1 and capacitive digital-to-analog converters CDAC are reset, the circuit is reset, and the next rising edge of the first second clock signal Clk2_1 is waited for, and the above sampling conversion reset steps are repeated.

[0084] Among them, after being processed by the delay unit 220, the first second clock signal Clk21 is delayed by one pulse period of the first clock signal Clk1 to obtain the second second clock signal Clk22 as the sampling clock of the second asynchronous analog-to-digital conversion module 102, and the quantization operation of the first asynchronous analog-to-digital conversion module 101 is repeated to obtain the conversion result Dout2<7:0> consisting of the second 8-bit quantization code.

[0085] Finally, the first clock signal Clk1 controls the output selection circuit 30 to alternately select the outputs Dout1<7:0> and Dout2<7:0>. At this point, the sampling frequency of the two asynchronous analog-to-digital conversion modules is the second frequency, and the digital output result D<7:0> consisting of an 8-bit quantization code with an output frequency of the first frequency is obtained.

[0086] Exemplarily, the duty cycle of the first clock signal Clk1 is 50%, the sampling period Ts occupies, for example, half of the pulse period of the first clock signal Clk1, the conversion stage Tc occupies, for example, 1.25 times of the pulse period of the first clock signal Clk1, and the reset extreme Tr occupies, for example, 0.25 times of the pulse period of the first clock signal Clk1. That is, the duration of a pulse period of the first clock signal Clk1 is recorded as 1clk; for any asynchronous analog-to-digital conversion module, after a high-level pulse of the connected second clock signal is completed for sampling, an 8-bit quantization code is obtained after 5 / 4clk, and before the next high-level pulse of the connected second clock signal comes, the reset of each dynamic comparator and digital-to-analog conversion unit in the asynchronous analog-to-digital conversion module is completed after 1 / 4clk. It can be understood that the duration required for each of the above steps is only for exemplary description and is not intended to limit the present invention.

[0087] In summary, the SAR-ADC circuit provided by the embodiment of the present invention has the following advantages:

[0088] 1. By assigning a comparison subunit to each bit of quantization code, the dynamic comparator acts as a latch, so that the dynamic comparator can directly pass the comparison result to the digital logic part of the capacitive digital-to-analog converter CDAC, eliminating the logical register structure steps required by the traditional SAR-ADC, greatly speeding up the quantization time, simplifying the circuit structure, reducing the production cost, and reducing the circuit area occupied.

[0089] 2. The delay time of each comparison sub-unit outputting the identification signal after completing the comparison can be customized and refined to achieve full asynchronous quantization from the dynamic comparator to the capacitive digital-to-analog converter CDAC, maximizing the use of the quantization time of the 1bit / cycle ADC.

[0090] 3. By using time interleaving technology for n-channel asynchronous analog-to-digital conversion modules, the input signal can be sampled at a frequency lower than the output bit rate, reducing the design difficulty of each asynchronous analog-to-digital conversion module while maintaining a high output rate.

[0091] An embodiment of the present invention further provides a communication system, including the SAR-ADC circuit provided by any embodiment of the present invention, and having corresponding beneficial effects. Exemplarily, the SAR-ADC circuit can be applied to a receiving (RX) link of a communication system. The communication system can be a vehicle-mounted communication system or a communication system in other application scenarios.

[0092] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0093] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A SAR-ADC circuit, characterized in that: include: n asynchronous analog-to-digital conversion modules; the input end of each asynchronous analog-to-digital conversion module is connected to an input signal, and the asynchronous analog-to-digital conversion module is used to start sampling and converting the input signal according to the signal connected to the clock end of the asynchronous analog-to-digital conversion module; n≥2, and n is a positive integer; A timing control module, connected to the clock end of each of the asynchronous analog-to-digital conversion modules, respectively, for converting a first clock signal having a first frequency into n second clock signals having a second frequency, and delaying each of the second clock signals in sequence at a preset time interval and outputting them to the clock end of each of the asynchronous analog-to-digital conversion modules respectively; wherein the second frequency is 1 / n of the first frequency, and the preset time interval is the pulse period of the first clock signal; The output selection module is connected to the output ends of the asynchronous analog-to-digital conversion modules respectively, and is used for selecting and outputting the conversion results of the asynchronous analog-to-digital conversion modules.

2. The SAR-ADC circuit according to claim 1, characterized in that: The asynchronous analog-to-digital conversion module includes: a sampling switch unit, a serial comparison unit and a digital-to-analog conversion unit; The sampling switch unit is connected to the input end of the asynchronous analog-to-digital conversion module and the clock end of the asynchronous analog-to-digital conversion module respectively, and the sampling switch unit is used to be turned on when the asynchronous analog-to-digital conversion module receives a pulse of the corresponding second clock signal, so as to start sampling the input signal; The serial comparison unit is connected to the sampling switch unit, the digital-to-analog conversion unit, and the clock end and the output end of the asynchronous analog-to-digital conversion module respectively; the serial comparison unit is used to cooperate with the digital-to-analog conversion unit to convert the sampling result output by the sampling switch unit between adjacent pulses of the second clock signal received by the asynchronous analog-to-digital conversion module to obtain a conversion result; The output selection module is used to output the conversion result obtained by the asynchronous analog-to-digital conversion module in the previous pulse period of the second clock signal within any pulse time of the second clock signal corresponding to the asynchronous analog-to-digital conversion module; The digital-to-analog conversion unit includes: a capacitive digital-to-analog converter.

3. The SAR-ADC circuit according to claim 2, characterized in that: The input end of the asynchronous analog-to-digital conversion module includes a first differential input end and a second differential input end; The first input end of the sampling switch unit is connected to the first differential input end, the second input end of the sampling switch unit is connected to the second differential input end, and the clock end of the sampling switch unit is connected to the clock end of the asynchronous analog-to-digital conversion module; The first input end of the serial comparison unit is respectively connected to the first output end of the sampling switch unit and the first output end of the digital-to-analog conversion unit, the second input end of the serial comparison unit is respectively connected to the second output end of the sampling switch unit and the second output end of the digital-to-analog conversion unit, the clock end of the serial comparison unit is connected to the clock end of the asynchronous analog-to-digital conversion module, the first output end of the serial comparison unit is connected to the first input end of the digital-to-analog conversion unit, the second output end of the serial comparison unit is connected to the second input end of the digital-to-analog conversion unit, and the third output end of the serial comparison unit is connected to the output end of the asynchronous analog-to-digital conversion module.

4. The SAR-ADC circuit according to claim 3, characterized in that: The serial comparison unit includes: m comparison subunits, the conversion result includes an m-bit quantization code; m≥2, and m is a positive integer; the first input end of the digital-to-analog conversion unit includes m-1 first sub-input ends, and the second input end of the digital-to-analog conversion unit includes m-1 second sub-input ends respectively corresponding to the m-1 first sub-input ends; The first input end of each of the comparison subunits is connected to the first input end of the serial comparison unit, and the second input end of each of the comparison subunits is connected to the second input end of the serial comparison unit; the first output ends of the first m-1 comparison subunits are respectively connected to the m-1 first sub-input ends of the digital-to-analog conversion unit, and the second output ends of the first m-1 comparison subunits are respectively connected to the m-1 second sub-input ends of the digital-to-analog conversion unit; the third output end of each of the comparison subunits is connected to the output end of the asynchronous analog-to-digital conversion module; wherein the clock end of the first comparison subunit is connected to the clock end of the serial comparison unit; the clock end of each subsequent comparison subunit is connected to the identification signal output end of the previous comparison subunit; The comparison subunit is used to start comparing the signals respectively input to the first input terminal and the second input terminal of the comparison subunit after receiving a pulse at the clock terminal of the comparison subunit; after completing the comparison, a pulse of the identification signal is output through the identification signal output terminal, the comparison result is fed back to the digital-to-analog conversion unit through the first output terminal and the second output terminal of the comparison subunit, and a one-bit quantization code in the conversion result is output through the third output terminal of the comparison subunit.

5. The SAR-ADC circuit according to claim 4, characterized in that: The comparison subunit includes: a dynamic comparator and a D flip-flop; The clock end of the dynamic comparator is connected to the clock end of the comparison subunit, the two input ends of the dynamic comparator are respectively connected to the first input end and the second input end of the comparison subunit, the two output ends of the dynamic comparator are respectively connected to the first output end and the second output end of the comparison subunit, the input end of the D flip-flop is connected to one of the output ends of the dynamic comparator, the output end of the D flip-flop is connected to the third output end of the comparison subunit, and the identification end of the dynamic comparator is respectively connected to the clock end of the D flip-flop and the identification signal output end of the comparison subunit; Among them, when the D flip-flop in the last one of the comparison subunits is triggered, the m-bit quantization code outputted by the third output terminal of each of the comparison subunits in the asynchronous analog-to-digital conversion module is used as the conversion result of the asynchronous analog-to-digital conversion module.

6. The SAR-ADC circuit according to claim 5, characterized in that: The dynamic comparator comprises: an operational amplifier circuit and a logic circuit; The two input ends of the operational amplifier circuit are respectively connected to the two input ends of the dynamic comparator, the clock end of the operational amplifier circuit is connected to the clock end of the dynamic comparator, and the two output ends of the operational amplifier circuit are respectively connected to the two output ends of the dynamic comparator; the operational amplifier circuit is used to compare the signals respectively connected to the two input ends of the operational amplifier circuit; The two output ends of the operational amplifier circuit are also connected to the two input ends of the logic circuit respectively, and the output end of the logic circuit is connected to the identification end of the dynamic comparator; the logic circuit is used to generate a pulse of the identification signal according to the comparison result of the operational amplifier circuit.

7. The SAR-ADC circuit according to claim 6, characterized in that: The dynamic comparator also includes: a delay control circuit connected to the logic circuit; the delay control circuit is used to control the delay length from the moment when the operational amplifier circuit completes the comparison to the moment when the identification signal output terminal outputs the pulse of the identification signal.

8. The SAR-ADC circuit according to claim 5, characterized in that: Also includes: A reset module is respectively connected to each of the dynamic comparators and each of the digital-to-analog conversion units; for any of the asynchronous analog-to-digital conversion modules, the reset module is used to reset each of the dynamic comparators and the digital-to-analog conversion units in the asynchronous analog-to-digital conversion module within any pulse cycle of the second clock signal connected to the asynchronous analog-to-digital conversion module and after the moment when the D flip-flop in the last comparison subunit in the asynchronous analog-to-digital conversion module is triggered.

9. The SAR-ADC circuit according to claim 1, characterized in that: The timing control module includes: a frequency division unit and n-1 delay units; The input end of the frequency division unit is connected to the first clock signal, and the output end of the frequency division unit is connected to the clock end of the first asynchronous analog-to-digital conversion module; the frequency division unit is used to divide the first clock signal into n frequencies; The input end of the first delay unit is connected to the output end of the frequency division unit, and the input end of each subsequent delay unit is connected to the output end of the previous delay unit; the output end of each frequency division unit is respectively connected to the clock end of the second to nth asynchronous analog-to-digital conversion modules; the delay unit is used to delay the signal connected to its input end for the preset time interval and then output it.

10. A communication system, characterized in that: include: The SAR-ADC circuit according to any one of claims 1 to 9.

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