Semiconductor device

Abstract

The semiconductor device includes: a substrate; a first transistor including a first source electrode, a first drain electrode, and a first gate electrode; a second transistor including a second source electrode, a second drain electrode, and a second gate electrode; a third transistor including a third source electrode provided within the first source electrode and the second source electrode when viewed from the second direction, a third drain electrode, and a third gate electrode disposed between the third source electrode and the third drain electrode in the first direction; a first gate wiring in which the third source electrode is disposed between the first gate wiring and the third gate electrode, the first gate wiring being provided within the first source electrode and the second source electrode when viewed from the second direction, and being electrically connected to the first gate electrode and the second gate electrode; and a back metal layer electrically connected to the first source electrode and the second source electrode through the first via hole and the second via hole, respectively.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] It is known that in a field effect transistor (FET) having finger-shaped source electrodes, gate electrodes, and drain electrodes, a plurality of unit FETs having source electrodes, gate electrodes, and drain electrodes are arranged in the extending direction of the electrodes (for example, Patent Documents 1 to 3).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2002-299351

[0006] Patent Document 2: U.S. Patent Application Publication No. 2017 / 0271329

[0007] Patent Document 3: Japanese Patent Application Publication No. 2022-135899

[0008] In order to improve high-frequency characteristics in FET, it is required to appropriately set gate resistance, source inductance, and the like. Summary of the invention

[0009] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to suppress degradation of characteristics.

[0010] One embodiment of the present disclosure is a semiconductor device comprising: a substrate having a main surface and a back surface opposite to the main surface; a first transistor having a first source electrode, a first drain electrode and a first gate electrode, wherein the first gate electrode is arranged between the first source electrode and the first drain electrode in a first direction, and the first transistor is arranged on the main surface; a second transistor having a second source electrode, a second drain electrode and a second gate electrode, wherein the second source electrode overlaps with the first source electrode when viewed from a second direction intersecting the first direction, the second drain electrode is electrically connected to the first drain electrode, the second gate electrode is arranged between the second source electrode and the second drain electrode in the first direction, and the second transistor is arranged on the main surface; a third transistor having a third source electrode, a third drain electrode and a third gate electrode, wherein the third source electrode is arranged above the first source electrode when viewed from the second direction and in the second source electrode and electrically connected to the first source electrode and the second source electrode, the third drain electrode is electrically connected to the first drain electrode and the second drain electrode, the third gate electrode is arranged between the third source electrode and the third drain electrode in the first direction, and the third transistor is arranged on the main surface between the first transistor and the second transistor; a first gate wiring is arranged on the main surface, so that the third source electrode is arranged between the first gate wiring and the third gate electrode, the first gate wiring is arranged in the first source electrode and the second source electrode when observed from the second direction, and is electrically connected to the first gate electrode and the second gate electrode; and a back metal layer is arranged on the back side, and is electrically connected to the first source electrode and the second source electrode via a first via and a second via that overlap with the first source electrode and the second source electrode respectively when observed from the thickness direction of the substrate.

[0011] One embodiment of the present disclosure is a semiconductor device comprising: a substrate having a main surface and a back surface opposite to the main surface; a first transistor having a first source electrode, a first drain electrode and a first gate electrode, wherein the first gate electrode is arranged between the first source electrode and the first drain electrode in a first direction, and the first transistor is arranged on the main surface; a second transistor having a second source electrode, a second drain electrode and a second gate electrode, wherein the second source electrode is arranged in the first source electrode and is electrically connected to the first source electrode when viewed from a second direction intersecting the first direction, the second drain electrode is electrically connected to the first drain electrode, and the second gate electrode is electrically connected to the first drain electrode. a first gate electrode and a second drain electrode arranged between the second source electrode and the second drain electrode in the first direction, the second transistor being arranged on the main surface; a third transistor comprising a third source electrode, the first drain electrode and a third gate electrode, wherein the third source electrode causes the first drain electrode to be arranged between the third source electrode and the first gate electrode, the third gate electrode being arranged between the third source electrode and the first drain electrode in the first direction, the third transistor being arranged on the main surface; a fourth transistor comprising a fourth source electrode, the second drain electrode and a fourth gate electrode, wherein the fourth source electrode is arranged inside the third source electrode when viewed from the second direction and is in contact with the first source electrode The third source electrode is electrically connected, the fourth gate electrode is arranged between the fourth source electrode and the second drain electrode in the first direction, and the fourth transistor is arranged on the main surface; a first gate wiring is arranged on the main surface, and the second source electrode is arranged between the first gate wiring and the second gate electrode in the first direction, and the first gate wiring is arranged inside the first source electrode when viewed from the second direction and is electrically connected to the first gate electrode; a second gate wiring is arranged on the main surface, and the fourth source electrode is arranged between the second gate wiring and the fourth gate electrode in the first direction, and the second gate wiring is viewed from the second direction When observed, it is arranged in the third source electrode and is electrically connected to the third gate electrode; the source connection wiring is arranged on the main surface, so that the second transistor and the fourth transistor are configured between the source connection wiring and the first transistor and the third transistor, and the source connection wiring electrically connects the second source electrode with the fourth source electrode; and the back metal layer is arranged on the back side and is electrically connected to the first source electrode, the third source electrode and the source connection wiring through a first via hole, a second via hole and a third via hole respectively overlapping with the first source electrode, the third source electrode and the source connection wiring when observed from the thickness direction of the substrate.

[0012] Effects of the Invention

[0013] According to the present disclosure, degradation of characteristics can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 1 is a top view of the semiconductor device of Example 1.

[0015] Figure 2 yes Figure 1 A-A section view.

[0016] Figure 3 yes Figure 1 B-B section view.

[0017] Figure 4 yes Figure 1 C-C section view.

[0018] Figure 5 yes Figure 1 D-D section view.

[0019] Figure 6 This is a simplified top view of the semiconductor device of Example 1.

[0020] Figure 7 3 is a top view of the semiconductor device of Comparative Example 1.

[0021] Figure 8 3 is a top view of a semiconductor device according to Comparative Example 2.

[0022] Fig. 9 It is a top view of the source wiring A in the simulation.

[0023] Fig.10 It is a top view of the source wiring B in the simulation.

[0024] Fig.11 : is a graph showing source inductance Ls with respect to cell gate width Wgu in simulation.

[0025] Fig.12 It is a top view of a semiconductor device according to Modification 1 of Embodiment 1.

[0026] Fig.13 yes Fig.12 A-A section view.

[0027] Fig.14 yes Fig.12 B-B section view.

[0028] Fig.15 yes Fig.12 C-C section view.

[0029] Fig.16 It is a top view of a semiconductor device according to a second variation of the first embodiment.

[0030] Fig.17 yes Fig.16 A-A section view.

[0031] Fig.18 yes Fig.16 B-B section view.

[0032] Fig.19 It is a top view of a semiconductor device according to a third variation of the first embodiment.

[0033] Fig. 20 yes Fig.19 A-A section view.

[0034] Fig.21 yes Fig.19 B-B section view.

[0035] Fig. 22 This is a simplified top view of a semiconductor device according to a fourth variation of the first embodiment.

[0036] Fig.23 This is a simplified top view of a semiconductor device according to a fifth variation of the first embodiment.

[0037] Fig.24 It is a top view of the semiconductor device of Example 2.

[0038] Fig.25 yes Fig.24 A-A section view.

[0039] Fig.26 yes Fig.24 B-B section view.

[0040] Fig. 27 It is a top view of a semiconductor device according to a first variation of the second embodiment.

[0041] Fig.28 This is a top view of a semiconductor device according to a second variation of the second embodiment.

[0042] Description of Reference Numerals

[0043] 10, 10a: substrate;

[0044] 10b: semiconductor layer;

[0045] 11a, 11c, 11d, 11e: active area;

[0046] 12, 12a, 12b, 12c, 12d, 12e, 12g: source electrodes;

[0047] 12h: Ohmic electrode layer;

[0048] 13: inactive area;

[0049] 14, 14a, 14b, 14c, 14d, 14e, 14f, 14g: gate electrodes;

[0050] 16, 16a, 16b, 16c, 16d, 16e, 16f, 16g: drain electrodes;

[0051] 20, 20a, 20b, 20e: vias;

[0052] 22, 22a, 22b, 22c, 22e: source wiring;

[0053] 23: Source connection wiring;

[0054] 24, 24c, 24d, 24e, 25a, 25b, 25c, 25d, 25e, 25f, 32a, 32b: gate wiring;

[0055] 24a: gate metal layer;

[0056] 24b, 33: wiring layer;

[0057] 26a, 26b, 26e, 26g: drain wiring;

[0058] 27: Open mouth;

[0059] 28, 28a: metal layer;

[0060] 30: insulation layer;

[0061] 31: Wiring;

[0062] 34: Gate busbar;

[0063] 35, 35a, 35b, 35c, 35d, 35e, 35f, 35g: transistors;

[0064] 36: drain busbar;

[0065] 38, 38a, 38b, 39a, 39b: transistor group;

[0066] 50: Main side;

[0067] 52: back;

[0068] 56: end edge;

[0069] 100 , 101 , 102 , 103 , 104 , 105 , 106 , 107 , 108 , 110 , 112 : semiconductor devices. DETAILED DESCRIPTION

[0070] [Description of Embodiments of the Present Disclosure]

[0071] First, the contents of the embodiments of the present disclosure will be listed and described.

[0072] (1) One embodiment of the present disclosure is a semiconductor device comprising: a substrate having a main surface and a back surface opposite to the main surface; a first transistor having a first source electrode, a first drain electrode, and a first gate electrode, wherein the first gate electrode is arranged between the first source electrode and the first drain electrode in a first direction, and the first transistor is provided on the main surface; a second transistor having a second source electrode, a second drain electrode, and a second gate electrode, wherein the second source electrode overlaps with the first source electrode when viewed from a second direction intersecting the first direction, the second drain electrode is electrically connected to the first drain electrode, and the second gate electrode is arranged between the second source electrode and the second drain electrode in the first direction, and the second transistor is provided on the main surface; a third transistor having a third source electrode, a third drain electrode, and a third gate electrode, wherein the third source electrode is arranged above the first source electrode when viewed from the second direction. The first source electrode and the second source electrode are in the first source electrode and the second source electrode and are electrically connected to the first source electrode and the second source electrode, the third drain electrode is electrically connected to the first drain electrode and the second drain electrode, the third gate electrode is arranged between the third source electrode and the third drain electrode in the first direction, and the third transistor is arranged on the main surface between the first transistor and the second transistor; a first gate wiring is arranged on the main surface, so that the third source electrode is arranged between the first gate wiring and the third gate electrode, the first gate wiring is arranged in the first source electrode and the second source electrode when viewed from the second direction, and is electrically connected to the first gate electrode and the second gate electrode; and a back metal layer is arranged on the back surface, and is electrically connected to the first source electrode and the second source electrode through a first via hole and a second via hole respectively overlapping the first source electrode and the second source electrode when viewed from the thickness direction of the substrate. Thus, the gate resistance and the source inductance can be reduced. Therefore, the degradation of the characteristics can be suppressed.

[0073] (2) In the above (1), the semiconductor device may include: a gate bus, which arranges the second transistor between the gate bus and the third transistor, and the gate bus is electrically connected to the second gate electrode; a second gate wiring provided on the main surface, which arranges the second drain electrode between the second gate wiring and the second gate electrode, and the second gate wiring is provided inside the first drain electrode and the third drain electrode when viewed from the second direction, and is electrically connected to the gate bus; and a third gate wiring provided on the main surface, which electrically connects the first gate wiring to the second gate wiring between the second transistor and the third transistor, and the second drain electrode is provided inside the first drain electrode and the third drain electrode when viewed from the second direction. Thus, the gate resistance can be reduced.

[0074] (3) In the above (2), the semiconductor device may include a first drain wiring, the first drain wiring is provided on the main surface, and electrically connects the second drain electrode to the third drain electrode, and the third gate wiring crosses the first drain wiring without contacting the first drain wiring, and electrically connects the first gate wiring to the second gate wiring. Thus, a gate potential can be supplied to the first gate wiring via the second gate wiring and the third gate wiring.

[0075] (4) In the above (1), the semiconductor device may include: a gate bus bar, which allows the second transistor to be arranged between the gate bus bar and the third transistor, and the gate bus bar is electrically connected to the second gate electrode; a second gate wiring, which is provided on the main surface, overlaps with the second drain electrode without contact when viewed from the thickness direction of the substrate, and is electrically connected to the gate bus bar; and a third gate wiring, which is provided on the main surface, and electrically connects the first gate wiring and the second gate wiring between the second transistor and the third transistor. In this way, the gate resistance can be reduced.

[0076] (5) In the above (1), the semiconductor device may include: a gate bus bar, which allows the second transistor to be arranged between the gate bus bar and the third transistor, and the gate bus bar is electrically connected to the second gate electrode; and a second gate wiring, which is provided on the main surface and overlaps with the second source electrode without contact when viewed from the thickness direction of the substrate, and electrically connects the gate bus bar to the first gate wiring. In this way, the gate resistance can be reduced.

[0077] (6) In any one of the above (1) to (5), a plurality of the third transistors may be arranged in the second direction. This can reduce gate resistance.

[0078] (7) In any one of the above (1) to (6), the semiconductor device may include: a fourth transistor including the first source electrode, a fourth drain electrode and a fourth gate electrode, wherein the fourth drain electrode enables the first source electrode to be arranged between the fourth drain electrode and the first gate electrode, the fourth gate electrode is arranged between the first source electrode and the fourth drain electrode in the first direction and is electrically connected to the first gate wiring, and the fourth transistor is provided on the main surface; and a fifth transistor including the second source electrode, a fifth drain electrode and a fifth gate electrode, wherein the fifth drain electrode enables the second source electrode to be arranged between the fifth drain electrode and the second gate electrode and is electrically connected to the fourth drain electrode, The fifth gate electrode is arranged between the second source electrode and the fifth drain electrode in the first direction, and the fifth transistor is arranged on the main surface; and a sixth transistor, which includes a fourth source electrode, a sixth drain electrode and a sixth gate electrode, wherein the fourth source electrode is arranged inside the first source electrode and the second source electrode when viewed from the second direction and is electrically connected to the first source electrode and the second source electrode, the sixth drain electrode is electrically connected to the fourth drain electrode and the fifth drain electrode, the sixth gate electrode is arranged between the fourth source electrode and the sixth drain electrode in the first direction and is electrically connected to the first gate wiring, and the sixth transistor is arranged on the main surface between the fourth transistor and the fifth transistor. Thus, miniaturization can be achieved.

[0079] (8) In the above (2) or (3), the semiconductor device may include a seventh transistor, the seventh transistor including: a seventh drain electrode, the second gate wiring being arranged between the seventh drain electrode and the second drain electrode, the seventh drain electrode being arranged inside the first drain electrode and the third drain electrode when viewed from the second direction, and being electrically connected to the first drain electrode and the third drain electrode; a fifth source electrode, the seventh drain electrode being arranged between the fifth source electrode and the second gate wiring; and a seventh gate electrode being arranged between the fifth source electrode and the seventh drain electrode in the first direction, the seventh transistor being arranged on the main surface. Thus, miniaturization can be achieved.

[0080] (9) One embodiment of the present disclosure is a semiconductor device comprising: a substrate having a main surface and a back surface opposite to the main surface; a first transistor having a first source electrode, a first drain electrode and a first gate electrode, wherein the first gate electrode is arranged between the first source electrode and the first drain electrode in a first direction, and the first transistor is arranged on the main surface; a second transistor having a second source electrode, a second drain electrode and a second gate electrode, wherein the second source electrode is arranged in the first source electrode and is electrically connected to the first source electrode when viewed from a second direction intersecting the first direction, the second drain electrode is electrically connected to the first drain electrode, and the second a second gate electrode arranged between the second source electrode and the second drain electrode in the first direction, and the second transistor is arranged on the main surface; a third transistor, comprising a third source electrode, the first drain electrode and a third gate electrode, wherein the third source electrode makes the first drain electrode arranged between the third source electrode and the first gate electrode, and the third gate electrode is arranged between the third source electrode and the first drain electrode in the first direction, and the third transistor is arranged on the main surface; a fourth transistor, comprising a fourth source electrode, the second drain electrode and a fourth gate electrode, wherein the fourth source electrode is arranged inside the third source electrode and outside the third source electrode when viewed from the second direction and electrically connected to the third source electrode, the fourth gate electrode is arranged between the fourth source electrode and the second drain electrode in the first direction, and the fourth transistor is arranged on the main surface; a first gate wiring is arranged on the main surface, and the second source electrode is arranged between the first gate wiring and the second gate electrode in the first direction, the first gate wiring is arranged inside the first source electrode when viewed from the second direction, and is electrically connected to the first gate electrode; a second gate wiring is arranged on the main surface, and the fourth source electrode is arranged between the second gate wiring and the fourth gate electrode in the first direction, and the second gate wiring is arranged inside the first source electrode when viewed from the second direction, and is electrically connected to the first gate electrode; and a second gate wiring is arranged on the main surface, and the fourth source electrode is arranged between the second gate wiring and the fourth gate electrode in the first direction, and the second gate wiring is arranged inside the first source electrode when viewed from the second direction. When viewed from the thickness direction of the substrate, the first source electrode, the third source electrode, and the source connection wiring are respectively arranged in the third source electrode and electrically connected to the third gate electrode; the source connection wiring is arranged on the main surface, so that the second transistor and the fourth transistor are arranged between the source connection wiring and the first transistor and the third transistor, and the source connection wiring electrically connects the second source electrode to the fourth source electrode; and the back metal layer is arranged on the back surface, and is electrically connected to the first source electrode, the third source electrode, and the source connection wiring through the first via hole, the second via hole, and the third via hole respectively overlapping with the first source electrode, the third source electrode, and the source connection wiring when viewed from the thickness direction of the substrate. Thus, the gate resistance and the source inductance can be reduced. Therefore, the degradation of the characteristics can be suppressed.

[0081] (10) In the above (9), the source connection wiring may be provided in an inactive region of the substrate which is deactivated. This can suppress parasitic capacitance.

[0082] (11) In the above (9) or (10), the source connection wiring may be arranged between the first gate wiring and the second gate wiring in the first direction. Thus, a gate potential can be supplied to the first gate wiring and the second gate wiring.

[0083] (12) In the above (11), the semiconductor device may include a gate bus, the source connection wiring is arranged between the gate bus and the second transistor and the fourth transistor, and the gate bus is electrically connected to the first gate wiring and the second gate wiring, thereby supplying a gate potential to the gate electrode.

[0084] (13) In any of the above (9) to (12), the width of the source connection wiring in the first direction may be greater than the width of the first source electrode in the first direction and the width of the third source electrode in the first direction. In this way, the width of the drain electrode can be greater than the width of the gate wiring.

[0085] (14) In the above (13), the width of the source connection wiring in the second direction may be smaller than the width of the first source electrode in the second direction and the width of the third source electrode in the second direction, the width of the first via hole and the second via hole in the first direction may be smaller than the width of the first via hole and the second via hole in the second direction, and the width of the source connection wiring in the first direction may be larger than the width of the source connection wiring in the second direction. Thus, miniaturization can be achieved.

[0086] (15) In the above (13), when viewed from the thickness direction, the number of the third vias connected to one source connection wiring may be greater than the number of the first vias connected to one first source electrode and the number of the second vias connected to one third source electrode. This can reduce source inductance.

[0087] [Details of the embodiments of the present disclosure]

[0088] Hereinafter, specific examples of semiconductor devices according to embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0089] [Example 1]

[0090] A semiconductor device of an amplifier used for amplifying a high-frequency signal of, for example, 0.5 GHz to 10 GHz in a base station for mobile communications will be described as an example. Figure 1 1 is a top view of the semiconductor device of Example 1.

[0091] Figures 2 to 5 They are Figure 1 The thickness direction of the substrate 10 is set to the Z direction, the extension direction of the finger-shaped source electrode 12, the gate electrode 14 and the drain electrode 16 is set to the Y direction (a second direction intersecting the first direction), and the arrangement direction of the source electrode 12, the gate electrode 14 and the drain electrode 16 is set to the X direction (the first direction). It should be noted that Figure 1 In the top view, if the source electrode 12 and the drain electrode 16 overlap with the source wiring 22 and the drain wiring 26, it is difficult to see clearly. Therefore, the source wiring 22 and the drain wiring 26 are seen through, and the thick line diagram showing only the outer periphery of the source wiring 22 and the drain wiring 26 is shown inside the source electrode 12 and the drain electrode 16. The same applies to the following figures.

[0092] In each figure, the active region 11, the source electrode 12, the gate electrode 14, the source wiring 22, the drain wiring 26, and the transistor 35 (unit FET) represent general elements, and the active regions 11a, 11c, 11d, 11e, the source electrodes 12a, 12c, 12d, 12e, the gate electrodes 14a to 14f, the drain electrodes 16a to 16f, the source wirings 22a to 22c, 22e, the drain wirings 26a and 26b, and the transistors 35a to 35f represent specific elements included in the general elements. Hereinafter, the transistors 35a to 35f will be described mainly using the active regions 11a, 11c, 11d, 11e, the source electrodes 12a, 12c, 12d, 12e, the gate electrodes 14a to 14f, the drain electrodes 16a to 16f, the source wirings 22a to 22c, 22e, and the drain wirings 26a and 26b.

[0093] like Figures 1 to 5 As shown, in the semiconductor device 100 of the first embodiment, the substrate 10 has a main surface 50 and a back surface 52 opposite to the main surface 50. A plurality of transistors 35 and transistors 35a to 35f are provided on the main surface 50 of the substrate 10. The transistors 35, 35a to 35f arranged in the Y direction form transistor groups 38, 38a and 38b. In the Y direction, the drain bus 36 and the gate bus 34 are provided on the main surface 50, and the transistor groups 38, 38a and 38b are arranged between the drain bus 36 and the gate bus 34.

[0094] The transistors 35 closest to the drain bus 36 are transistors 35a and 35b. The transistors 35 closest to the gate bus 34 are transistors 35e and 35f. The transistors 35 located between the transistors 35a and 35b and the transistors 35e and 35f are transistors 35c and 35d. The transistor group 38a includes one transistor 35a, two transistors 35c, and one transistor 35e. The transistor group 38b includes one transistor 35b, two transistors 35d, and one transistor 35f. The number of transistors 35c is one or more, and the number of transistors 35d is one or more.

[0095] The substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. In the XY plane parallel to the X direction and the Y direction, the region where the semiconductor layer 10b is deactivated by ion implantation or the like is the inactive region 13, and the region where the semiconductor layer 10b is not deactivated (i.e., the region where a part of the substrate 10 is activated) is the active region 11a, 11c to 11e. The active regions 11a and 11e extend in the X direction. The active regions 11c and 11d are arranged in the X direction. Two active regions 11c are arranged in the Y direction, and two active regions 11d are arranged in the Y direction. Transistors 35a and 35b are provided in the active region 11a. Transistors 35c and 35d are provided in the active regions 11c and 11d, respectively. Transistors 35e and 35f are provided in the active region 11e.

[0096] The transistor 35a (first transistor) includes a source electrode 12a (first source electrode), a gate electrode 14a (first gate electrode), and a drain electrode 16a (first drain electrode). The gate electrode 14a is disposed between the source electrode 12a and the drain electrode 16a in the X direction. The source electrode 12a, the gate electrode 14a, and the drain electrode 16a are arranged in sequence along the + direction of the X direction.

[0097] The transistor 35b (fourth transistor) includes a source electrode 12a (first source electrode), a gate electrode 14b (fourth gate electrode), and a drain electrode 16b (fourth drain electrode). The source electrode 12a is disposed between the drain electrode 16b and the gate electrode 14a. The gate electrode 14b is disposed between the source electrode 12a and the drain electrode 16b in the X direction. The source electrode 12a, the gate electrode 14b, and the drain electrode 16b are arranged in sequence along the - direction of the X direction. The transistors 35a and 35b share the source electrode 12a.

[0098] The transistor 35c (third transistor) includes a source electrode 12c (third source electrode), a gate electrode 14c (third gate electrode), and a drain electrode 16c (third drain electrode). The gate electrode 14c is disposed between the source electrode 12c and the drain electrode 16c in the X direction. The source electrode 12c is disposed inside the source electrodes 12a and 12e when viewed from the Y direction. That is, when viewed from the Y direction, the source electrode 12c is not disposed outside the source electrodes 12a and 12e. A plurality of source electrodes 12c overlap each other when viewed from the Y direction. A plurality of drain electrodes 16c overlap each other when viewed from the Y direction. The source electrode 12c, the gate electrode 14c, and the drain electrode 16c are arranged in sequence along the + direction of the X direction.

[0099] The transistor 35d (sixth transistor) includes a source electrode 12d (fourth source electrode), a gate electrode 14d (sixth gate electrode), and a drain electrode 16d (sixth drain electrode). The gate wiring 24 is arranged between the source electrode 12d and the source electrode 12c, and the source electrode 12d is arranged inside the source electrodes 12a and 12e when viewed from the Y direction. That is, when viewed from the Y direction, the source electrode 12d is not arranged outside the source electrodes 12a and 12e. The plurality of source electrodes 12d overlap each other when viewed from the Y direction. The plurality of drain electrodes 16d overlap each other when viewed from the Y direction. In the X direction, the gate electrode 14d is arranged between the source electrode 12d and the drain electrode 16d. The source electrode 12d, the gate electrode 14d, and the drain electrode 16d are arranged in sequence along the - direction of the X direction.

[0100] The transistor 35e (second transistor) includes a source electrode 12e (second source electrode), a gate electrode 14e (second gate electrode), and a drain electrode 16e (second drain electrode). The gate electrode 14e is disposed between the source electrode 12e and the drain electrode 16e in the X direction. When viewed from the Y direction, the source electrode 12e overlaps with the source electrode 12a. When viewed from the Y direction, the drain electrode 16e overlaps with the drain electrodes 16a and 16c. The source electrode 12e, the gate electrode 14e, and the drain electrode 16e are arranged in sequence along the + direction of the X direction.

[0101] The transistor 35f (fifth transistor) includes a source electrode 12e (second source electrode), a gate electrode 14f (fifth gate electrode), and a drain electrode 16f (fifth drain electrode). The source electrode 12e is disposed between the drain electrode 16f and the gate electrode 14e. The gate electrode 14f is disposed between the source electrode 12e and the drain electrode 16f in the X direction. When viewed from the Y direction, the drain electrode 16f overlaps with the drain electrodes 16b and 16d. The source electrode 12e, the gate electrode 14f, and the drain electrode 16f are arranged in sequence along the - direction of the X direction.

[0102] A source wiring 22c is provided in contact with the source electrode 12a. A source wiring 22e is provided in contact with the source electrode 12e.

[0103] A source wiring 22a is provided in contact with the source electrode 12c. The source wiring 22a extends in the Y direction, electrically connects the plurality of source electrodes 12c to each other, and electrically connects the plurality of source electrodes 12c to the source wirings 22c and 22e. A source wiring 22b is provided in contact with the source electrode 12d. The source wiring 22b extends in the Y direction, electrically connects the plurality of source electrodes 12d to each other, and electrically connects the plurality of source electrodes 12d to the source wirings 22c and 22e.

[0104] A drain wiring 26a is provided in contact with the drain electrodes 16a, 16c, and 16e. The drain wiring 26a extends in the Y direction, electrically connects the plurality of drain electrodes 16a, 16c, and 16e to each other, and electrically connects the plurality of drain electrodes 16a, 16c, and 16e to the drain bus 36. A drain wiring 26b is provided in contact with the drain electrodes 16b, 16d, and 16f. The drain wiring 26b extends in the Y direction, electrically connects the plurality of drain electrodes 16b, 16d, and 16f to each other, and electrically connects the plurality of drain electrodes 16b, 16d, and 16f to the drain bus 36.

[0105] A gate wiring 24 (first gate wiring) extending in the Y direction is provided on the inactive region 13 between the transistors 35c and 35d. The gate wiring 24 is provided inside the source electrodes 12a and 12e when viewed from the Y direction. That is, the gate wiring 24 is not provided outside the source electrode 12a when viewed from the Y direction. The gate wiring 24 is electrically connected to the gate bus 34 via the gate electrodes 14e and 14f. The gate wiring 24 includes a gate metal layer 24a provided on the substrate 10 and a wiring layer 24b provided in contact with the gate metal layer 24a.

[0106] A gate wiring 25a extending in the X direction is provided on the inactive region 13 between the transistors 35a and 35c and between the transistors 35c. The gate wiring 25a crosses the source wiring 22a without contacting each other, and electrically connects the gate wiring 24 to the gate electrodes 14a and 14c. A gate wiring 25b extending in the X direction is provided on the inactive region 13 between the transistors 35b and 35d and between the transistors 35d. The gate wiring 25b crosses the source wiring 22b without contacting each other, and electrically connects the gate wiring 24 to the gate electrodes 14b and 14d.

[0107] A gate wiring 25c extending in the X direction is provided on the inactive region 13 between the transistors 35c and 35e. The gate wiring 25c crosses the source wiring 22a without contact, and electrically connects the gate wiring 24 to the gate electrodes 14c and 14e. A gate wiring 25d extending in the X direction is provided on the inactive region 13 between the transistors 35d and 35f. The gate wiring 25d crosses the source wiring 22b without contact, and electrically connects the gate wiring 24 to the gate electrodes 14d and 14f. Thus, the gate electrodes 14a to 14d are electrically connected to the gate bus 34 via the gate wirings 24, 25a to 25d, and the gate electrodes 14e and 14f.

[0108] The vias 20a and 20e penetrate the substrate 10. The vias 20a and 20e overlap with the source electrodes 12a and 12e, respectively, when viewed from the Z direction, and are electrically connected to the source electrodes 12a and 12e, respectively. A metal layer 28 is provided on the back surface 52 of the substrate 10. A metal layer 28a is provided on the inner surface of the via 20. Thus, the metal layer 28 (back metal layer) is electrically connected to the source electrodes 12a and 12e, respectively, via the vias 20a (first via) and 20e (second via). The source electrodes 12c and 12d are not connected to the via 20. The top view shape of the vias 20a and 20e may be an ellipse, an oblong, a rounded quadrilateral, or a circle.

[0109] The source potential (for example, a reference potential such as a ground potential) is supplied from the metal layer 28 to the source electrodes 12a and 12e via the metal layer 28a in the vias 20a and 20e. Furthermore, the source potential is supplied from the source wirings 22c and 22e to the source electrodes 12c and 12d respectively via the source wirings 22a and 22b. The gate potential (for example, a high-frequency signal and a gate bias voltage) is supplied from the gate bus 34 to the gate electrodes 14a to 14d via the gate electrodes 14e and 14f, the gate wirings 24, 25a to 25d. The drain bias voltage is supplied from the drain bus 36 to the drain electrodes 16a to 16f via the drain wirings 26a and 26b. The high-frequency signal amplified in each transistor 35a to 35f is output from the drain wirings 26a and 26b to the drain bus 36.

[0110] The + ends of the gate electrodes 14c and 14d in the Y direction are connected to the - ends of the gate electrodes 14a and 14b in the Y direction. The + ends of the gate electrodes 14c and 14d in the Y direction may not be connected to the - ends of the gate electrodes 14a and 14b in the Y direction.

[0111] When the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10a is, for example, a silicon carbide (SiC) substrate, a silicon (Si) substrate, a gallium nitride (GaN) substrate, or a sapphire (Al2O3) substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, and / or an indium gallium nitride (InGaN) layer. When the transistors 35a to 35f are GaN HEMTs (Gallium Nitride High Electron Mobility Transistors), the semiconductor layer 10b includes a gallium nitride channel layer provided on the substrate 10a and an aluminum gallium nitride barrier layer provided on the channel layer. When the semiconductor device 100 is, for example, a gallium arsenide (GaAs) semiconductor device, the substrate 10a is, for example, a gallium arsenide substrate. The semiconductor layer 10b includes, for example, an arsenide semiconductor layer such as a gallium arsenide layer, an aluminum gallium arsenide (AlGaAs) layer, and / or an indium gallium arsenide (InGaAs) layer. The semiconductor device 100 may be a silicon semiconductor device such as LDMOS (Laterally Diffused Metal Oxide Semiconductor).

[0112] The source electrodes 12a, 12c, 12d, 12e and the drain electrodes 16a to 16f are metal films, for example, titanium films and aluminum films from the substrate 10 side. The gate electrodes 14a to 14f and the gate metal layer 24a are metal films, for example, nickel films and gold films from the substrate 10 side. The source wirings 22a to 22c, 22e, the drain wirings 26a, 26b, the wiring layer 24b, the metal layers 28, 28a and the drain bus 36 are, for example, gold layers, copper layers or aluminum layers. The insulating layer 30 provided on the substrate 10 so as to cover the transistors 35a to 35f is, for example, an organic insulating layer such as a polyimide layer or a BCB (Benzocyclobutene) layer.

[0113] The width of the source electrodes 12a and 12e in the X direction is, for example, 50 μm to 150 μm. The width of the source electrodes 12c and 12d in the X direction is, for example, 5 μm to 20 μm. The gate length of the gate electrodes 14a to 14f in the X direction is, for example, 0.25 μm to 2 μm. The width of the drain electrodes 16a to 16f in the X direction is, for example, 5 μm to 150 μm. The width of the gate wiring 24 in the X direction is, for example, 5 μm to 20 μm. The width of the gate wiring 25a to 25d in the Y direction is, for example, 3 μm to 20 μm. In order to reduce the gate resistance, the width of the gate wiring 24 in the X direction and the width of the gate wiring 25a to 25d in the Y direction are greater than the gate length, for example, more than twice the gate length. The gate width of the transistors 35a to 35f in the Y direction is, for example, 100 μm to 400 μm. The width of the via holes 20 a and 20 e in the X direction is, for example, 10 μm to 60 μm.

[0114] The widths of the source wirings 22a to 22c, 22e and the drain wirings 26a and 26b in the X direction are the same as or slightly smaller than the widths of the source electrodes 12a, 12c, 12d, 12e and the drain electrodes 16a and 16d in the X direction, respectively. The thickness of the source wirings 22a to 22c, 22e and the drain wirings 26a and 26b is, for example, 1 μm to 20 μm.

[0115] Figure 6 FIG. 1 is a simplified top view of the semiconductor device of Example 1. Figure 6 , the illustration of the active region 11, the source electrode 12, and the drain electrode 16 are omitted. The transistors 35 arranged in the X direction are set as transistor groups 39a and 39b. In transistor group 39a, transistors 35a (and 35e) and 35b (and 35f) share a source electrode, and a via 20a (and 20e) is provided. In transistor group 39b, a gate wiring 24 is provided between transistors 35c and 35d. The transistor group closest to the drain bus 36 is transistor group 39a, and the transistor group closest to the gate bus 34 is transistor group 39a.

[0116] [Comparative Example 1]

[0117] Comparative Example 1 is an example of a multi-finger FET. Figure 7 is a top view of the semiconductor device of Comparative Example 1. Figure 7 As shown, in the semiconductor device 110 of Comparative Example 1, the gate wirings 24, 25a to 25d are not provided. The gate electrode 14 extends in the Y direction and is directly electrically connected to the gate bus 34. The via 20 is directly provided in the source electrode.

[0118] [Comparative Example 2]

[0119] Figure 8is a top view of the semiconductor device of Comparative Example 2. Figure 8 As shown, in the semiconductor device 112 of the second comparative example, the transistor group closest to the gate bus 34 is the transistor group 39b, and the gate wiring 24 is directly electrically connected to the gate bus 34. The other configurations are the same as those of the first embodiment.

[0120] In Comparative Example 1, the via 20 is provided in the source electrode, so the source inductance can be suppressed. However, the gate electrode 14 is lengthened, so the gate resistance is increased.

[0121] In Comparative Example 2, gate wirings 24, 25a, and 25b are provided, so that gate resistance can be made smaller than in Comparative Example 1. However, source potential is supplied from the metal layer 28 to the source electrodes of the transistors 35c and 35d via the via 20, the source wirings 22c, 22a, and 22b. Therefore, the source inductance is larger than in Comparative Example 1.

[0122] In Comparative Example 2, in order to reduce gate resistance and source inductance, it is considered to reduce the width in the Y direction between the drain bus 36 and the gate bus 34. However, in this case, if the desired gate width is to be ensured and the saturation power is to be increased, the width in the X direction of the semiconductor chip on which the semiconductor device is provided will be increased. As a result, the ratio of the width in the Y direction to the width in the X direction of the semiconductor chip will become smaller. The semiconductor chip is easily broken, which is not realistic.

[0123] [simulation]

[0124] The source inductance of the source wiring in Comparative Example 2 and Example 1 was simulated. The source wiring A is the source wiring in Comparative Example 2. Fig. 9 is a top view of the source wiring A in the simulation. Fig. 9 As shown, in the source wiring A, source wirings 22a and 22b extend from source wiring 22c in the - direction in the Y direction. At the - ends of the source wirings 22a and 22b in the Y direction, the source wirings 22a and 22b are electrically connected by a source wiring 22d.

[0125] The source wiring B is the source wiring of the first embodiment. Fig.10 is a top view of the source wiring B in the simulation. Fig.10 As shown in FIG. 1 , source wirings 22c and 22e are arranged in the Y direction in source wiring B, and source wirings 22a and 22b are electrically connected to source wirings 22c and 22e. The other configurations are the same as those of source wiring A.

[0126] The width Wgu in the Y direction of the source wirings A and B is set as the cell gate width. The inductance between the via 20 (or 20a and 20e) and the positive end side 56 in the X direction of the source wiring 22a is set as the source inductance Ls.

[0127] Fig.11 is a graph showing the source inductance Ls relative to the cell gate width Wgu in the simulation. Fig.11 As shown in FIG. 1 , in the source wiring A of Comparative Example 2, if the unit gate width Wgu is increased, the source inductance Ls increases sharply. On the other hand, in the source wiring B of Example 1, even if the unit gate width Wgu is increased, the increase in source inductance Ls is slow. Thus, in Example 1, the source inductance can be reduced compared to Comparative Example 2.

[0128] According to Example 1, when viewed from the Y direction, the source electrode 12c and the gate wiring 24 are provided in the source electrodes 12a and 12e. The gate wirings 25a and 25c electrically connect the gate wiring 24 to the gate electrodes 14a and 14c. As a result, there is almost no enlargement compared with Comparative Example 1, and the gate resistance can be reduced compared with Comparative Example 1. In addition, a transistor 35c is provided between transistors 35a and 35e. The source potential is supplied to the source electrodes 12a and 12e of transistors 35a and 35e via vias 20a and 20e. As a result, there is almost no enlargement compared with Comparative Example 2, and the source inductance can be reduced compared with Comparative Example 2. In summary, the degradation of high-frequency characteristics can be suppressed. It should be noted that in Example 1, the gate resistance is greater than that in Comparative Example 2, but by designing a balance between the gate resistance and the source inductance, the high-frequency characteristics can be improved compared with Comparative Examples 1 and 2.

[0129] The gate bus bar 34 is electrically connected to the gate electrode 14e. Thus, a gate potential can be supplied to the gate wiring 24 via the gate electrode 14e and the gate wiring 25c. Therefore, the gate resistance can be reduced.

[0130] A transistor 35b that shares the source electrode 12a with the transistor 35a and a transistor 35f that shares the source electrode 12e with the transistor 35e are provided. The source electrode 12c of the transistor 35c and the source electrode 12d of the transistor 35d are accommodated in the source electrodes 12a and 12e when viewed from the Y direction. This enables miniaturization.

[0131] The number of transistors 35c and 35d in the Y direction may be one or more. As in the simulation, even if there are two transistors 35c and 35d in the Y direction, the source inductance can be reduced. From the perspective of reducing gate resistance, the number of transistors 35c and 35d in the Y direction may be set to be more than one. From the perspective of reducing source inductance, the number of transistors 35c and 35d in the Y direction may be set to less than five, less than four, or less than three.

[0132] [Variation 1 of Example 1]

[0133] Fig.12It is a top view of a semiconductor device according to Modification 1 of Embodiment 1. Figures 13 to 15 They are Fig.12 A-A section view, B-B section view and C-C section view.

[0134] like Figures 12 to 15 As shown, in the semiconductor device 101 according to the first modification of the first embodiment, the transistor 35g is provided in a region closer to the positive direction in the X direction than the transistor 35e.

[0135] The drain electrode 16e (second drain electrode) of the transistor 35e (second transistor) is provided inside the drain electrodes 16a (first drain electrode) and 16c (third drain electrode) when viewed from the Y direction. That is, the drain electrode 16e is not provided outside the drain electrodes 16a and 16c when viewed from the Y direction.

[0136] The transistor 35g (the seventh transistor) includes a source electrode 12g (the fifth source electrode), a gate electrode 14g (the seventh gate electrode), and a drain electrode 16g (the seventh drain electrode). The gate electrode 14g is disposed between the source electrode 12g and the drain electrode 16g in the X direction. When viewed from the Y direction, the drain electrode 16g is disposed inside the drain electrodes 16a and 16c. That is, when viewed from the Y direction, the drain electrode 16g is not disposed outside the drain electrodes 16a and 16c. The source electrode 12g, the gate electrode 14g, and the drain electrode 16g are arranged in sequence along the - direction of the X direction.

[0137] A drain wiring 26e (first drain wiring) is provided in contact with the drain electrode 16e. The drain wiring 26e extends in the Y direction and electrically connects the drain electrode 16e to the drain electrodes 16a and 16c via the drain wiring 26a. A drain wiring 26g (second drain wiring) is provided in contact with the drain electrode 16g. The drain wiring 26g extends in the Y direction and electrically connects the drain electrode 16g to the drain electrodes 16a and 16c via the drain wiring 26a.

[0138] A gate wiring 24c (second gate wiring) extending in the Y direction is provided on the inactive region 13 between the transistors 35e and 35g. The gate wiring 24c is provided inside the drain electrodes 16a and 16c when viewed from the Y direction. That is, the gate wiring 24c is not provided outside the drain electrodes 16a and 16c when viewed from the Y direction. The gate wiring 24c is electrically connected to the gate bus 34. The gate wiring 24c includes a gate metal layer 24a provided on the substrate 10 and a wiring layer 24b provided in contact with the gate metal layer 24a.

[0139] A gate wiring 25e (third gate wiring) extending in the X direction is provided on the inactive region 13 between the transistors 35c and 35e. The gate wiring 25e crosses the drain wiring 26e without contact, and electrically connects the gate wiring 24c to the gate wiring 25c. A gate wiring 25f extending in the X direction is provided on the inactive region 13 between the drain electrodes 16c and 16g. The gate wiring 25f crosses the drain wiring 26g without contact, and electrically connects the gate wiring 24c to the gate electrode 14g. The other configurations are the same as those in the first embodiment, and the description thereof is omitted.

[0140] In the first modification of the first embodiment, the gate wiring 24c (second gate wiring) is provided inside the drain electrodes 16a and 16c when viewed from the Y direction, so that the gate wiring 24c is electrically connected to the gate bus 34. The drain electrode 16e is arranged between the gate wiring 24c and the gate electrode 14e. The gate wiring 25e (third gate wiring) electrically connects the gate wiring 24c to the gate wiring 24 between the transistors 35c and 35e. Thus, the gate potential is supplied to the gate wiring 24 via the gate wirings 24c, 25e, and 25c. Therefore, the gate resistance can be reduced compared with the first embodiment.

[0141] The gate wiring 25f crosses the drain wiring 26g without contact, and electrically connects the gate wiring 24c to the gate wiring 24. Thus, the gate potential can be supplied to the gate wiring 24 via the gate wiring 24c and the gate wirings 25c to 25e. The width of the gate wiring 24c in the X direction and the width of the gate wirings 25e and 25f in the Y direction are larger than the width of the gate electrodes 14e and 14g in the X direction, for example, more than twice. Thus, the gate resistance can be further reduced.

[0142] The drain electrode 16e of the transistor 35e (second transistor), the drain electrode 16g of the transistor 35g (seventh transistor), and the gate wiring 24c are provided inside the drain electrodes 16a and 16c when viewed from the Y direction. This enables miniaturization.

[0143] [Variation 2 of Example 1]

[0144] Fig.16 It is a top view of a semiconductor device according to a second variation of the first embodiment. Fig.17 and Fig.18 They are Fig.16 A-A section view and B-B section view.

[0145] like Figures 16 to 18As shown, in the semiconductor device 102 of the second modification of the first embodiment, a transistor 35g is provided in a region closer to the + direction in the X direction than the transistor 35e. The transistor 35g includes a source electrode 12g, a gate electrode 14g, and a drain electrode 16e. The gate electrode 14g is arranged between the source electrode 12g and the drain electrode 16e in the X direction. The source electrode 12g, the gate electrode 14g, and the drain electrode 16e are arranged in sequence along the - direction in the X direction.

[0146] A gate wiring 32a is provided above the drain wiring 26a on the drain electrode 16e without contact therewith. The gate wiring 32a is electrically connected to a gate bus 34. The gate bus 34 includes a gate metal layer 24a, wiring layers 24b and 33 provided on the substrate 10 in this order.

[0147] Gate wirings 25e and 25f extending in the X direction are provided on the inactive region 13 between the drain electrodes 16c and 16e. The gate wiring 32a is electrically connected to the gate wirings 25e and 25f via the wiring 31 in the opening 27 that passes through the drain wiring 26a. The gate wiring 25e crosses the drain wiring 26a without contact, and the gate wiring 32a is electrically connected to the gate wiring 25c. The gate wiring 25f crosses the drain wiring 26a without contact, and the gate wiring 32a is electrically connected to the gate electrode 14g. The other configurations are the same as those in Embodiment 1, and the description thereof is omitted.

[0148] According to the second variation of the first embodiment, the gate wiring 32a (second gate wiring) overlaps the drain electrode 16e without contact when viewed from the Z direction, and is electrically connected to the gate bus 34. The gate wiring 25e (third gate wiring) electrically connects the gate wiring 24 to the gate wiring 32a between the transistors 35c and 35e. Thus, the gate potential is supplied to the gate wiring 24 via the gate wiring 32a, the wiring 31, the gate wiring 25e and 25c. Therefore, compared with the first embodiment, the gate resistance can be reduced. The width of the gate wiring 32a in the X direction is greater than the width of the gate electrodes 14e and 14g in the X direction, for example, more than twice. Thus, the gate resistance can be further reduced.

[0149] [Variation 3 of Example 1]

[0150] Fig.19 It is a top view of a semiconductor device according to a third variation of the first embodiment. Fig. 20 and Fig.21 They are Fig.19 A-A section view and B-B section view.

[0151] like Figures 19 to 21As shown, in the semiconductor device 103 of the third variation of the first embodiment, a gate wiring 32b is provided above the source wiring 22e without contact. The gate wiring 32b is electrically connected to the gate bus 34. The gate bus 34 is provided with a gate metal layer 24a, wiring layers 24b and 33 in sequence on the substrate 10.

[0152] The gate wiring 32b is electrically connected to the gate wiring 24 at the positive end in the Y direction of the gate wiring 32b via the wiring 31. The other configurations are the same as those in the first embodiment, and the description thereof is omitted.

[0153] According to the modification 3 of the first embodiment, the gate wiring 32b (second gate wiring) overlaps the source electrode 12e without contact when viewed from the Z direction, and the gate bus 34 is electrically connected to the gate wiring 24. Thus, the gate potential is supplied to the gate wiring 24 via the gate wiring 32b and the wiring 31. Therefore, compared with the first embodiment, the gate resistance can be reduced. The width of the gate wiring 32b in the X direction is larger than the width of the gate electrodes 14e and 14f in the X direction, for example, more than twice. Thus, the gate resistance can be further reduced.

[0154] Compared with the first embodiment, the modified examples 1 to 3 of the first embodiment can reduce the gate resistance. In the modified example 1 of the first embodiment, when viewed from the Z direction, the drain wiring 26e overlaps with the gate wiring 25e, so the gate / drain parasitic capacitance is larger than that of the first embodiment. In the modified example 2 of the first embodiment, when viewed from the Z direction, the drain wiring 26a overlaps with the gate wiring 32a, so the gate / drain parasitic capacitance is larger than that of the first embodiment. Compared with the modified example 2 of the first embodiment, the gate / drain parasitic capacitance can be reduced in the modified example 1 of the first embodiment. In the modified example 3 of the first embodiment, when viewed from the Z direction, the source wiring 22e overlaps with the gate wiring 32b, so the gate / source parasitic capacitance is larger than that of the first embodiment. In order to improve the high-frequency characteristics, the semiconductor device used in the semiconductor devices of the first embodiment and the modified examples 1 to 3 can be determined by considering the balance of the gate resistance, the source inductance, the gate / drain parasitic capacitance, and the gate / source parasitic capacitance.

[0155] [Variation 4 of Example 1]

[0156] Fig. 22 FIG. 1 is a simplified top view of a semiconductor device according to a fourth variation of the first embodiment. Fig. 22 In the figure, the active region 11, the source electrode 12, and the drain electrode 16 are omitted. Fig. 22As shown, in the semiconductor device 104 of the fourth variation of the first embodiment, the transistor group closest to the drain bus 36 among the transistor groups 39a and 39b arranged in the Y direction is the transistor group 39a, and the transistor group closest to the gate bus 34 is the transistor group 39b. There are seven transistor groups 39a and 39b in total, and two transistor groups 39b are provided between the transistor groups 39a adjacent to each other in the Y direction. The other configurations are the same as those of the first embodiment. Figure 6 The same, description omitted.

[0157] [Variation 5 of Example 1]

[0158] Fig.23 FIG. 1 is a simplified top view of a semiconductor device according to a fifth variation of the first embodiment. Fig.23 In the figure, the active region 11, the source electrode 12, and the drain electrode 16 are omitted. Fig.23 As shown, in the semiconductor device 105 of the fifth modification of the first embodiment, one transistor group 39b is provided between the transistor groups 39a adjacent to each other in the Y direction. The other configurations are the same as those of the fourth modification of the first embodiment, and the description thereof is omitted.

[0159] As in Modifications 4 and 5 of Embodiment 1, at least two transistor groups 39a may be provided in the Y direction, and at least one transistor group 39b may be provided between the transistor groups 39a adjacent to each other in the Y direction.

[0160] In the first embodiment and its modified example, an example in which four transistor groups 39a and 39b are arranged in the Y direction is described, but five or more transistor groups 39a and 39b may be arranged in the Y direction. A source wiring with the drain wiring 26 arranged therebetween in the X direction may also be connected between the drain wiring 26 and the gate bus 34.

[0161] In the first embodiment and its modified examples, the plurality of drain electrodes 16 (e.g., drain electrodes 16a, 16c, and 16e) electrically connected to the same drain wiring 26 (e.g., drain wiring 26a) are separated from each other in the inactive region 13. The plurality of drain electrodes 16 (e.g., drain electrodes 16a, 16c, and 16e) electrically connected to the drain wiring 26 (e.g., drain wiring 26a) may also be connected to each other in the inactive region 13. In the transistor 35 (e.g., transistor 35a), the source electrode 12 and the source wiring 22 (e.g., source electrode 12a and source wiring 22c) may also be collectively referred to as source electrodes, and the drain electrode 16 and the drain wiring 26 (e.g., drain electrode 16a and drain wiring 26a) may also be collectively referred to as drain electrodes.

[0162] [Example 2]

[0163] Fig.24 It is a top view of the semiconductor device of Example 2. Fig.25and Fig.26 They are Fig.24 A-A section view and B-B section view.

[0164] like Figure 24 to Figure 26 As shown, in the semiconductor device 106 of the second embodiment, the substrate 10 is provided with a plurality of transistors 35 and transistors 35a to 35d on the main surface of the substrate 10. The transistors 35, 35a to 35d arranged in the Y direction form transistor groups 38, 38a and 38b.

[0165] The transistors 35 closest to the drain bus 36 are transistors 35a and 35b. The transistors 35 closer to the gate bus 34 than the transistors 35a and 35b are transistors 35c and 35d. The transistor group 38a includes one transistor 35a and three transistors 35c. The transistor group 38b includes one transistor 35b and three transistors 35d. The number of transistors 35c is one or more, and the number of transistors 35d is one or more.

[0166] The active region 11a extends in the X direction. The active regions 11c and 11d are arranged in the X direction. The transistors 35a and 35b are provided in the active region 11a. The transistors 35c and 35d are provided in the active region 11c.

[0167] The transistor 35a (first transistor) includes a source electrode 12a (first source electrode), a gate electrode 14a (first gate electrode), and a drain electrode 16a (first drain electrode). The gate electrode 14a is disposed between the source electrode 12a and the drain electrode 16a in the X direction. The source electrode 12a, the gate electrode 14a, and the drain electrode 16a are arranged in sequence along the + direction of the X direction.

[0168] The transistor 35c (second transistor) includes a source electrode 12c (second source electrode), a gate electrode 14c (second gate electrode), and a drain electrode 16c (second drain electrode). The gate electrode 14c is disposed between the source electrode 12c and the drain electrode 16c in the X direction. The source electrode 12c is disposed inside the source electrode 12a when viewed from the Y direction. That is, the source electrode 12c is not disposed outside the source electrode 12a when viewed from the Y direction. A plurality of drain electrodes 16c overlap with the drain electrode 16a when viewed from the Y direction. The source electrode 12c, the gate electrode 14c, and the drain electrode 16c are arranged in sequence along the + direction of the X direction.

[0169] The transistor 35b (third transistor) includes a source electrode 12b (third source electrode), a gate electrode 14b (third gate electrode), and a drain electrode 16a (first drain electrode). The drain electrode 16a is shared by the transistors 35a and 35b. The drain electrode 16a is arranged between the source electrode 12b and the gate electrode 14a. The gate electrode 14b is arranged between the source electrode 12b and the drain electrode 16a in the X direction. The source electrode 12b, the gate electrode 14b, and the drain electrode 16a are arranged in sequence along the - direction of the X direction.

[0170] The transistor 35d (fourth transistor) includes a source electrode 12d (fourth source electrode), a gate electrode 14d (fourth gate electrode) and a drain electrode 16c (second drain electrode). The drain electrode 16c is shared by the transistors 35c and 35d. The drain electrode 16c is arranged between the source electrode 12d and the gate electrode 14c. The gate electrode 14d is arranged between the source electrode 12d and the drain electrode 16c in the X direction. The source electrode 12d is arranged inside the source electrode 12b when viewed from the Y direction. That is, when viewed from the Y direction, the source electrode 12d is not arranged outside the source electrode 12b. The source electrode 12d, the gate electrode 14d and the drain electrode 16c are arranged in sequence along the - direction of the X direction.

[0171] A source connection wiring 23 is provided on the inactive region 13 of the main surface 50 between the transistor groups 38, 38a, and 38b and the gate bus 34. The source connection wiring 23 includes an ohmic electrode layer 12h and a source wiring 22e provided in contact with the ohmic electrode layer 12h. The source connection wiring 23 electrically connects the source wirings 22a and 22b.

[0172] A source wiring 22c is provided in contact with the source electrode 12a. A source wiring 22d is provided in contact with the source electrode 12b. A source wiring 22a (first source wiring) is provided in contact with the source electrode 12c. The source wiring 22a extends in the Y direction, electrically connects the plurality of source electrodes 12c to each other, and electrically connects the plurality of source electrodes 12c to the source wiring 22c and the source connection wiring 23. A source wiring 22b (second source wiring) is provided in contact with the source electrode 12d. The source wiring 22b extends in the Y direction, electrically connects the plurality of source electrodes 12d to each other, and electrically connects the plurality of source electrodes 12d to the source wiring 22d and the source connection wiring 23.

[0173] A drain wiring 26 a is provided in contact with the drain electrodes 16 a and 16 c. The drain wiring 26 a extends in the Y direction, electrically connects the plurality of drain electrodes 16 a and 16 c to each other, and electrically connects the plurality of drain electrodes 16 a and 16 c to the drain bus bar 36 .

[0174] Gate wiring 24d (first gate wiring) and 24e (second gate wiring) extending in the Y direction are respectively provided on the two inactive regions 13 between which the transistors 35c and 35d are arranged. The gate wiring 24d is provided inside the source electrode 12a when viewed from the Y direction. That is, the gate wiring 24d is not provided outside the source electrode 12a when viewed from the Y direction. The gate wiring 24e is provided inside the source electrode 12b when viewed from the Y direction. That is, the gate wiring 24e is not provided outside the source electrode 12b when viewed from the Y direction. The gate wirings 24d and 24e are electrically connected to the gate bus 34. The gate wirings 24d and 24e include a gate metal layer 24a provided on the substrate 10 and a wiring layer 24b provided in contact with the gate metal layer 24a.

[0175] A gate wiring 25a extending in the X direction is provided between the transistors 35a and 35c and in the inactive region 13 between the transistors 35c. The gate wiring 25a intersects the source wiring 22a without contacting each other, and electrically connects the gate wiring 24d to the gate electrodes 14a and 14c.

[0176] A gate wiring 25b extending in the X direction is provided between the transistors 35b and 35d and in the inactive region 13 between the transistors 35d. The gate wiring 25b intersects the source wiring 22b without contacting each other, and electrically connects the gate wiring 24e to the gate electrodes 14b and 14d.

[0177] A gate wiring 25c extending in the X direction is provided on the inactive region 13 between the transistor 35c and the source connection wiring 23. The gate wiring 25c intersects the source wiring 22a without contacting each other, and electrically connects the gate wiring 24d and the gate electrode 14c.

[0178] A gate wiring 25d extending in the X direction is provided on the inactive region 13 between the transistor 35d and the source connection wiring 23. The gate wiring 25d intersects the source wiring 22b without contacting each other, and electrically connects the gate wiring 24e and the gate electrode 14d.

[0179] The vias 20a, 20b, and 20e penetrate the substrate 10. The vias 20a, 20b, and 20e overlap with the source electrodes 12a, 12b, and the source connection wiring 23 when viewed from the Z direction, and are electrically connected to the source electrodes 12a, 12b, and the source connection wiring 23, respectively. A metal layer 28 is provided on the back surface 52 of the substrate 10. A metal layer 28a is provided on the inner surface of the vias 20a, 20b, and 20e. Thus, the metal layer 28 (back metal layer) is electrically connected to the source electrodes 12a, 12b, and the source connection wiring 23, respectively, via the vias 20a (first via), 20b (second via), and 20e (third via). The via 20 is not connected to the source electrodes 12c and 12d. The top view shape of the vias 20a, 20b, and 20e may be an ellipse, an oblong, a rounded quadrilateral, or a circle.

[0180] The source potential (for example, a reference potential such as a ground potential) is supplied from the metal layer 28 to the source electrodes 12a, 12b and the source connection wiring 23 via the metal layer 28a in the vias 20a, 20b and 20e. Furthermore, the source potential is supplied from the source wirings 22c, 22d and the source connection wiring 23 to the source electrodes 12c and 12d via the source wirings 22a and 22b, respectively. The gate potential (for example, a high-frequency signal and a gate bias voltage) is supplied from the gate bus 34 to the gate electrodes 14a to 14d via the gate wirings 24d, 24e and the gate wirings 25a to 25d. The drain bias voltage is supplied from the drain bus 36 to the drain electrodes 16a and 16c via the drain wiring 26a. The high-frequency signal amplified in each transistor 35a to 35d is output from the drain wiring 26a to the drain bus 36.

[0181] The + ends of the gate electrodes 14c and 14d in the Y direction are not connected to the - ends of the gate electrodes 14a and 14b in the Y direction. The + ends of the gate electrodes 14c and 14d in the Y direction may be connected to the - ends of the gate electrodes 14a and 14b in the Y direction. The other structures are the same as those in Embodiment 1, and the description thereof is omitted.

[0182] According to Embodiment 2, the source connection wiring 23 is configured so that the transistors 35c and 35d are arranged between the source connection wiring 23 and the transistors 35a and 35b, and the source connection wiring 23 electrically connects the source electrodes 12c and 12d. The metal layer 28 (back metal layer) is electrically connected to the source electrodes 12a, 12b and the source connection wiring 23 via the vias 20a, 20b and 20e, thereby short-circuiting. As a result, the gate resistance can be reduced compared with Comparative Example 1. As compared with Comparative Example 2, the source inductance can be reduced. Therefore, the degradation of high-frequency characteristics can be suppressed.

[0183] The source connection wiring 23 is provided in the inactive region 13 of the substrate 10 which is deactivated. This can suppress parasitic capacitance.

[0184] The source connection wiring 23 is arranged between the gate wiring 24d and the gate wiring 24e in the X direction. Thus, a gate potential can be supplied to the gate wirings 24d and 24e from the - direction in the Y direction.

[0185] The source connection wiring 23 is disposed between the gate bus 34 and the transistors 35c and 35d, and is electrically connected to the gate wirings 24d and 24e. Thus, a gate potential can be supplied from the gate bus 34 to the gate electrodes 14a to 14d via the gate wirings 24d and 24e.

[0186] The width W2x of the source connection wiring 23 in the X direction is larger than the width W1x of each of the source electrodes 12a and 12b in the X direction. This is because a larger current flows through the drain wiring 26a than the gate wirings 24d and 24e. Therefore, the width W3 of the drain wiring 26a in the X direction is made larger than the width W4 of the gate wirings 24d and 24e in the X direction. In addition, in the transistor used for the power amplifier, the distance Lgd between the gate electrode and the drain electrode is made larger than the distance Lsg between the source electrode and the gate electrode. The width W2x is, for example, 1.1 times or more, 1.2 times or more, and 10 times or less of the width W1x. The width W3 is, for example, 1.2 times or more, 1.5 times or more, and 10 times or less of the width W4. The distance Lgd is, for example, 1.2 times or more, 1.5 times or more, and 10 times or less of the distance Lsg. It should be noted that the width W2x may be the same as the width W1x, or smaller than the width W1x.

[0187] The number of transistors 35c and 35d in the Y direction may be one or more. From the perspective of reducing gate resistance, the number of transistors 35c and 35d in the Y direction may be more than one. From the perspective of reducing source inductance, the number of transistors 35c and 35d in the Y direction may be less than five, less than four, or less than three.

[0188] [Variation 1 of Example 2]

[0189] Fig. 27 FIG. 1 is a top view of a semiconductor device according to a first variation of the second embodiment. Fig. 27 As shown, in the semiconductor device 107 of the first variation of the second embodiment, the width W2x of the source connection wiring 23 in the X direction is larger than the width W1x of the source electrodes 12a and 12b in the X direction. Moreover, the width W2y of the source connection wiring 23 in the Y direction is smaller than the width W1y of the source electrodes 12a and 12b in the Y direction. The width W5x of the vias 20a and 20b in the X direction is smaller than the width W5y in the Y direction. The width W6x of the via 20e in the X direction is larger than the width W6y in the Y direction. The other configurations are the same as those of the second embodiment, and the description thereof is omitted.

[0190] The top view shape of the vias 20a, 20b, and 20e may have a major axis and a minor axis such as an ellipse, an oblong circle, or a rounded rectangle. In the source electrodes 12a and 12b, for example, the width W1y is greater than the width W1x. Therefore, the major axis direction of the vias 20a and 20b is set to the Y direction. Thus, the vias 20a and 20b can be enlarged, and the source inductance can be reduced.

[0191] Due to the restriction caused by etching when forming the via holes 20a, 20b and 20e on the substrate 10, the top view shapes and areas of the via holes 20a, 20b and 20e are sometimes the same in the degree of manufacturing error. If the long axis direction of the via hole 20e is set to the Y direction as in the second embodiment, the width W2y of the source connection wiring 23 in the Y direction becomes larger. Therefore, the long axis direction of the via hole 20e is set to the X direction. As a result, the width W2y of the source connection wiring 23 in the Y direction can be reduced, and the semiconductor device 107 can be miniaturized.

[0192] Even if the major axis direction of vias 20a and 20b is not the Y direction, the width W5x in the X direction is smaller than the width W5y in the Y direction. Even if the major axis direction of via 20e is not the X direction, the width W6x in the X direction is larger than the width W6y in the Y direction.

[0193] Width W2y is, for example, 0.9 times or less, 0.7 times or less, or 0.1 times or more of width W2x. Widths W5y and W6x are, for example, 1.2 times or more, 1.5 times or more, or 2 times or more of widths W5x and W6y.

[0194] [Variation 2 of Example 2]

[0195] Fig.28 FIG. 2 is a top view of a semiconductor device according to a second variation of the second embodiment. Fig.28 As shown, in the semiconductor device 108 of the second modification of the second embodiment, one source electrode 12a is provided with one via hole 20a, and one source electrode 12b is provided with one via hole 20b. In contrast, two via holes 20e are provided in one source connection wiring 23. The other configurations are the same as those of the second embodiment, and the description thereof is omitted.

[0196] As in the second modification of the second embodiment, when the width W2x of the source connection wiring 23 in the X direction is larger than the width W1x of the source electrodes 12a and 12b in the X direction, the number N2 of vias 20e connected to one source connection wiring 23 can be made larger than the number N1 of vias 20a connected to one source electrode 12a and the number N1 of vias 20b connected to one source electrode 12b. Thus, the source inductance can be reduced. The number N2 is, for example, two or three, and the number N1 is, for example, one.

[0197] In the second embodiment and its modified example, an example in which five transistor groups 38 a and 38 b are arranged in the X direction is described. However, six or more transistor groups 38 a and 38 b may be arranged in the X direction.

[0198] In the second embodiment and its modified example, the plurality of drain electrodes 16 (e.g., drain electrodes 16a and 16c) electrically connected to the same drain wiring 26 (e.g., drain wiring 26a) are separated from each other in the inactive region 13. The plurality of drain electrodes 16 (e.g., drain electrodes 16a and 16c) electrically connected to the drain wiring 26 (e.g., drain wiring 26a) may also be connected to each other in the inactive region 13. In the transistor 35 (e.g., transistor 35a), the source electrode 12 and the source wiring 22 (e.g., source electrode 12a and source wiring 22c) may also be collectively referred to as source electrodes, and the drain electrode 16 and the drain wiring 26 (e.g., drain electrode 16a and drain wiring 26a) may also be collectively referred to as drain electrodes.

[0199] The embodiments disclosed herein are illustrative in all aspects and should not be considered restrictive. The scope of the present disclosure is indicated by the claims rather than the above meanings, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor device comprising: A substrate having a main surface and a back surface opposite to the main surface; The first transistor includes a first source electrode, a first drain electrode, and a first gate electrode, wherein: The first gate electrode is arranged between the first source electrode and the first drain electrode in a first direction, and the first transistor is provided on the main surface; a second transistor including a second source electrode, a second drain electrode, and a second gate electrode, wherein the second source electrode overlaps with the first source electrode when viewed from a second direction intersecting the first direction, the second drain electrode is electrically connected to the first drain electrode, the second gate electrode is arranged between the second source electrode and the second drain electrode in the first direction, and the second transistor is provided on the main surface; a third transistor, comprising a third source electrode, a third drain electrode, and a third gate electrode, wherein the third source electrode is provided inside the first source electrode and the second source electrode and is electrically connected to the first source electrode and the second source electrode when viewed from the second direction, the third drain electrode is electrically connected to the first drain electrode and the second drain electrode, the third gate electrode is arranged between the third source electrode and the third drain electrode in the first direction, and the third transistor is provided on the main surface between the first transistor and the second transistor; a first gate wiring provided on the main surface so that the third source electrode is arranged between the first gate wiring and the third gate electrode, the first gate wiring being provided inside the first source electrode and the second source electrode when viewed from the second direction and being electrically connected to the first gate electrode and the second gate electrode; and A back metal layer is provided on the back surface and is electrically connected to the first source electrode and the second source electrode through a first via hole and a second via hole respectively overlapping the first source electrode and the second source electrode when viewed in the thickness direction of the substrate.

2. The semiconductor device according to claim 1, comprising: A gate bus, so that the second transistor is arranged between the gate bus and the third transistor, and the gate bus is electrically connected to the second gate electrode; a second gate wiring provided on the main surface so that the second drain electrode is arranged between the second gate wiring and the second gate electrode, the second gate wiring being provided inside the first drain electrode and the third drain electrode when viewed from the second direction and being electrically connected to the gate bus; and a third gate wiring provided on the main surface and electrically connecting the first gate wiring and the second gate wiring between the second transistor and the third transistor; When viewed from the second direction, the second drain electrode is disposed inside the first drain electrode and the third drain electrode.

3. The semiconductor device according to claim 2, wherein: A first drain wiring is provided on the main surface and electrically connects the second drain electrode and the third drain electrode. The third gate wiring crosses the first drain wiring without contacting each other, and electrically connects the first gate wiring and the second gate wiring.

4. The semiconductor device according to claim 1, comprising: A gate bus, so that the second transistor is arranged between the gate bus and the third transistor, and the gate bus is electrically connected to the second gate electrode; a second gate wiring provided on the main surface, overlapping with the second drain electrode without contacting it when viewed in the thickness direction of the substrate, and electrically connected to the gate bus bar; and A third gate wiring is provided on the main surface and electrically connects the first gate wiring and the second gate wiring between the second transistor and the third transistor.

5. The semiconductor device according to claim 1, comprising: a gate bus bar, so that the second transistor is arranged between the gate bus bar and the third transistor, and the gate bus bar is electrically connected to the second gate electrode; and The second gate wiring is provided on the main surface, overlaps with the second source electrode without contacting it when viewed in the thickness direction of the substrate, and electrically connects the gate bus bar and the first gate wiring.

6. The semiconductor device according to any one of claims 1 to 5, wherein: A plurality of the third transistors are arranged in the second direction.

7. The semiconductor device according to any one of claims 1 to 5, comprising: The fourth transistor includes the first source electrode, a fourth drain electrode and a fourth gate electrode, wherein: The fourth drain electrode arranges the first source electrode between the fourth drain electrode and the first gate electrode, the fourth gate electrode is arranged between the first source electrode and the fourth drain electrode in the first direction and is electrically connected to the first gate wiring, and the fourth transistor is provided on the main surface; a fifth transistor comprising the second source electrode, a fifth drain electrode and a fifth gate electrode, wherein the fifth drain electrode arranges the second source electrode between the fifth drain electrode and the second gate electrode and is electrically connected to the fourth drain electrode, the fifth gate electrode is arranged between the second source electrode and the fifth drain electrode in the first direction, and the fifth transistor is provided on the main surface; and A sixth transistor comprises a fourth source electrode, a sixth drain electrode and a sixth gate electrode, wherein the fourth source electrode is arranged inside the first source electrode and the second source electrode when viewed from the second direction and is electrically connected to the first source electrode and the second source electrode, the sixth drain electrode is electrically connected to the fourth drain electrode and the fifth drain electrode, the sixth gate electrode is arranged between the fourth source electrode and the sixth drain electrode in the first direction and is electrically connected to the first gate wiring, and the sixth transistor is arranged on the main surface between the fourth transistor and the fifth transistor.

8. The semiconductor device according to claim 2 or 3, wherein: A seventh transistor is provided, the seventh transistor comprising: a seventh drain electrode, the second gate wiring is arranged between the seventh drain electrode and the second drain electrode, the seventh drain electrode is provided inside the first drain electrode and the third drain electrode when viewed from the second direction, and is electrically connected to the first drain electrode and the third drain electrode; a fifth source electrode, so that the seventh drain electrode is arranged between the fifth source electrode and the second gate wiring; and a seventh gate electrode arranged between the fifth source electrode and the seventh drain electrode in the first direction, wherein the seventh transistor is provided on the main surface.

9. A semiconductor device comprising: A substrate having a main surface and a back surface opposite to the main surface; The first transistor includes a first source electrode, a first drain electrode, and a first gate electrode, wherein: The first gate electrode is arranged between the first source electrode and the first drain electrode in a first direction, and the first transistor is provided on the main surface; a second transistor including a second source electrode, a second drain electrode, and a second gate electrode, wherein the second source electrode is provided inside the first source electrode and electrically connected to the first source electrode when viewed from a second direction intersecting the first direction, the second drain electrode is electrically connected to the first drain electrode, the second gate electrode is arranged between the second source electrode and the second drain electrode in the first direction, and the second transistor is provided on the main surface; a third transistor including a third source electrode, the first drain electrode, and a third gate electrode, wherein the third source electrode arranges the first drain electrode between the third source electrode and the first gate electrode, the third gate electrode is arranged between the third source electrode and the first drain electrode in the first direction, and the third transistor is provided on the main surface; a fourth transistor comprising a fourth source electrode, the second drain electrode and a fourth gate electrode, wherein the fourth source electrode is provided inside the third source electrode and electrically connected to the third source electrode when viewed from the second direction, the fourth gate electrode is arranged between the fourth source electrode and the second drain electrode in the first direction, and the fourth transistor is provided on the main surface; a first gate wiring provided on the main surface, so that the second source electrode is arranged between the first gate wiring and the second gate electrode in the first direction, the first gate wiring being provided inside the first source electrode when viewed from the second direction and being electrically connected to the first gate electrode; a second gate wiring provided on the main surface, so that the fourth source electrode is arranged between the second gate wiring and the fourth gate electrode in the first direction, the second gate wiring being provided in the third source electrode when viewed from the second direction and being electrically connected to the third gate electrode; a source connection wiring provided on the main surface, so that the second transistor and the fourth transistor are arranged between the source connection wiring and the first transistor and the third transistor, and the source connection wiring electrically connects the second source electrode and the fourth source electrode; and A back metal layer is provided on the back side and is electrically connected to the first source electrode, the third source electrode and the source connection wiring through a first via hole, a second via hole and a third via hole respectively overlapping with the first source electrode, the third source electrode and the source connection wiring when viewed from the thickness direction of the substrate.

10. The semiconductor device according to claim 9, wherein The source connection wiring is provided in an inactive region where the substrate is deactivated.

11. The semiconductor device according to claim 9 or 10, wherein: In the first direction, the source connection wiring is arranged between the first gate wiring and the second gate wiring.

12. The semiconductor device according to claim 11, wherein A gate bus bar is provided, the source connection wiring is arranged between the gate bus bar and the second transistor and the fourth transistor, and the gate bus bar is electrically connected to the first gate wiring and the second gate wiring.

13. The semiconductor device according to claim 9 or 10, wherein: The width of the source connection wiring in the first direction is larger than the width of the first source electrode in the first direction and the width of the third source electrode in the first direction.

14. The semiconductor device according to claim 13, wherein: The width of the source connection wiring in the second direction is smaller than the width of the first source electrode in the second direction and the width of the third source electrode in the second direction. The widths of the first via hole and the second via hole in the first direction are smaller than the widths of the first via hole and the second via hole in the second direction, The width of the source connection wiring in the first direction is greater than the width of the source connection wiring in the second direction.

15. The semiconductor device according to claim 13, wherein: When viewed in the thickness direction, the number of the third vias connected to one source connection wiring is greater than the number of the first vias connected to one first source electrode and the number of the second vias connected to one third source electrode.

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