Display device

Abstract

The present application provides a display device comprising: a substrate; a first metal layer disposed on the substrate, comprising a plurality of common lines and connecting lines, wherein the common lines are longitudinally parallel to a first direction and the plurality of common lines are arranged along a second direction; a gate insulating layer disposed on the first metal layer and the substrate; a semiconductor layer disposed on the gate insulating layer; and a second metal layer disposed on the gate insulating layer, comprising a plurality of shared lines, wherein the shared lines are longitudinally parallel to the second direction and the plurality of shared lines are arranged along the first direction; the common lines being electrically connected on both sides of the first direction via two first connecting lines, and the shared lines being electrically connected in the second direction via a second connecting line; or the common lines being electrically connected to a fifth connecting line of the second metal layer via a third through-hole, and the shared lines being electrically connected to a fourth connecting line of the first metal layer via a second through-hole. The present application can effectively reduce the risk of electrostatic breakdown in a display device during a first dry etching process, thereby improving product yield.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device. Background Art

[0002] At present, in order to improve the viewing angle characteristics of LCD display panels, three thin film transistors (TFT1, TFT2 and TFT3) are usually set in each pixel unit, and a shared line (SCOM1, SCOM2) is introduced to divide the voltage of the sub-pixels. Figure 1 However, as the resolution of LCD display panels continues to increase, the size of pixel units is getting smaller and smaller, resulting in a smaller spacing between the sharing lines (SCOM1, SCOM2) and the data lines (DL1, DL2).

[0003] During the manufacturing process of LCD display panels, when using the A-Si process 4-mask process to produce thin-film transistor array substrates, the semiconductor layer is typically dry-etched twice. The first dry etch is performed on the non-channel area of ​​the semiconductor layer. During this first dry etch, the high-power ionization of the gas to form a plasma can cause a large amount of static electricity to accumulate in the thin-film transistor array substrate.

[0004] However, during the first dry etching process, the accumulated static electricity is easily released between the data lines (DL1, DL2) and the shared lines (SCOM1, SCOM2) in the thin film transistor array substrate, causing electrostatic breakdown. Figure 2 As shown, the shared lines (SCOM1, SCOM2) or the data lines (DL1, DL2) are disconnected, thereby reducing the product yield. Summary of the Invention

[0005] An object of the embodiments of the present application is to provide a display device to reduce the risk of electrostatic breakdown during the first dry etching process and improve product yield.

[0006] An embodiment of the present application provides a display device, which includes a display panel, the display panel including a display area and a non-display area, the display panel also including: a substrate; a first metal layer arranged on the substrate, the first metal layer including a plurality of common lines and two first connecting lines, the length direction of the common lines being parallel to a first direction, the plurality of common lines being arranged along a second direction, the first direction being perpendicular to the second direction, the two first connecting lines being respectively arranged in the non-display area on opposite sides of the display panel in the first direction, the length direction of the first connecting lines being parallel to the second direction, and the ends of the plurality of common lines being electrically connected to the two first connecting lines, respectively; a gate insulating layer arranged on the first metal layer and the substrate; a semiconductor layer arranged on the gate insulating layer; and a second metal layer arranged on the gate insulating layer, the second metal layer including a plurality of shared lines and a second connecting line, the length direction of the shared lines being parallel to the second direction, the plurality of shared lines being arranged along the first direction, the second connecting line being arranged in the non-display area of ​​the display panel in the second direction, and one end of the plurality of shared lines being electrically connected to the second connecting line.

[0007] In the above-mentioned display device, the first metal layer also includes a third connecting line, which is arranged in the non-display area of ​​the display panel opposite to the second connecting line in the second direction. The length direction of the third connecting line is parallel to the first direction, and the third connecting line is electrically connected to the shared line through a first through hole penetrating the gate insulation layer.

[0008] In the above display device, a plurality of the first through holes are arranged at intervals along the first direction.

[0009] In the above display device, the width of the third connecting line is greater than the width of the sharing line.

[0010] In the above display device, the width of the first connection line is greater than the width of the common line; and the width of the second connection line is greater than the width of the shared line.

[0011] In the above display device, the first metal layer further includes a lead line, and the lead line is provided in the non-display area; the first connecting line is electrically connected to the lead line.

[0012] An embodiment of the present application further provides a display device, comprising a display panel, the display panel comprising a display area and a non-display area, the display panel further comprising: a substrate; a first metal layer disposed on the substrate, the first metal layer comprising a plurality of common lines and two fourth connecting lines, wherein the length directions of the common lines are parallel to a first direction, the plurality of common lines are arranged along a second direction, the first direction being perpendicular to the second direction, the two fourth connecting lines being respectively disposed in the non-display area on opposite sides of the display panel in the second direction, the length directions of the fourth connecting lines being parallel to the first direction; and a gate insulating layer disposed on the first metal layer and the substrate; A semiconductor layer arranged on the gate insulating layer; and a second metal layer arranged on the gate insulating layer, the second metal layer including a plurality of shared lines and two fifth connecting lines, the length direction of the shared lines being parallel to the second direction, the plurality of shared lines being arranged along the first direction, the plurality of shared lines being electrically connected to the fourth connecting lines via second through holes penetrating the gate insulating layer, the two fifth connecting lines being respectively arranged in the non-display areas on opposite sides of the display panel in the first direction, the length direction of the fifth connecting lines being parallel to the second direction; wherein the plurality of common lines are electrically connected to the fifth connecting lines via third through holes penetrating the gate insulating layer.

[0013] In the above display device, the width of the fourth connection line is greater than the width of the shared line; and the width of the fifth connection line is greater than the width of the common line.

[0014] In the above display device, a plurality of the second through holes are arranged at intervals along the first direction; and a plurality of the third through holes are arranged at intervals along the second direction.

[0015] In the above display device, the first metal layer further includes a lead line, and the lead line is arranged in the non-display area; the fifth connection line is electrically connected to the lead line through a fourth through hole penetrating the gate insulating layer.

[0016] The display device provided in the embodiment of the present application effectively reduces the risk of electrostatic breakdown of the display device during the first dry etching process through two different wiring design schemes. Specifically, in the first wiring design, the common line of the first metal layer is electrically connected on both sides in the first direction through two first connecting lines, and the shared line of the second metal layer is electrically connected on one side in the second direction through a second connecting line. The common line and the shared line are respectively formed into a grid structure. During the first dry etching process, even if a large amount of static electricity is accumulated in the common line network of the first metal layer, the shared line of the second metal layer also forms a grid structure, and after the first dry etching and before the second wet etching, all the data lines of the display device and the shared line grid form a unified electrical network, so that no potential difference is generated between the data lines and the shared lines of different columns, thereby avoiding electrostatic breakdown. In the second wiring design, the common line of the first metal layer is electrically connected to the fifth connecting line of the second metal layer through the third through hole, and the shared line of the second metal layer is electrically connected to the fourth connecting line of the first metal layer through the second through hole. During the first dry etching process, the common and shared lines remain single. Because the amount of static electricity generated by a single common line coupled to a single shared line via capacitance is small, the potential difference between the shared line and the adjacent data line is small, thus preventing electrostatic breakdown. Through the above-described technical solution, the display device of the present application can effectively solve the problem of shared or data line disconnection caused by electrostatic breakdown in the prior art, significantly improving product yield. The technical solution of the present application is suitable for high-resolution display devices with a small spacing between the shared and data lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of a pixel unit of a traditional LCD display panel.

[0018] Figure 2 yes Figure 1 The diagram shows a schematic diagram of an electrostatic breakdown phenomenon occurring in a pixel unit of an LCD display panel.

[0019] Figure 3 is a block diagram of a display device provided in an embodiment of the present application.

[0020] Figure 4 2 is a schematic diagram of a display device provided in the first embodiment of the present application.

[0021] Figure 5 2 is a schematic diagram of a display device provided in accordance with a second embodiment of the present application.

[0022] Figure 6 This is a cross-sectional view of the thin film transistor array substrate of the display device provided by an embodiment of the present application after the first dry etching is completed. DETAILED DESCRIPTION

[0023] The specific implementation methods of this application are described in detail below with reference to the accompanying drawings.

[0024] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise expressly limited.

[0025] The embodiments of the present application may be combined with each other.

[0026] The manufacturing of thin-film transistor array substrates for liquid crystal display panels typically uses an amorphous silicon four-mask process, which requires two dry etching steps. The first dry etching step etches the semiconductor layer (A-Si) in the non-channel region of the thin-film transistor array substrate. During this first dry etching process, high-power ionization of the gas to form a plasma causes a significant amount of static electricity to accumulate in the thin-film transistor array substrate.

[0027] like Figure 1 As shown in the figure, to improve the viewing angle characteristics of the LCD panel, three thin-film transistors (TFT1, TFT2, and TFT3) are set in each pixel unit, and a shared line SCOM is introduced to divide the voltage of the sub-pixels. However, as the resolution of LCD panels continues to increase, the size of the pixel unit is getting smaller and smaller, and the distance between the shared line SCOM and the data line is also getting smaller and smaller.

[0028] However, during the first dry etching process, if the wiring design of the common line ACOM and the shared line SCOM is improper, the accumulated static electricity is easily released between the data line and the shared line SCOM, causing electrostatic breakdown, such as Figure 2 As shown, the shared line SCOM or the data line is disconnected, thereby reducing the product yield. Specifically, when the first dry etching is completed, since the channel area of ​​the thin film transistors (TFT1, TFT2 and TFT3) is still covered by the photoresist PR, each data line and the source, drain and shared line SCOM of the thin film transistor of the corresponding pixel (all belonging to the second metal layer M2) are connected together to form a column unit, as shown in FIG. Figure 2 As shown. At this time, the common line ACOM of the first metal layer M1 will accumulate a large amount of static electricity, and couple the static electricity to the column unit of the second metal layer M2 through capacitive coupling. Since the through-hole layer has not yet been made, the shared line SCOM has not formed a grid structure, resulting in the voltage of the data line of the first column of pixels being equal to the voltage of the shared line SCOM of the first column of pixels, but not equal to the voltage of the data line of the second column of pixels (equal to the voltage of the shared line SCOM of the second column of pixels). Since there may be a large potential difference between the shared line SCOM of the first column of pixels and the data line of the second column of pixels, electrostatic breakdown is likely to occur when the spacing between them is small.

[0029] In order to solve the above technical problems, this application proposes two solutions.

[0030] like Figure 4 and Figure 6 As shown, the first solution is: the common lines ACOM of the first metal layer M1 form a grid structure through two first connection lines CL1, and the shared lines SCOM of the second metal layer M2 form a grid structure through second connection lines CL2. Specifically, the first metal layer M1 includes multiple common lines ACOM and two first connection lines CL1. The common lines ACOM are arranged in the display area of ​​the display panel, and the length direction of the common lines ACOM is parallel to the first direction. The multiple common lines ACOM are arranged along the second direction. The first connection line CL1 is arranged in the non-display area of ​​the display panel on opposite sides of the first direction. The length direction of the first connection line CL1 is parallel to the second direction, and the two ends of the multiple common lines ACOM are electrically connected to the two first connection lines CL1. The second metal layer M2 includes multiple shared lines SCOM and one second connection line CL2. The length direction of the shared line SCOM is parallel to the second direction. The multiple shared lines SCOM are arranged along the first direction. The shared line SCOM is arranged in the display area of ​​the display panel, and one end of the shared line SCOM is electrically connected to the second connection line CL2. The second connection line CL2 is arranged in the non-display area of ​​the display panel in the second direction. The first metal layer M1 also includes a third connection line CL3, which is located in the non-display area of ​​the display panel opposite to the second connection line CL2 in the second direction. The length direction of the third connection line CL3 is parallel to the first direction. The third connection line CL3 is electrically connected to the shared line SCOM through a first through hole VH1 that penetrates the gate insulation layer GI.

[0031] The beneficial effect of the first solution is: although the first dry etching process will cause the grid-shaped common line ACOM of the first metal layer M1 to accumulate a large amount of static electricity, since the shared line SCOM of the second metal layer M2 also forms a grid structure, after the first dry etching and before the second wet etching, since the channel area of ​​the thin film transistor (TFT1, TFT2 and TFT3) is still covered by the photoresist PR, the source and drain of the thin film transistor (TFT1, TFT2 and TFT3) are directly connected. Therefore, all data lines form a unified electrical network through the grid-shaped shared line SCOM, and no potential difference will be generated between the data lines of different columns and the shared line SCOM, thereby avoiding electrostatic breakdown.

[0032] like Figure 5As shown, the second solution is: the common lines ACOM of the first metal layer M1 and the shared lines SCOM of the second metal layer M2 are both set to a single-line structure, and then a grid structure is formed by connecting lines located in different layers. Specifically, the first metal layer M1 includes multiple common lines ACOM and two fourth connecting lines CL4. The common lines ACOM are set in the display area of ​​the display panel, and the length direction of the common lines ACOM is parallel to the first direction. The multiple common lines ACOM are arranged along the second direction. The two fourth connecting lines CL4 are respectively set in the non-display area on the two opposite sides of the display panel in the second direction, and the length direction of the fourth connecting lines CL4 is parallel to the first direction. The second metal layer M2 includes multiple shared lines SCOM and two fifth connecting lines CL5. The shared lines SCOM are set in the display area of ​​the display panel, and the length direction of the shared lines SCOM is parallel to the second direction. The multiple shared lines SCOM are arranged along the first direction. The two fifth connecting lines CL5 are respectively set in the non-display area on the two opposite sides of the display panel in the first direction, and the length direction of the fifth connecting lines CL5 is parallel to the second direction. The common lines ACOM are electrically connected to the fifth connection line CL5 through the third through-holes VH3 penetrating the gate insulating layer GI, and the share lines SCOM are electrically connected to the fourth connection line CL4 through the second through-holes VH2 penetrating the gate insulating layer GI.

[0033] The beneficial effect of the second solution is: during the first dry etching process, since the common line ACOM of the first metal layer M1 and the shared line SCOM of the second metal layer M2 are both single-line structures, the amount of static electricity from the single common line ACOM coupled to the single shared line SCOM through capacitance is small, so the potential difference between the shared line SCOM and the adjacent data line is small, and electrostatic breakdown is less likely to occur.

[0034] Through the above two solutions, the present application can effectively reduce the risk of electrostatic breakdown of display panels during the manufacturing process and improve product yield.

[0035] like Figure 3 As shown, the display device provided in the embodiment of the present application includes a display panel, a timing controller TCON, a source driver circuit DD, and a power management chip (not shown in the figure, the power management chip can be integrated into the same chip with the timing controller TCON). The display panel can be, for example, a liquid crystal display panel.

[0036] The display panel includes a display area and a non-display area. The display area is provided with m×n pixel units P arranged in an array, where m and n are integers greater than 1. The non-display area is located around the display area and is used to arrange drive circuits and various signal lines. The display panel also includes a plurality of scan lines (GL1 to GLn), a plurality of data lines (DL1 to DLm), and a gate drive circuit GOA. The plurality of scan lines (GL1 to GLn) extend along a first direction and are arranged along a second direction, and the plurality of data lines (DL1 to DLm) extend along a second direction and are arranged along the first direction, with the first direction being perpendicular to the second direction. The gate drive circuit GOA is provided in the non-display area and is electrically connected to the plurality of scan lines (GL1 to GLn). The source drive circuit DD is electrically connected to the plurality of data lines (DL1 to DLm) via a flexible printed circuit board. The timing controller TCON is electrically connected to the gate drive circuit GOA and the source drive circuit DD, respectively.

[0037] The display panel includes a thin-film transistor array substrate, an opposing substrate, and a liquid crystal layer disposed between the two substrates. The thin-film transistor array substrate includes a glass substrate, a first metal layer M1 disposed on the glass substrate, a gate insulating layer GI disposed on the first metal layer M1, a semiconductor layer A-Si disposed on the gate insulating layer GI, a second metal layer M2 disposed on the semiconductor layer A-Si, a passivation layer disposed on the second metal layer M2, and a pixel electrode disposed on the passivation layer. The first metal layer M1 includes scan lines (GL1 to GLn) and a gate electrode. The second metal layer M2 includes data lines (DL1 to DLm), a source electrode, a drain electrode, and the like. The opposing substrate includes a glass substrate, a black matrix disposed on the glass substrate, a color filter layer disposed on the black matrix, and a common electrode disposed on the color filter layer.

[0038] Each pixel unit P includes at least one thin-film transistor (TFT) and a pixel electrode. The gate of the TFT is electrically connected to the corresponding scan line, the source is electrically connected to the corresponding data line, and the drain is electrically connected to the corresponding pixel electrode. When the scan line outputs a high-level scan signal, the TFT turns on, and the data signal on the data line is transmitted to the pixel electrode through the TFT. When the scan line outputs a low-level scan signal, the TFT turns off, and the pixel electrode maintains the voltage corresponding to the data signal.

[0039] The gate drive circuit GOA includes n cascaded gate drive units, each of which is electrically connected to a scan line. Under the control of the timing controller TCON, the gate drive units sequentially output scan signals, scanning each row of pixel units in the display area line by line. Under the control of the timing controller TCON, the source drive circuit DD generates and outputs data signals based on image data. The timing controller TCON is used to receive and process externally input image data and timing signals, generate control signals, and transmit image data to the source drive circuit DD. The power management chip is used to provide operating voltages for various parts of the liquid crystal display device, including providing common voltages for the common electrodes, gate drive voltages for the gate drive circuit GOA, and gamma voltages for the source drive circuit DD.

[0040] like Figure 4 As shown, the first embodiment of the present application provides a display device, which includes a display panel, the display panel includes a display area and a non-display area, and the display panel also includes a thin film transistor array substrate, an opposing substrate and a liquid crystal layer arranged between the thin film transistor array substrate and the opposing substrate.

[0041] The thin film transistor array substrate includes a substrate SBT, a first metal layer M1 arranged on the substrate SBT, a gate insulating layer GI arranged on the first metal layer M1 and the substrate SBT, a semiconductor layer A-Si arranged on the gate insulating layer GI, and a second metal layer M2 arranged on the gate insulating layer GI.

[0042] The first metal layer M1 includes multiple common lines ACOM and two first connecting lines CL1. The length direction of the common lines ACOM is parallel to the first direction. The multiple common lines ACOM are arranged along the second direction. The first direction is perpendicular to the second direction. The two first connecting lines CL1 are respectively arranged in the non-display area on both sides of the display panel opposite to each other in the first direction. The length direction of the first connecting line CL1 is parallel to the second direction. The two ends of the multiple common lines ACOM are respectively electrically connected to the two first connecting lines CL1.

[0043] The second metal layer M2 includes multiple sharing lines SCOM and a second connecting line CL2. The length direction of the sharing line SCOM is parallel to the second direction. The multiple sharing lines SCOM are arranged along the first direction. The second connecting line CL2 is set in the non-display area of ​​the display panel in the second direction. The length direction of the second connecting line CL2 is parallel to the first direction. One end of the multiple sharing lines SCOM is electrically connected to the second connecting line CL2.

[0044] The first metal layer M1 further includes a plurality of gate lines, and the length directions of the gate lines are parallel to the first direction.

[0045] The second metal layer M2 further includes a plurality of data lines, the length direction of the data lines is parallel to the second direction, and there is a preset distance between the data lines and adjacent shared lines SCOM, and the preset distance is less than 10 microns.

[0046] In this embodiment, the substrate SBT is a glass substrate or a quartz substrate. The first metal layer M1 is a single metal layer or a multilayer metal layer. The gate insulating layer GI can be made of an insulating material such as silicon nitride, silicon oxide, or aluminum oxide. The semiconductor layer A-Si can be made of amorphous silicon. The second metal layer M2 is made of the same material as the first metal layer M1.

[0047] The counter substrate is provided with a black matrix and a color filter layer. The black matrix blocks light in non-display areas and is made of chromium or resin. The color filter layer includes red, green, and blue filter units, enabling color display. A common electrode made of a transparent conductive material is also provided on the counter substrate.

[0048] The display panel also includes multiple pixel units, each of which includes a primary pixel electrode, a secondary pixel electrode, a first thin-film transistor (TFT1), a second thin-film transistor (TFT2), and a third thin-film transistor (TFT3). The gates of the first, second, and third thin-film transistors (TFT1, TFT2, and TFT3) are electrically connected to a gate line, the source of the first and second thin-film transistors (TFT1 and TFT2) are electrically connected to a data line, the drain of the first and second thin-film transistors (TFT1 and TFT2) are electrically connected to the primary pixel electrode and the secondary pixel electrode, respectively. The drain of the second thin-film transistor (TFT2) is also electrically connected to the source of the third thin-film transistor (TFT3), and the drain of the third thin-film transistor (TFT3) is electrically connected to a common line (SCOM). The primary and sub-pixel electrodes are made of a transparent conductive material, such as indium tin oxide. The primary and sub-pixel electrodes are electrically connected to the drains of the corresponding thin-film transistors through vias in a passivation layer. The passivation layer can be made of either an organic or inorganic material.

[0049] The semiconductor layer A-Si includes a non-channel portion and a channel portion, and the channel portion connects the source and drain electrodes of the first thin film transistor TFT1 , the second thin film transistor TFT2 , and the third thin film transistor TFT3 .

[0050] The gate line is arranged in parallel with the common line ACOM, and the data line is arranged in parallel with the sharing line SCOM.

[0051] In the display area, gate lines and common lines ACOM are alternately arranged in the first direction, that is, a common line ACOM is arranged between every two adjacent gate lines. Data lines and shared lines SCOM are alternately arranged in the first direction, that is, a shared line SCOM is arranged between every two adjacent data lines.

[0052] The first connection line CL1 may have multiple connection portions in the connection area with the common line ACOM, and the width of each connection portion may be 1.5 to 2 times the width of the common line ACOM. The second connection line CL2 may also have multiple connection portions in the connection area with the shared line SCOM, and the width of each connection portion may be 1.5 to 2 times the width of the shared line SCOM.

[0053] In this embodiment, the edges of the first connection line CL1 and the second connection line CL2 may be configured to be serrated. The serrated edges are conducive to releasing stress and preventing the first connection line CL1 and the second connection line CL2 from cracking.

[0054] The first metal layer M1 also includes a third connection line CL3, which is arranged in a non-display area of ​​the display panel opposite to the second connection line CL2 in the second direction. The length direction of the third connection line CL3 is parallel to the first direction. The third connection line CL3 is electrically connected to the shared line SCOM through a first through hole VH1 penetrating the gate insulation layer GI.

[0055] A plurality of first through holes VH1 are arranged at intervals along the first direction.

[0056] The width of the third connection line CL3 is greater than the width of the sharing line SCOM. For example, the width of the third connection line CL3 may be 1.2 to 2 times the width of the sharing line SCOM.

[0057] The width of the first connection line CL1 is greater than the width of the common line ACOM; the width of the second connection line CL2 is greater than the width of the shared line SCOM. Specifically, the width of the first connection line CL1 can be 1.2 to 2 times the width of the common line ACOM, and the width of the second connection line CL2 can be 1.2 to 2 times the width of the shared line SCOM. Increasing the width of the connection lines can improve their conductivity, facilitating the conduction and dispersion of static electricity.

[0058] The first metal layer M1 further includes a lead line LW, which is disposed in the non-display area and electrically connected to the first connection line CL1. The lead line LW is used to provide a common voltage of the power management chip to the common line ACOM.

[0059] In this embodiment, the lead line LW may include multiple parallel sub-lead lines LW, each of which may be 1.5 to 3 times wider than the common line ACOM. By providing multiple parallel sub-lead lines LW, the resistance of the lead line LW can be reduced, improving the stability of the power supply.

[0060] The lead wire LW gradually widens as it extends outward from the end connected to the first connection wire CL1. For example, the width of the lead wire LW at the connection point with the first connection wire CL1 can be 1 to 1.2 times the width of the first connection wire CL1, and the width of the lead wire LW at the outer end can be 2 to 3 times the width of the first connection wire CL1. This gradual width design helps reduce stress concentration.

[0061] In this embodiment, the third connection line CL3 includes multiple fold line segments, with the angles between adjacent fold line segments being obtuse. This reduces stress concentration at the corners of the third connection line CL3. The fold line structure of the third connection line CL3 allows for a longer routing distance within the limited non-display area. During use of the display panel, the substrate SBT may undergo thermal expansion or contraction due to changes in ambient temperature, causing the third connection line CL3 to experience tensile or compressive stress. The third connection line CL3, with its fold line structure, can buffer these stresses through deformation between the fold line segments, preventing stress concentration from causing breakage in the third connection line CL3.

[0062] The first through holes VH1 are arranged in a staggered pattern, with adjacent rows of through holes interlaced in the first direction. Alternatively, they are arranged in groups, with multiple small through holes positioned at each intersection of the third connection line CL3 and the shared line SCOM. These small through holes are then grouped together to form a through hole. Because the intersections of the third connection line CL3 and the shared line SCOM require high current transmission, a large through hole structure composed of multiple small through holes can increase the conductive cross-sectional area and reduce contact resistance.

[0063] The outline of each through hole is set to be octagonal to reduce stress concentration at the edge of the through hole. The sidewall of the through hole is inclined, which helps to increase the coverage of the metal layer in the through hole.

[0064] The third connection line CL3 has a structural reinforcement at the location corresponding to the through-hole. This reinforcement is wider than the rest of the third connection line CL3. The reinforcement is annularly arranged around the through-hole, with an arc-shaped outer edge. This design enhances the mechanical strength of the through-hole, improves the reliability of the electrical connection, and prevents stress concentration.

[0065] Through the above-described technical solution, the display device of this embodiment can effectively reduce the risk of electrostatic breakdown during the first dry etching process. Specifically, because the common lines ACOM of the first metal layer M1 form a grid structure via two first connecting lines CL1, and the shared lines SCOM of the second metal layer M2 form a grid structure via second connecting lines CL2, after the first dry etching and before the second wet etching, all data lines form a unified electrical network via the grid-like shared lines SCOM. This prevents potential differences between data lines and shared lines SCOM in different columns, thereby preventing electrostatic breakdown.

[0066] like Figure 5 As shown, the second embodiment of the present application provides a display device. The second embodiment is similar to the first embodiment, except that:

[0067] The display device includes a display panel, which includes a display area and a non-display area. The display panel also includes a substrate SBT, a first metal layer M1 arranged on the substrate SBT, a gate insulating layer GI arranged on the first metal layer M1 and the substrate SBT, a semiconductor layer A-Si arranged on the gate insulating layer GI, and a second metal layer M2 arranged on the gate insulating layer GI.

[0068] The first metal layer M1 includes multiple common lines ACOM and two fourth connecting lines CL4. The length direction of the common lines ACOM is parallel to the first direction. The multiple common lines ACOM are arranged along the second direction. The first direction is perpendicular to the second direction. The two fourth connecting lines CL4 are respectively arranged in the non-display area on both sides of the display panel opposite to each other in the second direction. The length direction of the fourth connecting lines CL4 is parallel to the first direction.

[0069] The second metal layer M2 includes multiple sharing lines SCOM and two fifth connection lines CL5. The length direction of the sharing lines SCOM is parallel to the second direction. The multiple sharing lines SCOM are arranged along the first direction. The multiple sharing lines SCOM are electrically connected to the fourth connection line CL4 through the second through hole VH2 penetrating the gate insulation layer GI. The two fifth connection lines CL5 are respectively arranged in the non-display area on both sides of the display panel opposite to each other in the first direction. The length direction of the fifth connection line CL5 is parallel to the second direction.

[0070] The plurality of common lines ACOM are electrically connected to the fifth connection line CL5 through the third through hole VH3 penetrating the gate insulating layer GI.

[0071] The width of the fourth connection line CL4 is greater than the width of the sharing line SCOM; the width of the fifth connection line CL5 is greater than the width of the common line ACOM.

[0072] The plurality of second through holes VH2 are arranged at intervals along the first direction; and the plurality of third through holes VH3 are arranged at intervals along the second direction.

[0073] The first metal layer M1 further includes lead lines LW, and the lead lines LW are disposed in the non-display area.

[0074] The fifth connection line CL5 is electrically connected to the lead line LW through a fourth through hole penetrating the gate insulating layer GI.

[0075] In this embodiment, the fourth connecting line CL4 and the fifth connecting line CL5 include multiple fold line segments, and the angles between adjacent fold line segments are obtuse angles. This can reduce the stress concentration at the corners of the fourth connecting line CL4 and the fifth connecting line CL5. The fold line structure of the fourth connecting line CL4 and the fifth connecting line CL5 can provide a longer routing distance within the limited non-display area. During the use of the display panel, due to changes in ambient temperature, the substrate SBT will undergo thermal expansion or contraction, causing the fourth connecting line CL4 and the fifth connecting line CL5 to be subjected to tensile or compressive stress. The fourth connecting line CL4 and the fifth connecting line CL5 with a fold line structure can buffer these stresses through deformation between the fold line segments, thereby avoiding stress concentration that may cause the fourth connecting line CL4 and the fifth connecting line CL5 to break.

[0076] The first through holes VH1 are arranged in a staggered pattern, with adjacent rows of through holes interlaced in the first direction. Alternatively, they are arranged in groups, with multiple small through holes positioned at each intersection of the fourth and fifth connection lines CL4 and CL5 with the shared line SCOM. These small through holes are then grouped together to form a through hole. Because the intersections of the fourth and fifth connection lines CL4 and CL5 with the shared line SCOM require high current transmission, a large through hole structure composed of multiple small through holes can increase the conductive cross-sectional area and reduce contact resistance.

[0077] The outline of each through hole is set to be octagonal to reduce stress concentration at the edge of the through hole. The sidewall of the through hole is inclined, which helps to increase the coverage of the metal layer in the through hole.

[0078] The fourth and fifth connecting lines CL4 and CL5 are provided with structural reinforcements at locations corresponding to the through-holes. The width of these reinforcements is greater than the width of the remaining portions of the fourth and fifth connecting lines CL4 and CL5. The reinforcements are arranged in a circular shape around the through-holes, with their outer edges being arc-shaped. This design enhances the mechanical strength of the through-holes, improves the reliability of the electrical connection, and prevents stress concentration.

[0079] Through the above technical solution, the display device of this embodiment can effectively reduce the risk of electrostatic breakdown during the first dry etching process. Specifically, during the first dry etching process, since the common line ACOM of the first metal layer M1 and the shared line SCOM of the second metal layer M2 are both single-line structures, the amount of static electricity of the single common line ACOM coupled to the single shared line SCOM through capacitance is small, so the potential difference between the shared line SCOM and the adjacent data line is small, and electrostatic breakdown is not easy to occur. After the first dry etching is completed, the common line ACOM is electrically connected to the fifth connection line CL5 through the third through hole VH3 to form a grid structure, and the shared line SCOM is electrically connected to the fourth connection line CL4 through the second through hole VH2 to form a grid structure. This subsequently formed grid structure will not affect the electrostatic protection effect during the first dry etching process.

[0080] The display panel provided in this application is manufactured through the following steps.

[0081] A thin film transistor array substrate and an opposing substrate are formed.

[0082] A liquid crystal layer is provided on the thin film transistor array substrate.

[0083] An opposite substrate is provided on the thin film transistor array substrate.

[0084] The steps of forming a thin film transistor array substrate include:

[0085] A first metal thin film is deposited on the substrate SBT.

[0086] The first metal film is etched to form a plurality of gate lines and a common line ACOM (first metal layer M1). In the first embodiment of the present application, two first connecting lines CL1 are also formed in the first metal layer M1. In the second embodiment of the present application, two fourth connecting lines CL4 are also formed in the first metal layer M1.

[0087] The steps of etching the first metal film to form a plurality of gate lines and a common line ACOM include: coating the first metal film with a photoresist; exposing and developing the photoresist to form a mask including a pattern of the common lines ACOM, the first connection lines CL1, and the gate lines; etching the first metal film using a wet etching method; and removing the photoresist to obtain a first metal layer M1. The material of the first metal layer M1 can be chromium, molybdenum, aluminum, or alloys thereof.

[0088] A gate insulating layer GI is formed on the first metal layer M1 and the substrate SBT.

[0089] A semiconductor layer A-Si is formed on the gate insulating layer GI.

[0090] A second metal thin film is deposited on the semiconductor layer A-Si and the gate insulating layer GI.

[0091] The second metal film is wet-etched for the first time to form a plurality of electrically connected data lines and shared lines SCOM, wherein the step of wet-etching the second metal film for the first time to form a plurality of electrically connected data lines and shared lines SCOM includes: coating a photoresist PR on the second metal film; exposing and developing the photoresist PR to form a mask including the shared lines SCOM, the second connecting lines CL2, and the data line pattern; and etching the second metal film using a wet etching method. After the first wet etching, the second metal film exposes the non-channel region of the semiconductor layer A-Si. At this time, the source and drain electrodes of the three thin film transistors (the first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3) are not separated, that is, the data lines and shared lines SCOM are integrated. In the first embodiment of the present application, the second metal film also includes a second connecting line CL2. In the second embodiment of the present application, the second metal film also includes two fifth connecting lines CL5.

[0092] The non-channel region of the semiconductor layer A-Si is first dry-etched.

[0093] The second metal film is wet-etched a second time to remove the photoresist PR, forming the data line and the shared line SCOM (the second metal layer M2). At this point, the source and drain electrodes of the three thin-film transistors (the first thin-film transistor TFT1, the second thin-film transistor TFT2, and the third thin-film transistor TFT3) are separated, that is, the data line and the shared line SCOM (the second metal layer M2) are formed. The material of the second metal layer M2 can be chromium, molybdenum, aluminum, or alloys thereof.

[0094] The channel region of the semiconductor layer A-Si is dry-etched for the second time.

[0095] The above is a detailed introduction to the embodiments of the present application. The contents of this specification should not be understood as limiting the scope of protection of the present application.

Claims

1. A display device, characterized in that: The display device includes a display panel, the display panel includes a display area and a non-display area, and the display panel further includes: substrate; a first metal layer disposed on a substrate, the first metal layer comprising a plurality of common lines and two first connecting lines, wherein the length direction of the common lines is parallel to the first direction, the plurality of common lines are arranged along a second direction, the first direction being perpendicular to the second direction, the two first connecting lines being respectively disposed in the non-display area on opposite sides of the display panel in the first direction, the length direction of the first connecting lines being parallel to the second direction, and two ends of the plurality of common lines being electrically connected to the two first connecting lines respectively; a gate insulating layer disposed on the first metal layer and the substrate; A semiconductor layer disposed on the gate insulating layer; and A second metal layer is arranged on the gate insulating layer, the second metal layer includes multiple shared lines and a second connecting line, the length direction of the shared lines is parallel to the second direction, the multiple shared lines are arranged along the first direction, the second connecting line is arranged in the non-display area of ​​the display panel in the second direction, and one end of the multiple shared lines is electrically connected to the second connecting line.

2. The display device according to claim 1, wherein The first metal layer also includes a third connecting line, which is arranged in the non-display area of ​​the display panel opposite to the second connecting line in the second direction. The length direction of the third connecting line is parallel to the first direction, and the third connecting line is electrically connected to the shared line through a first through hole penetrating the gate insulation layer.

3. The display device according to claim 2, wherein: A plurality of first through holes are arranged at intervals along the first direction.

4. The display device according to claim 2, wherein: The width of the third connection line is greater than the width of the sharing line.

5. The display device according to claim 1, wherein The width of the first connecting line is greater than the width of the common line; The width of the second connection line is greater than the width of the sharing line.

6. The display device according to claim 1, wherein The first metal layer further includes a lead line, and the lead line is arranged in the non-display area; The first connecting wire is electrically connected to the lead wire.

7. A display device, characterized in that: The display device includes a display panel, the display panel includes a display area and a non-display area, and the display panel further includes: substrate; a first metal layer disposed on the substrate, the first metal layer comprising a plurality of common lines and two fourth connecting lines, wherein the length directions of the common lines are parallel to the first direction, the plurality of common lines are arranged along a second direction, the first direction being perpendicular to the second direction, the two fourth connecting lines being respectively disposed in the non-display area on opposite sides of the display panel in the second direction, and the length directions of the fourth connecting lines being parallel to the first direction; a gate insulating layer disposed on the first metal layer and the substrate; A semiconductor layer disposed on the gate insulating layer; and a second metal layer disposed on the gate insulating layer, the second metal layer comprising a plurality of shared lines and two fifth connecting lines, wherein the length directions of the shared lines are parallel to the second direction, the plurality of shared lines are arranged along the first direction, the plurality of shared lines are electrically connected to the fourth connecting lines via second through holes penetrating the gate insulating layer, the two fifth connecting lines are respectively disposed in the non-display area on two opposite sides of the display panel in the first direction, and the length directions of the fifth connecting lines are parallel to the second direction; The plurality of common lines are electrically connected to the fifth connection line through a third through hole penetrating the gate insulating layer.

8. The display device according to claim 7, wherein: The width of the fourth connecting line is greater than the width of the sharing line; The width of the fifth connection line is greater than that of the common line.

9. The display device according to claim 7, wherein: A plurality of the second through holes are spaced apart along the first direction; The plurality of third through holes are spaced apart along the second direction.

10. The display device according to claim 7, wherein: The first metal layer further includes a lead line, and the lead line is arranged in the non-display area; The fifth connecting line is electrically connected to the lead line through a fourth through hole penetrating the gate insulating layer.

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