Data transmission method and device, computing equipment and storage medium

By obtaining the shared memory address of the target device in the computing device and directly transmitting data with the shared memory using the PCIe bus, the problem of low data transmission efficiency among devices in the prior art is solved, and efficient data transmission is achieved.

CN119645919AActive Publication Date: 2025-03-18ZHEJIANG LAB
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Patent Information

Application Number
CN202510169425.3
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-02-17
Publication Date
2025-03-18
Estimated Expiration
2045-02-17

AI Technical Summary

Technical Problem

In the prior art, data transmission between devices is inefficient, especially in the asynchronous memory copying process between GMEM and SMEM, data needs to be transmitted through GMEM, resulting in low transmission efficiency.

Method used

By obtaining the shared memory address of the target device in the computing device, and using the PCIe bus to directly transmit data with the shared memory, skip GMEM transit and directly access SMEM.

Benefits of technology

The data transmission process is simplified, the data transmission efficiency is improved, the access speed of GMEM is avoided, and data transmission is directly used to utilize the high access speed of SMEM.

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Abstract

The invention discloses a data transmission method and device, computing equipment and a storage medium, and relates to the technical field of computers.The method comprises the steps that the computing equipment obtains a shared memory address of target equipment from the storage medium in response to a received data transmission request from the target equipment, the shared memory address refers to a unique address of a shared memory in the target equipment; wherein the shared memory and the global memory in the target device both adopt a unified addressing technology, so that the shared memory is directly connected to the PCIe bus through the shared memory address. And the computing device initiates a data transmission operation to the shared memory address through the PCIe bus. In this manner, the GMEM and the SMEM use a unified address space, and the address of the SMEM is exposed to the outside. It means that both the CPU and the RDMA controller can access the two types of memories through a single address space. The technical problem of low data transmission efficiency in the prior art is solved.
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