Time sequence optimization method and device, electronic equipment and storage medium

Abstract

The invention provides a time sequence optimization method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining the logic stage number of each module of a time sequence circuit through which a time sequence path passes according to a gate-level netlist of the time sequence circuit, determining the logic proportion of each module according to the logic stage number of each module and a preset logic stage number, according to the logic proportion of each module, determining a key module from each module, and determining a logic segment where the key module is located as a key logic segment from the time sequence path, the logic segment where the key module is located being a logic segment between logic input and logic output of the key module on the time sequence path, and performing time sequence optimization according to the logic code of the key logic section. According to the method, the critical path logic section is determined based on the logic series and time sequence optimization is performed, so that the purpose of time sequence convergence can be accurately and quickly achieved.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a timing optimization method, device, electronic device and storage medium. Background Art

[0002] In the logic design of the chip, due to the increase in functions, the number of transistors contained in the chip even reaches the order of one billion. Among them, the chip of this order of magnitude is divided into multiple modules in the physical implementation process for logic code design and physical implementation design respectively.

[0003] In the related art, at the front-end logic design stage, logic levels are usually reserved for the path between one or more modules. For example, the data path of module A passes through modules B and C and is sent to module D. The logic design of module A reserves 10 levels of logic, the logic design of module B reserves 5 levels of logic, the logic design of module C reserves 3 levels, and the logic design of module D reserves 8 levels.

[0004] However, the reservation of logic design is difficult to meet the timing check target in the physical design stage, resulting in a deviation between the front-end reservation and the actual physical implementation, and difficulty in path timing convergence. Summary of the invention

[0005] In view of this, embodiments of the present application provide a timing optimization method, device, electronic device and storage medium to determine key logic segments based on logic levels and perform timing optimization, thereby achieving the purpose of timing convergence accurately and quickly.

[0006] In a first aspect, an embodiment of the present application provides a timing optimization method, comprising:

[0007] According to the gate-level netlist of the sequential circuit, obtaining the logic level of each module of the sequential circuit through which the sequential path passes;

[0008] Determining the logic proportion of each module according to the logic level of each module and the preset logic level;

[0009] According to the logic proportion of each module, a key module is determined from each module, and a logic segment where the key module is located is determined from the timing path as a key logic segment, where the logic segment where the key module is located is a logic segment between a logic input and a logic output of the key module on the timing path;

[0010] Timing optimization is performed according to the logic code of the key logic segment.

[0011] In an optional implementation manner, determining the key module from the modules according to the logic proportion of the modules includes:

[0012] Determining a critical path from the timing path according to the logic proportion of each module;

[0013] The key module is determined from the modules on the critical path according to the logic proportion of the modules on the critical path.

[0014] In an optional implementation, the performing timing optimization according to the logic code of the key logic segment includes:

[0015] Deleting the logic code of the key logic segment from the logic code of the sequential circuit; or,

[0016] In the logic code of the sequential circuit, adjusting the logic code of the key logic segment to a previous stage or a later stage; or,

[0017] In the logic code of the key logic segment, splitting and / or combining the logic units on the key logic segment; or,

[0018] In the logic code of the critical logic segment, adjusting the input transition time and / or output load of the critical logic segment; or,

[0019] In the logic code of the critical logic segment, the delay constraint of the critical logic segment is adjusted.

[0020] In an optional implementation, the performing timing optimization according to the logic code of the key logic segment includes:

[0021] If the key module is in the first implementation mode, then in the logic code of the key logic segment, at least one of the weight value, the routing resources, and the layout position of the key logic segment is adjusted.

[0022] In an optional implementation, the performing timing optimization according to the logic code of the key logic segment includes:

[0023] If the key module is in the second implementation mode, the target output delay of the key module is determined according to the logic proportion of other modules on the timing path except the key module; and / or, according to the internal delay of the key module and the preset delay of the timing circuit, the delay margin of the other modules is calculated, and the target output delay of the key module is determined according to the delay margin;

[0024] According to the target output delay, the output delay of the key module is adjusted in the logic code of the key logic section.

[0025] In an optional implementation, after performing timing optimization according to the logic code of the key logic segment, the method further includes:

[0026] Running the logic code of the key logic segment after the timing optimization to obtain the timing optimization result of the key logic segment;

[0027] If the timing optimization result of the key logic segment does not meet the preset timing requirement, after the physical layout of the timing circuit is completed, the target delay and the actual delay of the key module are obtained;

[0028] If the actual delay exceeds the target delay, determining the key module as a target optimization object;

[0029] Timing optimization is performed according to the physical design of the target optimization object.

[0030] In an optional implementation manner, obtaining the target delay and the actual delay of the key module includes:

[0031] Determine the logic ratio of the key module as the target delay;

[0032] Static timing analysis is performed on the key modules to obtain the actual delay.

[0033] In an optional implementation, performing timing optimization according to the physical design of the target optimization object includes:

[0034] Obtaining the logical distance of each submodule in the target optimization object;

[0035] Determining a submodule to be optimized from among the submodules according to the logical distance;

[0036] The physical size and / or layout position of the submodule to be optimized is adjusted.

[0037] In an optional implementation, performing timing optimization according to the physical design of the target optimization object includes:

[0038] If the target submodule of the target optimization object is physically connected to the logic unit of the target module, the layout position of the target submodule is adjusted.

[0039] In an optional implementation, performing timing optimization according to the physical design of the target optimization object includes:

[0040] According to the positional relationship between the target submodule of the target optimization object and the logic unit of the target module, the layout position of the target submodule is adjusted.

[0041] In an optional implementation, before obtaining the logical distance of each submodule in the target optimization object, the method further includes:

[0042] According to the logical level of the target optimization object, the target optimization object is divided to generate the sub-modules.

[0043] In a second aspect, an embodiment of the present application further provides a timing optimization device, including:

[0044] An acquisition module, used for acquiring the logic levels of each module of the sequential circuit through which the sequential path passes according to the gate-level netlist of the sequential circuit;

[0045] A determination module, used to determine the logic proportion of each module according to the logic level of each module and the preset logic level;

[0046] The determination module is further configured to determine a key module from the modules according to the logic proportions of the modules, and determine the logic segment where the key module is located as the key logic segment from the timing path, wherein the logic segment where the key module is located is the logic segment between the logic input and the logic output of the key module on the timing path;

[0047] The optimization module is used to perform timing optimization according to the logic code of the key logic segment.

[0048] In an optional implementation manner, the determining module is specifically configured to:

[0049] Determining a critical path from the timing path according to the logic proportion of each module;

[0050] The key module is determined from the modules on the critical path according to the logic proportion of the modules on the critical path.

[0051] In an optional implementation, the optimization module is specifically used to:

[0052] Deleting the logic code of the key logic segment from the logic code of the sequential circuit; or,

[0053] In the logic code of the sequential circuit, adjusting the logic code of the key logic segment to a previous stage or a later stage; or,

[0054] In the logic code of the key logic segment, splitting and / or combining the logic units on the key logic segment; or,

[0055] In the logic code of the critical logic segment, adjusting the input transition time and / or output load of the critical logic segment; or,

[0056] In the logic code of the critical logic segment, the delay constraint of the critical logic segment is adjusted.

[0057] In an optional implementation, the optimization module is specifically used to:

[0058] If the key module is in the first implementation mode, then in the logic code of the key logic segment, at least one of the weight value, the routing resources, and the layout position of the key logic segment is adjusted.

[0059] In an optional implementation, the optimization module is specifically used to:

[0060] If the key module is in the second implementation mode, the target output delay of the key module is determined according to the logic proportion of other modules on the timing path except the key module; and / or, according to the internal delay of the key module and the preset delay of the timing circuit, the delay margin of the other modules is calculated, and the target output delay of the key module is determined according to the delay margin;

[0061] According to the target output delay, the output delay of the key module is adjusted in the logic code of the key logic section.

[0062] In an optional implementation manner, the acquisition module is further used to:

[0063] Running the logic code of the key logic segment after the timing optimization to obtain the timing optimization result of the key logic segment;

[0064] The acquisition module is further configured to acquire the target delay and actual delay of the key module after the physical layout of the sequential circuit is completed if the timing optimization result of the key logic segment does not meet the preset timing requirement;

[0065] The determination module is further configured to determine the key module as a target optimization object if the actual delay exceeds the target delay;

[0066] The optimization module is also used to perform timing optimization according to the physical design of the target optimization object.

[0067] In an optional implementation manner, the acquisition module is specifically used to:

[0068] Determine the logic ratio of the key module as the target delay;

[0069] Static timing analysis is performed on the key modules to obtain the actual delay.

[0070] In an optional implementation, the optimization module is specifically used to:

[0071] Obtaining the logical distance of each submodule in the target optimization object;

[0072] Determining a submodule to be optimized from among the submodules according to the logical distance;

[0073] The physical size and / or layout position of the submodule to be optimized is adjusted.

[0074] In an optional implementation, the optimization module is specifically used to:

[0075] If the target submodule of the target optimization object is physically connected to the logic unit of the target module, the layout position of the target submodule is adjusted.

[0076] In an optional implementation, the optimization module is specifically used to:

[0077] According to the positional relationship between the target submodule of the target optimization object and the logic unit of the target module, the layout position of the target submodule is adjusted.

[0078] In an optional embodiment, it also includes:

[0079] The division module is used to divide the target optimization object according to the logical level of the target optimization object to generate the sub-modules.

[0080] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the memory through the bus, and the processor executes the machine-readable instructions to execute any one of the methods described in the first aspect.

[0081] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method described in any one of the first aspects is executed.

[0082] The present application provides a timing optimization method, device, electronic device and storage medium, wherein the method includes: according to the gate-level netlist of the timing circuit, obtaining the logic level of each module of the timing circuit through which the timing path passes, determining the logic proportion of each module according to the logic level of each module and the preset logic level, determining the key module from each module according to the logic proportion of each module, and determining the logic segment where the key module is located from the timing path as the key logic segment, the logic segment where the key module is located is the logic segment between the logic input and the logic output of the key module on the timing path, and performing timing optimization according to the logic code of the key logic segment. The present application determines the critical path logic segment based on the logic level and performs timing optimization, which can accurately and quickly achieve the purpose of timing convergence. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0084] Figure 1 Schematic diagram of interface path zero logic;

[0085] Figure 2 Schematic diagram of the process of the timing optimization method provided in the embodiment of the present application Figure 1 ;

[0086] Figure 3 Schematic diagram of the process of the timing optimization method provided in the embodiment of the present application Figure 2 ;

[0087] Figure 4 Schematic diagram of the process of the timing optimization method provided in the embodiment of the present application Figure 3 ;

[0088] Figure 5 Schematic diagram of the process of the timing optimization method provided in the embodiment of the present application Figure 4 ;

[0089] Figure 6 Schematic diagram of the process of the timing optimization method provided in the embodiment of the present application Figure 5 ;

[0090] Figure 7 Schematic diagram of the submodules provided in the embodiment of the present application Figure 1 ;

[0091] Figure 8 Schematic diagram of the submodules provided in the embodiment of the present application Figure 2 ;

[0092] Fig. 9 A schematic diagram of the structure of a timing optimization device provided in an embodiment of the present application;

[0093] Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0094] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0095] With the development of chip technology, chips with different logic functions are used in various industries, which puts forward further requirements on the functions and performance of chips. In the logic design of the chip, due to the increase in functions, the number of transistors contained in the chip even reaches the order of one billion. Considering the project time cost and server resource cost, the chips of this order of magnitude are divided into multiple modules in the physical implementation process for logic code design and physical implementation design. In order to ensure the accuracy of chip functions between modules, it is necessary to formulate a timing convergence standard for request or response data links across multiple modules to ensure that the timing between modules meets the chip signoff target requirements.

[0096] When timing signals are transmitted across modules, the logic designers of independent modules are actually not clear about the signal transmission path outside the module. In order to improve performance, it is difficult for the logic of the interface to achieve stack in and out at high frequency and high speed (that is, the interface path cannot achieve zero logic). When two or more modules communicate with each other, there are multi-level accesses across modules. For such timing paths that span multiple modules and have multi-level accesses, how to standardize the feedback of the logic proportion of each module and whether the total proportion exceeds the requirements needs to be refined and quantified.

[0097] The zero logic of the interface path refers to the timing path between the module port and the module, which does not pass through the logic unit, but directly connects the logic input to the internal register, or connects the internal register to the module logic output. The connection line can contain buffer units (not logic units), but does not contain logic units with operation functions. Common logic units include AND gates, OR gates, selectors, etc. Figure 1 Schematic diagram of interface path zero logic, such as Figure 1As shown, the logic input of the internal register is in (Port_in), Port_in is connected to the internal register a through two buffer units, and is connected to the logic output out (Port_out) from the internal register a through two buffer units, where D is the input port of a, Q is the output port of a, CP is the clock signal input terminal, and CLK is the clock signal.

[0098] In the related art, in the front-end logic design stage, interfaces are reserved for one or more modules. The reserved interfaces refer to the reserved logic levels on the path between one or more modules. However, the reservation of the logic design is difficult to meet the timing check target in the physical design stage, resulting in a deviation between the front-end reservation and the actual physical implementation, and difficulty in path timing convergence. For example, for the data path from module A to module D through modules B and C, the logic design of module A reserves 10 levels of logic, the logic design of module B reserves 5 levels of logic, the logic design of module C reserves 3 levels, and the logic design of module D reserves 8 levels. Assuming that the recommended number of logic levels in a stack is 22 under a specific process, the reservation of the logic design (the total number of logic levels is 26) is difficult to meet the timing check target in the physical design stage, and the four modules A, B, C, and D need to jointly reduce the amount of logic (logic levels) to achieve the goal of timing convergence.

[0099] In addition, it is impossible to stack in and out conventional modules, and it is difficult to standardize the interface reservations for different modules. In addition, the back-end merging multi-level implementation process has the problem of too long cross-module paths, making it difficult to determine the effective optimization points of the paths. Merging multi-levels refers to merging hierarchical designs in physical designs, that is, merging multiple modules at the bottom for independent design (bottom-up).

[0100] Based on this, the present application provides a timing optimization method for an efficient customized integrated circuit across multiple modules, which determines the critical path logic segment based on the logic level and performs timing optimization, and can achieve the purpose of timing convergence accurately and quickly.

[0101] Figure 2 Schematic diagram of the process of the timing optimization method provided in the embodiment of the present application Figure 1 The execution subject of this embodiment may be an electronic device.

[0102] like Figure 2 As shown, the method may include:

[0103] S101 . Obtain the logic level of each module of the sequential circuit through which the sequential path passes according to the gate-level netlist of the sequential circuit.

[0104] The modules of the sequential circuit through which the sequential path passes are modules into which the chip constituting the sequential circuit is divided according to a preset division rule in order to facilitate logic code design and physical implementation design in physical implementation.

[0105] The sequential circuit can be an integrated circuit with long logic spanning multiple modules. The gate-level netlist is a netlist after logic synthesis. The gate-level netlist of the sequential circuit stores information about each module of the sequential circuit through which the sequential path passes. The information about each module of the sequential circuit is obtained from the gate-level netlist of the sequential circuit, and the logic level of each module is obtained based on the information of each module, wherein each level of logic unit through which the signal passes is counted as one level. The logic level of each module is the number of logic units through which the signal on the sequential path propagates from the logic input of each module to the logic output of each module. The sum of the logic levels of all modules is the total logic level of the sequential path. Among them, the logic unit can include, for example, an AND gate, an OR gate, and a selector, and the buffer unit does not belong to the logic unit.

[0106] For example, if the timing path passes through four modules A, B, C, and D, the signal starts from the register of the starting module A and ends at the register of the end module D. The logic levels that need to be determined are: A(reg->port out)->B(port in->port out)->C(port in->port out)->D(port in->reg), where A(reg->port out) represents the logic level from the logic input of module A (i.e., the register of module A) to the logic output of module A, B(port in->portout) represents the logic level from the logic input of module B to the logic output of module B, C(port in->port out) represents the logic level from the logic input of module C to the logic output of module C, and D(port in->reg) represents the logic level from the logic input of module D to the logic output of module D (i.e., the register of module D).

[0107] S102: Determine the logic proportion of each module according to the logic level of each module and the preset logic level.

[0108] The preset logic level is the maximum logic level that a data path can pass through within a clock cycle, determined according to the chip manufacturing process and the chip target frequency, that is, the longest logic level allowed under a specific process, denoted as M (Max logicstages).

[0109] The ratio of the logic level of each module to the preset logic level is determined as the logic proportion of each module. For example, the logic levels of module A to module N are s1, s2...sn, and the logic levels are s1 / M*100%, s2 / M*100%,...sn / M*100% respectively.

[0110] S103 . According to the logic proportion of each module, determine the key module from each module, and determine the logic segment where the key module is located as the key logic segment from the timing path.

[0111] According to the logic proportion of each module, the module whose logic proportion meets the preset condition is determined as the key module. The preset condition may be, for example, that the logic proportion exceeds the preset logic proportion threshold, and the logic segment where the key module is located is determined from the timing path as the key logic segment, wherein the logic segment where the key module is located is the logic segment between the logic input and logic output of the key module on the timing path.

[0112] S104: Perform timing optimization according to the logic code of the key logic segment.

[0113] Based on the logic ratio, the key logic segment is determined, that is, the possible problem points and the worst path segment of the timing path are determined. Then, the timing can be optimized according to the logic code of the key logic segment. For example, the logic code of the key logic segment can be adjusted and / or the key logic segment can be physically optimized.

[0114] In this embodiment, by obtaining the ratio of the logic level of each module of the timing circuit to the preset logic level, the logic level ratio of each module is obtained, so that the problem points of the entire design timing path can be quickly and accurately obtained at an early stage (i.e., the key logic segments can be determined), and the timing can be optimized through logic adjustment and other methods to achieve the purpose of timing convergence accurately and quickly.

[0115] Figure 3 Schematic diagram of the process of the timing optimization method provided in the embodiment of the present application Figure 2 ,like Figure 2 As shown, in an optional implementation, the above step S103, determining the key module from each module according to the logic proportion of each module, may include:

[0116] S201. Determine a critical path from a timing path according to the logic proportion of each module.

[0117] According to the logic proportion of each module, the sum of the logic proportions of at least two consecutive modules is calculated. If the sum of the logic proportions exceeds the preset sum of proportions, the logic segment where the at least two modules are located in the timing path is determined to be a critical path, wherein the logic segment where the at least two modules are located is the logic segment between the logic input of the first module and the logic output of the last module in the at least two modules on the timing path.

[0118] For example, the logic proportions of modules A, B, and C are 90%, 5%, and 15% respectively, and the total is 110%, which is greater than the preset proportion and value (such as 100%). Then the logic segment where modules A, B, and C are located in the timing path is the critical path.

[0119] S202. Determine a key module from the modules on the critical path according to the logic proportion of the modules on the critical path.

[0120] Among them, there are at least two modules on the critical path. According to the logic proportion of the modules on the critical path, the module whose logic proportion meets the preset conditions is determined from the modules on the critical path as the critical module, wherein the preset condition can be, for example, the largest logic proportion, that is, the critical module is the module with the largest logic proportion corresponding to the critical path.

[0121] For example, if s1 / M*100%+s2 / M*100%+…sn / M*100%>100%, then the logic segment where module A to module N in the timing path is located is determined to be the critical path, and modules A to N are sorted according to the logic proportion. The module A to module N with the largest logic proportion is taken as the critical module, and the logic segment where the critical module is located is taken as the critical logic segment. For example, module C is taken as the critical module, which is the key optimization object.

[0122] In this embodiment, the critical path is first found based on the logic ratio, and then the key module is found from the critical path, so as to quickly find the key logic segment that needs to be adjusted. Compared with the traditional optimization method of the entire critical path, the design iteration can be reduced to a certain extent, which not only has little impact on the overall timing, but also makes the optimization of the critical path more purposeful.

[0123] In an optional implementation, the above step S105, performing timing optimization according to the logic code of the key logic segment, may include:

[0124] Delete the logic code of the key logic section from the logic code of the sequential circuit; or,

[0125] In the logic code of the sequential circuit, adjust the logic code of the key logic segment to the previous level or the next level; or,

[0126] In the logic code of the key logic segment, splitting and / or combining the logic units in the logic code of the key logic segment; or,

[0127] In the logic code of the critical logic section, adjust the input transition time or output load of the critical logic section; or,

[0128] In the logic code of the critical logic section, adjust the delay constraint of the critical logic section.

[0129] In the logic design stage, after determining the key logic segment according to the logic ratio, the EDA tool can be used to delete the logic code of the key logic segment from the logic code of the sequential circuit. That is, the logic function implemented by the key logic segment is also deleted. In this way, the timing of the sequential circuit can be optimized in the logic code design stage to quickly achieve timing convergence.

[0130] By using EDA tools to adjust the logic code of the key logic segment in the logic code of the sequential circuit to the previous or next level to optimize the timing of the sequential circuit, the timing convergence can be achieved quickly. For example, the logic segment between modules A and B is a stack, and the logic segment between A and B is the key logic segment. The function of the key logic segment between A and B can be implemented by placing it in the stack behind A and in front of B, which is equivalent to adding a cascaded register C between A and B, and the logic behavior of the entire design system from A to C and then to B is consistent with A directly to B, that is, the delay from A to B is increased, A to C is one cycle, and C to B also requires one cycle, while previously there was only one clock cycle from A to B. This solution can ensure that the logic function is not affected while quickly achieving timing convergence.

[0131] An EDA tool is used to provide a standard cell library for digital circuits, the standard cell library includes a two-input NAND gate, etc. In the logic code of the key logic segment, the logic cells in the logic code of the key logic segment are split and / or combined based on the standard cell library. For example, the NAND gate on the key logic segment is split into an AND gate and a NOT gate, or the OR gate and the NOT gate on the key logic segment are combined into a NOR gate, so that the delay of the key logic segment after splitting and / or combining is less than the delay before splitting and / or combining, thereby optimizing the timing of the sequential circuit under the condition of logical equivalence.

[0132] Using EDA tools, in the logic code of the key logic segment, adjust the input transition time and / or output load of the key logic segment, where the input transition time and output load of the key logic segment is the constraint strength of the key logic segment, and the input transition time is Transition time (trans). Since the level flip is not instantaneous in the actual digital circuit, the Transition time is introduced to describe the time required for the signal to flip. This time reflects the time required for the signal to change from one level to another, which is crucial to ensure that the signal completes the conversion within the specified time.

[0133] The output load is Load. In circuit design, load refers to the capacitive load of the wire net, which reflects the capacitive components connected to the circuit, such as capacitors, resistors, etc. These components affect the propagation speed and delay of the signal. In timing path analysis, load is an important parameter because it directly affects the delay value of the signal from the input port to the first unit. By specifying the appropriate drive strength and drive unit, the drive capability of the port can be more accurately described, thereby optimizing circuit performance.

[0134] By using EDA tools, the delay constraint of the key logic segment is adjusted in the logic code of the key logic segment, wherein the delay constraint can be the maximum delay requirement (max delay) allowed for the key logic segment, and the delay constraint of the key logic segment is the constraint strength of the key logic segment.

[0135] In this embodiment, the modification of the logic code is based on the feedback of the key logic segment, and the optimization of the logic code is based on the optimization to achieve the purpose of timing closure accurately and quickly.

[0136] Figure 4 Schematic diagram of the process of the timing optimization method provided in the embodiment of the present application Figure 3 ,like Figure 4 As shown, in an optional implementation, the above step S105, performing timing optimization according to the logic code of the key logic segment, may include:

[0137] S301. If the key module is in the first implementation mode, at least one of a weight value, a routing resource, and a layout position of the key logic segment is adjusted in the logic code of the key logic segment.

[0138] The first implementation mode may be flatten, that is, the key modules and other modules except the key modules in the key logic segment are physically implemented as a design level.

[0139] If the key module is in the first implementation mode, an EDA tool is used to adjust at least one of a weight value, a routing resource, and a layout position of the key logic segment in the logic code of the key logic segment.

[0140] The weight value of the critical logic segment is the weight value of the metal line of the critical logic segment. In the subsequent physical design process, the corresponding metal line can be selected according to the weight value. For example, the higher the weight value, the smaller the resistance of the metal line is, which can reduce the delay.

[0141] If the routing resources provided by the EDA tool are sufficient, then in the logic code of the critical logic segment, the routing resources of the critical logic segment are adjusted to widen the metal wire to reduce the path delay. In the logic code of the critical logic segment, the layout position of the logic units on the critical logic segment can also be adjusted. For example, other logic units in this area that originally had no timing constraints (i.e., no timing violations) can be moved away. This is because there are fewer units on the timing path and the corresponding delay is also reduced.

[0142] S302. If the key module is in the second implementation mode, the target output delay of the key module is determined according to the logic proportion of other modules except the key module on the timing path, and / or, according to the output delay of the key module, the delay margin of other modules is calculated, and the target output delay of the key module is determined according to the delay margin.

[0143] The second implementation mode may be Hierarchy, that is, the design is divided into levels from top to bottom, and the key modules and modules other than the key modules in the key logic segments are respectively physically implemented as a design level.

[0144] If the key module is in the second implementation mode, the output delay of the key module is re-determined according to the logic proportion of other modules except the key logic segment on the timing path. Taking module A as the key module, the other modules are B to module N, and the logic levels are s2...sn respectively. Then the target output delay (output delay) of module A is expressed as: 1-(s2 / M*100%+s2 / M*100%……sn / M*100%).

[0145] According to the output delay of the key module, the delay margin of other modules is calculated. The delay margin is used to indicate the maximum output delay of other modules. For example, the output delay of the key module A is delay(Ax), and the delay margin of other modules (as a proportion of the clock cycle) is ratiox=(1-delay(Ax) / T)×100%, where T represents the clock cycle.

[0146] Obtain the internal delay of other modules, and obtain the total delay of other modules based on the internal delay and delay margin of other modules. The total delay of other modules is the sum of the internal delay and delay margin of other modules. Then, determine the difference between the preset required delay of the timing circuit and the total delay of other modules as the total delay D of the key module.

[0147] The internal delay F of the key module is obtained, and the target output delay of the key module is determined according to the total delay D of the key module and the internal delay F of the key module. The target output delay of the key module is expressed as DF.

[0148] S303. According to the target output delay, adjust the output delay of the key module in the logic code of the key logic segment.

[0149] According to the target output delay, the output delay of the key module is adjusted to the target output delay in the logic code of the key logic segment.

[0150] In this embodiment, according to different implementation modes of key modules, corresponding modifications are made in the logic code of the key logic segment to achieve the purpose of timing closure accurately and quickly.

[0151] It is worth noting that in module design, when the module is implemented in the first implementation mode, the unit logic name on the same timing path varies due to different versions. The specific timing path can be located through the hierarchical pin (port of the module). Among them, the design of the module can adopt the ordinary group method, that is, the sub-modules are not broken up, and the hierarchical pins of all sub-modules are retained. If the ungroup method is used, the corresponding hierarchy cannot be found after the logic unit is broken up, and the critical path logic cannot be optimized, and the problem point is not easy to locate.

[0152] Among them, the breaking up of logical units can be understood as the reconstruction of logical units. Logical units are implemented in different combinations, such as merging, heterogeneity, etc. to become multiple other equivalent logical units. The inability to find a hierarchy can be understood as due to the reconstruction of logical units, some logical units may be replaced by other structures and redefined, and the corresponding logical units cannot be retained and cannot be found.

[0153] Based on this, the above method can be used to calculate the logic level of the module under different timing paths.

[0154] When the module is a second implementation module, the logic level of the module is extracted from the gate-level netlist, and the logic level of the module can also be calculated using the above method.

[0155] Figure 5 Schematic diagram of the process of the timing optimization method provided in the embodiment of the present application Figure 4 ,like Figure 5 As shown, in an optional implementation, after the above step S105, timing optimization is performed according to the logic code of the key logic segment, the method may further include:

[0156] S401 . Execute the logic code of the key logic segment after the timing optimization to obtain the timing optimization result of the key logic segment.

[0157] S402: If the timing optimization result of the key logic segment does not meet the preset timing requirement, after the physical layout of the sequential circuit is completed, the target delay and actual delay of the key module are obtained.

[0158] Use EDA tools to run the logic code of the key logic segment after timing optimization to obtain the timing optimization result of the key logic segment. If the timing optimization result of the key logic segment does not meet the preset timing requirements, then after the physical layout is completed, obtain the target delay and actual delay of the key module, wherein the logic proportion of the key module is determined as the target delay, and perform static timing analysis on the key module to obtain the actual delay of the key module.

[0159] Among them, the actual delay of the key module is the sum of the unit delay and the line delay of the key module. The EDA tool can be used to import the process information and physical design data of the timing circuit to automatically obtain the line delay of the key module, and the EDA tool can be used to query the delay information table in the standard cell library to determine the unit delay of the key module, wherein the line delay is the delay between the logic output of the key module to the load, and the unit delay is the delay between the logic input and the logic output of the key module.

[0160] S403: If the actual delay exceeds the target delay, the key module is determined as the target optimization object.

[0161] S404 , performing timing optimization according to the physical design of the target optimization object.

[0162] For example, the target delay of the key module is sn / M*100%, the actual delay is Dn / T*100%, T is the clock cycle, if Dn / T*100%>sn / M*100% of the key module, the module is selected as the target optimization object.

[0163] After the target optimization object is determined, timing optimization can be performed according to the physical design of the target optimization object to adjust the physical design of the target optimization object, thereby performing timing optimization on the sequential circuit.

[0164] In this embodiment, if the timing optimization result after logic optimization does not meet certain timing requirements, the constraints and optimization points of the physical design (i.e., the target optimization object) are further found to adjust the physical design for timing optimization, thereby accurately and quickly achieving the purpose of timing convergence of the entire design.

[0165] Figure 6 Schematic diagram of the process of the timing optimization method provided in the embodiment of the present application Figure 5 ,like Figure 6 As shown, in an optional implementation, the above step S404, performing timing optimization according to the physical design of the target optimization object, may include:

[0166] S501: Obtain the logical distance of each submodule in the target optimization object.

[0167] According to the logic level of the target optimization object, the target optimization object is divided to generate various sub-modules, where the logic level is divided into the top level and multiple sub-levels, or even sub-sub-levels, which can be derived from the hierarchical design concept of the chip. The entire design task is divided into layers and blocks in a "top-down" manner to reduce the complexity of each layer and simplify the functions of each level. For example, if the target optimization object is module A, the sub-modules of module A include a1, a2, and a3.

[0168] Figure 7Schematic diagram of the submodules provided in the embodiment of the present application Figure 1 ,like Figure 7 As shown, module A is divided according to the module level to generate sub-modules a1, a2..., an, wherein the sub-modules a1, a2..., an have the same logical level within module A and the logical scales of the sub-modules a1, a2..., an are at the same order of magnitude.

[0169] For example, the instruction pipeline in the computer architecture has five-level pipeline operations such as instruction fetch, decoding, execution, memory access and write-back (corresponding to the instruction fetch logic submodule, decoding submodule, execution submodule, memory access submodule and write-back submodule, respectively) in similar logic design. The modules can be divided according to the logical level. For example, the external communication module can be divided into modules according to each stack of the data transfer pipeline. In actual applications, according to the design requirements and specific analysis of specific problems, the modules can still be divided at the next level.

[0170] Assume that the path Q->D is the worst setup timing path of BlockA, that is, the critical path. The starting point of the path is from the register Q end of module A, through the multi-level logic of multiple modules B, C... to the register D end of module N, where A corresponds to the starting module, B is the module passed on the path, and N is the end module.

[0171] The submodule may include a logic unit. Figure 8 Schematic diagram of the submodules provided in the embodiment of the present application Figure 2 ,like Figure 8 As shown, module A spans multiple sub-modules a1, a2..., an, is connected to a1 through two buffer units, and is connected to port 1 through a1 through a NOT gate. Port 1 reaches the OR gate through the AND gate, and the OR gate passes through a logic unit until it reaches an.

[0172] After the physical layout of the sequential circuit is completed, the logical distance of each submodule in the target optimization object is obtained. The logical distance may be the distance that the metal line track passes through the metal layer of each submodule after the physical layout of the sequential circuit is completed.

[0173] The logical distance may be, for example, the Manhattan distance, which is the distance between the two endpoints of the metal wire in the north-south direction plus the distance in the east-west direction, that is, d(i, j) = |x i -x j |+|y i -y j |, where the positions of the two endpoints are coordinate points on the two-dimensional coordinate axis, denoted as (x i ,y i )、(x j ,y j), the horizontal axis (X axis) of the two-dimensional coordinate axis can be understood as the east-west direction, and the vertical axis (Y axis) can be understood as the north-south direction.

[0174] S502: Determine a submodule to be optimized from among the submodules according to the logical distance.

[0175] According to the logical distance, the logical unit that meets the preset length condition is determined from each sub-module as the sub-module to be optimized, wherein the preset length condition may be, for example, the longest logical distance, that is, the logical distances of each sub-module are sorted, and the longest logical distance is obtained as the sub-module to be optimized, such as ay, wherein the longer the logical distance, the longer the delay, and the shorter the logical distance, the shorter the delay.

[0176] S503: Adjust the physical size and / or layout position of the submodule to be optimized.

[0177] After the submodule to be optimized is determined, the physical size (such as Floorplan size) and / or layout position of the submodule to be optimized can be adjusted to reduce the delay of the submodule to be optimized, thereby performing timing optimization from the perspective of physical design.

[0178] In an optional implementation, the above step S404, performing timing optimization according to the target optimization object, may include:

[0179] S504: If the target submodule of the target optimization object has a physical connection relationship with the logic unit of the target module, adjust the layout position of the target submodule.

[0180] The target module is a module other than the module on the key logic segment in the timing path, and the target submodule is a submodule among the multiple submodules of the target module that has a physical connection relationship with the logic unit of the target module.

[0181] If there is a physical connection between the target submodule of the target optimization object and the logic unit of the target module, it means that there is a logical pull between the target optimization object and the logic unit of the target module. Since the target optimization object is on the critical path in the timing path and the logic unit of the target module is on the non-critical path, the optimization level of the target optimization object is higher. Therefore, the layout position of the target submodule can be adjusted to bring the two pulling target submodules and the logic unit of the target module closer together to reduce the delay, thereby achieving timing optimization.

[0182] In an optional implementation, the above step S404, performing timing optimization according to the target optimization object, may include:

[0183] S505: Adjust the layout position of the target submodule according to the positional relationship and distance between the target submodule of the target optimization object and the logic unit of the target module.

[0184] The target module is a module other than the module on the critical logic segment in the timing path, and the target sub-module is any sub-module among the multiple sub-modules of the target module.

[0185] Obtain the positional relationship between the target submodule and the logic unit of the target module in the target optimization object, and determine whether there is a logic return in the target submodule based on the positional relationship. If there is a logic return, adjust the layout position of the target submodule to perform timing optimization.

[0186] It is worth mentioning that for a signal flowing from A->B->C, where A and C are relatively close, returning from B to C near A is called logic return.

[0187] For example, the target submodule is B, and the logic units of the target module are A and C. If the distance between the logic units A and C of the target module is less than the preset distance, and the distance between the target submodule B and the logic units A and C of the target module is greater than the preset distance, it means that after the signal propagates from A to B, it needs to return to C. Therefore, there is a logical return in B. The layout position of B can be adjusted to achieve the shortest distance from the starting point A to the end point C, so that ABC is as straight as possible.

[0188] It is understandable that when performing timing optimization from the perspective of physical design, at least one of the above steps S501 - S503 , S504 , and S505 may be performed to perform timing optimization.

[0189] In this embodiment, after the timing optimization, the delay of the timing path after the physical design adjustment can also be checked and compared with the delay of the initial timing path. Multiple iterations can be performed to quickly find the problem points in the physical design, locate the target and iterate the optimization to achieve the purpose of timing convergence. Compared with the traditional optimization method of the entire critical path, the design iterations can be reduced to a certain extent. The key points are accurately divided into a small range at the logical level or the physical level, which not only has a small impact on the overall timing, but also makes the optimization of the critical path more purposeful.

[0190] Fig. 9 This is a schematic diagram of the structure of a timing optimization device provided in an embodiment of the present application, which can be integrated into an electronic device.

[0191] like Fig. 9 As shown, the device may include:

[0192] An acquisition module 601 is used to acquire the logic levels of each module of the sequential circuit through which the timing path passes according to the gate-level netlist of the sequential circuit;

[0193] A determination module 602 is used to determine the logic proportion of each module according to the logic level of each module and the preset logic level;

[0194] The determination module 602 is further used to determine the key module from each module according to the logic proportion of each module, and determine the logic segment where the key module is located from the timing path as the key logic segment, and the logic segment where the key module is located is the logic segment between the logic input and the logic output of the key module on the timing path;

[0195] The optimization module 603 is used to perform timing optimization according to the logic code of the key logic segment.

[0196] In an optional implementation, the determination module 602 is specifically configured to:

[0197] Determine the critical path from the timing path based on the logic proportion of each module;

[0198] According to the logic proportion of the modules on the critical path, determine the key modules from the modules on the critical path.

[0199] In an optional implementation, the optimization module 603 is specifically configured to:

[0200] Delete the logic code of the key logic section from the logic code of the sequential circuit; or,

[0201] In the logic code of the sequential circuit, adjusting the logic code of the key logic segment to the previous level or the next level; or,

[0202] In the logic code of the critical logic segment, split and / or combine the logic units on the critical logic segment; or,

[0203] In the logic code of the critical logic section, adjust the input transition time or output load of the critical logic section; or,

[0204] In the logic code of the critical logic section, adjust the delay constraint of the critical logic section.

[0205] In an optional implementation, the optimization module 603 is specifically configured to:

[0206] If the key module is in the first implementation mode, at least one of a weight value, a routing resource, and a layout position of the key logic segment is adjusted in the logic code of the key logic segment.

[0207] In an optional implementation, the optimization module 603 is specifically configured to:

[0208] If the key module is in the second implementation mode, the target output delay of the key module is determined according to the logic proportion of other modules except the key module on the timing path; and / or, according to the internal delay of the key module and the preset delay of the timing circuit, the delay margin of other modules is calculated, and the target output delay of the key module is determined according to the delay margin;

[0209] According to the target output delay, adjust the output delay of the key module in the logic code of the key logic section.

[0210] In an optional implementation, the acquisition module 601 is further configured to:

[0211] Running the logic code of the key logic segment after the timing optimization to obtain the timing optimization result of the key logic segment;

[0212] The acquisition module 601 is further used to acquire the target delay and actual delay of the key module after the physical layout of the sequential circuit is completed if the timing optimization result of the key logic segment does not meet the preset timing requirement;

[0213] The determination module 602 is further used to determine the key module as a target optimization object if the actual delay exceeds the target delay;

[0214] The optimization module 603 is also used to perform timing optimization according to the physical design of the target optimization object.

[0215] In an optional implementation, the acquisition module 601 is specifically configured to:

[0216] Determine the logic ratio of key modules as the target delay;

[0217] Perform static timing analysis on key modules to obtain actual delay.

[0218] In an optional implementation, the optimization module 603 is specifically configured to:

[0219] Obtain the logical distance of each submodule in the target optimization object;

[0220] According to the logical distance, determine the submodule to be optimized from each submodule;

[0221] Adjust the physical size and / or layout position of the sub-module to be optimized.

[0222] In an optional implementation, the optimization module 603 is specifically configured to:

[0223] If a target submodule of the target optimization object is physically connected to a logic unit of the target module, the layout position of the target submodule is adjusted.

[0224] In an optional implementation, the optimization module 603 is specifically configured to:

[0225] According to the positional relationship between the target submodule of the target optimization object and the logic unit of the target module, the layout position of the target submodule is adjusted.

[0226] In an optional embodiment, it also includes:

[0227] The division module 604 is used to divide the target optimization object according to the logical level of the target optimization object to generate various sub-modules.

[0228] For descriptions of the processing flow of each module in the device and the interaction flow between each module, reference may be made to the relevant descriptions in the above method embodiment, which will not be described in detail here.

[0229] Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application, such as Fig.10 As shown, the device may include: a processor 701, a memory 702 and a bus 703. The memory 702 stores machine-readable instructions executable by the processor 701. When the electronic device is running, the processor 701 communicates with the memory 702 through the bus 703, and the processor 701 executes the machine-readable instructions to perform the above method.

[0230] An embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the processor executes the above method.

[0231] In the embodiment of the present application, the computer program can also execute other machine-readable instructions when run by the processor to execute other methods described in the embodiment. For the specific execution method steps and principles, please refer to the description of the embodiment, which will not be repeated here.

[0232] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0233] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0234] In addition, each functional unit in the embodiments provided in the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0235] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0236] It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and are not to be understood as indicating or implying relative importance.

[0237] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application. They should all be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A timing optimization method, characterized in that: include: According to the gate-level netlist of the sequential circuit, obtaining the logic level of each module of the sequential circuit through which the sequential path passes; Determining the logic proportion of each module according to the logic level of each module and the preset logic level; According to the logic proportion of each module, a key module is determined from each module, and a logic segment where the key module is located is determined from the timing path as a key logic segment, where the logic segment where the key module is located is a logic segment between a logic input and a logic output of the key module on the timing path; Timing optimization is performed according to the logic code of the key logic segment.

2. The method according to claim 1, characterized in that Determining the key modules from the modules according to the logic proportions of the modules includes: Determining a critical path from the timing path according to the logic proportion of each module; The key module is determined from the modules on the critical path according to the logic proportion of the modules on the critical path.

3. The method according to claim 1, characterized in that The performing timing optimization according to the logic code of the key logic segment includes: Deleting the logic code of the key logic segment from the logic code of the sequential circuit; or, In the logic code of the sequential circuit, adjusting the logic code of the key logic segment to a previous stage or a later stage; or, In the logic code of the key logic segment, splitting and / or combining the logic units on the key logic segment; or, In the logic code of the critical logic segment, adjusting the input transition time and / or output load of the critical logic segment; or, In the logic code of the critical logic segment, the delay constraint of the critical logic segment is adjusted.

4. The method according to claim 1, characterized in that: The performing timing optimization according to the logic code of the key logic segment includes: If the key module is in the first implementation mode, then in the logic code of the key logic segment, at least one of the weight value, the routing resources, and the layout position of the key logic segment is adjusted.

5. The method according to claim 1, characterized in that The performing timing optimization according to the logic code of the key logic segment includes: If the key module is in the second implementation mode, the target output delay of the key module is determined according to the logic proportion of other modules on the timing path except the key module; and / or, according to the internal delay of the key module and the preset delay of the timing circuit, the delay margin of the other modules is calculated, and the target output delay of the key module is determined according to the delay margin; According to the target output delay, the output delay of the key module is adjusted in the logic code of the key logic section.

6. The method according to claim 1, characterized in that After performing timing optimization according to the logic code of the key logic segment, the method further includes: Running the logic code of the key logic segment after the timing optimization to obtain the timing optimization result of the key logic segment; If the timing optimization result of the key logic segment does not meet the preset timing requirement, after the physical layout of the sequential circuit is completed, the target delay and the actual delay of the key module are obtained; If the actual delay exceeds the target delay, determining the key module as a target optimization object; Timing optimization is performed according to the physical design of the target optimization object.

7. The method according to claim 6, characterized in that The obtaining of the target delay and the actual delay of the key module includes: Determine the logic ratio of the key module as the target delay; Static timing analysis is performed on the key modules to obtain the actual delay.

8. The method according to claim 6, characterized in that The performing timing optimization according to the physical design of the target optimization object includes: Obtaining the logical distance of each submodule in the target optimization object; Determining a submodule to be optimized from among the submodules according to the logical distance; The physical size and / or layout position of the submodule to be optimized is adjusted.

9. The method according to claim 6, characterized in that The performing timing optimization according to the physical design of the target optimization object includes: If the target submodule of the target optimization object is physically connected to the logic unit of the target module, the layout position of the target submodule is adjusted.

10. The method according to claim 6, characterized in that The performing timing optimization according to the physical design of the target optimization object includes: According to the positional relationship between the target submodule of the target optimization object and the logic unit of the target module, the layout position of the target submodule is adjusted.

11. The method according to claim 8, characterized in that Before obtaining the logical distance of each submodule in the target optimization object, the method further includes: According to the logical level of the target optimization object, the target optimization object is divided to generate the sub-modules.

12. A timing optimization device, characterized in that: include: An acquisition module, used for acquiring the logic levels of each module of the sequential circuit through which the sequential path passes according to the gate-level netlist of the sequential circuit; A determination module, used to determine the logic proportion of each module according to the logic level of each module and the preset logic level; The determination module is further configured to determine a key module from the modules according to the logic proportions of the modules, and determine the logic segment where the key module is located as the key logic segment from the timing path, wherein the logic segment where the key module is located is the logic segment between the logic input and the logic output of the key module on the timing path; The optimization module is used to perform timing optimization according to the logic code of the key logic segment.

13. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and the processor executes the machine-readable instructions to execute the method described in any one of claims 1 to 11.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 11 is executed.

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