DC bus voltage stabilization control method and system based on three-level uninterruptible power supply

Abstract

The present invention discloses a DC bus voltage stabilization control method based on three-level uninterruptible power supply, including: monitoring the voltage value of the DC bus; based on the monitored voltage value of the DC bus, allocating voltage control response instructions to the transmission line of the DC bus; if the control response instruction allocated based on the monitored voltage value of the DC bus is the first control, maintain Class A power supply; if the control response instruction allocated based on the monitored voltage value of the DC bus is the second control, disconnect Class A power supply; maintain Class B power supply, continuously monitor Class D power supply connection status, and set it to a stable state; if the control response instruction allocated based on the monitored voltage value of the DC bus is the third control, disconnect Class A and Class B power supplies; maintain Class D power supply. The staged power supply abnormality switching scheme designed by the present invention, combined with the technical solution of fault location, supports the entire power supply system to make accurate judgments in a short time, and provides an intelligent switching power supply strategy.

Description

Technical Field

[0001] The invention belongs to the technical field of DC bus voltage stabilization control, and in particular relates to a DC bus voltage stabilization control method and system based on three-level uninterruptible power supply. Background Art

[0002] With the growing demand for high-reliability power supply in modern society, DC power supply systems are increasingly used in data centers, communication base stations, electric vehicle charging stations, renewable energy access, industrial automation and other fields. The DC bus is the core part of these power supply systems, and its voltage stability has an important impact on the system's operating efficiency, reliability and equipment life. DC power supply systems usually operate in a complex dynamic environment, and are affected by rapid load switching, grid fluctuations, aging of energy storage equipment and external interference, which makes it easy for the DC bus voltage to fluctuate violently or deviate from the target value for a long time, ultimately leading to frequent power supply failures.

[0003] In order to deal with the above objective problems, a three-level uninterruptible power supply solution design is proposed. When the DC bus power supply is abnormal, by setting up a multi-level power replenishment solution, it can quickly switch to the backup power supply at the moment of bus failure, thereby ensuring safe and stable power transmission.

[0004] However, as a high-intensity operating system of the power supply network, the existing technology has design deficiencies in the design of the DC bus voltage stabilization solution, such as the failure to locate the power supply fault in a timely manner. During the switching of the main and standby power supply systems, a certain amount of time will be spent on feedback and adjustment of the fault location. In the power system, a short-term fault will cause a major accident. At the same time, the existing technology lacks a stable voltage stabilization design solution for the DC bus, making it difficult to achieve global line monitoring and regulation, circuit voltage monitoring is not sensitive, and the intelligent automatic switching power supply system is not obvious. In view of the shortcomings of the existing technology, it is urgent to design a DC bus voltage stabilization control method and system based on three-level uninterruptible power supply to solve the above technical problems. Summary of the invention

[0005] In order to solve the above-mentioned deficiencies in the prior art, the present invention provides a DC bus voltage stabilization control method based on a three-level uninterruptible power supply, the method comprising:

[0006] Monitor the voltage value of the DC bus;

[0007] Allocating a voltage control response instruction to a power transmission line of the DC bus based on the monitored voltage value of the DC bus;

[0008] If the control response instruction assigned based on the monitored voltage value of the DC bus is the first control, maintain the A-level power supply; continue to monitor the connection status of the B-level and D-level power supplies, and mark them as stable;

[0009] If the regulation response instruction assigned based on the monitored voltage value of the DC bus is the second regulation, disconnect the power supply of level A; maintain the power supply of level B, continuously monitor the connection status of the power supply of level D, and mark it as a stable state;

[0010] If the regulation response instruction assigned based on the monitored voltage value of the DC bus is the third regulation, disconnect the power supplies of levels A and B; maintain the power supply of level D.

[0011] As a further optimization of the above solution, the method for monitoring the voltage value of the DC bus includes the following:

[0012] Continuously collect the voltage values of the circuit sections of the power supplies of levels A, B, and D respectively, and output a continuous line graph of the collected continuous interval voltage values and the corresponding moments;

[0013] Set the image analysis time points, t1, t2,..., ti, where t2 - t1 = t3 - t2 =... = ti - t(i - 1);

[0014] Obtain a line graph with an observation time threshold of t1 ± Δt based on the image analysis time points, where |t2 - t1| < Δt;

[0015] Traverse all the collected voltage values in the current observation time domain, and obtain the voltage difference and the corresponding voltage values Vt11 and Vt12 at any t11 moment and t12 moment:

[0016] If the voltage difference between the t11 moment and the t12 moment is within the stable threshold Δstable, mark it as a single stability;

[0017] If the voltage difference between the t11 moment and the t12 moment is not within the stable threshold Δstable, mark it as a single fluctuation and record it as Δwave;

[0018] If the voltage difference between the voltage value at the t11 or t12 moment and the normal voltage is within the safety threshold Δsafe, mark it as a single safety; otherwise, mark it as a single danger Δdanger;

[0019] Repeat the above steps until all the voltage values within the observation time threshold of t1 ± Δt are collected and the status of all the collected voltage values is marked.

[0020] As a further optimization of the above solution, the method for monitoring the voltage value of the DC bus further includes the following:

[0021] Based on the collected voltage values and the voltage value status, perform real-time calibration of the circuit fluctuation state:

[0022] If the voltage difference between the voltage value at any current moment and the normal voltage is within △ An, continuously obtain the next moment of the current moment. (1) If it is detected that the next moment is within △ Wen and △ An, calibrate the circuit as safe; (2) If it is detected that the next moment is within △ Wei, further obtain the state of the second next moment: (1) If it is detected that the second next moment is within △ Wen and △ An, calibrate the circuit as safe; (2) If it is detected that the second next moment is within △ Wei, calibrate the circuit as in warning; (3) If it is detected that the second next moment is within △ Bo and △ An, calibrate the circuit as acceptable for fluctuations;

[0023] (3) If it is detected that the next moment is within △ Bo and △ An, further obtain the state of the second next moment: (1) If it is detected that the second next moment is within △ An, calibrate the circuit as safe; (2) If it is detected that the second next moment is within △ Wen and △ Wei, calibrate the circuit as acceptable for fluctuations; (3) If it is detected that the second next moment is within △ Bo and △ Wei, calibrate the circuit as in warning.

[0024] As a further optimization of the above solution, based on all the circuit fluctuation state calibrations, count all the acceptable fluctuation situations within the observation time range of t1 ± △t;

[0025] Based on the statistics of all the acceptable fluctuation situations, calculate the time difference between any two adjacent times marked as acceptable for fluctuations: If this time difference is less than the preset threshold, increase the number of circuit warning times within the observation time range of t1 ± △t by 1 time;

[0026] Suppose within the time range with t1 ± △t as the observation time range, the number of times marked as circuit warning exceeds the stable circuit limit range, then mark that within the observation time range of t1 ± △t, the current observed time range circuit voltage is unstable and there are large fluctuations;

[0027] If it does not exceed the stable circuit limit range, mark the current observed time range circuit voltage as stable.

[0028] As a further optimization of the above solution, based on all the image analysis time points, obtain the time range circuit voltage marking results corresponding to all the image analysis time points. If the number of observation time ranges marked as circuit voltage unstable exceeds the calibration coefficient, mark the current circuit voltage as unstable; otherwise mark it as stable;

[0029] If it is detected that the voltage of the A-level circuit is stable, allocate the control response instruction as the first control;

[0030] If it is detected that the voltage of the A-level circuit is unstable and the voltage of the B-level circuit is stable, allocate the control response instruction as the second control;

[0031] If it is detected that the voltages of the A and B-level circuits are unstable and the voltage of the D-level circuit is stable, allocate the control response instruction as the third control;

[0032] If it is detected that the voltages of the A, B, and C-level circuits are unstable, allocate the control response instruction as the fourth control.

[0033] As a further optimization of the above solution, the monitoring of the voltage value of the DC bus also includes monitoring the power supply status of the transmission line, and the specific method includes the following:

[0034] Assume that the main power supply of the DC bus is Class A, and the terminals from the detection end to the load connection end are A1 and A2 respectively; multiple Class B power supplies are connected to the bus respectively, marked as B1, B2, ..., Bm; the detection section from the DC bus to the load is Class C; any Class B power supply is composed of multiple Class D power supplies, marked as D1, D2, ..., Dn; any fault falling on the A1A2 section is ErrA, any fault falling on the Class B connecting the DC bus section is ErrB, and any fault falling on the bus connecting the load line section is ErrC;

[0035] Assume that the transmission speed parameters of any fault in the power supply system are Vli and Vze, T1li and T1ze are the time consumed by the intersection fault point to transmit power to Class A based on the transmission speeds Vli and Vze, T2li and T2ze are the time consumed by the intersection fault point to transmit power to Class B based on the transmission speeds Vli and Vze, T3li and T3ze are the time consumed by the intersection fault point to transmit power to Class C based on the transmission speeds Vli and Vze;

[0036] The time difference between any intersection fault point and different detection ends based on the transmission speeds Vli and Vze is calculated as:

[0037] δ1=T1ze-T1li; δ2=T2ze-T2li; δ3=T3ze-T3li.

[0038] As a further optimization of the above scheme, let TAli and TAze be the time consumed by any fault point in the interval to reach level A based on the transmission speeds Vli and Vze, TBli and TBze be the time consumed by any fault point in the interval to reach level B based on the transmission speeds Vli and Vze, and TCli and TCze be the time consumed by any fault point in the interval to reach level C based on the transmission speeds Vli and Vze;

[0039] The time difference between the fault point in any interval and the corresponding detection end based on the transmission speed Vli and Vze is calculated as:

[0040] δErrA=TAze-TAli; δErrB=TBze-TBli; δErrC=TCze-TCli;

[0041] Based on the above, the ErrA fault point is constructed based on the time difference calculation formula of the transmission speed Vli and Vze to different detection ends:

[0042] δErrA==TAze-TAli=(T1ze-TErrAze)-(T1li-TErrAli)=(T1ze-T1li)+(TErrAli-TErrAze);

[0043] δErrB==TBze-TBli=(T2ze +TErrAze)-(T2li+TErrAli)=(T2ze – T2li)+(TErrAze – TErrAli);

[0044] δErrC==TCze-TCli=(T3ze +TErrAze)-(T3li+TErrAli)=(T3ze – T3li)+(TErrAze – TErrAli);

[0045] Among them, TErrAli and TErrAze are the time from ErrA to the intersection point based on the transmission speeds Vli and Vze respectively;

[0046] Based on the parameter values ​​of TErrAli and TErrAze, the relationship between the time difference between any interval fault point and any intersection fault point is obtained as follows:

[0047] ErrA: δErrA<δ1; δErrB>δ2; δErrC>δ3.

[0048] As a further optimization of the above scheme, repeat the above steps to construct the time difference calculation formulas of the ErrB and ErrC fault points based on the transmission speeds Vli and Vze to different detection ends, and then obtain the relationship between the time difference between any interval fault point and any intersection fault point corresponding to the ErrB and ErrC fault points based on the calculation formulas, which are:

[0049] ErrB: δErrA>δ1; δErrB<δ2; δErrC>δ3;

[0050] ErrC: δErrA>δ1; δErrB>δ2; δErrC<δ3.

[0051] A computer-readable storage medium storing one or more programs, wherein the one or more programs include instructions, and when the instructions are executed by a computing device, the computing device executes a DC bus voltage stabilization control method based on a three-level uninterruptible power supply as described above.

[0052] A computing device comprises one or more processors, a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include instructions for executing a DC bus voltage stabilization control method based on a three-level uninterruptible power supply as described above.

[0053] The present invention adopts the above technical solution, which has the following beneficial effects compared with the prior art:

[0054] 1. The present invention innovatively designs a DC bus voltage stabilization control method based on three-level uninterruptible power supply. By real-time monitoring of the power supply status of the DC bus, its transmission voltage value is constantly acquired, and according to the transmission status and voltage value of the line, an intelligent power supply strategy is enabled, and the existing DC bus power supply system is divided into three layers of different levels of power supply guarantee methods, and technical protection for transmission line faults or power outages is performed, realizing a high-efficiency and high-accuracy fault power switching design, ensuring efficient and stable operation of the power system during the distribution and transmission process.

[0055] 2. The present invention sets the voltage value state calibration at any time, and calibrates the voltage state at any time according to the voltage difference between the voltage value at any current time and the normal voltage and the voltage difference at adjacent times. It designs the description of the voltage stability trend and the power supply state feedback of the line respectively. At the same time, it improves the analysis accuracy of the current circuit transmission state based on the combined analysis of multiple times, thereby providing accurate power supply selection and switching of the DC bus power supply system.

[0056] 3. The technology of the present invention utilizes the principle that the line mode speed of any monitoring point is greater than the zero mode speed. It can accurately judge the difference in detection time caused by the size of Vli and Vze parameters detected by different detection ends after a fault occurs in the DC bus, so as to obtain the time difference judgment inequality for the fault occurring at this position, and through the feedback of the time difference, reversely infer the fault location of any DC bus circuit, providing an accurate judgment strategy for the voltage stabilization control method of the three-level uninterruptible power supply, facilitating its instruction scheduling.

[0057] 4. The phased power supply abnormality switching scheme designed based on the present invention, combined with the technical solution of fault location, supports the entire power supply system to make accurate judgments in a short time, and provides intelligent power supply switching strategies to deal with power supply failures in different locations and forms, greatly improving the power transmission stability performance of the power system and ensuring safe production. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0059] Figure 1 A schematic diagram of a process of the present invention;

[0060] Figure 2 Another schematic diagram of the process of the present invention;

[0061] Figure 3 It is a schematic diagram of the interval fault point of the present invention;

[0062] Figure 4 This is a schematic diagram of the Class B power supply of the present invention. DETAILED DESCRIPTION

[0063] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0064] like Figure 1-4 As shown, an embodiment of the present invention discloses a DC bus voltage stabilization control method based on a three-level uninterruptible power supply, the method comprising:

[0065] Monitor the voltage value of the DC bus;

[0066] allocating a voltage control response instruction to a transmission line of the DC bus based on a monitored voltage value of the DC bus;

[0067] If the control response instruction assigned based on the monitored voltage value of the DC bus is the first control, maintain the A-level power supply; continue to monitor the connection status of the B-level and D-level power supplies and set them to a stable state;

[0068] If the control response instruction assigned based on the monitored DC bus voltage value is the second control, disconnect the A-level power supply; maintain the B-level power supply, continuously monitor the connection status of the D-level power supply, and set it to a stable state;

[0069] If the control response instruction assigned based on the monitored voltage value of the DC bus is the third control, the A-level and B-level power supplies are disconnected; and the D-level power supply is maintained.

[0070] The power system, including power generation, transmission and distribution, involves multiple devices and complex network structures. With the widespread application of renewable energy and the continuous growth of electricity demand, the power system faces a more complex operating environment and challenges. With the extensive use of high-tech equipment and information equipment, users' requirements for power quality are constantly increasing. The access to renewable energy such as solar and wind energy has made the power system more complex. The output of these energy sources is uncertain, which poses a challenge to voltage stability. Especially in many industries with extremely strict requirements on power supply, such as data centers, hospitals and high-tech manufacturing industries, stable voltage and continuous power supply are particularly important.

[0071] The present invention innovatively designs a method for controlling the stability of the DC bus voltage based on three - level uninterrupted power supply. By real - time monitoring the power supply status of the DC bus, obtaining its transmission voltage value at all times, and enabling an intelligent power supply strategy according to the transmission status and voltage value of the line, the existing DC bus power supply system is divided into three different levels of power supply guarantee methods for technical protection against transmission line faults or power outages, realizing a high - efficiency and high - accuracy design for switching to power consumption during faults, and ensuring the efficient and stable operation of the power system during the distribution and transmission process.

[0072] Specifically, the method for monitoring the voltage value of the DC bus includes the following:

[0073] Continuously collect the voltage values of the circuit sections powered by level A, level B, and level D respectively, and output the continuously collected interval voltage values and the corresponding time moments as a continuous line graph;

[0074] Set the image analysis time points, t1, t2, …, ti, where t2 - t1 = t3 - t2 = …… = ti - t(i - 1);

[0075] Based on the image analysis time points, obtain the line graph with the observation time domain of t1±△t, where |t2 - t1|<△t; It should be particularly noted that the continuous line graph generated by the present invention can be output, displayed, and recorded through a power parameter detection device. Since this technical solution is an existing technology, it will not be elaborated here;

[0076] Traverse all the collected voltage values in the current observation time domain, and obtain the voltage difference and the corresponding voltage values Vt11 and Vt12 at any t11 moment and t12 moment:

[0077] If the voltage difference between the t11 moment and the t12 moment is within the stable threshold △stable, mark it as a single stability;

[0078] If the voltage difference between the t11 moment and the t12 moment is not within the stable threshold △stable, mark it as a single fluctuation and record it as △wave;

[0079] If the voltage difference at the t11 or t12 moment and the voltage difference of the normal voltage are within the safety threshold △safe, mark it as a single safety; otherwise, mark it as a single danger △danger;

[0080] Repeat the above steps until all the voltage values within the observation time domain of t1±△t are collected and the status of all the collected voltage values is marked.

[0081] The present invention specifically monitors the voltage values of each level of power supply in real - time, and outputs and displays the monitored voltage values as a line graph for the detection and analysis of power equipment; at the same time, according to the analysis and comparison of the real - time voltage values, the voltage status at any moment is calibrated for subsequent further circuit analysis.

[0082] Specifically, the method for monitoring the voltage value of the DC bus further includes the following:

[0083] Based on the collected voltage value and the voltage value status, perform real-time calibration of the circuit fluctuation status:

[0084] If the voltage difference between the voltage value at any current moment and the normal voltage is within △A, continuously obtain the next moment of the current moment. (1) If the next moment is detected to be within △W and △A, calibrate the circuit as safe; (2) If the next moment is detected to be within △W, further obtain the status of the second next moment: (1) If the second next moment is detected to be within △W and △A, calibrate the circuit as safe; (2) If the second next moment is detected to be within △W, calibrate the circuit as in warning; (3) If the second next moment is detected to be within △B and △A, calibrate the circuit as acceptable for fluctuations;

[0085] (3) If the next moment is detected to be within △B and △A, further obtain the status of the second next moment: (1) If the second next moment is detected to be within △A, calibrate the circuit as safe; (2) If the second next moment is detected to be within △W and △W, calibrate the circuit as acceptable for fluctuations; (3) If the second next moment is detected to be within △B and △W, calibrate the circuit as in warning.

[0086] By setting the calibration of the voltage value status at any moment, the present invention respectively calibrates the voltage status at any moment according to the voltage difference between the voltage value at any current moment and the normal voltage and the voltage difference between adjacent moments, and respectively designs the description of the stable trend of the voltage and the feedback on the power supply status of the line. At the same time, through the combined analysis of multiple moments, the accuracy of the analysis of the current circuit power transmission status is improved, so as to provide an accurate power supply selection and switching for the DC bus power supply system.

[0087] Specifically, based on all the circuit fluctuation status calibrations, count all the acceptable fluctuation situations within the observation time range of t1±△t;

[0088] Based on the statistics of all the acceptable fluctuation situations, calculate the time difference between any two adjacent times marked as acceptable fluctuations: If the time difference is less than the preset threshold, add 1 to the number of circuit warning times within the observation time range of t1±△t; According to the fluctuation statistics of the detection results, the present invention further analyzes the remaining possible influencing factors, improves the judgment of the current circuit power transmission status, and ensures that the accuracy of the DC power supply system can be enhanced according to the fluctuation range and amplitude value, so as to guarantee the evaluation accuracy of the overall power supply line;

[0089] If the number of times marked as circuit warning within the time range with t1±△t as the observation time range exceeds the stable circuit limit range, mark that the current circuit voltage within the observation time range of t1±△t is unstable and there are large fluctuations;

[0090] If it does not exceed the stable circuit limit range, mark that the current circuit voltage is stable.

[0091] Specifically, based on all image analysis time points, the time threshold circuit voltage marking results corresponding to all image analysis time points are obtained. If the number of observed time thresholds marking circuit voltage instability exceeds the calibration coefficient, the current circuit voltage is set to be unstable; otherwise, it is set to be stable. It is particularly noted that the calibration coefficient mentioned in the present invention is used to accurately determine the power supply status of the current circuit. Given different power supply lines and configuration requirements, the calibration coefficient can be adaptively adjusted to ensure that the final circuit status judgment is accurate and effective.

[0092] If the voltage of the class A circuit is detected to be stable, the control response instruction is allocated as the first control;

[0093] If it is detected that the voltage of the A-level circuit is unstable and the voltage of the B-level circuit is stable, the control response instruction is allocated as the second control;

[0094] If it is detected that the voltage of the A and B level circuits is unstable and the voltage of the D level circuit is stable, the control response instruction is allocated as the third control;

[0095] If it is detected that the voltage of the A, B, and D level circuits is unstable, the control response instruction is allocated as the fourth control.

[0096] More specifically, the present invention also provides an embodiment for real-time monitoring of the fault state of the DC bus and setting the DC bus voltage stability trend; specifically, by real-time monitoring of the voltage value of the transmission line, comparing it with the voltage value corresponding to the stable transmission, and performing intelligent scheduling and allocation instructions based on the calculated voltage difference:

[0097] When the voltage of the A-level circuit is stable, it means that the DC bus is in a normal power transmission state, so levels B and D do not need to be powered, and only status monitoring is required to confirm normal access to the power grid system; when the voltage of the A-level circuit is unstable, level B is prioritized for power supply. After the voltage difference is detected for level B, if its circuit voltage is stable, it will be powered by it, and level D does not need to be powered. Only status monitoring is required to confirm normal access to the power grid system; if the voltage of the A and B-level circuits is unstable, indicating that both levels A and B are faulty, then only level D is left for power supply. After the voltage difference is detected for level D, if the circuit voltage is stable, it will be powered by it.

[0098] It is particularly important to note that the present invention also designs a fourth control instruction, that is, the voltage of the A, B, and D level circuits is unstable, indicating that all DC bus uninterruptible power supply systems have failed and there is no available power supply. Based on this situation, an emergency alarm is triggered to notify the power grid maintenance personnel to urgently handle the failure. Since the triggering of the emergency alarm can be notified through existing text messages, phone calls, ringtones, emails, etc., it is not within the protection scope of the present invention and will not be described in detail here.

[0099] The staged power supply abnormality switching solution designed based on the present invention, combined with the technical solution of fault location, supports the entire power supply system to make accurate judgments in a short time, and provides intelligent power supply switching strategies to deal with power supply failures in different locations and forms, greatly improving the power transmission stability performance of the power system and ensuring safe production.

[0100] Specifically, the above-mentioned monitoring of the voltage value of the DC bus includes monitoring the power supply status of the transmission line, which specifically includes the following:

[0101] Assume that the main power supply of the DC bus is Class A, and the terminals from the detection end to the load connection end are A1 and A2 respectively; multiple Class B power supplies are connected to the bus respectively, marked as B1, B2, ..., Bm; the detection section from the DC bus to the load is Class C; any Class B power supply is composed of multiple Class D power supplies, marked as D1, D2, ..., Dn; suppose that any fault falling on the A1A2 section is ErrA, any fault falling on the Class B connecting the DC bus section is ErrB, and any fault falling on the bus connecting the load section is ErrC; it should be particularly noted that the DC bus A1A2, multiple Class B power supplies, and Class D power supplies marked in the present invention are used to describe the three-level uninterruptible power supply strategy for DC bus voltage stabilization, which is suitable for three-layer power supply systems of different levels; and the Class B is a grouped battery that boosts the 12V voltage to 220V through a bidirectional DC / DC parallel power supply module for output and load; the Class D is a power supply system composed of multiple battery cells connected in series;

[0102] Assume that the transmission speed parameters of any fault in the power supply system are Vli and Vze, T1li and T1ze are the time consumed by the intersection fault point to transmit electric energy to Class A based on the transmission speeds Vli and Vze, T2li and T2ze are the time consumed by the intersection fault point to transmit electric energy to Class B based on the transmission speeds Vli and Vze, and T3li and T3ze are the time consumed by the intersection fault point to transmit electric energy to Class C based on the transmission speeds Vli and Vze; more specifically, Vli and Vze are the transmission speeds of the line mode and zero mode components of any fault traveling wave in the transmission line, T1li and T1ze are the time consumed by the line mode and zero mode of the intersection fault point to the Class A detection end, and the intersection fault point is a connection intersection point of the busbar and the branch line in any transmission line where a fault occurs;

[0103] The time difference between any intersection fault point and different detection ends based on the transmission speeds Vli and Vze is calculated as:

[0104] δ1=T1ze-T1li; δ2=T2ze-T2li; δ1=T3ze-T3li.

[0105] The present invention designs the transmission time difference between the line mode wave velocity and the zero mode wave velocity of any intersection fault point to reach the detection end, and uses this situation as a special fault point sample. Based on the calculation result, the propagation time from any end to the intersection fault point is obtained, and then according to the wave velocity, the intersection fault point position can be accurately obtained;

[0106] Specifically, TAli and TAze are respectively the time from any interval fault point to A1 based on the transmission speeds Vli and Vze, TBli and TBze are respectively the time from any interval fault point to Class B power supply terminal based on the transmission speeds Vli and Vze, and TCli and TCze are respectively the time from any interval fault point to the load based on the transmission speeds Vli and Vze; more specifically, the time from any interval fault point to each detection terminal based on the transmission speeds Vli and Vze is characterized as a power grid system based on the DC bus and other branches connected to the bus, and the line part between each detection terminal and the intersection of the DC bus and the branch line. By setting up parameters such as TAli and TAze, TBli and TBze, and TCli and TCze, it is convenient to construct a relationship judgment formula for the distance position between the interval fault point and the intersection fault point to each detection terminal, so that the fault location can be quickly and effectively performed;

[0107] The time difference between the fault point in any interval and the corresponding detection end based on the transmission speed Vli and Vze is calculated as:

[0108] δErrA=TAze-TAli; δErrB=TBze-TBli; δErrC=TCze-TCli;

[0109] Based on the above, the ErrA fault point is constructed based on the time difference calculation formula of the transmission speed Vli and Vze to different detection ends:

[0110] δErrA==TAze-TAli=(T1ze-TErrAze)-(T1li-TErrAli)=(T1ze-T1li)+(TErrAli-TErrAze);

[0111] δErrB==TBze-TBli=(T2ze +TErrAze)-(T2li+TErrAli)=(T2ze – T2li)+(TErrAze – TErrAli);

[0112] δErrC==TCze-TCli=(T3ze +TErrAze)-(T3li+TErrAli)=(T3ze – T3li)+(TErrAze – TErrAli);

[0113] Among them, TErrAli and TErrAze are the time from ErrA to the intersection point based on the transmission speeds Vli and Vze respectively;

[0114] Based on the parameter values ​​of TErrAli and TErrAze, the relationship between the time difference between any interval fault point and any intersection fault point is obtained as follows:

[0115] ErrA: δErrA<δ1; δErrB>δ2; δErrC>δ3.

[0116] It is particularly important to note that, since any line mode velocity is greater than the zero mode velocity, its components also follow the same rule, that is, TErrAli – TerrAze must be less than 0, which means that δErrA<δ1; δErrB>δ2; δErrC>δ3;

[0117] Specifically, repeat the above steps to construct the time difference calculation formulas of the ErrB and ErrC fault points based on the transmission speeds Vli and Vze to different power supply ends, and then obtain the relationship formulas of the time difference between any interval fault point and any intersection fault point corresponding to the ErrB and ErrC fault points based on the calculation formulas, which are:

[0118] ErrB: δErrA>δ1; δErrB<δ2; δErrC>δ3;

[0119] ErrC: δErrA>δ1; δErrB>δ2; δErrC<δ3.

[0120] The technology of the present invention utilizes the principle that the line mode speed of any monitoring point is greater than the zero mode speed, and can accurately judge the difference in detection time caused by the size of Vli and Vze parameters detected at different power supply ends after a fault occurs in the DC bus, so as to obtain the time difference judgment inequality for the fault occurring at this section, and through the feedback of the time difference, reversely infer the fault location of any DC bus circuit, provide an accurate judgment strategy for the voltage stabilization control method of the three-level uninterruptible power supply, and facilitate its instruction scheduling.

[0121] It should be noted that another embodiment of the present invention is a DC bus voltage stabilization control system based on a three-level uninterruptible power supply, and its implementation technical means are the same as the DC bus voltage stabilization control method based on a three-level uninterruptible power supply, so it will not be described in detail here.

[0122] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be noted that the scope of the method and device in the embodiment of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0123] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods of each embodiment of the present application.

[0124] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose and technical requirements of the present application, all of which are within the protection of the present application.

[0125] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0126] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and purpose of the present application, and that the scope of the present application is defined by the technical requirements and their equivalents.

Claims

1. A DC bus voltage stabilization control method based on three-level uninterruptible power supply, characterized in that: The method includes: Monitoring the voltage value of the DC bus; Based on the monitored voltage value of the DC bus, allocating a voltage regulation response instruction to the transmission line of the DC bus; If the voltage of the Class A circuit is detected to be stable, allocating the regulation response instruction as the first regulation; If the voltage of the Class A circuit is detected to be unstable and the voltage of the Class B circuit is stable, allocating the regulation response instruction as the second regulation; If the voltages of the Class A and Class B circuits are detected to be unstable and the voltage of the Class D circuit is stable, allocating the regulation response instruction as the third regulation; If the voltages of the Class A, Class B, and Class D circuits are detected to be unstable, allocating the regulation response instruction as the fourth regulation; If the regulation response instruction allocated based on the monitored voltage value of the DC bus is the first regulation, maintaining the Class A power supply; continuously monitoring the power supply connection status of the Class B and Class D, and marking it as a stable state; If the regulation response instruction allocated based on the monitored voltage value of the DC bus is the second regulation, disconnecting the Class A power supply; maintaining the Class B power supply, continuously monitoring the power supply connection status of the Class D, and marking it as a stable state; If the regulation response instruction allocated based on the monitored voltage value of the DC bus is the third regulation, disconnecting the Class A and Class B power supplies; maintaining the Class D power supply; Based on the collected voltage value and the voltage value status, performing real-time circuit fluctuation state calibration: If the voltage difference between the voltage value at any current moment and the normal voltage is within △An, continuously obtain the next moment of the current moment. (1) If the next moment is detected to be within △Wen and △An, calibrate the circuit as safe; (2) If the next moment is detected to be within △Wei, further obtain the state of the second next moment: (1) If the second next moment is detected to be within △Wen and △An, calibrate the circuit as safe; (2) If the second next moment is detected to be within △Wei, calibrate the circuit as a warning; (3) If the second next moment is detected to be within △Bo and △An, calibrate the circuit as acceptable fluctuation; being within △Wen means the voltage difference between two adjacent moments is within the stable threshold △Wen, being within △Bo means the voltage difference between two adjacent moments is not within the stable threshold △Wen, being within △An means the voltage difference between any moment and the normal voltage is within the safety threshold △An, and being within △Wei means the voltage difference between any moment and the normal voltage is not within the safety threshold △An; (3) If the next moment is detected to be within △Bo and △An, further obtain the state of the second next moment: (1) If the second next moment is detected to be within △An, calibrate the circuit as safe; (2) If the second next moment is detected to be within △Wen and △Wei, calibrate the circuit as acceptable fluctuation; (3) If the second next moment is detected to be within △Bo and △Wei, calibrate the circuit as a warning; Calibrate the circuit voltage state according to the voltage differences between the voltage values at multiple moments and the normal voltage and the voltage differences between adjacent moments, and determine the circuit voltage stable state based on the circuit voltage calibration results at multiple moments.

2. The method for controlling the DC bus voltage stability of a three-level uninterruptible power supply according to claim 1, characterized in that: The method for monitoring the voltage value of the DC bus includes the following: Continuously collect the voltage values of the circuit sections of the Class A, Class B, and Class D power supplies respectively, and generate and output a continuous line graph of the collected continuous interval voltage values and the corresponding moments; Set image analysis time points, t1, t2,..., ti, where t2 - t1 = t3 - t2 =...... = ti - t(i - 1); Based on the image analysis time points, obtain a line graph image with an observation time range of t1 ± △t, where |t2 - t1| < △t; Traverse all the collected voltage values in the current observation time domain, and obtain the voltage differences and corresponding voltage values at any two adjacent moments: If the voltage difference between two adjacent moments is within the stable threshold Δstable, it is marked as a stable state once; If the voltage difference between two adjacent moments is not within the stable threshold Δstable, it is marked as a fluctuation once and recorded as Δwave; If the voltage difference between the voltage value at any moment in the observation time domain and the normal voltage is within the safety threshold Δsafe, it is marked as a safe state once; otherwise, it is marked as a dangerous state Δdanger; Repeat the above steps until all voltage values within the observation time domain of t1±Δt are collected and all the states of the collected voltage values are marked.

3. The method for controlling the DC bus voltage stability of a three-level uninterruptible power supply according to claim 2 is characterized in that: Based on all the circuit fluctuation state calibrations, count all the acceptable fluctuation situations within the observation time domain of t1±Δt; Based on the statistics of all the acceptable fluctuation situations, calculate the time difference between any two adjacent times marked as acceptable fluctuations: if the time difference is less than the preset threshold, increase the number of circuit early warning times within the observation time domain of t1±Δt by 1; Suppose that within the time range with t1±Δt as the observation time domain, the number of times marked as circuit early warning exceeds the stable circuit limit range, then mark that the circuit voltage within the observation time domain of t1±Δt is unstable and there are large fluctuations; If it does not exceed the stable circuit limit range, mark that the circuit voltage within the current observation time domain is stable.

4. A DC bus voltage stabilization control method based on three-level uninterruptible power supply according to claim 3, characterized in that: Based on all the image analysis time points, obtain the marked results of the time domain circuit voltages corresponding to all the image analysis time points. If the number of observation time domains marked with unstable circuit voltages exceeds the calibration coefficient, mark the current circuit voltage as unstable; otherwise, mark it as stable.

5. The DC bus voltage stabilization control method based on three-level uninterruptible power supply according to claim 1 is characterized in that: The monitoring of the voltage value of the DC bus also includes monitoring the power supply status of the transmission line. The specific method is as follows: Suppose the main power supply of the DC bus is level A, and the connection endpoints from the detection end to the load are A1 and A2 respectively; multiple level B power supplies are connected to the bus respectively, marked as B1, B2,..., Bm; The detection section from the DC bus to the load is level C; any level B power supply is composed of multiple level D power supplies, marked as D1, D2,..., Dn; suppose any fault falling on the A1A2 section is ErrA, any fault falling on the DC bus connection section of level B is ErrB, and any fault falling on the bus connection load section is ErrC; Suppose the transmission speed parameters of any fault in the power supply system are Vli and Vze respectively. Vli and Vze are the transmission speeds of the traveling wave line mode and zero mode components of any fault on the transmission line respectively. T1li and T1ze are the power consumption times for the intersection fault point to transmit electrical energy to level A based on the transmission speeds Vli and Vze respectively. T2li and T2ze are the power consumption times for the intersection fault point to transmit electrical energy to level B based on the transmission speeds Vli and Vze respectively. T3li and T3ze are the power consumption times for the intersection fault point to transmit electrical energy to level C based on the transmission speeds Vli and Vze respectively; Calculate the time differences for any intersection fault point to reach different detection ends based on the transmission speeds Vli and Vze as follows: δ1 = T1ze - T1li; δ2 = T2ze - T2li; δ3 = T3ze - T3li.

6. A DC bus voltage stabilization control method based on three-level uninterruptible power supply according to claim 5, characterized in that: TAli and TAze are the time consumed by any fault point in the interval to reach level A based on the transmission speeds Vli and Vze, TBli and TBze are the time consumed by any fault point in the interval to reach level B based on the transmission speeds Vli and Vze, and TCli and TCze are the time consumed by any fault point in the interval to reach level C based on the transmission speeds Vli and Vze; The time difference between the fault point in any interval and the corresponding detection end based on the transmission speed Vli and Vze is calculated as: δErrA=TAze-TAli; δErrB=TBze-TBli; δErrC=TCze-TCli; Based on the above, the ErrA fault point is constructed based on the time difference calculation formula of the transmission speed Vli and Vze to different detection ends: δErrA==TAze-TAli=(T1ze-TErrAze)-(T1li-TErrAli)=(T1ze-T1li)+(TErrAli-TErrAze); δErrB==TBze-TBli=(T2ze+TErrAze)-(T2li+TErrAli)=(T2ze-T2li)+(TErrAze-TErrAli); δErrC==TCze-TCli=(T3ze+TErrAze)-(T3li+TErrAli)=(T3ze-T3li)+(TErrAze-TErrAli); Among them, TErrAli and TErrAze are the time from ErrA to the intersection point based on the transmission speeds Vli and Vze respectively; Based on the parameter values ​​of TErrAli and TErrAze, the relationship between the time difference between any interval fault point and any intersection fault point is obtained as follows: ErrA: δErrA<δ1; δErrB>δ2; δErrC>δ3.

7. A DC bus voltage stabilization control method based on three-level uninterruptible power supply according to claim 6, characterized in that: Repeat the above steps to construct the time difference calculation formulas from the ErrB and ErrC fault points to different detection ends based on the transmission speeds Vli and Vze, and then obtain the relationship between the time difference between any interval fault point and any intersection fault point corresponding to the ErrB and ErrC fault points based on the calculation formulas, which are: ErrB: δErrA>δ1; δErrB<δ2; δErrC>δ3; ErrC: δErrA>δ1; δErrB>δ2; δErrC<δ3.

8. A computer-readable storage medium storing one or more programs, characterized in that: The one or more programs include instructions which, when executed by a computing device, cause the computing device to perform any one of the methods according to claims 1 to 7.

9. A computing device, characterized in that The method comprises one or more processors, a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for executing any one of the methods according to claims 1 to 7.

Images