Semiconductor device, circuit board, and method for manufacturing semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, a circuit board and a method for manufacturing the semiconductor device, wherein the semiconductor device and the circuit board can prevent accidental short circuit between wiring lines of the circuit board. According to one embodiment, a semiconductor device includes: a circuit board having a first surface and a second surface facing each other; a memory chip disposed on the first surface; a capacitor connected via solder to a pad provided on the first surface; a sealing resin covering the first surface and the surfaces of the memory chip and the capacitor; and a solder ball disposed on the second surface. A trench is formed on the first surface along at least a portion of the peripheral edge of the pad, and a plating layer is formed on the inner wall of the trench.

Description

[0001] Related Applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-155486 (filing date: September 21, 2023). This application incorporates all the contents of the basic application by reference. Technical Field

[0003] The present embodiment relates to a semiconductor device, a circuit board, and a method for manufacturing the semiconductor device. Background Art

[0004] A semiconductor device has been proposed in which passive components such as capacitors are provided on a circuit board together with a semiconductor chip. Summary of the invention

[0005] The problem to be solved by the present invention is to provide a semiconductor device and a circuit board, and a method for manufacturing the semiconductor device, which are capable of preventing an unintended short circuit between wirings formed on a circuit board.

[0006] The semiconductor device of this embodiment comprises: a circuit board having a first surface and a second surface located on the opposite side to the first surface; a semiconductor chip provided on the first surface of the circuit board; a passive component connected to an electrode provided on the first surface of the circuit board via solder; a sealing resin covering the first surface of the circuit board and the surfaces of the semiconductor chip and the passive component; and a terminal for connecting to an external device provided on the second surface of the wiring substrate. A groove is formed on the first surface along at least a portion of the periphery of the electrode, and a plating layer is formed on the inner wall of the groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment.

[0008] Figure 2 This is a diagram for explaining an example of the arrangement of memory chips and capacitors mounted on a circuit board.

[0009] Figure 3 This is a cross-sectional view illustrating an example of a circuit board according to an embodiment.

[0010] A in Figure 4 is an illustration Figure 3 A diagram showing the manufacturing steps of a circuit board.

[0011] B in Figure 4 is a diagram showing Figure 3 A diagram showing the manufacturing steps of a circuit board.

[0012] C in Figure 4 is a Figure 3 A diagram showing the manufacturing steps of a circuit board.

[0013] D in Figure 4 is a Figure 3 A diagram showing the manufacturing steps of a circuit board.

[0014] E in Figure 4 is an illustration Figure 3 A diagram showing the manufacturing steps of a circuit board.

[0015] F in Figure 4 is an illustration Figure 3 A diagram showing the manufacturing steps of a circuit board.

[0016] G in Figure 4 is a Figure 3 A diagram showing the manufacturing steps of a circuit board.

[0017] H in Figure 4 is a Figure 3 A diagram showing the manufacturing steps of a circuit board.

[0018] The I in Figure 4 indicates Figure 3 A diagram showing the manufacturing steps of a circuit board.

[0019] Figure 5 This is a cross-sectional view illustrating another example of the circuit board according to the embodiment.

[0020] Figure 6 This is a flowchart illustrating an example of a manufacturing process of a semiconductor device according to an embodiment.

[0021] A in Figure 7 is the Figure 2 An enlarged top view of the rectangular area B surrounded by the dotted line.

[0022] FIG. 7B is a cross-sectional view taken along line CC' of the circuit board shown in FIG. 7A.

[0023] FIG. 7C is a cross-sectional view taken along line DD' of the circuit board shown in FIG. 7A.

[0024] FIG. 7D is a cross-sectional view taken along line CC' of the circuit board shown in FIG. 7A, showing the cross section after the reflow process.

[0025] Figure 8 7 is another cross-sectional view taken along the line CC' of the circuit board shown in A in FIG. 7 . DETAILED DESCRIPTION

[0026] Hereinafter, embodiments will be described with reference to the drawings.

[0027] In the following description, an example of an orthogonal coordinate system is used, namely, the XYZ coordinate system. That is, a plane parallel to the surface of the circuit board 2 constituting the semiconductor device 1 is set as the XY plane, and a direction orthogonal to the XY plane is set as the Z axis. In addition, the X axis and the Y axis are set as two orthogonal directions in the XY plane. In addition, although the following uses the relative up-down relationship of setting the positive direction side of the Z axis (the surface where the semiconductor chip is set) as the upper side to explain the up-down direction of the wiring substrate for the sake of convenience, it does not mean the up-down relationship according to the vertical direction.

[0028] Figure 1 1 is a cross-sectional view illustrating an example of a semiconductor device according to an embodiment. Figure 1 The cross-sectional structure of a semiconductor device of an embodiment is schematically shown, and the ratios between the constituent elements are different from the actual ratios. The semiconductor device 1 of the embodiment is, for example, a semiconductor package in which a semiconductor chip or passive components mounted on a wiring substrate are sealed with a mold resin. The semiconductor device 1 includes a circuit board 2, a NAND flash memory chip (hereinafter referred to as a memory chip) 3 as a semiconductor chip, a capacitor 4 as a passive component, a solder ball 5, and a mold resin 6. The mold resin 6 is an example of a sealing resin. In addition, the semiconductor device 1 may also include passive components other than the capacitor 4, such as a resistor element or a coil. In addition, the semiconductor device 1 may also include a semiconductor chip other than the memory chip 3, such as a controller chip.

[0029] The circuit board 2 is, for example, an insulating resin circuit board or a ceramic circuit board with a wiring layer provided on the surface or inside. The circuit board 2 has a first surface 2s and a second surface 2b. A memory chip 3 and a capacitor 4 are provided on the first surface 2s. The memory chip 3 is physically bonded to the first surface 2s via a film adhesive 31. The film adhesive 31 is a non-conductive tape adhesive containing a resin adhesive component containing a thermosetting resin (for example, an epoxy resin, a polyimide resin, an acrylic resin, or a resin mixed therewith). The film adhesive 31 makes objects attached above and below it closely adhere by applying heat and load. The memory chip 3 is electrically connected to the wiring layer via a pad 32 provided on the circuit board 2 using a conductive wire 33 or the like. The capacitor 4 is physically and electrically connected to a pad 80 provided on the first surface 2s of the circuit board 2 via a solder 41. Lead-free solder is used for the solder 41. For example, it has a composition with Sn (tin) as the main component and Ag (silver) or Cu (copper) added (Su-Ag-Cu). In addition, in the case of a composition with Sn as the main component, the solder 41 may also have a composition with Bi (bismuth) added (Sn-Bi), a composition with Zn (zinc) added (Sn-Zn), or a composition with Ag added (Sn-Ag). Solder balls 5 serving as external terminals for BGA (Ball Grid Array) packaging are formed on the second surface 2b. The solder balls 5 are an example of terminals for connecting external devices. The solder balls 5 are physically and electrically connected to the solder joints 90 provided on the second surface 2b of the circuit board 2.

[0030] Figure 2 This is a diagram for explaining an example of the arrangement of memory chips and capacitors mounted on a circuit board. Figure 2 This is a top view of the circuit board on which the memory chip and the capacitor are arranged, viewed from above the first surface (positive side in the Z direction). Figure 1 The semiconductor device 1 is shown in Figure 2 The cross section is taken when the portion is cut at the position indicated by AA'.

[0031] like Figure 2 As shown, a memory chip 3 and a capacitor 4 are mounted on a circuit board 2. The memory chip 3 is a thin plate having a rectangular shape in a plane. The memory chip 3 is arranged on the first surface 2s of the circuit board 2 so that the thickness direction of the thin plate is parallel to the Z direction.

[0032] The capacitor 4 has a rectangular parallelepiped shape. The capacitor 4 is arranged on the first surface 2s of the circuit board 2 in such a manner that the bottom surface faces the first surface 2s. The capacitor 4 is arranged at a predetermined distance so as not to overlap with the memory chip 3 in the Z direction. In the capacitor 4, a pair of external electrodes 4a are formed on a pair of faces (hereinafter referred to as end faces) that are perpendicular to the bottom surface and opposite to the long side direction of the bottom surface.

[0033] Next, use Figure 3 The structure of the circuit board 2 will be described. Figure 3 1 is a cross-sectional view illustrating an example of a circuit board according to an embodiment of the present invention. Figure 3 Indicates that Figure 2 The circuit board 2 is a cross-sectional view of a circuit board with a memory chip and a capacitor arranged therein, cut along line EE'. The circuit board 2 has an internal circuit IC and an external circuit OC.

[0034] The external circuit OC is composed of wiring layers L1 and L3 formed on the first surface 2s or the second surface 2b. In the wiring layer L1 formed on the first surface 2s, there are formed pads 32 electrically connected to the terminals 34 of the memory chip 3, pads 80 electrically connected to the capacitor 4, etc. In addition, wiring 60a is formed in the wiring layer L1. The wiring 60a also includes wiring that electrically connects the pads 32 connected to the terminals 34 of the memory chip 3 and the pads 80 electrically connected to the capacitor 4. The surface of the wiring layer L1 is covered with a solder resist 70. In addition, in order to expose the surface of the pad 80, an opening is provided in the solder resist 70. Under the wiring layer L1, an internal circuit IC is formed through a prepreg layer 50. A groove TT is formed in the prepreg layer 50. The groove TT is formed to capture solder particles that are not expected to fly when the solder 41 is formed on the upper surface of the pad 80. Therefore, the groove TT is formed near the periphery of the pad 80, which is a portion where solder particles are likely to scatter. Figure 3 As an example, a structure in which a trench TT is formed between two pads 80 is shown. A plating layer 100 is formed on the inner wall of the trench TT. The plating layer 100 can prevent solder particles captured in the trench TT from penetrating into the prepreg layer 50 and reaching the wiring layer L2.

[0035] The internal circuit IC is composed of a multilayer wiring layer formed by laminating a plurality of wiring layers L2. Figure 3 As an example, an internal circuit IC formed by stacking two wiring layers L2 is shown. The pad 80 or wiring 60a formed on the wiring layer L1 is electrically connected to the wiring 20a formed on the wiring layer L2 via a conductive hole not shown. A core layer 10 is formed between the wirings 20a and 20b stacked on the wiring layer L2 (between the upper and lower adjacent wirings). The core layer 10 is, for example, a hard plate-like component containing glass fiber and epoxy resin. The wirings 20a and 20b formed on the upper and lower surfaces of the core layer 10 are electrically connected via through-hole wiring not shown. In addition, in Figure 3 Although the circuit board 2 having the core layer 10 is shown in FIG. 1 , a so-called coreless circuit board may be used which does not have the core layer 10. In this case, the plurality of wirings 20a and 20b formed on the wiring layer L2 are stacked with the prepreg layer 50 interposed therebetween.

[0036] The wiring layer L3 formed on the second surface 2b is formed with a plurality of solder joints 90 or wirings 60b for electrically connecting the solder balls 5 as external terminals. The surface of the wiring layer L3 is covered with a solder resist 70. In addition, in order to expose the surfaces of all the solder joints 90, openings are provided in the solder resist 70. The wiring 20b formed on the wiring layer L2 is electrically connected to the solder joints 90 via a via hole not shown. With this configuration, the memory chip 3 is electrically connected to the solder balls 5 via various parts of the circuit board 2. In addition, a through hole TH is formed in the circuit board 2, which passes from the surface of the solder resist 70 covering the wiring layer L1 to the surface of the solder resist 70 covering the wiring layer L3.

[0037] A to I in FIG. 4 are diagrams showing Figure 3 The figure shows the manufacturing steps of the circuit board shown in FIG4. First, as shown in A in FIG4, the copper foil 201 is attached to the upper and lower surfaces of the core layer 10 and heated and pressed. In this way, the circuit board with the copper foil attached to the upper and lower surfaces of the core layer is called a copper clad laminate (CCL). Copper clad laminates are widely used in internal circuits.

[0038] Next, a photoresist 30 is applied to the surface of the copper foil 201 attached to the upper surface of the core layer 10. A template 40 on which a wiring pattern of an internal circuit IC is formed is arranged above the photoresist 30. Ultraviolet light (UV) is irradiated from above the template 40 using a UV (Ultraviolet) light source (high pressure mercury lamp, etc.) not shown in the figure, and the wiring pattern of the internal circuit IC to be formed on the template 40 using the photolithography technology is transferred to the photoresist 30 as shown in B of FIG.

[0039] Next, the patterned photoresist 30 is used as a mask to etch the copper foil 201 using an anisotropic etching technique. After the etching is completed, the photoresist 30 is immediately removed using a cleaning technique to complete the formation of the wiring 20a as shown in C in FIG. 4. The copper foil 201 on the lower surface of the core layer 10 is also processed using photolithography and anisotropic etching techniques to form wiring 20b as shown in D in FIG. 4.

[0040] Next, the copper foil 201 is bonded to the surface of the wiring 20a, 20b via the prepreg layer 50. The prepreg constituting the prepreg layer 50 is a semi-cured resin sheet containing a resin in glass fiber. The copper clad laminate is sandwiched between the upper and lower parts by the prepreg layer 50, so that the copper foil 201 overlaps with the surface of each prepreg layer 50. In this state, when these laminates are heated and pressurized from the upper and lower parts, the prepreg hardens, and as shown in E in FIG. 4, the copper clad laminate can be bonded to the copper foil 201.

[0041] Next, the copper foil 201 bonded to the upper surface of the prepreg layer 50 is processed using photolithography technology and anisotropic etching technology to form wiring 60a and pads 80. In addition, the copper foil 201 bonded to the lower surface of the prepreg layer 50 is processed using photolithography technology and anisotropic etching technology to form wiring 60b and solder joints 90 as shown in F in FIG. 4 .

[0042] Next, a solder resist 70 is formed as a protective film on the surface of the external circuit OC, that is, the wiring layers L1 and L3. For example, a sheet of solder resist is attached, and ultraviolet rays are irradiated only on the cured portion using photolithography technology. Then, an anisotropic etching technology is used to remove the uncured portion. That is, as shown in G in FIG. 4 , the solder resist covering the surface of the pad 80 or the solder joint 90 is removed, and the solder resist 70 is processed in a manner to form an opening.

[0043] Next, a through hole TH is formed that penetrates from the surface of one solder resist 70 to the surface of another solder resist 70. A through hole TH is formed using a micro-machining drill. When forming the through hole TH of the circuit board 2, a groove TT is also formed as shown in H in FIG. 4. A micro-machining drill is used to form a groove TT at a position at a predetermined distance from the pad 80. The groove TT is formed to a depth that does not penetrate the prepreg layer 50 and does not reach the wiring layer L2. The position or shape of the groove TT will be described in detail later.

[0044] Next, as shown in I in FIG. 4 , the inner wall of the groove TT is plated to form a coating 100. The plating uses a material (e.g., Ni (nickel)) with low wettability to the solder. Since Ni cannot be directly plated on the prepreg layer 50, Ni plating is performed using palladium as a catalyst. Specifically, first, the upper surface of the first surface 2s is covered by an unillustrated mask having an opening in the groove TT forming region, and a dilute palladium solution is applied to the inner wall of the groove TT using a sputtering technique or the like. The dilute palladium solution may also be immersed in the groove TT. Then, using an electroless plating method, Ni is plated on the inner wall of the groove TT. In addition, the material forming the coating 100 only needs to have low wettability to the solder, for example, materials other than Ni such as Cr (chromium) may also be used. The thickness of the coating 100 formed in this way is, for example, about 3 μm. After Ni plating, the unillustrated mask is removed, the interior of the groove TT is cleaned, and the palladium solution is completely removed. When the palladium solution remains in the trench TT, Cu (copper) may be precipitated on the surface of the plated layer 100 formed of Ni, thereby increasing the wettability to solder. To prevent this, cleaning is required after plating.

[0045] Finally, the inner wall of the through hole TH is plated with a material such as Cu (copper) to form a plating layer 110, and the process is completed. Figure 3 The production of the circuit board 2 is shown.

[0046] Figure 5 2 is a cross-sectional view of another example of a circuit board for explaining an embodiment. In the method, when an opening is formed in the solder resist 70 on the first surface 2s side so that the surface of the pad 80 is exposed, the solder resist 70 is processed in such a way that the size of the opening is larger than the size of the pad 80 (see Figure 3 , G in Figure 4). In contrast, Figure 5 As shown, the opening may be formed smaller than the size of the pad 80, and the solder resist 70 may be processed so that a portion of the solder resist 70 covers the upper surface of the pad 80. Figure 5 In the case of the structure shown, the groove TT is also formed to a depth that does not penetrate the prepreg layer 50 and does not reach the wiring layer L2.

[0047] Next, a method for manufacturing the semiconductor device 1 according to the embodiment will be described. Figure 6 1 is a flowchart for explaining an example of a manufacturing step of a semiconductor device according to an embodiment. First, a capacitor 4 is soldered to a pad 80 formed on a circuit board 2 (S1). In S1, first, solder paste is applied to the first surface 2s of the circuit board 2 using a method such as scraper printing to form solder 41 on the pad 80. For example, if the release of scraper printing is poor, solder particles may fly from the solder paste and adhere to an undesired location other than the pad 80.

[0048] A in Figure 7 is the Figure 2 FIG. 7 is an enlarged top view of a rectangular area B surrounded by a dotted line. FIG. 7A shows a state before the capacitor 4 is mounted, that is, a top view showing a point in time when the solder 41 is formed on the pad 80. The solder particles 41a are captured inside the groove TT formed between the two pads 80. Here, the shape of the groove TT is described in detail. The groove TT is formed in the gap between the two pads 80. The upper surface of the groove TT has a rectangular shape. In the direction in which the opposite sides of the two pads 80 extend (in the Y direction in FIG. 7A ), the length of the groove TT is formed to be longer than the length of the pad 80.

[0049] B in FIG. 7 is a cross-sectional view along the line CC' of the circuit board shown in A in FIG. 7. In addition, C in FIG. 7 is a cross-sectional view along the line DD' of the circuit board shown in A in FIG. 7. In addition, B in FIG. 7 and C in FIG. 7 show the structure above the wiring layer L2. As shown in B in FIG. 7, the groove TT is formed between the two opposite sides of the two pads 80 in the X direction. The two sides extending in the Y direction in the groove TT are respectively formed at positions that are a distance L1 away from the two opposite sides of the two pads 80. If the diameter of the scattered solder particles 41a is set to the length Ds, the distance L1 is preferably less than half of the length Ds. This is because, by setting the distance between the groove TT and the pad 80 to be less than the radius of the solder particles 41a, even if the solder particles 41a are scattered to the prepreg layer 50 located between the pad 80 and the groove TT in the X direction, they are easy to roll down to the inside of the groove TT, and the possibility of the groove TT capturing the solder particles 41a becomes high.

[0050] As shown in B of FIG. 7 and C of FIG. 7 , the width of the groove TT is formed in a manner that is non-uniform in the depth direction (Z direction) and becomes narrower as the depth increases. In addition, the bottom of the groove TT may be a planar shape, but is preferably a curved shape that bulges downward. By setting it to such a shape, the solder particles 41a that roll into the groove TT are captured in the center of the bottom of the groove TT, and the possibility of escaping from the groove TT can be reduced. In this way, by providing the groove TT, the solder particles 41a can be prevented from scattering to the upper surface of the solder resist 70 or the upper surface of the prepreg layer 50, and an undesirable short circuit in the wiring layer L1 can be prevented.

[0051] After the solder 41 is formed on the pad 80, each of the pair of electrodes 4a formed on the capacitor 4 is aligned with the solder 41 formed on the pair of pads 80. Then, reflow is performed to fix the solder 41 to the capacitor 4. In the reflow, the solder 41 is heated and melted and then cooled, so that the capacitor 4 is fixed to the pad 80 with the solder 41 as an adhesive. D in FIG. 7 is a cross-sectional view along the line C-C' of the circuit board shown in A in FIG. 7, showing the cross-section after the reflow treatment. By heating the solder 41 in the reflow treatment, the solder particles 41a that are scattered and captured in the groove TT are also melted. The molten solder particles 41a may penetrate into the prepreg layer 50 and reach the wiring layer L2.

[0052] However, a plating layer 100 having low wettability to solder particles 41a such as Ni is formed on the inner wall of the groove TT. Therefore, as shown in D in FIG. 7 , even when the solder particles 41a melt, the plating layer 100 can prevent them from penetrating into the prepreg layer 50. Therefore, an unexpected short circuit between the wiring layers L1 and L2 caused by the scattered solder particles 41a can be prevented. As described above, when a lead-free solder having Sn as the main component is used as the solder, the wettability of Ni to the solder is reduced due to Sn. Therefore, regardless of the constituent components added to Sn, the plating layer 100 can prevent the solder particles 41a from penetrating into the prepreg layer 50.

[0053] In order to prevent the solder particles 41a captured in the trench TT from being scattered outside the trench TT again, the shape of the trench TT may be set as follows: Figure 8 Shape as shown. Figure 8 This is another cross-sectional view along the line CC' of the circuit board shown in A in FIG7. The groove TT is formed in such a way that the width of the groove TT widens as the depth increases from the entrance of the groove TT to a predetermined depth. When the predetermined depth is exceeded, the width of the groove TT is formed in such a way that the width narrows as the depth increases, similar to B in FIG7. That is, a so-called return structure TTa is provided at the entrance of the groove TT. By providing the return structure TTa, it is possible to further suppress the solder particles 41a captured in the groove TT from being scattered again, and it is possible to further prevent an unexpected short circuit.

[0054] Return to Figure 6 In the process, after the capacitor 4 is physically and electrically connected to the pad 80 in S1, the memory chip 3 is bonded to the first surface 2s of the circuit board 2 (S2). S2 is a step called die bonding. A specified area of ​​the first surface 2s of the circuit board 2 is bonded to the back of the memory chip 3 using a film adhesive 31 such as a die attach film (DAF). Next, the circuit board 2 is heated in an oven to cure the film adhesive 31. In addition, a metal wire 33 such as gold (Au) is used to connect the terminal 34 of the memory chip 3 to the pad 32 formed on the wiring layer L1 of the circuit board 2 (S3). S3 is a step called wire bonding.

[0055] Next, the circuit board 2 is sealed with resin (S4). S4 is a so-called molding step. In S4, since the groove TT is also filled with the mold resin 6, the captured solder particles 41a are fixed in the groove TT. Next, the external terminal, that is, the solder ball 5, is bonded to the solder joint 90 formed in the wiring layer L3 of the circuit board 2 using a conductive adhesive such as solder paste. Then, the circuit board 2 is heated by a reflow process to fix the solder joint 90 to the solder ball 5 (S5). By implementing the above steps, the semiconductor device 1 of the embodiment is manufactured.

[0056] Thus, according to the present embodiment, the groove TT is formed along the pad 80 formed on the first surface 2s of the circuit board 2. With this structure, when the solder 41 is formed on the upper surface of the pad 80, even if a part of the solder 41 becomes particulate and scatters to a place outside the pad, it can be captured in the groove TT. Therefore, it is possible to prevent an accidental short circuit in the wiring layer L1. In addition, a plating layer 100 using a metal with low wettability to the solder 41 is formed on the inner wall of the groove TT. Therefore, even if a heat treatment such as reflow is performed and the solder 41 is melted, it is possible to prevent the solder 41 from penetrating into the wiring layer L2 below the groove TT, and it is also possible to prevent an accidental short circuit in the wiring layer L2 or between the wiring layers L1 and L2.

[0057] In addition, the wiring layers stacked on the circuit board 2 are not limited to 4 layers. The circuit board 2 can be composed of only the external circuit OC, that is, only two layers of wiring layers L1 and L3, or it can be composed of more than five layers of wiring layers. In addition, although the groove TT is formed in the gap between a pair of pads 80, the groove TT can also be formed in a manner corresponding to each side of the pad 80. For example, the groove TT can be formed in a manner surrounding the pad 80. In addition, in the case of connecting electronic components such as the memory chip 3 to the pad using solder as in the flip chip method, the groove TT can also be formed relative to the pad that electrically connects the electronic component to the circuit board 2.

[0058] Although the embodiments of the present invention have been described, the embodiments are shown as an example and are not intended to limit the scope of the invention. These new embodiments can be implemented in many other ways, and can be omitted, replaced, and changed in many ways without departing from the scope of the invention. These embodiments or their variations are included in the scope or purpose of the invention, and are included in the invention recorded in the scope of the patent application and its equivalent.

[0059] [Explanation of Symbols]

[0060] 1 Semiconductor devices

[0061] 2 Circuit Board

[0062] 2s 1st surface

[0063] 2b Surface 2

[0064] 3 Memory chips

[0065] 4 Capacitors

[0066] 5 Solder balls

[0067] 6. Mold resin

[0068] 41 Solder

[0069] 80 pads

[0070] TT Groove.

Claims

1. A semiconductor device comprising A circuit board having a first surface and a second surface located on the opposite side to the first surface; a semiconductor chip disposed on the first surface of the circuit board; a passive component connected to an electrode disposed on the first surface of the circuit board via solder; a sealing resin covering the first surface of the circuit board, the semiconductor chip, and the surface of the passive component; and a terminal for connecting to an external device disposed on the second surface of the circuit board; and A groove is formed on the first surface along at least a portion of the periphery of the electrode, A plating layer is formed on the inner wall of the groove.

2. The semiconductor device according to claim 1, wherein Two of the electrodes are disposed on the first surface; and The groove is formed between the two electrodes.

3. The semiconductor device according to claim 2, wherein The passive component is a capacitor having two external electrodes; and The two electrodes are connected to each of the two external electrodes.

4. The semiconductor device according to claim 1, wherein The plating layer is formed of a metal material having low wettability with respect to the solder.

5. The semiconductor device according to claim 4, wherein The metal material is nickel.

6. The semiconductor device according to claim 1, wherein The groove is formed in such a manner that the width becomes narrower as the depth increases.

7. The semiconductor device according to claim 1, wherein The solder is attached to the inner wall of the groove.

8. A circuit board comprising a first surface and a second surface located on the opposite side of the first surface, wherein electrodes capable of being electrically connected to passive components are formed on the first surface; and A groove is formed on the first surface along at least a portion of the periphery of the electrode; A plating layer is formed on the inner wall of the groove.

9. The circuit board according to claim 8, wherein Two of the electrodes are disposed on the first surface; and The groove is formed between the two electrodes.

10. The circuit board according to claim 8, wherein An internal circuit is formed between the first surface and the second surface; and The depth of the groove is shallower than the depth from the first surface to the internal circuit.

11. The circuit board according to claim 8, wherein The plating layer is formed of a metal material having low wettability to tin.

12. The circuit board according to claim 11, wherein The metal material is nickel.

13. A method for manufacturing a semiconductor device, comprising: A circuit board having a first surface and a second surface located on the opposite side of the first surface, wherein an electrode electrically connected to a passive component is formed on the first surface, a groove is formed on the first surface along at least a portion of the periphery of the electrode, and a plated layer is formed on an inner wall of the groove, bonding the passive component to the electrode using solder; electrically connecting the circuit board to the semiconductor chip; Covering the first surface of the circuit board, the semiconductor chip, the surface of the passive component and the inside of the groove with a sealing resin; and The external device connection terminal is connected to the second surface of the circuit board using a conductive adhesive.

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