Method for automatically keeping startup and shutdown time delay of launching channel of low earth orbit satellite navigation

Abstract

The invention discloses a low-orbit satellite navigation launching channel startup and shutdown time delay automatic keeping method, and belongs to the field of satellite navigation. The method comprises the following steps: starting a satellite, and measuring coarse time delay of a transmitting channel; measuring fine time delay of a transmitting channel; repeatedly measuring for multiple times, and calculating an average value of the time delays of the transmitting channels; calculating a time delay to-be-adjusted amount according to a measurement result; time delay coarse adjustment is completed according to the time delay to-be-adjusted amount; time delay fine adjustment is completed according to the time delay to-be-adjusted amount, and it is ensured that the time delay of the transmitting channel is consistent when the transmitting channel is started each time. The method can ensure that the time delay of the navigation transmitting channel is kept stable after the satellite is turned on and off each time, and provides guarantee for realizing accurate positioning of a satellite navigation system.

Description

Technical Field

[0001] The invention relates to a transmission channel delay maintenance technology in the field of satellite navigation, and in particular to a method for automatically maintaining a power-on / off delay of a low-orbit satellite navigation transmission channel. Background Art

[0002] The satellite navigation system achieves positioning by measuring the distance between the satellite and the ground. The delay of the navigation satellite transmission channel will affect the distance measurement between the satellite and the ground. Maintaining a stable transmission channel power-on and power-off delay is an important prerequisite for the satellite navigation system to achieve precise positioning applications.

[0003] At present, the main function of low-orbit satellites with the ability to transmit navigation signals is communication, and the hardware is not designed specifically for navigation signals. Every time the satellite is turned on and off, the clock phase on the satellite (relative to the 1PPS pulse per second) may change, causing the transmission channel delay on the satellite. It will also change every time the satellite is turned on, thus affecting the positioning accuracy of the navigation system. Summary of the invention

[0004] The purpose of the present invention is to avoid the shortcomings of the above-mentioned background technology and provide a method for automatically maintaining the power-on and power-off delay of the low-orbit satellite navigation transmission channel. The present invention adopts a method of automatically detecting and adjusting the transmission channel delay after powering on, ensuring that the transmission channel delay is consistent each time the power is turned on, providing a guarantee for the satellite navigation system to achieve accurate positioning.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is:

[0006] A method for automatically maintaining the power-on and power-off delay of a low-orbit satellite navigation transmission channel comprises the following steps:

[0007] Step 1: Turn on the satellite and measure the coarse delay of the transmission channel;

[0008] Step 2, measure the precise delay of the transmission channel and calculate the total transmission delay of the transmission channel;

[0009] Step 3, repeating steps 1 and 2, measuring the total transmission delay multiple times, and taking the average value of the multiple measurements as the delay measurement result;

[0010] Step 4, calculating the delay amount to be adjusted according to the delay measurement result;

[0011] Step 5, completing the coarse adjustment of the delay according to the delay to be adjusted;

[0012] Step 6: Complete the delay fine adjustment according to the delay to be adjusted.

[0013] Furthermore, the specific method of step 1 is:

[0014] When the rising edge of the second pulse signal ext_PPS provided by the external time and frequency equipment arrives, the counting is started, and the count is increased by 1 when each rising edge of the system clock sys_clk is detected. When the rising edge of the second pulse signal int_PPS generated inside the navigation transmission channel is detected, the counting is stopped to obtain the coarse delay measurement value t1:

[0015] t1=n*T sysclk

[0016] Among them, T sysclk Represents the system clock cycle, and n represents the number of counts.

[0017] Furthermore, the specific method of step 2 is:

[0018] Using the tapped delay line time-to-digital conversion circuit of FPGA, delay units with the same delay time of τ are cascaded into a linear delay chain, and a tap is drawn out after each delay unit to input into the trigger array;

[0019] The second pulse signal ext_PPS provided by the external time-frequency device is used as the gate-opening signal start, and the first rising edge of the system clock sys_clk after the rising edge of ext_PPS is used as the gate-closing signal stop. According to the number of taps k that the rising edge of ext_PPS propagates in the delay chain when the gate-closing signal arrives, the precise delay measurement value t2 is obtained:

[0020] t2 = kτ;

[0021] Calculate the total transmission delay t of the transmission channel:

[0022] t=t1+t2.

[0023] Furthermore, in step 4, the delay amount Δt to be adjusted is:

[0024] Δt=t0-t avr

[0025] Among them, t0 is the reference delay value, t avr The delay measurement result.

[0026] Furthermore, the specific method of step 5 is:

[0027] Step 501, calculate the coarse adjustment control word code_tw according to the delay to be adjusted Δt:

[0028] code_tw=floor(Δt / T p )

[0029] Where, T p is the pseudo code clock period, that is, the minimum chip width, floor() means rounding down;

[0030] Step 502: perform coarse adjustment of the delay according to the coarse adjustment control word code_tw.

[0031] Furthermore, the specific method of step 6 is:

[0032] Step 601, calculate the delay fine adjustment value Δt j :

[0033] Δt j =Δt-floor(Δt / T p )*T p

[0034] Where Δt is the delay to be adjusted, floor() means rounding down, T p is the pseudo code clock period;

[0035] Step 602: fine-tune the delay according to Δt j , calculate the fine-tuning phase control word stw;

[0036] stw=(Δt j / T p )×2 N

[0037] Wherein, N is the bit width of the fine-tuning phase control word stw;

[0038] Step 603: perform fine adjustment of the delay according to the fine adjustment phase control word stw.

[0039] The advantages of the present invention compared with the background technology are:

[0040] 1. The present invention has the characteristic of high measurement accuracy. The present invention is based on the TDC (time to digital conversion) circuit of FPGA and uses the physical delay of the internal logic of FPGA for measurement, and the measurement accuracy can reach 13ps.

[0041] 2. The present invention has the characteristic of high adjustment accuracy. The delay adjustment accuracy is related to the bit width of the fine-tuning phase control word. The wider the bit width of the phase control word, the higher the delay adjustment accuracy. When the code clock frequency is 100MHz and the bit width of the fine-tuning phase control word is 16bit, the adjustment accuracy of the present invention can reach 0.15ps.

[0042] 3. The present invention has the characteristic of automatic adjustment, and no manual operation is required. The time delay adjustment is automatically completed after power-on. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a schematic diagram of the principle of the present invention.

[0044] Figure 2 This is a flow chart of automatic maintenance of power on / off delay.

[0045] Figure 3 This is the delay measurement principle diagram.

[0046] Figure 4 It is a schematic diagram of the structure of a tapped delay line.

[0047] Figure 5 This is the delay adjustment principle diagram. DETAILED DESCRIPTION

[0048] The present invention will be further described below in conjunction with the accompanying drawings.

[0049] A method for automatically maintaining the power-on and power-off delay of a low-orbit satellite navigation transmission channel, the implementation principle of which is as follows: Figure 1 As shown in FIG. 1 , the system mainly includes two parts: delay measurement and delay adjustment. The delay measurement part measures the transmission channel delay, and the delay adjustment part adjusts the transmission channel delay in real time according to the measured delay value, thereby realizing the delay automatic maintenance function.

[0050] like Figure 2 As shown, the specific steps of this method are as follows:

[0051] (101) After the device is powered on, the coarse delay value of the current transmission channel is measured.

[0052] The time interval between the rising edge of the second pulse (ext_PPS) provided externally by the current transmission channel and the rising edge of the second pulse (int_PPS) generated internally can be considered as the delay value t of the current transmission channel;

[0053] The delay measurement principle is as follows Figure 3 shown.

[0054] ext_PPS is the pulse per second signal provided by external time and frequency equipment, which serves as the time and frequency reference for generating navigation signals.

[0055] This pulse is not affected by the power on and off of the device;

[0056] int_PPS is a pulse-per-second signal generated inside the navigation transmission channel. The pulse is generated by dividing the pseudo-code clock. Its rising edge is aligned with sys_clk and is synchronized with ext_PPS.

[0057] The measurement of time delay t is divided into two parts, coarse measurement t1 and fine measurement t2.

[0058] The coarse measurement t1 is in units of sys_clk cycles, measuring the number of sys_clk cycles within the interval between ext_PPS and int_PPS:

[0059] t1=n*T sysclk

[0060] Among them, T sysclkrepresents the sys_clk cycle, and n represents the T contained in the measurement interval. sysclk Number.

[0061] Coarse measurement method: Start counting when the ext_PPS rising edge arrives, and add 1 for each sys_clk rising edge. Stop counting after detecting the int_PPS rising edge.

[0062] (102) Measure the precise delay value of the current transmission channel.

[0063] The precise measurement t2 measures the time interval from the rising edge of ext_PPS to the first rising edge of sys_clk. Since this interval is less than one clock cycle, it cannot be directly obtained by clock counting. Here, a time-to-digital conversion (TDC) circuit based on an FPGA tapped delay line is used.

[0064] The structure of the tapped delay line structure is as follows Figure 4 As shown, inside the FPGA, delay units with a delay time of τ are cascaded into a linear delay chain, and a tap is drawn behind each delay unit and input to the trigger array. The start signal propagates in the delay line, and when the stop signal arrives, the trigger array latches the data of each tap in the delay line. The latched data can be used to calculate the number of delay units that the start signal has passed through in the delay chain, so the time interval t2 to be measured can be expressed as:

[0065] t2=kτ

[0066] Where k represents the number of delay units through which the start signal propagates within the time interval t2, and τ represents the delay time of a single delay unit.

[0067] This method implements the design of the tap delay line by using the cascade carry chain logic unit CARRY4 inside the FPGA. Through simulation and actual measurement, the delay time between adjacent taps is about 13ps. A single CARRY4 delay unit can output 4 taps. According to the design, the precision measurement range should be greater than T sysclk , which can completely cover the time interval that cannot be measured by coarse measurement. The number of CARRY4 m required by the delay chain satisfies:

[0068] m>T sysclk / (13*4)

[0069] Take ext_PPS as the start gate opening signal, and the first sys_clk rising edge after the ext_PPS rising edge as the stop gate closing signal. If the number of taps propagated by the ext_PPS rising edge in the delay chain when the gate closing signal arrives is k, the precise measurement result can be obtained:

[0070] t2=k*13(ps)

[0071] Then the total transmission delay of the current channel is:

[0072] t=t1+t2=n*T sysclk +k*13(ps)

[0073] (103) In order to eliminate the single measurement error, the measurement is performed once per second for 5 consecutive times, and the average value of the 5 times is taken as the delay measurement result t avr .

[0074] (104) According to the measured delay value t of the current transmission channel avr With the reference delay value t0, calculate the delay adjustment amount Δt of the current transmission channel:

[0075] Δt=t0-t avr

[0076] Because the delay adjustment Δt cannot be a negative number, when designing the system, it should be ensured that t0>t avr .

[0077] (105) A coarse adjustment of the time delay is completed according to the amount of delay to be adjusted.

[0078] The transmission channel delay adjustment mainly adjusts int_PPS. Because the transmission signal pseudo code and telegram are aligned with int_PPS, adjusting the int_PPS position will change the pseudo code and telegram accordingly, that is, the transmission channel delay changes.

[0079] Delay adjustment is divided into coarse adjustment and fine adjustment. Coarse adjustment is to adjust the delay with the code clock period as the minimum unit. Delay adjustment within the code chip is completed according to the delay adjustment amount, i.e. fine adjustment. The principle of delay adjustment is as follows: Figure 5 shown.

[0080] int_PPS is generated by counting pn_clk. When the rising edge of ext_PPS arrives, the count is reset, and the reset initial value is code_tw. By adjusting the size of code_tw, the relative position relationship between int_PPS and ext_PPS can be changed.

[0081] Calculate the coarse control word code_tw according to the delay adjustment value Δt:

[0082] code_tw=floor(Δt / T p )

[0083] Where Δt is the delay adjustment, T p is the pseudo code clock period, that is, the minimum chip width, and the operator floor means rounding down.

[0084] (105) Perform fine delay adjustment according to the delay adjustment amount.

[0085] The delay adjustment within the code segment is completed according to the delay adjustment amount, that is, fine adjustment. The fine adjustment is to adjust the part where the delay adjustment amount is smaller than the pseudo code period.

[0086] The essence of the fine-tuning module is digital frequency synthesis (DDS), which uses the system clock sys_clk as the beat and synthesizes the pseudo code clock pn_clk according to the fine-tuning frequency control word vtw and the fine-tuning phase control word stw. vtw controls the frequency of pn_clk, which cannot exceed half of sys_clk. stw controls the phase of pn_clk.

[0087] Since the pseudo code is aligned with pn_clk, the pseudo code phase will change accordingly when the pn_clk phase changes. Fine tuning is to adjust the pn_clk phase by changing the phase control word stw, thereby achieving the purpose of adjusting the pseudo code phase.

[0088] The fine-tuning process is as follows:

[0089] First, calculate the delay fine adjustment value Δt j :

[0090] Δt j =Δt-floor(Δt / T p )*T p

[0091] Among them, Δt is the delay to be adjusted, floor means rounding down, T p is the pseudo code clock period;

[0092] Then, according to the time delay fine adjustment amount Δt j Calculate the fine-tuning phase control word stw;

[0093] stw=(Δt j / T p )×2 N

[0094] Wherein, N is the bit width of the fine-tuning phase control word stw.

[0095] Assuming the phase control word stw bit width is 16 and the code clock frequency is 100MHz, the delay adjustment accuracy is:

[0096]

[0097] The stw bit width can be adjusted according to the delay adjustment accuracy requirements. The wider the bit width, the higher the adjustment accuracy.

[0098] In addition to the above embodiments, the present invention may also have other implementations. Any technical solution using equivalent replacement or equivalent transformation forms falls within the protection scope required by the present invention.

Claims

1. A method for automatically maintaining the power-on and power-off delay of a low-orbit satellite navigation transmission channel, characterized in that: The following steps are involved: Step 1: Turn on the satellite and measure the coarse delay of the transmission channel; Step 2, measure the precise delay of the transmission channel and calculate the total transmission delay of the transmission channel; Step 3, repeating steps 1 and 2, measuring the total transmission delay multiple times, and taking the average value of the multiple measurements as the delay measurement result; Step 4, calculating the delay amount to be adjusted according to the delay measurement result; Step 5, completing the coarse adjustment of the delay according to the delay to be adjusted; Step 6: Complete the delay fine adjustment according to the delay to be adjusted.

2. According to claim 1, a method for automatically maintaining the power on / off delay of a low-orbit satellite navigation transmission channel is characterized in that: The specific method of step 1 is: When the rising edge of the second pulse signal ext_PPS provided by the external time and frequency equipment arrives, the counting is started, and the count is increased by 1 when each rising edge of the system clock sys_clk is detected. When the rising edge of the second pulse signal int_PPS generated inside the navigation transmission channel is detected, the counting is stopped to obtain the coarse delay measurement value t1: t1=n*T sysclk Among them, T sysclk Represents the system clock cycle, and n represents the number of counts.

3. The method for automatically maintaining the power on / off delay of a low-orbit satellite navigation transmission channel according to claim 1, characterized in that: The specific method of step 2 is: Using the tapped delay line time-to-digital conversion circuit of FPGA, delay units with the same delay time of τ are cascaded into a linear delay chain, and a tap is drawn out after each delay unit to input into the trigger array; The second pulse signal ext_PPS provided by the external time-frequency device is used as the gate-opening signal start, and the first rising edge of the system clock sys_clk after the rising edge of ext_PPS is used as the gate-closing signal stop. According to the number of taps k that the rising edge of ext_PPS propagates in the delay chain when the gate-closing signal arrives, the precise delay measurement value t2 is obtained: t2 = kτ; Calculate the total transmission delay t of the transmission channel: t=t1+t2.

4. The method for automatically maintaining the power on / off delay of a low-orbit satellite navigation transmission channel according to claim 1, characterized in that: In step 4, the delay to be adjusted Δt is: Δt=t0-t avr Among them, t0 is the reference delay value, t avr The delay measurement result.

5. The method for automatically maintaining the power on / off delay of a low-orbit satellite navigation transmission channel according to claim 1, characterized in that: The specific method of step 5 is: Step 501, calculate the coarse adjustment control word code_tw according to the delay to be adjusted Δt: code_tw=floor(Δt / T p ) Where, T p is the pseudo code clock period, that is, the minimum chip width, floor() means rounding down; Step 502: perform coarse adjustment of the delay according to the coarse adjustment control word code_tw.

6. The method for automatically maintaining the power on / off delay of a low-orbit satellite navigation transmission channel according to claim 1, characterized in that: The specific method of step 6 is: Step 601, calculate the delay fine adjustment value Δt j : Δt j =Δt-floor(Δt / T p )*T p Where Δt is the delay to be adjusted, floor() means rounding down, T p is the pseudo code clock period; Step 602: fine-tune the delay according to Δt j , calculate the fine-tuning phase control word stw; stw=(Δt j / T p )×2 N Wherein, N is the bit width of the fine-tuning phase control word stw; Step 603: perform fine adjustment of the delay according to the fine adjustment phase control word stw.

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