Word line driver, word line driving method, memory, and storage system

Abstract

This application provides a word line driver, a word line driving method, a memory, and a memory system, belonging to the field of memory technology. The word line driver provided in this application includes a driving circuit, a first switching circuit, and a switching control circuit. The first switching circuit can pull down the voltage of a first node to the voltage of a first power supply terminal, and then, through the driving circuit, pull down the word line to the voltage of the first power supply terminal. This effectively improves the flexibility of driving the word line. Furthermore, the switching control circuit can pull down the voltage of a second node to the voltage of the first power supply terminal. Since the first switching circuit is also connected to the first power supply terminal, it can be effectively turned off under the control of the second node, thereby effectively reducing the leakage current at the first node.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a word line driver, a word line driving method, a memory, and a storage system. Background Technology

[0002] Dynamic random access memory (DRAM) consists of multiple memory cells arranged in an array. Each memory cell is connected to a word line (WL) and a bit line (BL), and can perform data read and write operations under the control of the WL and BL.

[0003] DRAM also includes a word line driver, which is connected to the word line (WL) and used to drive the WL to which it is connected. For example, the word line driver can enable the selection or deselection of the WL. Summary of the Invention

[0004] This application provides a word line driver, a word line driving method, a memory, and a memory system. The technical solution is as follows:

[0005] In a first aspect, a word line driver is provided, the word line driver comprising: a driving circuit, a first switching circuit, and a switching control circuit;

[0006] The driving circuit is connected to the first node and the word line respectively, and is used to control the connection and disconnection between the first node and the word line;

[0007] The first switching circuit is connected to the first enable terminal, the second node, the first power supply terminal and the first node respectively, and is used to control the connection and disconnection between the first power supply terminal and the first node under the control of the first enable terminal and the second node.

[0008] The switch control circuit is connected to the first selection terminal, the first enable terminal, the first power supply terminal, the second power supply terminal and the second node respectively, and is used to control the first power supply terminal or the second power supply terminal to be connected to the second node under the control of the first selection terminal and the first enable terminal.

[0009] The voltage at the first power supply terminal is lower than the voltage at the second power supply terminal.

[0010] Optionally, the switch control circuit includes: a first control sub-circuit and a second control sub-circuit;

[0011] The first control sub-circuit is connected to the first enable terminal, the first power supply terminal, and the third node respectively, and is used to control the connection and disconnection between the first power supply terminal and the third node under the control of the first enable terminal.

[0012] The second control sub-circuit is connected to the first selection terminal, the second power supply terminal, the third node, and the second node respectively, and is used to control the second power supply terminal or the third node to be connected to the second node under the control of the first selection terminal.

[0013] Optionally, the first control sub-circuit includes: a first transistor; the gate of the first transistor is connected to the first enable terminal, the first electrode of the first transistor is connected to the first power supply terminal, and the second electrode of the first transistor is connected to the third node.

[0014] Optionally, the second control sub-circuit includes: a second transistor and a third transistor with opposite polarities;

[0015] The gate of the second transistor is connected to the first selection terminal, the first terminal of the second transistor is connected to the second power supply terminal, and the second terminal of the second transistor is connected to the second node;

[0016] The gate of the third transistor is connected to the first selection terminal, the first electrode of the third transistor is connected to the third node, and the second electrode of the third transistor is connected to the second node.

[0017] Optionally, the first switching circuit includes a fourth transistor and a fifth transistor;

[0018] The gate of the fourth transistor is connected to the first enable terminal, the first terminal of the fourth transistor is connected to the second terminal of the fifth transistor, and the second terminal of the fourth transistor is connected to the first node; the gate of the fifth transistor is connected to the second node, and the first terminal of the fifth transistor is connected to the first power supply terminal.

[0019] Optionally, the driving circuit is also connected to the second selection terminal, the main word line, and the word line driving terminal respectively; the driving circuit is used to control the word line driving terminal or the first node to conduct with the word line under the control of the main word line and the second selection terminal.

[0020] Optionally, the driving circuit includes: a sixth transistor, a seventh transistor, and an eighth transistor;

[0021] The gate of the sixth transistor is connected to the main word line, the first terminal of the sixth transistor is connected to the word line driving terminal, and the second terminal of the sixth transistor is connected to the word line.

[0022] The gate of the seventh transistor is connected to the main word line, the first terminal of the seventh transistor is connected to the first node, and the second terminal of the seventh transistor is connected to the word line;

[0023] The gate of the eighth transistor is connected to the second selection terminal, the first terminal of the eighth transistor is connected to the first node, and the second terminal of the eighth transistor is connected to the word line.

[0024] Optionally, the word line driver further includes: a second switching circuit; the second switching circuit is connected to a second enable terminal, a third power supply terminal, and the first node respectively, and is used to control the connection and disconnection between the third power supply terminal and the first node under the control of the second enable terminal; wherein the voltage of the third power supply terminal is higher than the voltage of the first power supply terminal and lower than the voltage of the second power supply terminal.

[0025] Optionally, the second switching circuit includes: a ninth transistor;

[0026] The gate of the ninth transistor is connected to the second enable terminal, the first terminal of the ninth transistor is connected to the third power supply terminal, and the second terminal of the ninth transistor is connected to the first node.

[0027] Optionally, the word line driver further includes: a first enable circuit and a second enable circuit;

[0028] The first enabling circuit is connected to the initial enabling terminal, the first power supply terminal, the second power supply terminal and the second enabling terminal respectively, and is used to control the first power supply terminal or the second power supply terminal to be connected to the second enabling terminal under the control of the initial enabling terminal.

[0029] The second enabling circuit is connected to the second enabling terminal, the first power supply terminal, the second power supply terminal, and the first enabling terminal, respectively, and is used to control the first power supply terminal or the second power supply terminal to be connected to the first enabling terminal under the control of the second enabling terminal.

[0030] Optionally, the first enabling circuit includes: a tenth transistor and an eleventh transistor with opposite polarities;

[0031] The gate of the tenth transistor is connected to the initial enable terminal, the first terminal of the tenth transistor is connected to the second power supply terminal, and the second terminal of the tenth transistor is connected to the second enable terminal.

[0032] The gate of the eleventh transistor is connected to the initial enable terminal, the first terminal of the eleventh transistor is connected to the first power supply terminal, and the second terminal of the eleventh transistor is connected to the second enable terminal.

[0033] Optionally, the second enabling circuit includes: a twelfth transistor and a thirteenth transistor with opposite polarities; the gate of the twelfth transistor is connected to the second enabling terminal, the first terminal of the twelfth transistor is connected to the second power supply terminal, and the second terminal of the twelfth transistor is connected to the first enabling terminal;

[0034] The gate of the thirteenth transistor is connected to the second enable terminal, the first terminal of the thirteenth transistor is connected to the first power supply terminal, and the second terminal of the thirteenth transistor is connected to the first enable terminal.

[0035] Secondly, a word line driving method is provided, the method comprising:

[0036] During the selection phase of the word line connected to the word line driver, the driving circuit in the word line driver controls the connection between the first node and the word line to be disconnected.

[0037] The switch control circuit in the word line driver controls the first power supply terminal to be connected to the second node under the control of the first selection terminal and the first enable terminal;

[0038] The first switching circuit in the word line driver, under the control of the second node, controls the connection between the first power supply terminal and the first node to be disconnected.

[0039] Optionally, during the selection phase of the character line, the method further includes:

[0040] Under the control of the main word line, the driving circuit controls the word line driving end to be connected to the word line;

[0041] The second switching circuit in the word line driver, under the control of the second enable terminal, controls the connection between the third power supply terminal and the first node to be disconnected.

[0042] Optionally, the method further includes:

[0043] During the selection phase of other word lines, the driving circuit, under the control of the second selection terminal, controls the first node to be connected to the word line;

[0044] The second switching circuit in the driving circuit, under the control of the second enable terminal, controls the connection between the third power supply terminal and the first node to be disconnected.

[0045] Under the control of the first selection terminal, the switch control circuit controls the second power supply terminal to be connected to the second node;

[0046] Under the control of the second node and the first enable terminal, the first switching circuit controls the first power supply terminal to be connected to the first node.

[0047] Optionally, the method further includes:

[0048] During the standby phase, the driving circuit, under the control of the second selection terminal, controls the first node to be connected to the word line;

[0049] Under the control of the second enable terminal, the second switching circuit controls the third power supply terminal to be connected to the first node;

[0050] Under the control of the first selection terminal, the switch control circuit controls the second power supply terminal to be connected to the second node;

[0051] Under the control of the first enable terminal, the first switching circuit controls the connection between the first power supply terminal and the first node to be disconnected.

[0052] Thirdly, a memory is provided, the memory comprising: a memory array, a plurality of word lines connected to the memory array, and a plurality of word line drivers as provided in the first aspect above; wherein each word line driver is connected to one of the word lines and is used to drive the word line.

[0053] Fourthly, a storage system is provided, the storage system comprising: a memory controller, and at least one memory as provided in the above aspects.

[0054] The technical solution provided in this application can include at least the following beneficial effects:

[0055] This application provides a word line driver, a word line driving method, a memory, and a storage system. The word line driver provided by this application includes a driving circuit, a first switching circuit, and a switching control circuit. The first switching circuit can pull down the voltage of a first node to the voltage of a first power supply terminal, and then, through the driving circuit, pull down the word line to the voltage of the first power supply terminal. This effectively improves the flexibility of driving the word line. Furthermore, the switching control circuit can pull down the voltage of a second node to the voltage of the first power supply terminal. Since the first switching circuit is also connected to the first power supply terminal, it can be effectively turned off under the control of the second node, thereby effectively reducing the leakage current at the first node. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0058] Figure 2 This is a schematic diagram of the structure of a memory provided in an embodiment of this application;

[0059] Figure 3 This is a schematic diagram of the structure of a word line driver provided in an embodiment of this application;

[0060] Figure 4 This is a schematic diagram of another word line driver provided in an embodiment of this application;

[0061] Figure 5 This is a schematic diagram of the structure of another word line driver provided in the embodiments of this application;

[0062] Figure 6 This is a schematic diagram of an enable circuit provided in an embodiment of this application;

[0063] Figure 7 This is a flowchart of a word line driving method provided in an embodiment of this application;

[0064] Figure 8 This is a timing diagram of a word line driving method provided in an embodiment of this application;

[0065] Figure 9 This is a flowchart of another word line driving method provided in the embodiments of this application;

[0066] Figure 10 This is a timing diagram of another word line driving method provided in an embodiment of this application;

[0067] Figure 11 This is a simulation diagram of leakage current at the first node provided in an embodiment of this application. Detailed Implementation

[0068] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0069] The solutions provided in this application can be applied to electronic devices. These electronic devices can be mobile terminals, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality devices, augmented reality devices, or any other suitable electronic device having memory.

[0070] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 1As shown, the electronic device includes a storage system 01 and a host 02. The host 02 can be a central processing unit (CPU) or a system-on-chip (SOC) of the electronic device. The host 02 is used to send data to the storage system 01 for storage or to read data from the storage system 01.

[0071] refer to Figure 1 The storage system 01 includes a memory controller 2000 and at least one memory 1000, for example... Figure 1 Multiple memories 1000 are shown. A memory controller 2000 is connected to at least one memory 1000 and a host 02, respectively. The memory controller 2000 is used to manage the data stored in the memory 1000 and to communicate with the host 02.

[0072] It is understood that at least one memory 1000 in the storage system 01 may include DRAM. The DRAM may be synchronous dynamic random-access memory (SDRAM), and may be low power double data rate (LPDDR) SDRAM.

[0073] Figure 2 This is a schematic diagram of the structure of a memory provided in an embodiment of this application, and Figure 2 The illustration is based on DRAM as an example. Figure 2 As shown, the memory may include a memory array 200, multiple word lines (WLs) connected to the memory array 200, and multiple word line drivers 100. Each word line driver 100 is connected to one WL and is used to drive the WL it is connected to.

[0074] like Figure 2 As shown, the memory array 200 includes multiple memory cells 201 arranged in an array. Each memory cell 201 includes a transistor M0 and a capacitor C0. The gate of the transistor M0 is connected to WL, the first terminal is connected to BL, the second terminal is connected to one end of the capacitor C0, and the other end of the capacitor C0 is grounded.

[0075] Continue to refer to Figure 2The memory 1000 also includes multiple BLs and multiple sensing amplifier circuits 300. Each BL is connected to the gate of a transistor M0 in a plurality of memory cells 201 located in the same row, and each BL is connected to the first terminal of a transistor M0 in a plurality of memory cells 201 located in the same column. Furthermore, each pair of adjacent BLs can be complementary bit lines and can be connected to the same sensing amplifier circuit 300.

[0076] Understandably, when data needs to be written to a certain storage cell 201, an enable voltage can be applied to WL connected to the storage cell 201 to turn on the transistor M0 in the storage cell 201. At the same time, data to be written can be loaded to BL connected to the storage cell 201, and the data to be written can then be written to capacitor C0 through the turned-on transistor M0.

[0077] When data needs to be read from a memory cell 201, the BL connected to the memory cell 201 and its complementary bit line BLB can be pre-charged. Then, an enable voltage can be applied to the WL connected to the memory cell 201 to turn on the transistor M0 in the memory cell 201. After transistor M0 is turned on, capacitor C0 can share charge with BL. Specifically, if the data stored in capacitor C0 is 1, the voltage of BL can increase slightly based on this charge-sharing operation; if the data stored in capacitor C0 is 0, the voltage of BL can decrease slightly based on this charge-sharing operation. The sensing amplifier circuit 300 can then sense and amplify the voltage difference between BL and BLB based on the voltage of the complementary bit line BLB, thereby enabling the reading of data stored in capacitor C0.

[0078] Understandably, reference Figure 2 The storage array 200 may include multiple blocks, and BL and BLB may be connected to storage cells 201 in different blocks. For example Figure 2 The BL in block B1 can be connected to storage unit 201 in block B1, and the BLB can be connected to storage unit 201 in block B2.

[0079] It is also understood that the memory provided in the embodiments of this application can be LPDDR SDRAM, such as LPDDR5 memory. Since LPDDR5 mainly focuses on the low power consumption characteristics of DRAM products, reducing leakage current is an important factor in LPDDR5 circuit design.

[0080] This application provides a word line driver that can be applied to, for example... Figure 2 In the memory shown. (As shown in the image) Figure 3As shown, the word line driver includes: a driving circuit 10, a first switching circuit 20, and a switching control circuit 30.

[0081] The driving circuit 10 is connected to the first node P1 and WL respectively, and is used to control the on / off state of the first node P1 and WL.

[0082] The first switching circuit 20 is connected to the first enable terminal EN1, the second node P2, the first power supply terminal VN1 and the first node P1 respectively, and is used to control the on / off state of the first power supply terminal VN1 and the first node P1 under the control of the first enable terminal EN1 and the second node P2.

[0083] The switch control circuit 30 is connected to the first selection terminal WLDN, the first enable terminal EN1, the first power supply terminal VN1, the second power supply terminal VPP, and the second node P2, respectively, and is used to control the first power supply terminal VN1 or the second power supply terminal VPP to conduct with the second node P2 under the control of the first selection terminal WLDN and the first enable terminal EN1.

[0084] The voltage at the first power supply terminal VN1 is lower than the voltage at the second power supply terminal VPP. For example, the voltage at the second power supply terminal VPP can be positive, and the voltage at the first power supply terminal VN1 can be negative.

[0085] Understandably, during the active phase of the word line driver connected to the WL, the driver circuit 10 can control the connection between the first node P1 and the WL to be disconnected. Furthermore, under the control of the first selection terminal WLDN and the first enable terminal EN1, the switch control circuit 30 can control the first power supply terminal VN1 to conduct with the second node P2, thereby pulling the voltage of the second node P2 down to the voltage of the first power supply terminal VN1. The first switch circuit 20 can then, under the control of the second node P2, control the connection between the first power supply terminal VN1 and the first node P1 to be disconnected.

[0086] Since the switch control circuit 30 can pull down the voltage of the second node P2 to the voltage of the first power supply terminal VN1, and the first switch circuit 20 is also connected to the first power supply terminal VN1, the transistor in the first switch circuit 20 can be effectively turned off. Therefore, the leakage current at the first node P1 can be effectively reduced.

[0087] During the selection phase of other WLs, the drive circuit 10 can control the first node P1 to conduct with WL. Furthermore, the switch control circuit 30, under the control of the first selection terminal WLDN, can control the second power supply terminal VPP to conduct with the second node P2, so that the first switch circuit 20, under the control of the second node P2 and the first enable terminal EN1, can control the first power supply terminal VN1 to conduct with the first node P1. Thus, the voltage of WL can be pulled down to the voltage of the first power supply terminal VN1.

[0088] In summary, this application provides a word line driver, which includes a driving circuit, a first switching circuit, and a switching control circuit. The first switching circuit can pull down the voltage of a first node to the voltage of a first power supply terminal, and then, through the driving circuit, pull down the word line to the voltage of the first power supply terminal. This effectively improves the flexibility of driving the word line. Furthermore, the switching control circuit can pull down the voltage of a second node to the voltage of the first power supply terminal. Since the first switching circuit is also connected to the first power supply terminal, it can be effectively turned off under the control of the second node, thereby effectively reducing the leakage current at the first node.

[0089] Figure 4 This is a schematic diagram of another word line driver provided in an embodiment of this application. For example... Figure 4 As shown, the driving circuit 10 can also be connected to the main word line (MWL), the word line driving terminal XPP, and the second selection terminal WLD, respectively, and is used to control the word line driving terminal XPP or the first node P1 to conduct with WL under the control of the main word line MWL and the second selection terminal WLD.

[0090] Continue to refer to Figure 4 The word line driver may further include a second switching circuit 40. The second switching circuit 40 is connected to a second enable terminal EN2, a third power supply terminal VN2 and a first node P1 respectively, and is used to control the connection and disconnection between the third power supply terminal VN2 and the first node P1 under the control of the second enable terminal EN2.

[0091] It is understandable that the voltage on the second enable terminal EN2 can be opposite to the voltage on the first enable terminal EN1, and the voltage on the second select terminal WLD can be opposite to the voltage on the first select terminal WLDN. Specifically, the opposite voltages on the two signal terminals can mean that when one signal terminal has a high voltage, the other signal terminal has a low voltage; or when one signal terminal has a low voltage, the other signal terminal has a high voltage.

[0092] It is also understandable that during the selection phase of the WL connected to the word line driver, the drive circuit 10 can control the word line driver terminal XPP to conduct with the WL under the control of the main word line MWL, so as to select the WL. At the same time, the second switch circuit 40 can control the connection between the third power supply terminal VN2 and the first node P1 to disconnect under the control of the second enable terminal EN2.

[0093] During the selection phase of other WLs, the drive circuit 10 can control the first node P1 to conduct with the WL under the control of the second selection terminal WLD. At the same time, the second switch circuit 40 can control the connection between the third power supply terminal VN2 and the first node P1 to disconnect under the control of the second enable terminal EN2.

[0094] During standby, the drive circuit 10, under the control of the second selection terminal WLD, can control the first node P1 to conduct with WL. Simultaneously, the second switching circuit 40, under the control of the second enable terminal EN2, can control the third power supply terminal VN2 to conduct with the first node P1. Thus, the voltage of WL can be pulled down to the voltage of the third power supply terminal VN2.

[0095] Based on the above analysis, it can be seen that since the first switching circuit 20 and the second switching circuit 40 are connected to different power supply terminals, the first node P1 can be pulled down to different voltages, and thus the driving circuit 10 can pull down WL to different voltages. This effectively improves the flexibility of driving WL.

[0096] Optionally, the voltage of the first power supply terminal VN1 can be -0.8 volts (V) or -1V, the voltage of the second power supply terminal VPP can be 1.8V, and the voltage of the third power supply terminal VN2 can be -0.5V.

[0097] Figure 5 This is a schematic diagram of another word line driver provided in an embodiment of this application. For example... Figure 5 As shown, the switch control circuit 30 may include: a first control sub-circuit 301 and a second control sub-circuit 302.

[0098] The first control sub-circuit 301 is connected to the first enable terminal EN1, the first power supply terminal VN1 and the third node P3 respectively, and is used to control the on / off state of the first power supply terminal VN1 and the third node P3 under the control of the first enable terminal EN1.

[0099] The second control sub-circuit 302 is connected to the first selection terminal WLDN, the second power supply terminal VPP, the third node P3, and the second node P2, respectively, and is used to control the second power supply terminal VPP or the third node P3 to conduct with the second node P2 under the control of the first selection terminal WLDN.

[0100] For example, during the selection phase of the WL connected to the word line driver, the first control sub-circuit 301, under the control of the first enable terminal EN1, controls the first power supply terminal VN1 to conduct with the third node P3. The second control sub-circuit 302, under the control of the first select terminal WLDN, controls the third node P3 to conduct with the second node P2. Thus, the conduction of the first power supply terminal VN1 and the second node P2 can be achieved.

[0101] During the selection phase of other WLs, the first control sub-circuit 301, under the control of the first enable terminal EN1, can control the first power supply terminal VN1 to conduct with the third node P3. The second control sub-circuit 302, under the control of the first selection terminal WLDN, can control the second power supply terminal VPP to conduct with the second node P2.

[0102] During the standby phase, the first control sub-circuit 301, under the control of the first enable terminal EN1, can control the connection between the first power supply terminal VN1 and the third node P3 to be disconnected. The second control sub-circuit 302, under the control of the first select terminal WLDN, can control the second power supply terminal VPP to be turned on and connected to the second node P2.

[0103] Optionally, continue to refer to Figure 5 The first control sub-circuit 301 may include a first transistor T1. The gate of the first transistor T1 is connected to the first enable terminal EN1, the first terminal of the first transistor T1 is connected to the first power supply terminal VN1, and the second terminal of the first transistor T1 is connected to the third node P3.

[0104] The first transistor T1 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). Furthermore, the first transistor T1 can be an N-type MOSFET, i.e., an NMOS.

[0105] Understandably, the first terminal of a transistor can refer to one of the source and drain terminals, and the second terminal can refer to the other of the source and drain terminals.

[0106] Optionally, continue to refer to Figure 5 The second control sub-circuit 302 may include a second transistor T2 and a third transistor T3 with opposite polarities. The gate of the second transistor T2 is connected to the first selection terminal WLDN, the first terminal of the second transistor T2 is connected to the second power supply terminal VPP, and the second terminal of the second transistor T2 is connected to the second node P2.

[0107] The gate of the third transistor T3 is connected to the first select terminal WLDN, the first terminal of the third transistor T3 is connected to the third node P3, and the second terminal of the third transistor T3 is connected to the second node P2.

[0108] Both the second transistor T2 and the third transistor T3 can be MOSFETs. Specifically, the second transistor T2 can be a P-type MOSFET (PMOS), and the third transistor T3 can be an NMOS. When a high voltage (e.g., the voltage of the second power supply terminal VPP) is applied to the first selection terminal WLDN, the third transistor T3 turns on, and the second transistor T2 turns off. When a low voltage (e.g., VSS) is applied to the first selection terminal WLDN, the second transistor T2 turns on, and the third transistor T3 turns off.

[0109] Optionally, continue to refer to Figure 5 The first switching circuit 20 may include a fourth transistor T4 and a fifth transistor T5.

[0110] Specifically, the gate of the fourth transistor T4 is connected to the first enable terminal EN1, the first terminal of the fourth transistor T4 is connected to the second terminal of the fifth transistor T5, and the second terminal of the fourth transistor T4 is connected to the first node P1. The gate of the fifth transistor T5 is connected to the second node P2, and the first terminal of the fifth transistor T5 is connected to the first power supply terminal VN1.

[0111] In this embodiment, the fourth transistor T4 and the fifth transistor T5 can both be MOSFETs, and the two transistors have the same polarity, for example, both can be NMOS. Accordingly, when a high voltage is applied to the first enable terminal EN1 (e.g., the voltage of the second power supply terminal VPP), the fourth transistor T4 is turned on. When a low voltage is applied to the first enable terminal EN1 (e.g., the voltage of the first power supply terminal VN1), the fourth transistor T4 is turned off. When the second node P2 is at a high voltage (i.e., the second transistor T2 is turned on), the fifth transistor T5 is turned on. When the second node P2 is at a low voltage (i.e., both the third transistor T3 and the first transistor T1 are turned on), the fifth transistor T5 is turned off.

[0112] It is understandable that directly connecting the gate of the fifth transistor T5 to the second selection terminal WLD would also enable control of the first switching circuit 20. However, when it is necessary to turn off the fifth transistor T5, the low voltage VSS provided by the second selection terminal WLD is 0V. Since the voltage of the first power supply terminal VN1 connected to the first electrode of the fifth transistor T5 is generally -0.8V, the gate-source voltage difference Vgs of the fifth transistor T5 will be 0.8V. This gate-source voltage difference Vgs is very close to the threshold voltage Vth of the fifth transistor T5, which will prevent the fifth transistor T5 from being effectively turned off, resulting in leakage current at the first node P1.

[0113] In this embodiment, since the switch control circuit 30 can pull down the voltage of the second node P2 (i.e., the gate of the fifth transistor T5) to the voltage of the first power supply terminal VN1, the gate-source voltage difference Vgs of the fifth transistor T5 can be made 0V. This gate-source voltage difference Vgs can effectively turn off the fifth transistor T5, thereby effectively reducing the leakage current at the first node P1.

[0114] Optionally, such as Figure 5 As shown, the driving circuit 10 may include a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The gate of the sixth transistor T6 is connected to the main word line MWL, the first terminal of the sixth transistor T6 is connected to the word line driving terminal XPP, and the second terminal of the sixth transistor T6 is connected to MWL.

[0115] The gate of the seventh transistor T7 is connected to the main word line MWL, the first terminal of the seventh transistor T7 is connected to the first node P1, and the second terminal of the seventh transistor T7 is connected to WL.

[0116] The gate of the eighth transistor T8 is connected to the second selection terminal WLD, the first terminal of the eighth transistor T8 is connected to the first node P1, and the second terminal of the eighth transistor T8 is connected to WL.

[0117] In this embodiment, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can all be MOSFETs. Furthermore, the seventh transistor T7 and the eighth transistor T8 have the same polarity, but opposite to the polarity of the sixth transistor T6. For example, the seventh transistor T7 and the eighth transistor T8 can both be NMOS, and the sixth transistor T6 can be a PMOS.

[0118] Accordingly, when a high voltage is applied to the main word line MWL (e.g., the voltage of the second power supply terminal VPP), the seventh transistor T7 is turned on and the sixth transistor T6 is turned off. When a low voltage is applied to the main word line MWL (e.g., VSS), the sixth transistor T6 is turned on and the seventh transistor T7 is turned off. When a high voltage is applied to the second select terminal WLD (e.g., the voltage of the second power supply terminal VPP), the eighth transistor T8 is turned on. When a low voltage is applied to the second select terminal WLD (e.g., VSS), the eighth transistor T8 is turned off.

[0119] Optionally, continue to refer to Figure 5 The second switching circuit 40 may include a ninth transistor T9. The gate of the ninth transistor T9 is connected to the second enable terminal EN2, the first terminal of the ninth transistor T9 is connected to the third power supply terminal VN2, and the second terminal of the ninth transistor T9 is connected to the first node P1.

[0120] The ninth transistor T9 can be a MOSFET, such as an NMOS. Accordingly, when a high voltage is applied to the second enable terminal EN2 (e.g., the voltage of the second power supply terminal VPP), the ninth transistor T9 is turned on. When a low voltage is applied to the second enable terminal EN2 (e.g., the voltage of the first power supply terminal VN1), the ninth transistor T9 is turned off.

[0121] Optionally, such as Figure 4 As shown, the word line driver may further include: a first enable circuit 50 and a second enable circuit 60.

[0122] The first enabling circuit 50 is connected to the initial enabling terminal EN0, the first power supply terminal VN1, the second power supply terminal VPP, and the second enabling terminal EN2, respectively, and is used to control the first power supply terminal VN1 or the second power supply terminal VPP to conduct with the second enabling terminal EN2 under the control of the initial enabling terminal EN0.

[0123] The second enabling circuit 60 is connected to the second enabling terminal EN2, the first power supply terminal VN1, the second power supply terminal VPP, and the first enabling terminal EN1, respectively, and is used to control the first power supply terminal VN1 or the second power supply terminal VPP to conduct with the first enabling terminal EN1 under the control of the second enabling terminal EN2.

[0124] Understandably, the first enable circuit 50 can make the voltage of the second enable terminal EN2 opposite to the voltage of the initial enable terminal EN0. The second enable circuit 60 can make the voltage of the first enable terminal EN1 opposite to the voltage of the first enable terminal EN2.

[0125] For example, when the initial enable terminal EN0 is high, the first enable circuit 50 can connect the first power supply terminal VN1 to the second enable terminal EN2, thereby pulling the voltage of the second enable terminal EN2 low. At this time, the second enable circuit 60 can connect the second power supply terminal VPP to the first enable terminal EN1, thereby pulling the voltage of the first enable terminal EN1 high.

[0126] When the initial enable terminal EN0 is at a low voltage, the first enable circuit 50 can turn on the second power supply terminal VPP and the second enable terminal EN2, thereby pulling up the voltage of the second enable terminal EN2. At this time, the second enable circuit 60 can turn on the first power supply terminal VN1 and the first enable terminal EN1, thereby pulling down the voltage of the first enable terminal EN1.

[0127] Figure 6 This is a schematic diagram of the structure of a first enabling circuit and a second enabling circuit provided in an embodiment of this application. Figure 6 As shown, the first enabling circuit 50 may include a tenth transistor T10 and an eleventh transistor T11 with opposite polarities.

[0128] The gate of the tenth transistor T10 is connected to the initial enable terminal EN0, the first terminal of the tenth transistor T10 is connected to the second power supply terminal VPP, and the second terminal of the tenth transistor T10 is connected to the second enable terminal EN2.

[0129] The gate of the eleventh transistor T11 is connected to the initial enable terminal EN0, the first terminal of the eleventh transistor T11 is connected to the first power supply terminal VN1, and the second terminal of the eleventh transistor T11 is connected to the second enable terminal EN2.

[0130] In this embodiment, both the tenth transistor T10 and the eleventh transistor T11 can be MOSFETs. Furthermore, the tenth transistor T10 can be a PMOS, and the eleventh transistor T11 can be an NMOS. Accordingly, when the initial enable terminal EN0 is high, the eleventh transistor T11 is turned on, and the tenth transistor T10 is turned off. When the initial enable terminal EN0 is low, the tenth transistor T10 is turned on, and the eleventh transistor T11 is turned off.

[0131] Continue to refer to Figure 6 The second enabling circuit 60 may include a twelfth transistor T12 and a thirteenth transistor T13 with opposite polarities.

[0132] The gate of the twelfth transistor T12 is connected to the second enable terminal EN2, the first terminal of the twelfth transistor T12 is connected to the second power supply terminal VPP, and the second terminal of the twelfth transistor T12 is connected to the first enable terminal EN1.

[0133] The gate of the thirteenth transistor T13 is connected to the second enable terminal EN2, the first terminal of the thirteenth transistor T13 is connected to the first power supply terminal VN1, and the second terminal of the thirteenth transistor T13 is connected to the first enable terminal EN1.

[0134] In this embodiment, both the twelfth transistor T12 and the thirteenth transistor T13 can be MOSFETs. Furthermore, the twelfth transistor T12 can be a PMOS, and the thirteenth transistor T13 can be an NMOS. Accordingly, when the second enable terminal EN2 is high, the thirteenth transistor T13 is turned on, and the twelfth transistor T12 is turned off. When the second enable terminal EN2 is low, the twelfth transistor T12 is turned on, and the thirteenth transistor T13 is turned off.

[0135] In summary, this application provides a word line driver, which includes a driving circuit, a first switching circuit, and a switching control circuit. The first switching circuit can pull down the voltage of a first node to the voltage of a first power supply terminal, and then, through the driving circuit, pull down the word line to the voltage of the first power supply terminal. This effectively improves the flexibility of driving the word line. Furthermore, the switching control circuit can pull down the voltage of a second node to the voltage of the first power supply terminal. Since the first switching circuit is also connected to the first power supply terminal, it can be effectively turned off under the control of the second node, thereby effectively reducing the leakage current at the first node.

[0136] Furthermore, since the first and second switching circuits in this word line driver are connected to different power supplies, the first node can be pulled down to different voltages, and thus the word line can be pulled down to different voltages via the driving circuit. This effectively improves the flexibility of driving the word lines.

[0137] It is understood that, since the first switching circuit 20, the second switching circuit 40, and the switching control circuit 30 in this embodiment are used to provide a negative voltage to the first node P1, they can also be collectively referred to as a negative switch circuit. Furthermore, each word line driver 100 can have a separate negative switch circuit deployed, or multiple word line drivers 100 can share the same negative switch circuit; for example, four word line drivers 100 can share one negative switch circuit.

[0138] It is also understood that, in this embodiment of the application, each block in the memory 1000 can deploy a main word line (MWL), which can be connected to eight word lines (WL) via word line driver 100, meaning that the eight WL can share one main word line (MWL). If each word line driver 100 deploys a separate negative voltage switching circuit, then since the switching control circuit 30 in each word line driver 100 requires three transistors (two NMOS and one PMOS), a total of 24 transistors need to be added to each block. These 24 transistors require approximately 1.2 square micrometers (um²) of area. To avoid increasing the total area of ​​each block, the newly added transistors can be deployed in a junction area with free space in the memory. For example, the newly added transistors can be deployed in the deep N-well (DNW) region of the junction area.

[0139] Figure 7 This is a flowchart illustrating a word line driving method provided in an embodiment of this application. This word line driving method can be applied to the word line driver provided in the above embodiment. (Reference) Figure 7 The method includes:

[0140] Step S11: During the selection phase of the word line connected to the word line driver, the drive circuit in the word line driver controls the connection between the first node and the word line to be disconnected.

[0141] like Figure 8 As shown, assume the word line driver is connected to word line WL. <n>Then in the WL <n>During the selection phase, the drive circuit 10 can select the first node P1 <n>With WL <n>The path between them is broken. For example, the eighth transistor T8 in the drive circuit 10 can remain in the off state.

[0142] Step S12: Under the control of the first selection terminal and the first enable terminal, the switch control circuit in the word line driver controls the first power supply terminal to be connected to the second node.

[0143] Continue to refer to Figure 8 In WL <n>During the selection phase, the first selection end is WLDN <n>and the first enable terminal EN1 <n>The voltages applied are all high voltages (e.g., VPP). At this time, the switch control circuit 30 can control the connection between the first power supply terminal VN1 and the second node P2. <n>This enables the second node P2 to conduct. <n>The voltage is pulled down to the voltage of the first power supply terminal VN1.

[0144] For example, in the switch control circuit 30, the first control sub-circuit 301 can be enabled at the first enable terminal EN1. <n>Under the control of [the circuit], the first power supply terminal VN1 is connected to the third node P3. For example, the first transistor T1 in the first control sub-circuit 301 can be turned on.

[0145] The second control sub-circuit 302 can be configured at the first selection terminal WLDN <n>Under the control of [the system], the third node P3 and the second node P2 are [connected / connected]. <n>Conduction. For example, the third transistor T3 in the second control sub-circuit 302 can be turned on. This allows the first power supply terminal VN1 to connect with the second node P2. <n>The conduction.

[0146] Step S13: Under the control of the second node, the first switching circuit in the word line driver controls the connection between the first power supply terminal and the first node to be disconnected.

[0147] The first switching circuit 20 can be located at the second node P2. <n>Under the control of the first power supply terminal VN1, the first node P1 is controlled. <n>The connection between them is broken. For example, the fifth transistor T5 in the first switching circuit 20 can be connected at the second node P2. <n>Under the control of [the system], it remains in the off state. At this time, even if the first enable terminal EN1... <n>It will control the fourth transistor T4 to turn on, but because the fifth transistor T5 is turned off, it can ensure that the first power supply terminal VN1 is connected to the first node P1. <n>The connection between them is broken.

[0148] Figure 9 This is a flowchart of another word line driving method provided in an embodiment of this application. This word line driving method can be applied to the word line driver provided in the above embodiments. (Reference) Figure 9 The method includes:

[0149] Step S21: During the selection phase of the word line connected to the word line driver, the driving circuit controls the word line driving end to conduct with the word line under the control of the main word line, and controls the connection between the first node and the word line to disconnect under the control of the second selection end.

[0150] In WL <n>During the selection phase, the voltage applied to the main word line MWL can be a low voltage (e.g., VSS). At this time, the drive circuit 10 can, under the control of this low voltage, drive the word line terminal XPP. <n>With WL <n>Conductive. For example, refer to... Figure 5 The sixth transistor T6 in the drive circuit 10 is turned on, thereby turning on the word line drive terminal XPP. <n>With WL <n>Conduction is achieved when a high voltage (e.g., VPP) is applied to the word line driver terminal XPP. <n>Selected.

[0151] Understandably, in WL <n>The selected phase, such as Figure 8 As shown, the second selection terminal WLD <n>The voltage applied is a low voltage (e.g., VSS). The drive circuit 10 is able to control the first node P1 under the control of this low voltage. <n>With WL <n>The pathways between them were disconnected to avoid affecting WL. <n>The voltage on. For example, the eighth transistor T8 in the drive circuit 10 can be selected at the second selection terminal WLD. <n>It remains in the off state under control.

[0152] Step S22: Under the control of the second enable terminal, the second switching circuit in the word line driver controls the connection between the third power supply terminal and the first node to be disconnected.

[0153] Continue to refer to Figure 8 In WL <n>During the selection phase, the second enable terminal EN2 <n>The voltage can be a low voltage (e.g., VN2). In this case, the second switching circuit 40 can, under the control of this low voltage, control the disconnection between the third power supply terminal VN2 and the first node P1. For example, the ninth transistor T9 in the second switching circuit 40 can, at the second enable terminal EN2... <n>It remains in the off state under control.

[0154] Step S23: Under the control of the first selection terminal and the first enable terminal, the switch control circuit in the word line driver controls the first power supply terminal to be connected to the second node. Under the control of the second node, the first switch circuit controls the connection between the first power supply terminal and the first node to be disconnected.

[0155] The implementation process of step S23 can be referred to the relevant descriptions of steps S12 and S13 above, and will not be repeated here.

[0156] Continue to refer to Figure 9 The method may also include:

[0157] Step S24: During the selection phase of other word lines, the driving circuit, under the control of the second selection terminal, controls the first node to be connected to the word line.

[0158] During the selection phase of other text lines, such as Figure 10 As shown, the second selection terminal WLD <n>The applied voltage can be a high voltage (e.g., VPP). In this case, the drive circuit 10 can, under the control of this high voltage, control the first node P1. <n>With WL <n>Conductive. For example, refer to... Figure 5 The eighth transistor T8 in the drive circuit 10 can be selected at the second selection terminal WLD. <n>Under the control of [the system], the first node P1 is turned on, thereby [activating / conducting]. <n>With WL <n>Conduction.

[0159] Step S25: Under the control of the second enable terminal, the second switching circuit controls the connection between the third power supply terminal and the first node to be disconnected.

[0160] Continue to refer to Figure 10 During the selection phase of other word lines, the second enable terminal EN2 <n>The voltage can be low (e.g., VN1). In this case, the second switching circuit 40 can, under the control of this low voltage, control the disconnection between the third power supply terminal VN2 and the first node P1. For example, the ninth transistor T9 in the second switching circuit 40 can, at the second enable terminal EN2... <n>It remains in the off state under control.

[0161] Step S26: Under the control of the first selection terminal, the switch control circuit controls the second power supply terminal to be connected to the second node. Under the control of the second node and the first enable terminal, the first switch circuit controls the first power supply terminal to be connected to the first node.

[0162] Continue to refer to Figure 10 During the selection phase of this other word line, the first selection terminal WLDN <n>The applied voltage is a low voltage (e.g., VSS), and the first enable terminal EN1 <n>The applied voltage is a high voltage (e.g., VPP). At this time, the switch control circuit 30 can control the second power supply terminal VPP and the second node P2. <n>This enables the second node P2 to conduct. <n>The voltage is pulled up to the voltage of the second power supply terminal VPP. The first switching circuit 20 can then be applied to the second node P2. <n>and the first enable terminal EN1 <n>Under the control of the first power supply terminal VN1, the first node P1 is controlled. <n>Conduction.

[0163] For example, the first control sub-circuit 301 in the switch control circuit 30 can be enabled at the first enable terminal EN1. <n>Under the control of [the circuit], the first power supply terminal VN1 is connected to the third node P3. For example, the first transistor T1 in the first control sub-circuit 301 can be turned on.

[0164] The second control sub-circuit 302 can be configured at the first selection terminal WLDN <n>Under the control of [the system], the second power supply terminal VPP is connected to the second node P2. <n>Turning on. For example, the second transistor T2 in the second control sub-circuit 302 can be turned on.

[0165] The fifth transistor T5 in the first switching circuit 20 can be connected at the second node P2. <n>Under the control of the transistor, the fourth transistor T4 can be turned on at the first enable terminal EN1. <n>Under the control of [the system], the circuit is turned on, thereby enabling the first power supply terminal VN1 to connect with the first node P1. <n>The conduction.

[0166] During the selection phase of other word lines, the first power supply terminal VN1 and the first node P1 are connected. <n>The first node P1 is activated. <n>With WL <n>It is conductive, so WL can be turned on. <n>The voltage is pulled down to the voltage of the first power supply terminal VN1. That is, it allows WL to... <n>The voltage is low. Therefore, even WL <n>Even when the voltage is coupled to the high voltage of other word lines that are in the selected state, it can still be kept at a low voltage, thus effectively improving the coupling problem between word lines.

[0167] Similarly, in WL <n>During the selection phase, other word lines can also be pulled down to the voltage of the first power supply terminal VN1, thereby avoiding being affected by WL. <n>Coupled to a higher voltage. See example for reference. Figure 8 In WL <n>During the selection phase, its voltage can be driven by the word line driver terminal XPP. <n>Apply to a high voltage (e.g., VPP), and WL <n>The voltage at the near end (i.e., the end closest to the word line driver) can be higher than the voltage at its far end. Meanwhile, except for WL... <n>Other letter lines, such as WL<n+1> and WL <n-1>The connected word line driver circuit can drive the first node P1<n+1 or n-1> The voltage is pulled down to the voltage of the first power supply terminal VN1. This allows WL to...<n+1> and WL <n-1>The voltage is also pulled down to a lower voltage. Correspondingly, even WL<n+1> and WL <n-1>The far-end voltage in WL <n>Even when pulled up by the coupling effect, it can still maintain a low voltage.

[0168] Optionally, continue to refer to Figure 9 The method may also include:

[0169] Step S27: During the standby phase, the driving circuit controls the first node to be connected to the word line under the control of the second selection terminal.

[0170] During standby, such as Figure 8 and Figure 10 As shown, the second selection terminal WLD <n>The voltage applied is a high voltage (e.g., VPP). At this time, the drive circuit 10 can, under the control of this high voltage, control the first node P1. <n>With WL <n>Conductive. For example, refer to... Figure 5 The eighth transistor T8 in the drive circuit 10 can be selected at the second selection terminal WLD. <n>Under the control of [the system], the first node P1 is turned on, thereby [activating / conducting]. <n>With WL <n>Conduction.

[0171] Step S28: Under the control of the second enable terminal, the second switching circuit controls the third power supply terminal to be connected to the first node.

[0172] Continue to refer to Figure 8 and Figure 10 During the standby phase, the second enable terminal EN2 <n>The voltage can be a high voltage (e.g., VPP). In this case, the second switching circuit 40 can control the third power supply terminal VN2 to conduct with the first node P1 under the control of this high voltage. For example, the ninth transistor T9 in the second switching circuit 40 can be activated at the second enable terminal EN2. <n>The control is turned on, thereby pulling down the voltage of the first node P1.

[0173] Understandably, during this standby phase, the word line drivers connected to each WL in the memory can connect the third power supply terminal VN2 to the first node P1. Accordingly, each WL in the memory can maintain the voltage of the third power supply terminal VN2.

[0174] Step S29: Under the control of the first selection terminal, the switch control circuit controls the second power supply terminal to be connected to the second node, and under the control of the first enable terminal, the first switch circuit controls the connection between the first power supply terminal and the first node to be disconnected.

[0175] Continue to refer to Figure 8 and Figure 10 During this standby phase, the first selection terminal WLDN <n>The applied voltage is a low voltage (e.g., VSS), and the first enable terminal EN1 <n>The applied voltage is a low voltage (e.g., the voltage at the first power supply terminal VN1). At this time, the switch control circuit 30 can control the second power supply terminal VPP and the second node P2. <n>This enables the second node P2 to conduct. <n>The voltage is pulled up to the voltage of the second power supply terminal VPP.

[0176] However, during the standby phase, the first enable terminal EN1 <n>Because the voltage is low, the first switching circuit 20 can operate at the first enable terminal EN1. <n>Under the control of the first power supply terminal VN1, the first node P1 is controlled. <n>The connection between them is broken.

[0177] For example, the first control sub-circuit 301 in the switch control circuit 30 can be enabled at the first enable terminal EN1. <n>Under the control of [the system], the connection between the first power supply terminal VN1 and the third node P3 is disconnected. For example, the first transistor T1 in the first control sub-circuit 301 can be turned off.

[0178] The second control sub-circuit 302 can be configured at the first selection terminal WLDN <n>Under the control of [the system], the second power supply terminal VPP is connected to the second node P2. <n>Turning on. For example, the second transistor T2 in the second control sub-circuit 302 can be turned on.

[0179] The fifth transistor T5 in the first switching circuit 20 can be connected at the second node P2. <n>Under the control of the transistor, the fourth transistor T4 can be turned on at the first enable terminal EN1. <n>Under the control of [the system], the power supply terminal VN1 is turned off, thereby achieving [connection] between the first power supply terminal VN1 and the first node P1. <n>The connection between them is broken.

[0180] Figure 11 These are simulation test diagrams of leakage current at the first node under different schemes provided in the embodiments of this application. Figure 11 The diagram sequentially shows the voltage waveforms of the first node P1<0:3>, the second selection terminal WLD<0:3>, voltage waveforms of different WL values, and the current waveforms of the first node P1 under different schemes. Here, <0:3> can refer to the 0th to the 3rd node.

[0181] from Figure 11 It can be seen that in WL <1> During the selection phase, WL <0> To WL <3> The first node P1 (i.e., P1<0:3>) in the connected word line driver can all be at a low voltage. Furthermore, WLD <1> The voltage can be low, while WLD<0,2,3> can be high, thus allowing WL to... <1> With the first node P1 <1> The connection between them is broken, and WL<0,2,3> is connected to the corresponding first node P1. Accordingly, WL in the selected state... <1> The voltage of the line is pulled up, while the voltage of the other word lines WL<0,2,3> is pulled down.

[0182] Furthermore, in that WL <1> During the selection phase, if the scheme in one embodiment is adopted, and the gate of the fifth transistor T5 in the first switching circuit 20 is directly connected to the second selection terminal WLD, then as follows: Figure 11 As shown, the first node P1 <1> The average leakage current at the point is approximately 20.8 μA. In this embodiment, because the switch control circuit 30 can pull down the gate voltage of the fifth transistor T5 to the voltage of the first power supply terminal VN1, the fifth transistor T5 can be effectively turned off. Correspondingly, as... Figure 11 As shown, the first node P1 <1> The average leakage current at this location is only about 0.8uA.

[0183] Therefore, during the selection phase of a single WL, the solution provided in this application embodiment can reduce the leakage current of the first node by approximately 20uA. In the memory refresh mode, since a group of word line drivers (typically four word line drivers) connected to each main word line MWL will turn off the fifth transistor T5 in the second switching circuit, the leakage current can be reduced by approximately 80uA.

[0184] It is understood that a read operation on the storage unit connected to the WL generally includes the following stages: access, sense, restore, and precharge. The selection stage of the WL described in this application embodiment may refer to the access stage.

[0185] In summary, the embodiments of this application provide a word line driving method. During the word line selection stage, the switch control circuit can pull down the voltage of the second node to the voltage of the first power supply terminal. Since the first switch circuit is also connected to the first power supply terminal, the first switch circuit can be effectively turned off under the control of the second node, thereby effectively reducing the leakage current at the first node.

[0186] Furthermore, during the selection phase of other word lines, the first switching circuit can pull down the voltage of the first node to the voltage of the first power supply terminal, and then pull down the word line to the voltage of the first power supply terminal through the driving circuit. This effectively improves the flexibility of driving word lines. It also effectively improves the coupling problem between word lines.

[0187] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0188] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. The scope of protection of this application should be determined by the scope of the claims.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A word line driver characterized by comprising: The word line driver includes: a driving circuit, a first switching circuit, and a switching control circuit; The driving circuit is connected to the first node and the word line respectively, and is used to control the connection and disconnection between the first node and the word line; The driving circuit is also connected to the second selection terminal, the main word line and the word line driving terminal respectively. The driving circuit is also used to control the word line driving terminal or the first node to be connected to the word line under the control of the main word line and the second selection terminal. The first switching circuit is connected to the first enable terminal, the second node, the first power supply terminal and the first node respectively, and is used to control the connection and disconnection between the first power supply terminal and the first node under the control of the first enable terminal and the second node. The switch control circuit is connected to the first selection terminal, the first enable terminal, the first power supply terminal, the second power supply terminal and the second node respectively, and is used to control the first power supply terminal or the second power supply terminal to be connected to the second node under the control of the first selection terminal and the first enable terminal. The voltage at the first power supply terminal is lower than the voltage at the second power supply terminal.

2. The word line driver according to claim 1, characterized in that, The switch control circuit includes: a first control sub-circuit and a second control sub-circuit; The first control sub-circuit is connected to the first enable terminal, the first power supply terminal, and the third node respectively, and is used to control the connection and disconnection between the first power supply terminal and the third node under the control of the first enable terminal. The second control sub-circuit is connected to the first selection terminal, the second power supply terminal, the third node, and the second node respectively, and is used to control the second power supply terminal or the third node to be connected to the second node under the control of the first selection terminal.

3. The word line driver according to claim 2, characterized in that, The first control sub-circuit includes: a first transistor; The gate of the first transistor is connected to the first enable terminal, the first electrode of the first transistor is connected to the first power supply terminal, and the second electrode of the first transistor is connected to the third node.

4. The word line driver according to claim 2, characterized in that, The second control sub-circuit includes: a second transistor and a third transistor with opposite polarities; The gate of the second transistor is connected to the first selection terminal, the first terminal of the second transistor is connected to the second power supply terminal, and the second terminal of the second transistor is connected to the second node; The gate of the third transistor is connected to the first selection terminal, the first electrode of the third transistor is connected to the third node, and the second electrode of the third transistor is connected to the second node.

5. The word line driver according to any one of claims 1 to 4, characterized in that, The first switching circuit includes: a fourth transistor and a fifth transistor; The gate of the fourth transistor is connected to the first enable terminal, the first terminal of the fourth transistor is connected to the second terminal of the fifth transistor, and the second terminal of the fourth transistor is connected to the first node. The gate of the fifth transistor is connected to the second node, and the first terminal of the fifth transistor is connected to the first power supply terminal.

6. The word line driver according to any one of claims 1 to 4, characterized in that, The driving circuit includes: a sixth transistor, a seventh transistor, and an eighth transistor; The gate of the sixth transistor is connected to the main word line, the first terminal of the sixth transistor is connected to the word line driving terminal, and the second terminal of the sixth transistor is connected to the word line. The gate of the seventh transistor is connected to the main word line, the first terminal of the seventh transistor is connected to the first node, and the second terminal of the seventh transistor is connected to the word line; The gate of the eighth transistor is connected to the second selection terminal, the first terminal of the eighth transistor is connected to the first node, and the second terminal of the eighth transistor is connected to the word line.

7. The word line driver according to any one of claims 1 to 4, characterized in that, The word line driver further includes: a second switching circuit; The second switching circuit is connected to the second enable terminal, the third power supply terminal and the first node respectively, and is used to control the connection and disconnection between the third power supply terminal and the first node under the control of the second enable terminal; The voltage at the third power supply terminal is higher than the voltage at the first power supply terminal and lower than the voltage at the second power supply terminal.

8. The word line driver according to claim 7, characterized in that, The second switching circuit includes: a ninth transistor; The gate of the ninth transistor is connected to the second enable terminal, the first terminal of the ninth transistor is connected to the third power supply terminal, and the second terminal of the ninth transistor is connected to the first node.

9. The word line driver according to claim 7, characterized in that, The word line driver further includes: a first enable circuit and a second enable circuit; The first enabling circuit is connected to the initial enabling terminal, the first power supply terminal, the second power supply terminal and the second enabling terminal respectively, and is used to control the first power supply terminal or the second power supply terminal to be connected to the second enabling terminal under the control of the initial enabling terminal. The second enabling circuit is connected to the second enabling terminal, the first power supply terminal, the second power supply terminal, and the first enabling terminal respectively, and is used to control the first power supply terminal or the second power supply terminal to be connected to the first enabling terminal under the control of the second enabling terminal.

10. The word line driver according to claim 9, characterized in that, The first enabling circuit includes: a tenth transistor and an eleventh transistor with opposite polarities; The gate of the tenth transistor is connected to the initial enable terminal, the first terminal of the tenth transistor is connected to the second power supply terminal, and the second terminal of the tenth transistor is connected to the second enable terminal. The gate of the eleventh transistor is connected to the initial enable terminal, the first terminal of the eleventh transistor is connected to the first power supply terminal, and the second terminal of the eleventh transistor is connected to the second enable terminal.

11. The word line driver according to claim 9 or 10, characterized in that, The second enabling circuit includes: a twelfth transistor and a thirteenth transistor with opposite polarities; The gate of the twelfth transistor is connected to the second enable terminal, the first terminal of the twelfth transistor is connected to the second power supply terminal, and the second terminal of the twelfth transistor is connected to the first enable terminal. The gate of the thirteenth transistor is connected to the second enable terminal, the first terminal of the thirteenth transistor is connected to the first power supply terminal, and the second terminal of the thirteenth transistor is connected to the first enable terminal.

12. A word line driving method, characterized in that, Applied to a word line driver as described in any one of claims 1 to 11, the method comprises: During the selection phase of the word line connected to the word line driver, the driving circuit in the word line driver controls the connection between the first node and the word line to be disconnected. The switch control circuit in the word line driver controls the first power supply terminal to be connected to the second node under the control of the first selection terminal and the first enable terminal; The first switching circuit in the word line driver, under the control of the second node, controls the connection between the first power supply terminal and the first node to be disconnected.

13. The method according to claim 12, characterized in that, During the selection phase of the character line, the method further includes: Under the control of the main word line, the driving circuit controls the word line driving end to be connected to the word line; The second switching circuit in the word line driver, under the control of the second enable terminal, controls the connection between the third power supply terminal and the first node to be disconnected.

14. The method according to claim 12 or 13, characterized in that, The method further includes: During the selection phase of other word lines, the driving circuit, under the control of the second selection terminal, controls the first node to be connected to the word line; The second switching circuit in the driving circuit, under the control of the second enable terminal, controls the connection between the third power supply terminal and the first node to be disconnected. Under the control of the first selection terminal, the switch control circuit controls the second power supply terminal to be connected to the second node; Under the control of the second node and the first enable terminal, the first switching circuit controls the first power supply terminal to be connected to the first node.

15. The method according to claim 12 or 13, characterized in that, The method further includes: During the standby phase, the driving circuit, under the control of the second selection terminal, controls the first node to be connected to the word line; The second switching circuit in the driving circuit controls the third power supply terminal to be connected to the first node under the control of the second enable terminal. Under the control of the first selection terminal, the switch control circuit controls the second power supply terminal to be connected to the second node; Under the control of the first enable terminal, the first switching circuit controls the connection between the first power supply terminal and the first node to be disconnected.

16. A memory, characterized in that, The memory includes: a memory array, multiple word lines connected to the memory array, and multiple word line drivers as described in any one of claims 1 to 11; Each of the word line drivers is connected to one of the word lines and is used to drive the word line.

17. A storage system, characterized in that, The storage system includes: a memory controller, and at least one memory as described in claim 16.

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