Contactless communication device modulated by active load

Abstract

An apparatus for contactless communication by active load modulation comprises a receiving circuit configured to receive as an input a receive signal originating from an electromagnetic field intended to be received by an antenna and to deliver as an output a first clock signal. The transmission circuit includes an output coupled to the antenna and operates to deliver a modulated signal on its output that is in phase with the received signal. The compensation circuit is configured to compensate for a first delay of the first clock signal due to amplitudes of the receiving circuit and the received signal. The compensation circuit operates to determine an input signal to be applied to the transmission circuit to compensate for a phase shift value of the first delay.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority of French patent application No. 2310038, filed on September 22, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present disclosure generally relates to the field of wireless communication between a reader and a contactless communication device by active load modulation, in particular the field of wireless communication between a reader and such a device in card emulation (CE) mode. The present disclosure may particularly relate to the field of contactless communication implemented with near field communication (NFC) technology. Background Art

[0004] Near Field Communication (NFC) is a wireless connectivity technology that allows communication over short distances (e.g., a few tens of centimeters) between electronic devices (such as, for example, between a contactless chip card and a reader, or between a card emulation (CE) device (e.g., a cellular phone or a connected object) and a reader).

[0005] A contactless communication device is a device capable of exchanging information with another contactless device (eg, a reader) via an antenna according to a contactless communication protocol.

[0006] An NFC device, which is a contactless device, is a device compatible with NFC technology. NFC technology is an open technology platform that is standardized in the ISO / IEC 18092 and ISO / IEC 21481 standards, but combines many existing standards (such as, for example, the Type A and Type B protocols defined in the ISO-14443 standard), which may be communication protocols that can be used in NFC technology.

[0007] The CE device may be used to exchange information with another contactless device (eg, a contactless reader) using a contactless communication protocol available in NFC technology.

[0008] During the information transmission between the reader and the CE device or NFC card, the reader generates an electromagnetic field via its antenna, which is generally a sine wave with a frequency equal to 13.56 MHz according to the commonly used standards. Each NFC device (reader and CE device) transmits data by using a modulation scheme, such as Amplitude Shift Keying (ASK) modulation.

[0009] There are two modes of operation possible: passive mode (corresponding to the mode used by NFC cards) or active mode (corresponding to the mode generally used by CE devices).

[0010] In passive mode, also called passive load modulation (PLM), only the reader generates the electromagnetic field, while the card is passive. The card's antenna modulates the electromagnetic field generated by the reader by modifying the load connected across the card antenna, which changes the output impedance of the reader antenna due to the magnetic coupling between the two antennas. This results in a change in the amplitude and / or phase of the voltage and current present at the reader and card's antennas. Thus, information is transmitted from the card to the reader by load modulation of the reader's antenna current.

[0011] In active mode, also called active load modulation (ALM), both the reader and the CE device generate an electromagnetic field. This mode of operation is used when the CE device is provided with a specific power source, such as a battery.

[0012] Generally speaking, CE devices comprise smaller antennas than those of NFC cards, and this is why active load modulation is generally used in such devices.

[0013] During active load modulation, the electromagnetic fields emitted by the reader and the CE device are in phase with each other so that the detection sensitivity of the device is not reduced. The CE device may in particular comprise a receiving circuit comprising, for example, a variable gain amplifier (VGA), and a converter that converts a sinusoidal signal into a square wave signal so as to enable a clock signal to be extracted from the field generated by the reader, the clock signal being used to synchronize in phase a phase locked loop (PLL) that is in particular used to compensate for propagation delays in the receiving circuit.

[0014] However, VGAs and converters are subject to process, voltage, temperature (PVT) variations that can produce delays or advances in the received signal, resulting in a phase shift between the electromagnetic field emitted by the reader and the electromagnetic field emitted by the CE device. Variations in the amplitude of the electromagnetic field emitted by the reader and / or in the amplitude of the coupling between the reader's antenna and the CE device's antenna may also contribute to this phase shift, given that the delay in the transmission of the signal through the receiving circuit also varies depending on the amplitude of the received electromagnetic field and therefore on the coupling between the reader's antenna and the CE device's antenna.

[0015] There is a need to provide a solution that enables solving the problems encountered with existing solutions. Summary of the invention

[0016] An embodiment that overcomes all or part of the aforementioned disadvantages provides a device for contactless communication by active load modulation, comprising: a receiving circuit configured to receive a received signal originating from an electromagnetic field intended to be received by an antenna as input and to deliver a first clock signal as output; a transmitting circuit comprising a modulated signal coupled to an output of the antenna and intended to deliver a modulated signal at its output that is in phase with the received signal; a circuit for compensating for a first delay of the first clock signal caused by the receiving circuit and the amplitude of the received signal, configured to determine a phase shift value to be applied to the input signal of the transmitting circuit to compensate for the first delay.

[0017] According to one embodiment, the receiving circuit includes at least: a variable gain amplifier configured to receive a receive signal as input; a converter of a sinusoidal signal to a square wave signal, including an input terminal coupled to an output terminal of the variable gain amplifier, and an output terminal intended to deliver a first clock signal thereon.

[0018] According to an embodiment, the apparatus further comprises a phase locked loop configured to receive the first clock signal and the phase shift value as input and to deliver an input signal of the transmission circuit on a first output.

[0019] According to one embodiment, the compensation circuit includes at least one lookup table configured to store a plurality of phase shift values, each phase shift value being associated with an amplitude value of a received signal, and configured to deliver one of the phase shift values ​​as an output depending on the value of a control signal applied at an input of the lookup table and whose value depends on the amplitude of the received signal.

[0020] According to one embodiment, the compensation circuit also includes: an analog-to-digital converter, including an input terminal coupled to the output terminal of the variable gain amplifier; a first calculation circuit, including an input terminal coupled to the output terminal of the analog-to-digital converter, and configured to determine the amplitude value of the received signal and deliver as an output a control signal whose value depends on the determined amplitude value of the received signal.

[0021] According to an embodiment, the output of the first calculation circuit is coupled to a gain control input of the variable gain amplifier.

[0022] According to an embodiment, the compensation circuit comprises at least one circuit for measuring a phase difference between a first clock signal and a second clock signal synchronized with the received signal.

[0023] According to one embodiment, the measurement circuit includes at least: a counting trigger circuit, including two input terminals to which the first and second clock signals are intended to be applied, and is configured to deliver a counting trigger signal as an output, which has a first value within a time period equal to the first delay and has a second value different from the first value outside the time period; a counter, including a clock input terminal coupled to the output terminal of the counting trigger circuit, and a data input terminal coupled to the second output terminal of the phase-locked loop, the second output terminal of the phase-locked loop is intended to deliver thereon a periodic signal whose frequency is equal to a multiple of the frequency of the input signal of the transmission circuit; a second calculation circuit, configured to determine a phase shift value based on the value of the counting signal intended to be output by the counter.

[0024] According to an embodiment, the compensation circuit further comprises a buffer memory circuit configured to receive the second clock signal as input and comprising an output terminal coupled to one of the two input terminals of the counting flip-flop circuit.

[0025] Another embodiment provides a calibration method for an apparatus such as defined above, comprising the implementation of at least the following steps: a) applying a received signal at the input of a receiving circuit of the apparatus; b) calculating and storing a phase shift value as a function of the amplitude of the received signal by a compensation circuit of the apparatus; and wherein steps a) and b) are repeated multiple times by modifying the amplitude value of the received signal at each repetition.

[0026] According to an embodiment, steps a) and b) are repeated by scanning the range of amplitude values ​​of the received signal, from an expected minimum value to a maximum value of this amplitude.

[0027] According to an embodiment, for each amplitude value of the received signal, steps a) and b) are repeated multiple times by modifying the supply voltage value of the device and / or the temperature value of the device at each repetition.

[0028] Another embodiment provides a method for contactless communication between a reader and a device such as defined above, comprising the implementation of at least the following steps: detecting an electromagnetic field by the device; when the device detects the electromagnetic field, transmitting a first clock signal by a receiving circuit of the device, which receives a received signal originating from the electromagnetic field as input; applying a phase shift value to a signal applied at the input end of the transmission circuit of the device by a compensation circuit of the device, the applied phase shift value is intended to compensate for a first delay of the first clock signal caused by the receiving circuit and the amplitude of the received signal and depending on the amplitude of the received signal; applying a modulated signal that is in phase with the received signal to the antenna by the transmission circuit of the device.

[0029] According to an embodiment, a receiving circuit of an apparatus comprises at least one variable gain amplifier configured to receive a receive signal as input, and further comprising, before applying a phase shift value to a signal applied at an input of a transmitting circuit of the apparatus, controlling the gain of the variable gain amplifier by a compensation circuit, the value of the gain being selected as a function of the amplitude of the receive signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above features and advantages and other features and advantages will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0031] Figure 1 An example of an apparatus for contactless communication by active load modulation with a contactless reader is schematically shown;

[0032] Figure 2 schematically shows details of an example of an apparatus for contactless communication by active load modulation;

[0033] Figure 3 Schematically showing the steps of an example of a method of calibrating an apparatus for contactless communication by active load modulation;

[0034] Figure 4 The steps of an example of a method for communicating between a device and a reader by contactless communication using active load modulation are schematically shown;

[0035] Figure 5 schematically shows details of an example of an apparatus for contactless communication by active load modulation;

[0036] Figure 6 Schematically shows an example of a counter of a phase-locked loop of a device for contactless communication by active load modulation;

[0037] Figure 7 schematically shows an example of a counting trigger circuit and a counter forming part of an apparatus for contactless communication by active load modulation;

[0038] Figure 8 Shows Figure 7 An example timing diagram of the signals used in the circuit. DETAILED DESCRIPTION

[0039] Similar features in the various figures are indicated by similar reference numerals. In particular, common structural and / or functional features between various embodiments may have the same reference numerals and may have exactly the same structure, size, and material properties.

[0040] For the sake of clarity, only the steps and elements useful for understanding the described embodiments are illustrated and described in detail. In particular, the formation of the different elements and circuits of the device (variable gain amplifier, converter of sinusoidal signal to square wave signal, phase-locked loop, lookup table, analog-to-digital converter, calculation circuit, delay circuit, trigger, counter, etc.) is not described in detail. Those skilled in the art can implement the different functions of the device in detail based on the functional description given herein.

[0041] Unless otherwise indicated, when two elements are referred to as being connected together, this means a direct connection without any intervening elements except conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0042] Unless otherwise indicated, the expressions "approximately", "approximately", "substantially" and "about" mean plus or minus 10%, preferably plus or minus 5%.

[0043] Combine the following Figure 1 An example of an apparatus 100 for contactless communication by active load modulation according to a specific embodiment is described.

[0044] The device 100 is of NFC type, ie, configured to use a communication protocol compatible with NFC technology. In the example described, the device 100 corresponds to a device in card emulation mode (CE). Figure 1 , the device 100 is shown during communication with a contactless reader (R) 200 of the NFC type.

[0045] In the example described, the device 100 comprises an antenna 102 intended to exchange data with an antenna 202 of the reader 200 via the emission of electromagnetic fields by these antennas 102 , 202 and magnetic coupling of these antennas 102 , 202 .

[0046] exist Figure 1 In the specific configuration shown in FIG. 1 , the device 100 further includes a matching circuit (M) 104 coupled between the antenna 102 and other elements of the device 100. The circuit 104 may be used to match the impedance of the antenna 102 to interface the antenna 102 input and output signals.

[0047] The apparatus 100 further comprises a receiving circuit 110 configured to receive as input a received signal originating from an electromagnetic field intended to be received by the antenna 102 and to deliver as output a first clock signal. Figure 1 In the invention, the received signal is called "RFI" and corresponds to a sinusoidal signal. The frequency of the signal RFI is, for example, equal to 13.56 MHz.

[0048] In with Figure 1 In a specific configuration corresponding to the configuration shown in , the receiving circuit 110 includes at least: a variable gain amplifier (VGA) 112, configured to receive an input signal RFI; and a converter 114 that converts a sinusoidal signal into a square wave signal, including an input end coupled to an output end of the VGA 112, and an output end, intended to deliver a first clock signal thereon.

[0049] In this particular configuration, the signal transmitted from the output of converter 114 corresponds to a square wave signal having an amplitude greater than that of signal RFI, ie corresponds to transforming signal RFI into a square wave signal amplified with a gain greater than one.

[0050] As a variant, the receiving circuit 110 may include additional components and / or Figure 1 The elements of the example embodiments are different elements.

[0051] The device 100 also includes a transmission circuit 116 that includes a modulated signal (referred to as "RFO") coupled to an output of the circuit 104 and intended to be delivered at the output to the antenna 102. The signal RFO includes information intended to be delivered by the device 100 to the reader 200. The signal RFO is intended to be in phase with the signal RFI.

[0052] The apparatus 100 further includes a compensation circuit (Cmp) 118 for compensating for a first delay δ of the first clock signal caused by the receiving circuit 110. clex , which includes delays due to at least a portion of PVT variations of components of the receiving circuit 110 and due to the amplitude of the signal RFI. When the device 100 is communicating with the reader 200, the amplitude of the received signal RFI may be proportional to the amplitude of the electromagnetic field received by the antenna 102, and thus proportional to the coupling between the antennas 102, 202. The compensation circuit 118 is configured to determine an input signal to be applied to the transmission circuit 116 to compensate for the first delay δ clex The phase shift value.

[0053] exist Figure 1In the specific configuration shown in , the device 100 further comprises a phase-locked loop (PLL) 120, intended to synchronize the signal RFO with the received signal RFI, thereby compensating for the delays caused by the processing of the signals in the different circuits and elements of the device 100. This PLL 120 is configured to receive as input the first clock signal delivered by the receiving circuit 110 and the phase shift value determined by the compensation circuit 118, and to deliver on a first output the input signal of the transmission circuit 116. Thus, the PLL 120 is here configured to take into account the phase shift value determined by the compensation circuit 118, so that the signal delivered from the output of the PLL 120 to the transmission circuit 116 no longer includes a phase shift or delay caused by the receiving circuit 110 and by the amplitude of the received signal RFI.

[0054] exist Figure 1 In the figure, only some of the elements of the device 100 are shown. Figure 1 In addition to the elements shown in , device 100 also includes other circuits and elements not described herein, such as, for example, circuits for modulating and demodulating data received and transmitted by device 100.

[0055] exist Figure 1 In the configuration shown in FIG. 1 , the device 100 also includes a battery (B) 122 , which is intended to power the various circuits and components of the device 100 .

[0056] Combine the following Figure 2 A more detailed example of the apparatus 100 is described. Figure 2 In the embodiment, only some of the components and circuits of the device 100 are shown and described below. Figure 1 compared to, Figure 2 The antenna 102 and the circuit 104 of the device 100 are not shown.

[0057] In this example, the device 100 comprises an input 124 having a square wave signal (the square wave signal is of the same frequency and in phase with the signal RFI) which is intended to be applied to the input 124 during a calibration method of the device 100 to be described below. The square wave signal applied to the input 124 during the calibration method is delivered, for example, by a calibrated oscillator whose output is coupled to the input 124 during the calibration method of the device 100.

[0058] exist Figure 2 In the example of FIG. 1 , the compensation circuit 118 includes a buffer memory circuit 126 (or buffer) to allow good propagation of the signal received at the input 124 during calibration of the device 100. The circuit 126 applies a second delay, referred to as δ static And its value is much lower than the first delay δ clex The second delay δ staticThe value of does not depend on the amplitude of the received signal and can be considered static or constant during calibration of the device 100. The signal delivered as an output of the circuit 126 forms the second clock signal with which the first clock signal delivered as an output of the receiving circuit 110 will be compared in order to be able to determine a phase shift that enables compensation of the first delay.

[0059] As a variant, the second clock signal may be obtained in a different way than described herein.

[0060] In the depicted example, compensation circuit 118 also includes circuitry for measuring a phase difference between the first and second clock signals.

[0061] In with Figure 2 In the corresponding specific configuration shown in , the measurement circuit includes: a counting trigger circuit 128, which includes two input terminals (the first and second clock signals are intended to be actually applied to these two input terminals), and is configured to deliver a counting trigger signal as an output, which has a first value for a time period equal to the first delay and has a second value different from the first value outside the time period; a counter (C) 130, including a clock input terminal coupled to the output terminal of the circuit 128, and a data input terminal coupled to the second output terminal of the PLL 120, and is intended to deliver thereon a periodic signal having a frequency equal to a multiple of the frequency of the input signal of the transmission circuit 116; and a calculation circuit (CM) 132, which is configured to determine the phase shift value to be applied based on the value of the counting signal intended to be delivered by the counter 130, and the output terminal of the counter 130 is coupled to the input terminal of the calculation circuit 132.

[0062] The value of the frequency of the periodic signal delivered at the second output of PLL 120 may depend on the components of PLL 120 and, for example, on the operating frequency of an oscillator present in PLL 120. For example, the frequency of the received signal and the frequency of the input signal of the transmission circuit 116 may be equal to 13.56 MHz, while the frequency of the periodic signal delivered at the second output of PLL 120 may be equal to approximately 868 MHz (64*13.56 MHz).

[0063] Thus, this example of a measurement circuit provides for measuring a phase difference between the first and second clock signals via counting, the phase difference representing the first delay δ clex , the result of the count will represent the phase difference, thus representing the first delay δ clex .

[0064] As a variant, the functions performed by the measuring circuit may be obtained by using different circuits and components than those described above.

[0065] In the described example, the compensation circuit 118 also includes a lookup table (LUT) 134 configured to store a plurality of phase shift values, each phase shift value being associated with an amplitude value of the received signal. These phase shift values ​​can be sent from an output of the calculation circuit 132, which is coupled to one of the inputs of the lookup table 134. The LUT 134 also includes an output, on which one of the stored phase shift values ​​is intended to be delivered to the PLL 120, the value being selected from the stored values ​​according to the value of a control signal intended to be applied to the input of the LUT 134. As described below, the value of the control signal, and therefore the phase shift value delivered as the output of the LUT 134, will be a function of the amplitude value of the received signal received by the receiving circuit 110.

[0066] In combination Figure 2 In the described example, the compensation circuit 118 also includes: an analog-to-digital converter (ADC) 136, which includes an input terminal coupled to the output terminal of the VGA 112; and another computing circuit 138, which includes an input terminal coupled to the output terminal of the ADC 136 and is configured to determine the amplitude value of the received signal and deliver a control signal as an output, the value of the control signal depending on the determined amplitude value of the received signal.

[0067] The output of the calculation circuit 138 is coupled to a second input of the LUT 134. Thus, depending on the value supplied at this second input, i.e. depending on the determined amplitude value of the received signal, the LUT 134 can deliver as output one of the stored phase shift values, which corresponds to the phase shift value stored for this amplitude value. Figure 2 The phase shift value delivered by the lookup table 134 is referred to as “φ offset ", and enables compensation of the first delay δ clex (Compensation is indicated at the output of LUT 134 by “-δ clex "express).

[0068] As a variation, circuits different from the circuits 136 and 138 described below may be used to perform similar functions.

[0069] In the depicted example, the output of the computation circuit 138 is also coupled to a gain control input of the VGA 112. Thus, depending on the value of the amplitude of the received signal, the gain of the VGA 112 may be adjusted.

[0070] During a calibration method of the device 100 , the following steps may be implemented: a) applying a received signal as input to the receiving circuit 110 of the device 100 ; and b) calculating and storing a phase shift value as a function of the amplitude of the received signal by the compensation circuit 118 .

[0071] Therefore, this calibration method enables a plurality of phase shift values ​​to be associated and stored in the LUT 134 according to a plurality of amplitude values ​​of the received signal.

[0072] Figure 3 The steps of an example of a calibration method of the device 100 are schematically shown.

[0073] During an initial step 300, a reception signal of minimum amplitude is applied to the input of the reception circuit 110, either preferably via direct coupling to the wiring of the card on which the device 100 is formed (e.g. during industrial testing during the manufacture of the device 100), or via application of a minimum electromagnetic field detected by the antenna 102 (e.g. during tests performed on the final device 100). This minimum amplitude is, for example, in the range of 1 mV to 100 mV.

[0074] The received signal is amplified by VGA 112, digitally converted by ADC 136, and processed by computing circuit 138. The gain of VGA 112 is automatically adjusted according to the amplitude of the received signal (step 302).

[0075] A first clock signal is obtained at the output of converter 114 , after which its phase is compared by circuit 128 with the phase of a second clock signal applied to input 124 and placed in a buffer memory in circuit 126 .

[0076] Then, elements 130 and 132 calculate the delay δ to be applied to the received signal to compensate for the first delay δ clex The phase shift value of (step 304).

[0077] The calculated phase shift value is then stored in the LUT 134, where it is associated with the amplitude value of the received signal (step 306).

[0078] During step 308, the amplitude value of the received signal is compared with the maximum amplitude value of the received signal. If the amplitude value of the received signal is lower than the maximum value, the amplitude of the received signal is increased (step 310) and steps 302 to 308 are repeated. The amplitude of the received signal is increased, for example, by a value corresponding to the gain pitch of the VGA 112. If the amplitude value of the received signal is equal to the maximum value, the calibration method ends (step 312). The maximum amplitude value of the received signal is, for example, in the range of 10V to 30V. In addition, steps 302 to 308 can be repeated X times, where X is an integer in the range of 10 to 20.

[0079] Therefore, implementation of this calibration method enables storing in the LUT 134 a phase shift value to be applied to the received signal to compensate for the delay due to process variations of the receiving circuit 110 and the amplitude of the received signal.

[0080] As a variant, the calibration method of the device 100 may include other steps and / or steps different from the above steps. For example, in order to compensate for the delay caused by voltage and / or temperature variations of the receiving circuit 110 in addition to the delay caused by process variations of the receiving circuit 110 (however, this delay is much lower than the delay caused by process variations), the calibration method of the device 100 may include repeating the previously described steps for different values ​​of the supply voltage of the device 100 and / or different values ​​of the temperature of the device 100.

[0081] Figure 4 The steps of an example of a method for the device 100 to communicate with the reader 200 are schematically shown.

[0082] The device 100 may be in an inactive state (step 400).

[0083] During a step 402 , the device 100 verifies whether an electromagnetic field corresponding to a communication is detected.

[0084] When no such electromagnetic field is present, the device 100 remains in an inactive state (returning to step 400).

[0085] In the presence of such an electromagnetic field, a first clock signal is delivered by the receive circuit 110, which receives as input a receive signal originating from the electromagnetic field received by the antenna 102 (step 404).

[0086] The gain of VGA 112 may be adjusted by compensation circuit 118, with the gain value being a function of the amplitude of the received signal (step 406).

[0087] Then, a phase shift value is applied by the compensation circuit 118, for example, as an input to the PLL 120, wherein the phase shift value may correspond to the phase shift value for the amplitude value of the received signal in the phase shift values ​​stored in the LUT 134 (step 408). The PLL 120 may then take the phase shift value into account and apply it to the signal at the input of the transmission circuit 116 to compensate for the first delay.

[0088] A modulated signal in phase with the received signal is then obtained at the output of the transmission circuit 116 and applied to the antenna 102, thereby allowing communication between the device 100 and the reader 200 (step 410).

[0089] The following will combine Figure 5 An example of the apparatus 100 is described. Figure 5 In the embodiment, only some of the components and circuits of the device 100 are shown and described below. Figure 1 In comparison, the antenna 102 and circuit 104 of the device 100 are Figure 5 In addition, the previous Figure 2The circuits 134, 136, 138 described in Figure 5 Not shown in FIG.

[0090] Compared with the previous Figure 2 The described device 100 is compared to Figure 5 An example of PLL 120 is shown in detail in FIG.

[0091] exist Figure 5 In the example of , the PLL 120 includes a counter (C) 140 , an oscillator (O) 142 , a filter (F) 144 , a subtractor 146 , and an adder 148 .

[0092] In this example, the counter 140 includes a clock input coupled to the output of the receiving circuit 110, an output coupled to an oscillator 142 (which is similar to the output of the oscillator 142 described previously). Figure 2 The second output terminal of the described PLL 120 corresponds to the data input terminal of ), and the output terminal coupled to the negative input terminal of the subtractor 146 and delivering the count value thereon. The counter 140 also delivers the input signal of the transmission circuit 116 at another output terminal.

[0093] The target phase value (called “φ target ”) is applied to the positive input of subtractor 146. Taking into account the delays caused by the different components and circuits of device 100, and not taking into account the delays caused by PVT variations of receiving circuit 110 and the amplitude of the received signal, the value φ target The predetermined value may correspond to a predetermined value, which is stored, for example, in a register of the apparatus 100 and corresponds, for example, to an expected phase shift.

[0094] The output of the subtractor 146 is coupled to a first input of the adder 148, and the phase shift value φ offset is applied to a second input terminal of adder 148 .

[0095] The output of adder 148 is coupled to the input of filter 144 , and the output of filter 144 is coupled to the input of oscillator 142 .

[0096] According to an example, the oscillator 142 may be of the digitally controlled oscillator (DCO) type.

[0097] According to an example, the frequency of the periodic signal delivered by the oscillator 142 may be equal to approximately 868 MHz (64*13.56 MHz), and the frequency of the input signal of the transmission circuit 116 delivered by the counter 140 and the frequencies of the received signal and the first clock signal may be equal to 13.56 MHz.

[0098] As a variant, PLL 120 may include the same Figure 5The circuits and / or components shown in FIG. 5 are different from those shown in FIG.

[0099] Figure 6 An example embodiment of the counter 140 is shown in FIG.

[0100] In this example, counter 140 includes an input 149 to which the output signal of oscillator 142 is applied. Figure 6 In the example of , the counter 140 also includes a plurality of frequency dividers 150, which are coupled in series with each other so that the output of each of these frequency dividers is coupled to the clock input of the next frequency divider. In this example, the output signal of the oscillator 142 is applied to the clock input of the first frequency divider 150. In addition, the output signal of one of the frequency dividers 150 corresponds to the input signal of the transmission circuit 116. In this example, the frequency divider 150 is configured to divide the frequency of the signal received at its input by a factor of 2. Thus, in the described example, assuming that the ratio of the frequency of the periodic signal delivered by the oscillator 142 to the frequency of the input signal of the transmission circuit 116 is equal to 64, then the input signal of the transmission circuit 116 (2 6 =64). Furthermore, in a specific configuration, each frequency divider 150 configured to divide the frequency of a signal received at its input by a factor of 2 may be formed by a D flip-flop, the output of which is fed back to its input via an inverter.

[0101] In this example, the counter 140 also includes a plurality of flip-flops 152 ( Figure 6 The oscillator 142 is a clock signal that is applied to the clock input of each flip-flop 152. The first clock signal delivered by the receiving circuit 110 is applied to the data input of the first flip-flop 152. These flip-flops 152 make it possible to avoid metastable states in the counter 140.

[0102] In the example described, the counter 140 further comprises other D-type flip-flops 154, which are coupled in series with each other so that the clock inputs of these flip-flops 154 are coupled with each other. The first of these flip-flops 154 receives the output signal of the last flip-flop 152 at its clock input and the output signal of the oscillator 142 at its data input. The other flip-flops 154 receive the output signal of the frequency divider 150 at their data input. The output signals of the flip-flops 154 together form the count signal (in Figure 6 154), which is encoded in binary form in this example (the output signal of each flip-flop 154 ​​corresponds to one bit of the count signal).

[0103] As a variant, the counter 140 may be composed of the same Figure 6 The elements and / or components shown in FIG. 1 are formed by different elements and / or components.

[0104] Figure 7 An example embodiment of the count trigger circuit 128 and the counter 130 is shown in FIG. Figure 8 Also shown in FIG. 1 are timing diagrams for signals used in these circuits 128 , 130 .

[0105] exist Figure 7 and Figure 8 The following captions were used:

[0106] CLK_FIRST: clock signal, previously called the second clock signal;

[0107] CLK_SECD: clock signal, previously called the first clock signal;

[0108] Window: count the trigger signals;

[0109] WINDOW_EN: a signal for activating the counting trigger circuit 128;

[0110] DCO: output signal of oscillator 142;

[0111] Gated DCO: Figure 7 The output signal of the gate and counter 130 shown in;

[0112] DFLL_counter: output signal of counter 130;

[0113] Delay_meas_done: This signal is delivered at the output of circuit 128 and indicates that counting is complete and can be read at the output of circuit 130;

[0114] RN: This signal resets the D flip-flop when its value is in state 0, and causes the D flip-flop to operate on every clock edge when its value is in state 1;

[0115] Rni: Measurement end indication signal.

[0116] exist Figure 7 In FIG. 1 , the box “Dff” corresponds to a D flip-flop and the box “ / 2” corresponds to a frequency divider applying a frequency division factor equal to 2.

[0117] Figure 7 The operation details of the circuits 128 and 130 shown in FIG. 1 are not described herein, and those skilled in the art will Figure 7 The components and wiring shown in the Figure 8 The timing diagrams will help understand the operation of these circuits. Figure 8 The signals of the timing diagrams are shown schematically, and the amplitudes as well as the durations of different parts of these signals are not to scale relative to each other.

[0118] In different examples, the provided device 100 can enable a calibration method to be implemented during subsequent use of the device to communicate with a reader, in order to compensate for delays caused by at least a part of PVT variations of a receiving circuit 110 of the device 100 and by the amplitude of a received signal received as an input of the receiving circuit 110. In particular, different elements of the device 100 can allow: synchronization of a clock signal (a first clock signal in the above disclosure) with the received signal without delay variations, wherein the clock signal corresponds, for example, to a square wave signal, while the received signal corresponds, for example, to a sinusoidal signal, the amplitude of which can vary; measurement of the delay between the received signal and the first clock signal derived from the received signal; automatic measurement of the delay occurring in the device using a PLL as an accurate time reference, and calibration of the device to compensate for the delay; and storage of phase shift values ​​(for example, in a lookup table) enabling compensation of different delay values ​​depending on the amplitude of the received signal, which can depend on the gain of a variable gain amplifier.

[0119] In all examples, the apparatus may perform accurate compensation on the first extracted clock signal according to the input amplitude of the received signal.

[0120] In all examples, the provided devices can facilitate contactless communication between the device and the reader, allowing the device to have a small antenna and / or low power and / or a large distance between the device and the reader.

[0121] In all examples, delay compensation of a device may be achieved without using an external device to measure the delay, and / or without delivering one or more measurement signals as output, as the compensation may be performed within the device.

[0122] In all examples, the apparatus may include a counter to automatically perform the delay measurement.

[0123] In all examples, due to the delay compensation implemented, the phase of the signal transmitted by the device remains stable even when the amplitude of the electromagnetic field received by the device varies (which results in a resulting electromagnetic field where the amplitude levels differ significantly from each other).

[0124] In the above disclosure, the device 100 corresponds to a device for contactless communication by active load modulation, and the device is in a card emulation mode during communication with a reader. The device 100 may be provided with functionality other than the above functionality. For example, the device 100 may correspond to a cellular phone or a connected object such as a watch.

[0125] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations can be combined, and those skilled in the art will recognize other variations.

[0126] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. A device for contactless communication via active load modulation, comprising: a receiving circuit configured to receive a receive signal originating from an electromagnetic field intended to be received by the antenna and to generate a first clock signal; a transmission circuit comprising an output coupled to an antenna and intended to deliver thereon a modulated signal in phase with the received signal; as well as a compensation circuit configured to compensate for a first delay of the first clock signal due to the receiving circuit and the amplitude of the received signal, wherein the compensation circuit is configured to determine a phase shift value to be applied to the input signal of the transmitting circuit to compensate for the first delay; The compensation circuit includes at least one phase difference measurement circuit, which is configured to measure a phase difference between a first clock signal and a second clock signal synchronized with the received signal.

2. The apparatus according to claim 1, wherein the receiving circuit comprises: a variable gain amplifier configured to receive the received signal; as well as A converter circuit is configured to convert a sinusoidal signal into a square wave signal, the converter circuit having an input coupled to the output of the variable gain amplifier and an output generating a first clock signal.

3. The apparatus of claim 2 , wherein the compensation circuit comprises at least one lookup table configured to store a plurality of phase shift values, each phase shift value being associated with an amplitude value of the received signal, and configured to generate one of the phase shift values ​​according to a value of a control signal applied to an input of the lookup table and having a value dependent on the amplitude of the received signal, and wherein the compensation circuit further comprises: an analog-to-digital converter including an input coupled to an output of the variable gain amplifier; The first calculation circuit comprises an input terminal coupled to the output terminal of the analog-to-digital converter and is configured to determine an amplitude value of the received signal and to generate a control signal whose value depends on the determined amplitude value of the received signal.

4. The apparatus of claim 3, wherein an output of the first computation circuit is coupled to a gain control input of the variable gain amplifier. 5 . The apparatus of claim 1 , further comprising a phase locked loop configured to receive the first clock signal and the phase shift value and generate an input signal of the transmission circuit at a first output terminal.

6. The apparatus of claim 5, wherein the compensation circuit comprises at least one circuit for measuring a phase difference between the first clock signal and a second clock signal synchronized with the received signal, and wherein the measuring circuit comprises at least: a counting trigger circuit comprising two input terminals to which a first clock signal and a second clock signal are intended to be applied and configured to generate a counting trigger signal having a first value for a time period equal to the first delay and having a second value different from the first value outside the time period; a counter comprising a clock input coupled to the output of the counting trigger circuit, and a data input coupled to the second output of the phase-locked loop intended to deliver thereon a periodic signal having a frequency equal to a multiple of the frequency of the input signal of the transmission circuit; as well as A second calculation circuit is configured to determine a phase shift value as a function of the value of the count signal intended to be delivered by the counter. 7 . The apparatus of claim 6 , wherein the compensation circuit further comprises a buffer memory circuit configured to receive the second clock signal and comprising an output terminal coupled to one of the two input terminals of the counting flip-flop circuit.

8. The apparatus of claim 1 , wherein the compensation circuit comprises at least one lookup table configured to store a plurality of phase shift values, each phase shift value being associated with an amplitude value of the received signal, and configured to deliver one of the phase shift values ​​in accordance with a value of a control signal applied to an input of the lookup table and having a value that depends on the amplitude of the received signal.

9. A method for calibrating a device, wherein the device is the device according to claim 1, and the calibration method comprises implementing at least the following steps: a) applying a receive signal at an input of a receive circuit of the device; b) calculating and storing, by a compensation circuit of the device, a phase shift value as a function of the amplitude of the received signal; and Steps a) and b) are repeated multiple times by modifying the amplitude value of the received signal at each repetition.

10. The method of claim 9, wherein steps a) and b) are repeated by scanning a range of amplitude values ​​of the received signal, the range ranging from an expected minimum value to a maximum value of the amplitude.

11. The method according to claim 9, wherein: For each amplitude value of the received signal, steps a) and b) are repeated a number of times by modifying the value of the supply voltage of the device at each repetition.

12. The method according to claim 9, wherein: For each amplitude value of the received signal, steps a) and b) are repeated a number of times by modifying the value of the temperature of the device at each repetition.

13. A method for contactless communication between a reader and a device, the device being the device according to claim 1, the method comprising the implementation of at least the following steps: detecting an electromagnetic field by means of the device; When the device detects the electromagnetic field, transmitting a first clock signal through a receiving circuit of the device, the receiving circuit receiving as input a received signal originating from the electromagnetic field; applying, by a compensation circuit of the device, a phase shift value to a signal applied at an input of a transmission circuit of the device, the applied phase shift value being intended to compensate for a first delay of the first clock signal caused by the receiving circuit and the amplitude of the received signal and depending on the amplitude of the received signal; as well as A modulated signal in phase with the received signal is applied to the antenna by the transmission circuit of the device.

14. The method of claim 13, wherein the receiving circuit of the device comprises at least a variable gain amplifier configured to receive the received signal as input, and The method further comprises, before applying the phase shift value to the signal applied at the input of the transmission circuit of the apparatus, controlling the gain of the variable gain amplifier by means of a compensation circuit, the value of the gain being selected as a function of the amplitude of the received signal.

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