Transmission driver IC, device provided with same, and bus system

Abstract

The invention provides a transmission driver IC, a device provided with the transmission driver IC, and a bus system, which can suppress the collapse of a communication waveform. A bus system is provided with: a first transmission driver IC; a second transmission driver IC; a first communication line and a second communication line connecting the first transmission driver IC and the second transmission driver IC; and a termination resistor connected between the first communication line and the second communication line, the first transmission driver IC and the second transmission driver IC each having: a transmission circuit that transmits a differential signal to the first communication line and the second communication line; a reception circuit that converts the differential signal received from the first communication line and the second communication line into an internal signal; a bypass circuit connected to the first communication line or the second communication line; and a control circuit that operates the bypass circuit so that a communication line current flowing through the first communication line or the second communication line flows through the bypass circuit by being triggered by the internal signal.

Description

Technical Field

[0001] The present disclosure relates to a transmission driver IC, a device having the transmission driver IC, and a bus system. Background Art

[0002] Conventionally, there is known a bus system that transmits a differential signal via a pair of wirings (for example, see Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2014-107660 Summary of the invention

[0004] In a conventional bus system that transmits differential signals via a pair of wirings, if impedance matching is not achieved between the signal transmitter and receiver, the current (communication line current) generated in the pair of wirings due to communication delay, reflection, etc. flows into the terminal resistor connected between the pair of wirings. When the communication line current flows into the terminal resistor, a voltage is sometimes generated at both ends of the terminal resistor, and the communication waveform propagated through the pair of wirings collapses. The collapse of the communication waveform leads to poor communication.

[0005] An object of the present disclosure is to suppress the collapse of a communication waveform.

[0006] The present disclosure provides a bus system, comprising: a first transmission driver IC; a second transmission driver IC; a first communication line and a second communication line, which connect the first transmission driver IC and the second transmission driver IC; and a terminal resistor, which is connected between the first communication line and the second communication line, and the first transmission driver IC and the second transmission driver IC respectively have: a sending circuit, which sends a differential signal to the first communication line and the second communication line; a receiving circuit, which converts the differential signal received from the first communication line and the second communication line into an internal signal; a bypass circuit, which is connected to the first communication line or the second communication line; and a control circuit, which activates the bypass circuit with the internal signal as a trigger, so that the communication line current flowing through the first communication line or the second communication line flows through the bypass circuit.

[0007] The present disclosure provides a transmission driver IC, comprising: a transmitting circuit, which transmits a differential signal to a first communication line and a second communication line, wherein the terminal resistor is disposed between the first communication line and the second communication line; a receiving circuit, which converts the differential signal received from the first communication line and the second communication line into an internal signal; a bypass circuit; and a control circuit, which activates the bypass circuit with the internal signal as a trigger, so that the communication line current flowing through the first communication line or the second communication line flows through the bypass circuit connected to the first communication line or the second communication line.

[0008] The present disclosure provides a device, comprising: an input-output circuit that outputs a transmission signal and receives a reception signal; and a transmission driver IC, the transmission driver IC having: a transmission circuit that converts the transmission signal into a differential signal sent to a first communication line and a second communication line, with a terminal resistor between the first communication line and the second communication line; a receiving circuit that converts the differential signal received from the first communication line and the second communication line into an internal signal; a bypass circuit; and a control circuit that activates the bypass circuit with the internal signal as a trigger, so that the communication line current flowing through the first communication line or the second communication line flows through the bypass circuit connected to the first communication line or the second communication line.

[0009] According to the present disclosure, it is possible to suppress the collapse of the communication waveform. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 : is a diagram illustrating a bus system to which the transmission driver IC of the present disclosure can be applied.

[0011] Figure 2 is a timing diagram illustrating waveforms of various components of the bus system.

[0012] Figure 3 FIG. 1 is a diagram illustrating a bus system including a transmission driver IC according to a first comparative example.

[0013] Figure 4 1 is a diagram illustrating waveforms of various parts of a bus system including a transmission driver IC according to a first comparative example.

[0014] Figure 5 This is a diagram illustrating a bus system including the transmission driver IC according to the first embodiment.

[0015] Figure 6 1 is a diagram illustrating waveforms of various components of a bus system including the transmission driver IC according to the first embodiment.

[0016] Figure 7 This is a timing chart for explaining an example of the structure and method of controlling the bypass circuit by the transmission driver IC according to the first embodiment.

[0017] Figure 8 It is a diagram illustrating a bus system including a transmission driver IC according to the second embodiment.

[0018] Fig. 9 This is a timing chart for explaining an example of the structure and method of controlling the bypass circuit by the transmission driver IC according to the second embodiment.

[0019] Fig.10 It is a diagram illustrating a bus system including a transmission driver IC according to the third embodiment.

[0020] Fig.11 This is a diagram showing an example of the effect of suppressing waveform collapse of an AMI signal with a communication speed of 9.6 kbps.

[0021] Fig.12 This is a diagram showing an example of the effect of suppressing waveform collapse of an AMI signal with a communication speed of 300 kbps. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0023] Figure 1 : is a diagram illustrating a bus system to which the transmission driver IC of the present disclosure can be applied. Figure 1 The bus system 1000 shown is a communication system including a plurality of transmission driver ICs (Integrated Circuits) connected to each other via a pair of communication lines A and B in a balanced manner. Figure 1 Five drivers 211, 212, 213, 214, and 215 (hereinafter also referred to as "drivers 211, etc.") are exemplified as a plurality of transmission driver ICs. Drivers 211, etc. are circuits that have the same communication interface circuits and communicate with each other through differential signals transmitted on a pair of communication lines A and B.

[0024] Figure 1 The bus system 1000 is applied to communication between air-conditioning devices. The bus system 1000 includes a plurality of air-conditioning devices connected to each other in a balanced manner via a pair of communication lines A and B. Figure 1 In FIG. 1 , an indoor unit 201 , a remote control terminal 202 , an indoor unit 203 , a remote control terminal 204 , and an outdoor unit 205 are exemplified as a plurality of air-conditioning devices.

[0025] The indoor unit 201 has a driver 211 and an input / output circuit 221, and performs air conditioning of a room 241. The remote control terminal 202 has a driver 212 and an input / output circuit 222, and is an operation terminal for remotely controlling the indoor unit 201. The indoor unit 203 has a driver 213 and an input / output circuit 223, and performs air conditioning of a room 242. The remote control terminal 204 has a driver 214 and an input / output circuit 224, and is an operation terminal for remotely controlling the indoor unit 203. The outdoor unit 205 has a driver 215 and an input / output circuit 225, and discharges air that has undergone heat exchange with the refrigerant circulating between the indoor units 201 and 203 to the outside.

[0026] Specific examples of the input / output circuits 221 and 223 include processors such as MPU (Micro Processing Unit) and power controllers for controlling the air-conditioning operation of the indoor units 201 and 203. Specific examples of the input / output circuits 222 and 224 include MPUs, display devices such as LCDs (Liquid Crystal Displays), switches (SW), etc. Specific examples of the input / output circuits 225 include MPUs and power controllers for controlling the compression operation of the refrigerant in the outdoor unit 205.

[0027] Driver 211 and the like are based on the home bus system (HBS), but may be based on a bus system different from HBS. Driver 211 and the like each have a transmission terminal OUTA connected to communication line A via a capacitor not shown and a transmission terminal OUTB connected to communication line B via a capacitor not shown.

[0028] Figure 2 It is a timing diagram illustrating the waveforms of each part of the bus system. The bus system 1000, for example, adopts the AMI (Alternate Mark Inversion) method for the waveform of the signal transmitted between multiple devices. The driver 211 and the like have a transmitting circuit, which converts the rectangular wave signal received from the microcomputer such as the MPU through the input terminal DIN into a differential pair of AMI signals and transmits them from the transmitting terminals OUTA and OUTB. The driver 211 and the like have a receiving circuit, which converts the differential pair of AMI signals received from a pair of communication lines A and B into a rectangular wave signal and transmits it from the output terminal DOUT to the microcomputer such as the MPU. The AMI signal propagating in the communication line A and the AMI signal propagating in the communication line B are opposite in phase to each other.

[0029] Figure 3 FIG. 1 is a diagram illustrating a bus system including a transmission driver IC according to a first comparative example. Figure 3 The bus system 300 shown is a communication system for transmitting and receiving differential signals between multiple devices. Figure 3 Two devices 231 and 232 are illustrated as being connected to each other via a pair of communication lines A and B. The bus system 300 includes the device 231, the device 232, the communication line A, and the communication line B. The device 231 includes the MPU 15, the transmission driver IC 1, capacitors 31, 32, 33, 34, and a terminal resistor 30. The terminal resistor 30 is connected between the communication line A and the communication line B. The device 232 includes the MPU 25, the transmission driver IC 2, and capacitors 35, 36, 37, 38.

[0030] The transmission driver IC1 includes a transmission circuit 11 and a receiving circuit 12. The transmission circuit 11 converts the rectangular wave signal Din received from the MPU15 through the input terminal DIN into a differential pair of AMI signals, and transmits them from the transmission terminals OUTA and OUTB to the communication lines A and B. The transmission terminal OUTA is electrically connected to the communication line A via the capacitor 31. The transmission terminal OUTB is electrically connected to the communication line B via the capacitor 32. The receiving circuit 12 converts the differential pair of AMI signals received from the pair of communication lines A and B through the receiving terminals INA and INB into a rectangular wave signal Dout, and transmits it from the output terminal DOUT to the MPU15. The receiving terminal INA is electrically connected to the communication line A via the capacitor 34. The receiving terminal INB is electrically connected to the communication line B via the capacitor 33.

[0031] The transmission driver IC2 includes a transmission circuit 21 and a receiving circuit 22. The transmission circuit 21 converts the rectangular wave signal Din received from the MPU25 through the input terminal DIN into a differential pair of AMI signals and transmits them from the transmission terminals OUTA and OUTB to the communication lines A and B. The transmission terminal OUTA is electrically connected to the communication line A via a capacitor 35. The transmission terminal OUTB is electrically connected to the communication line B via a capacitor 36. The receiving circuit 22 converts the differential pair of AMI signals received from the pair of communication lines A and B by the receiving terminals INA and INB into a rectangular wave signal Dout and transmits it to the MPU25 from the output terminal DOUT. The receiving terminal INA is electrically connected to the communication line A via a capacitor 38. The receiving terminal INB is electrically connected to the communication line B via a capacitor 37.

[0032] In the bus system 300, the terminal resistor 30 is provided in the device 231, but the terminal resistor is not provided in the device 232. Therefore, the longer the communication lines A and B between the device 231 and the device 232 are, the more difficult it is to obtain impedance matching between the device 231 and the device 232. In the case where impedance matching is not obtained between the device 231 and the device 232, part or all of the current (communication line current Itrans) generated in a pair of communication lines A and B due to communication delay, reflection, etc. flows into the terminal resistor 30 as the current Iterm. When the communication line current Itrans flows into the terminal resistor 30, a voltage Vtrans is generated at both ends of the terminal resistor 30, and the communication waveform propagated through the pair of communication lines A and B sometimes collapses. The collapse of the communication waveform leads to poor communication.

[0033] Figure 4 1 is a diagram illustrating waveforms of various parts of a bus system including a transmission driver IC according to the first comparative example. "H" indicates a high level, and "L" indicates a low level (the same applies to waveforms in other figures).

[0034] The transmission circuit 11 converts the rectangular wave signal Din received from the MPU 15 through the input terminal DIN into a pair of differential AMI signals, and transmits them from the transmission terminals OUTA and OUTB to the communication lines A and B. The voltage Vtrans is the voltage generated at both ends of the terminal resistor 30, and is the difference voltage obtained by subtracting the potential of the communication line B from the potential of the communication line A.

[0035] When impedance matching is not achieved between device 231 and device 232, the communication line current Itrans caused by communication delay, reflection, etc. flows to a pair of communication lines A and B. Part or all of the communication line current Itrans flows into the terminal resistor 30 as current Iterm. As the current Iterm changes, the voltage Vtrans rings, and the communication waveform (in this case, the voltage Vtrans) propagated through a pair of communication lines A and B collapses. The ringing of the communication waveform causes oscillation of the received signal Dout output from the receiving circuit 22 to the MPU25 via the output terminal DOUT, which may cause poor reception of the MPU25. In this way, if the excess current Iterm flows into the terminal resistor 30 and the communication waveform collapses, the communication between the device 231 and the device 232 sometimes becomes unstable.

[0036] In contrast, Figure 5 The bus system 301 of the first embodiment shown suppresses the collapse of the communication waveform by reducing the excess current Iterm flowing into the terminal resistor 30. Next, the bus system 301 of the first embodiment will be described.

[0037] Figure 5 It is a diagram of a bus system including the transmission driver IC according to the first embodiment. Figure 5 The bus system 301 shown is a communication system for transmitting and receiving differential signals between multiple devices. Figure 5 Two devices 231 and 232 are shown as examples, which are connected to each other via a pair of communication lines A and B. The number of devices connected to the pair of communication lines A and B is not limited to two, but may be three or more. The devices 231 and 232 may be any of the above-mentioned plurality of air-conditioning devices, for example.

[0038] exist Figure 5 In the embodiment, the bus system 301 includes a device 231, a device 232, a communication line A, and a communication line B. The device 231 includes an MPU 15, a transmission driver IC 10, capacitors 31, 32, 33, 34, and a terminal resistor 30. The terminal resistor 30 is connected between the communication line A and the communication line B. The device 232 includes an MPU 25, a transmission driver IC 20, and capacitors 35, 36, 37, 38.

[0039] The terminal resistor 30 is a resistor between the communication line A and the communication line B. In the example shown in the figure, the terminal resistor 30 is only provided in the device 231, but it can also be provided only in the device 232, or it can be provided in both the devices 231 and 232. Even in the case where the terminal resistor 30 is provided in both the devices 231 and 232, there is a situation where the impedance matching between the device 231 and the device 232 is more difficult to obtain due to the impedance of the communication lines A and B, etc. The terminal resistor 30 only needs to be electrically connected between the communication line A and the communication line B, and can be built into one or both of the transmission driver ICs 10 and 20, or it can be provided outside the devices 231 and 232.

[0040] MPU15 and MPU25 are examples of input-output circuits that output transmission signals and receive reception signals. MPU15 and MPU25 can be any of the above-mentioned input-output circuits provided in the above-mentioned air-conditioning equipment. MPU15 outputs the rectangular wave signal Din as a transmission signal to the transmission driver IC10, and receives the rectangular wave signal Dout as a reception signal from the transmission driver IC10. MPU25 outputs the rectangular wave signal Din as a transmission signal to the transmission driver IC20, and receives the rectangular wave signal Dout as a reception signal from the transmission driver IC20.

[0041] The transmission driver IC 10 is an example of a first transmission driver IC. The transmission driver IC 10 is a semiconductor integrated circuit including a transmission circuit 11, a reception circuit 12, bypass circuits 13A, 13B, and a control circuit 14. In this example, the transmission driver IC 10 further includes a plurality of terminals including a transmission terminal OUTA, a transmission terminal OUTB, a reception terminal INA, and a reception terminal INB. The transmission terminal OUTA is an example of a first transmission terminal. The transmission terminal OUTB is an example of a second transmission terminal. The reception terminal INA is an example of a first reception terminal. The reception terminal INB is an example of a second reception terminal.

[0042] The transmission circuit 11 converts the rectangular wave signal Din received from the MPU 15 via the input terminal DIN into a pair of differential AMI signals, and transmits them from the transmission terminals OUTA and OUTB to the communication lines A and B. The transmission terminal OUTA is electrically connected to the communication line A via the capacitor 31 , and the transmission terminal OUTB is electrically connected to the communication line B via the capacitor 32 .

[0043] The receiving circuit 12 converts a pair of differential AMI signals received from a pair of communication lines A and B via receiving terminals INA and INB into an internal signal RO and outputs the internal signal RO to the control circuit 14. The receiving terminal INA is electrically connected to the communication line A via a capacitor 34. The receiving terminal INB is electrically connected to the communication line B via a capacitor 33.

[0044] Communication lines A and B are wirings that connect the transmission driver IC 10 and the transmission driver IC 20. Communication line A is an example of a first communication line. Communication line A is connected to the transmission terminal OUTA via a capacitor 31, and is connected to the receiving terminal INA via a capacitor 34. Communication line B is an example of a second communication line. Communication line B is connected to the transmission terminal OUTB via a capacitor 32, and is connected to the receiving terminal INB via a capacitor 33.

[0045] The capacitors 31 and 34 may be combined into one capacitor, and the transmission terminal OUTA and the reception terminal INA may be combined into one transmission and reception terminal. The one transmission and reception terminal is branched and connected to the transmission circuit 11 and the reception circuit 12 in the transmission driver IC 10. Similarly, the capacitors 32 and 33 may be combined into one capacitor, and the transmission terminal OUTB and the reception terminal INB may be combined into one transmission and reception terminal. The one transmission and reception terminal is branched and connected to the transmission circuit 11 and the reception circuit 12 in the transmission driver IC 10.

[0046] The bypass circuit 13A is connected to the communication line A. In this example, the transmission driver IC 10 has a bypass terminal BPA, and the bypass circuit 13A is electrically connected to the communication line A via the bypass terminal BPA. The bypass circuit 13A has the ability to sink current and the ability to source current via the bypass terminal BPA. Figure 5 In the case of , the bypass circuit 13A has a buffer 13Aa, which has a current sinking capability and a current sourcing capability. The buffer 13Aa has an output terminal connected to the bypass terminal BPA, an inverting input terminal connected to the output terminal, and a non-inverting input terminal to which a constant voltage (VCC / 2) is input. VCC is a power supply voltage of the transmission driver IC10.

[0047] The bypass circuit 13B is connected to the communication line B. In this example, the transmission driver IC 10 includes a bypass terminal BPB, and the bypass circuit 13B is electrically connected to the communication line B via the bypass terminal BPB. The bypass circuit 13B has the capability of sinking current and the capability of sourcing current via the bypass terminal BPB. Figure 5 In the case of , the bypass circuit 13B includes a buffer 13Ba having a current sinking capability and a current sourcing capability. The buffer 13Ba has an output terminal connected to the bypass terminal BPB, an inverting input terminal connected to the output terminal, and a non-inverting input terminal to which a constant voltage (VCC / 2) is input.

[0048] The control circuit 14 uses the internal signal RO output from the receiving circuit 12 as a trigger to operate the bypass circuit 13A, so that the communication line current Itrans flowing through the communication line A flows through the bypass circuit 13A. Similarly, the control circuit 14 uses the internal signal RO output from the receiving circuit 12 as a trigger to operate the bypass circuit 13B, so that the communication line current Itrans flowing through the communication line B flows through the bypass circuit 13B. The control circuit 14 outputs an enable signal EN for operating the bypass circuits 13A and 13B.

[0049] In this example, the enable signal EN generated by the control circuit 14 is input to the buffers 13Aa and 13Ba. The buffers 13Aa and 13Ba output (VCC / 2) when the enable signal EN is valid, and output high impedance when the enable signal EN is invalid.

[0050] For example, the control circuit 14 has a signal generating circuit 14a that makes the enable signal EN effective by using the internal signal RO as a trigger. The signal generating circuit 14a can also determine the time to make the enable signal EN effective according to the time to charge the capacitor 16 connected via the connection terminal CDF of the transmission driver IC 10 to a predetermined first voltage. The control circuit 14 has a logic circuit 14b that outputs the logical product of the enable signal EN and the internal signal RO. The logic circuit 14b generates the reception signal Dout output to the MPU 15 based on the logical product.

[0051] The transmission driver IC 20 is an example of a second transmission driver IC. The transmission driver IC 20 is a semiconductor integrated circuit including a transmission circuit 21, a reception circuit 22, bypass circuits 23A and 23B, and a control circuit 24. The transmission driver IC 20 has the same structure and function as the transmission driver IC 10, so the above description is cited to simplify the description.

[0052] The transmitting circuit 21 converts the rectangular wave signal Din received from the MPU 25 through the input terminal DIN into a pair of differential AMI signals and transmits them from the transmitting terminals OUTA and OUTB to the communication lines A and B. The receiving circuit 22 converts the differential pair of AMI signals received from the pair of communication lines A and B through the receiving terminals INA and INB into an internal signal RO and outputs it to the control circuit 24. The bypass circuit 23A has the ability to sink current and the ability to source current through the bypass terminal BPA. Figure 5 In the case of, the bypass circuit 23A includes a buffer 23Aa having a current sinking capability and a current sourcing capability. The bypass circuit 23B has a current sinking capability and a current sourcing capability via the bypass terminal BPB. Figure 5 In the case of , the bypass circuit 23B includes a buffer 23Ba having current sinking capability and current sourcing capability.

[0053] The control circuit 24 uses the internal signal RO output from the receiving circuit 22 as a trigger to operate the bypass circuit 23A so that the communication line current Itrans flowing through the communication line A flows through the bypass circuit 23A. Similarly, the control circuit 24 uses the internal signal RO output from the receiving circuit 22 as a trigger to operate the bypass circuit 23B so that the communication line current Itrans flowing through the communication line B flows through the bypass circuit 23B. The control circuit 24 outputs an enable signal EN for operating the bypass circuits 23A and 23B.

[0054] In this example, the enable signal EN generated by the control circuit 24 is input to the buffers 23Aa and 23Ba. The buffers 23Aa and 23Ba output (VCC / 2) when the enable signal EN is valid, and output high impedance when the enable signal EN is invalid.

[0055] For example, the control circuit 24 has a signal generating circuit 24a that makes the enable signal EN effective by using the internal signal RO as a trigger. The signal generating circuit 24a can also determine the time to make the enable signal EN effective according to the time to charge the capacitor 26 connected via the connection terminal CDF of the transmission driver IC 20 to a predetermined first voltage. The control circuit 24 has a logic circuit 24b that outputs the logical product of the enable signal EN and the internal signal RO. The logic circuit 24b generates the reception signal Dout output to the MPU 25 based on the logical product.

[0056] The control circuit 14 uses the internal signal RO output from the receiving circuit 12 as a trigger to operate the bypass circuits 13A and 13B, so that the communication line current Itrans flowing through the communication lines A and B flows through the bypass circuits 13A and 13B. Similarly, the control circuit 24 uses the internal signal RO output from the receiving circuit 22 as a trigger to operate the bypass circuits 23A and 23B, so that the communication line current Itrans flowing through the communication lines A and B flows through the bypass circuits 23A and 23B.

[0057] The control circuit 14 operates the bypass circuits 13A and 13B as described above, and the control circuit 24 operates the bypass circuits 23A and 23B as described above. As a result, part or all of the excess communication line current Itrans generated due to the failure to obtain impedance matching between the device 231 and the device 232 does not flow to the terminal resistor 30 but flows to the bypass circuits 13A, 13B, 23A, and 23B. By allowing the bypass current Ibyps to flow through the bypass circuits 13A, 13B, 23A, and 23B, the excess current Iterm flowing into the terminal resistor 30 is reduced, so the excess voltage Vtrans generated at both ends of the terminal resistor 30 is reduced. Therefore, the collapse of the communication waveform propagated through the pair of communication lines A and B is suppressed, so the generation of communication failure is reduced.

[0058] exist Figure 5 In the example of , the bypass current Ibyps flowing in the bypass circuit 13A flows bidirectionally in the bypass path passing through the capacitor 31, the resistor 41, the bypass terminal BPA, and the buffer 13Aa. The bypass current Ibyps flowing in the bypass circuit 13B flows bidirectionally in the bypass path passing through the capacitor 32, the resistor 42, the bypass terminal BPB, and the buffer 13Ba. The bypass current Ibyps flowing in the bypass circuit 23A flows bidirectionally in the bypass path passing through the capacitor 35, the resistor 43, the bypass terminal BPA, and the buffer 23Aa. The bypass current Ibyps flowing in the bypass circuit 23B flows bidirectionally in the bypass path passing through the capacitor 36, the resistor 44, the bypass terminal BPB, and the buffer 23Ba.

[0059] Figure 6 1 is a diagram illustrating waveforms of various parts of the bus system including the transmission driver IC of the first embodiment. The transmission circuit 11 converts the rectangular wave signal Din received from the MPU 15 through the input terminal DIN into a pair of differential AMI signals, and transmits them from the transmission terminals OUTA and OUTB to the communication lines A and B. The voltage Vtrans is a voltage generated at both ends of the terminal resistor 30, and is a differential voltage obtained by subtracting the potential of the communication line B from the potential of the communication line A.

[0060] When impedance matching is not achieved between the device 231 and the device 232, the communication line current Itrans caused by communication delay, reflection, etc. flows to a pair of communication lines A and B. The control circuit 14 is triggered by the rising edge or falling edge of the internal signal RO generated by the receiving circuit 12, and sets the enable signal EN that activates the bypass circuits 13A and 13B to be valid, so that the communication line current Itrans flows to the bypass circuits 13A and 13B. Similarly, the control circuit 24 is triggered by the rising edge or falling edge of the internal signal RO generated by the receiving circuit 22, and sets the enable signal EN that activates the bypass circuits 23A and 23B to be valid, so that the communication line current Itrans flows to the bypass circuits 23A and 23B. The bypass current Ibyps flows through the bypass circuits 13A, 13B, 23A, and 23B, thereby reducing the excess current Iterm flowing into the terminal resistor 30, and thus reducing the excess voltage Vtrans generated at both ends of the terminal resistor 30. Therefore, collapse of the communication waveform propagating through the pair of communication lines A and B is suppressed, thereby reducing the occurrence of communication failures.

[0061] like Figure 6 As shown, the control circuit 14 disconnects the differential signal transmitted on the communication lines A and B (in this example, the voltage of the AMI signal (in Figure 6The communication line current Itrans flows through the bypass circuits 13A and 13B. Figure 6 As shown, the control circuit 24 causes the communication line current Itrans to flow through the bypass circuits 23A and 23B during the disconnection period of the differential signal transmitted in the communication lines A and B. This improves the accuracy of the timing for suppressing the collapse of the communication waveform generated during the disconnection period of the differential signal.

[0062] like Figure 6 As shown, the control circuit 14 allows the communication line current Itrans to flow through the bypass circuits 13A and 13B during the first half period Tm of the disconnection period, and stops allowing the communication line current Itrans to flow through the bypass circuits 13A and 13B during the second half period Tn of the disconnection period. Figure 6 As shown, the control circuit 24 allows the communication line current Itrans to flow through the bypass circuits 23A and 23B during the first half period Tm of the disconnection period, and stops allowing the communication line current Itrans to flow through the bypass circuits 23A and 23B during the second half period Tn of the disconnection period. As a result, the timing accuracy of suppressing the collapse of the communication waveform generated during the first half period Tm of the disconnection period is improved.

[0063] like Figure 6 As shown, the control circuit 14 shields the output of the internal signal RO to the outside during the first half period Tm, and releases the shielding of the output of the internal signal RO to the outside during the second half period Tn. As a result, the control circuit 14 does not directly send the internal signal RO as the reception signal Dout to the MPU15 via the output terminal DOUT during the first half period Tm, and directly sends the internal signal RO as the reception signal Dout to the MPU15 via the output terminal DOUT during the second half period Tn. As a result, even if the internal signal RO is disturbed during the first half period Tm, the disturbance of the internal signal RO does not affect the reception signal Dout, so the reception error in the MPU15 is reduced. The control circuit 24 also operates in the same manner as the control circuit 14, thereby reducing the reception error in the MPU25.

[0064] exist Figure 5 For example, the bypass circuit 13A has an impedance lower than the terminal resistor 30 (for example, a resistance value of 10% or less of the terminal resistor 30). As a result, the excess communication line current Itrans generated by the impedance mismatch is easier to flow to the bypass circuit 13A than the terminal resistor 30, so the bypass current Ibyps flowing to the bypass circuit 13A increases. Therefore, the effect of suppressing waveform collapse is improved. The bypass circuits 13B, 23A, and 23B also have impedances lower than the terminal resistor 30 (for example, resistance values ​​of 10% or less of the terminal resistor 30) like the bypass circuit 13A, thereby improving the effect of suppressing waveform collapse.

[0065] exist Figure 5 In the bypass circuit 13A, the bypass circuit 13A may also have a resistor element 41 having a lower resistance value than the terminal resistance 30 (for example, a resistor element 41 having a resistance value of less than 10% of the terminal resistance 30). The resistor element 41 functions as an auxiliary terminal resistance. By changing the resistance value of the resistor element 41, the impedance matching between the device 231 and the device 232 can be finely adjusted. The bypass circuits 13B, 23A, and 23B may also have resistor elements 42, 43, and 44 having a lower resistance value than the terminal resistance 30 (for example, resistor elements 42, 43, and 44 having a resistance value of less than 10% of the terminal resistance 30) in the same manner as the bypass circuit 13A. By changing the resistance values ​​of some or all of the resistor elements 41, 42, 43, and 44, the impedance matching between the device 231 and the device 232 can be finely adjusted.

[0066] The resistor element 41 may also be provided outside the transmission driver IC 10. Thus, compared with the method of providing the resistor element 41 inside the transmission driver IC 10, the resistance value of the resistor element 41 can be easily changed, so that the fine adjustment of the impedance matching becomes easy (the same applies to the resistor element 42). The resistor element 43 may also be provided outside the transmission driver IC 20. Thus, compared with the method of providing the resistor element 43 inside the transmission driver IC 20, the resistance value of the resistor element 43 can be easily changed, so that the fine adjustment of the impedance matching becomes easy (the same applies to the resistor element 44).

[0067] Figure 7 This is a timing diagram for illustrating an example of the structure and method of the transmission driver IC controlling the bypass circuit of the first embodiment. The control circuit 14 is triggered by the change of the internal signal RO corresponding to the change of the differential signal (in this example, the AMI signal) transmitted on the communication lines A and B from on (ON) to off (OFF), so that the excess communication line current Itrans flows through the bypass circuits 13A and 13B. Similarly, the control circuit 24 is triggered by the change of the internal signal RO corresponding to the change of the differential signal (in this example, the AMI signal) transmitted in the communication lines A and B from on to off, so that the excess communication line current Itrans flows through the bypass circuits 23A and 23B. Figure 7 In the case of , the change of the AMI signal from on to off refers to an edge at which the level of the voltage Vtrans drops from 1 to zero, and an edge at which the level of the voltage Vtrans rises from -1 to zero.

[0068] like Figure 7 As shown in FIG. 1 , as the waveform of the AMI signal rings, the internal signal RO may also ring. In this case, when the control circuit 14, 24 changes the internal signal RO in accordance with the change of the AMI signal from on to off (in Figure 7 When the enable signal EN is enabled by a trigger (in the case of a rising edge), the enable signal EN may become unstable. This is because the ringing of the internal signal RO occurs immediately after the trigger timing.

[0069] exist Figure 7 In the case of the above, the control circuit 14, 24 detects the change of the internal signal RO corresponding to the change of the AMI signal from on to off ( Figure 7 In the case of a rising edge, the enable signal EN is latched. Thus, even if the internal signal RO becomes unstable, the enable signal EN is maintained valid. The control circuits 14 and 24 can invalidate the enable signal EN in the second half period Tn by releasing the latch of the enable signal EN after the first half period Tm.

[0070] Figure 8 3 is a diagram illustrating a bus system including a transmission driver IC of the second embodiment. In the bus system 302 of the second embodiment, the description of the same structure, function and effect as the bus system 301 of the first embodiment is omitted by citing the above description. The control circuits 14 and 24 of the transmission driver ICs 10 and 20 of the second embodiment are different from the control circuits 14 and 24 of the transmission driver ICs 10 and 20 of the first embodiment in that they also include delay circuits 14c and 24c for generating a delay time D.

[0071] The delay circuit 14c may also generate the delay time D according to the time taken to charge the capacitor 17 connected via the connection terminal CT of the transmission driver IC 10 to a predetermined second voltage. The signal generation circuit 14a changes the enable signal EN from invalid to valid after the delay time D has passed from the edge of the internal signal RO. The delay circuit 24c may also generate the delay time D according to the time taken to charge the capacitor 27 connected via the connection terminal CT of the transmission driver IC 20 to a predetermined second voltage. The signal generation circuit 24a changes the enable signal EN from invalid to valid after the delay time D has passed from the edge of the internal signal RO.

[0072] Fig. 9This is a timing diagram for illustrating an example of the structure and method of the transmission driver IC controlling the bypass circuit of the second embodiment. The control circuit 14 is triggered by the change of the internal signal RO corresponding to the change of the differential signal (AMI signal in this example) transmitted in the communication lines A and B from disconnection to connection. After the delay time D, the control circuit 14 allows the excess communication line current Itrans to flow through the bypass circuits 13A and 13B. Similarly, the control circuit 24 is also triggered by the change of the internal signal RO corresponding to the change of the differential signal (AMI signal in this example) transmitted in the communication lines A and communication lines B from disconnection to connection. After the delay time D, the control circuit 24 allows the excess communication line current Itrans to flow to the bypass circuits 23A and 23B. Fig. 9 In the case of , the change of the AMI signal from OFF to ON refers to an edge at which the level of the voltage Vtrans rises from zero to 1, and an edge at which the level of the voltage Vtrans falls from zero to 1.

[0073] like Fig. 9 As shown in FIG. 1 , as the waveform of the AMI signal rings, the internal signal RO may also ring. In this case, when the control circuit 14, 24 changes the internal signal RO in accordance with the change of the AMI signal from on to off (in Figure 7 When the enable signal EN is enabled by a trigger (in the case of a rising edge), the enable signal EN may become unstable. This is because the ringing of the internal signal RO occurs immediately after the trigger timing.

[0074] exist Fig. 9 In the case of the AMI signal from off to on, the control circuit 14, 24 detects the change in the internal signal RO corresponding to the change (in Figure 7 In the case of a falling edge), the enable signal EN can be maintained invalid until the delay time D has passed, and after the delay time D has passed, the enable signal EN can be turned valid. The signal generating circuit 14a can also determine the time to make the enable signal EN valid based on the time to charge the capacitor 16 connected via the connection terminal CDF of the transmission driver IC 10 to a predetermined first voltage. Thus, even if the internal signal RO becomes unstable, the enable signal EN is maintained valid. The control circuit 14, 24 invalidates the enable signal EN after the first half period Tm.

[0075] Fig.101 is a diagram illustrating a bus system including a transmission driver IC of the third embodiment. In the bus system 303 of the third embodiment, the description of the same structure, function and effect as the bus system 301 of the first embodiment is omitted by citing the above description. The bypass circuits 13 and 23 of the transmission driver ICs 10 and 20 of the third embodiment are different from the bypass circuits of the transmission driver ICs 10 and 20 of the first embodiment in that they include switches 13a and 23a that electrically connect the communication line A and the communication line B.

[0076] In this example, the enable signal EN generated by the control circuit 14 is input to the switch 13a, and the enable signal EN generated by the control circuit 24 is input to the switch 23a. When the enable signal EN is valid, the switches 13a and 23a electrically connect (turn on) the communication line A and the communication line B, and when the enable signal EN is invalid, the electrical connection between the communication line A and the communication line B is cut off (disconnected). Figure 6 Likewise, the excess current Iterm flowing into the terminal resistor 30 is reduced, so the excess voltage Vtrans generated across the terminal resistor 30 is reduced. Therefore, the collapse of the communication waveform propagating through the pair of communication lines A and B is suppressed, so the occurrence of communication failure is reduced.

[0077] Fig.11 This is a diagram showing an example of the effect of suppressing waveform collapse of an AMI signal having a communication speed of 9.6 kbps. Fig.12 1 is a diagram showing an example of the effect of suppressing waveform collapse of an AMI signal having a communication speed of 300 kbps. Fig.11 and Fig.12 In the legend, the comparison method indicates Figure 3 The first comparison method shown in the embodiment shows Figure 5 The first embodiment shown in FIG. Fig.11 as well as Fig.12 As shown, by causing a current to flow through the bypass circuit with the internal signal RO as a trigger, collapse of the communication waveform can be suppressed, thereby achieving a higher communication speed.

[0078] As described above, the embodiments are described, but the above embodiments are presented as examples, and the present invention is not limited to the above embodiments. The above embodiments can be implemented in various other ways, and various combinations, omissions, substitutions, changes, etc. can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and purpose of the invention, and are included in the invention described in the protection scope of the requested patent and its equivalent scope.

[0079] For example, the communication method may be different from the AMI method.

[0080] Devices including the transmission driver IC are not limited to air-conditioning devices, but may be other devices such as telephone devices, security devices, audio devices, video devices, and communication devices.

[0081] Explanation of symbols

[0082] 1, 2, 10, 20 transmission driver IC

[0083] 11, 21 transmission circuit

[0084] 12, 22 receiving circuit

[0085] 13, 13A, 13B, 23, 23A, 23B bypass circuit

[0086] 13Aa, 23Aa, 23Aa, 23Ba buffers

[0087] 13a, 23a switch

[0088] 14, 24 control circuit

[0089] 14a, 24a signal generation circuit

[0090] 14b, 24b logic circuit

[0091] 14c, 24c delay circuit

[0092] 15, 25 MPU

[0093] 16, 17, 26, 27, 31, 32, 32, 33, 34, 35, 36, 37, 38 capacitors

[0094] 30 terminal resistor

[0095] 41, 42, 43, 44 resistor elements

[0096] 201, 203 indoor units

[0097] 202, 204 remote control terminal

[0098] 205 outdoor unit

[0099] 211, 212, 213, 214, 215 drivers

[0100] 221, 222, 223, 224, 225 input and output circuits

[0101] 231, 232 devices

[0102] Room 241, 242

[0103] 300, 301, 302, 303, 1000 bus systems

[0104] A, B communication line

[0105] BPA, BPB bypass terminal

[0106] CDF, CT connection terminals

[0107] INA, INB receiving terminal

[0108] OUTA, OUTB sending terminals.

Claims

1. A bus system, characterized in that: have: a first transmission driver IC; a second transmission driver IC; a first communication line and a second communication line connecting the first transmission driver IC and the second transmission driver IC; and a terminal resistor connected between the first communication line and the second communication line, The first transmission driver IC and the second transmission driver IC respectively have: a transmitting circuit, which transmits a differential signal to the first communication line and the second communication line; a receiving circuit that converts a differential signal received from the first communication line and the second communication line into an internal signal; a bypass circuit connected to the first communication line or the second communication line; as well as A control circuit is configured to activate the bypass circuit using the internal signal as a trigger so as to allow the communication line current flowing through the first communication line or the second communication line to flow through the bypass circuit.

2. The bus system according to claim 1, characterized in that: The control circuit causes the communication line current to flow through the bypass circuit during an off segment of the differential signal.

3. The bus system according to claim 2, characterized in that: The control circuit allows the communication line current to flow through the bypass circuit during a first half of the disconnection period, and stops allowing the communication line current to flow through the bypass circuit during a second half of the disconnection period.

4. The bus system according to claim 3, characterized in that: The control circuit masks the output of the internal signal to the outside during the first half period, and releases the masking of the output during the second half period.

5. The bus system according to any one of claims 2 to 4, characterized in that: The control circuit causes the communication line current to flow through the bypass circuit, triggered by a change in the internal signal corresponding to a change in the differential signal from on to off.

6. The bus system according to any one of claims 2 to 4, characterized in that The control circuit includes a delay circuit for generating a delay time. The control circuit uses the change of the internal signal corresponding to the change of the differential signal from disconnection to connection as a trigger, and allows the communication line current to flow through the bypass circuit after the delay time has passed.

7. The bus system according to any one of claims 1 to 4, characterized in that: The bypass circuit has an impedance lower than that of the terminal resistance.

8. The bus system according to claim 7, characterized in that: The bypass circuit includes a resistance element having a resistance value lower than that of the terminal resistance.

9. The bus system according to claim 8, characterized in that: The resistance element is provided outside the first transmission driver IC or the second transmission driver IC.

10. The bus system according to any one of claims 1 to 4, characterized in that: The bypass circuit has current sinking capability and current sourcing capability.

11. The bus system according to any one of claims 1 to 4, characterized in that: The bypass circuit includes a switch electrically connecting the first communication line and the second communication line.

12. A transmission driver IC, characterized in that: have: A sending circuit, which sends a differential signal to a first communication line and a second communication line, and a terminal resistor is interposed between the first communication line and the second communication line; a receiving circuit that converts a differential signal received from the first communication line and the second communication line into an internal signal; Bypass circuit; as well as A control circuit that activates the bypass circuit using the internal signal as a trigger so that the communication line current flowing through the first communication line or the second communication line flows through the bypass circuit connected to the first communication line or the second communication line.

13. The transmission driver IC according to claim 12, wherein: The transmission driver IC further includes a plurality of terminals including a first transmission terminal, a second transmission terminal, a first reception terminal, and a second reception terminal. The transmitting circuit transmits a differential signal to the first communication line and the second communication line via the first transmitting terminal and the second transmitting terminal. The receiving circuit receives a differential signal from the first communication line and the second communication line via the first receiving terminal and the second transmitting terminal.

14. A device, characterized in that have: an input-output circuit that outputs a transmission signal and receives a reception signal; and Transmission driver IC, The transmission driver IC has: a transmitting circuit, which converts the transmitting signal into a differential signal transmitted to a first communication line and a second communication line, wherein a terminal resistor is disposed between the first communication line and the second communication line; a receiving circuit that converts a differential signal received from the first communication line and the second communication line into an internal signal; Bypass circuit; as well as A control circuit that activates the bypass circuit using the internal signal as a trigger so that the communication line current flowing through the first communication line or the second communication line flows through the bypass circuit connected to the first communication line or the second communication line.

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