Chip packaging structure and preparation method thereof, storage system and electronic equipment
CN119698936APending Publication Date: 2025-03-25YANGTZE MEMORY TECH CO LTD
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Patent Information
- Application Number
- CN202380009913.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-25
- Publication Date
- 2025-03-25
AI Technical Summary
Technical Problem
In the existing 3D NAND packaging structure, how to reduce the size of the device has become an urgent problem.
Method used
The first chips, second chips, and third chips that set different process parameters through stacking include peripheral circuits, decoders and control circuits, respectively. The difference in crystal tube under the same process conditions can be used to achieve the compactness of the chip packaging structure.
Benefits of technology
Compared with the leveling of multiple chips along the horizontal direction, the size of the chip packaging structure can significantly reduce the size of the chip by stacking settings, thereby reducing the size of the storage system of the chip packaging structure.
✦ Generated by Eureka AI based on patent content.
Abstract
The invention provides a chip packaging structure and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to reduce the size of a device. The chip packaging structure comprises a first chip, a second chip and a third chip which are stacked, the first chip at least comprises a peripheral circuit, and the peripheral circuit comprises a first transistor. The second chip at least comprises a column decoder, and the column decoder comprises a second transistor. The third chip at least comprises a control circuit, and the control circuit comprises a third transistor. The length of the channel of the first transistor, the length of the channel of the second transistor and the length of the channel of the third transistor are all different. The chip packaging structure is applied to a storage system so as to realize data reading and writing operation.
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