Server system resource allocation method and device

Abstract

The invention provides a server system resource allocation method and device. The method comprises the following steps: acquiring hardware wiring data of a server backboard; determining the number of high-speed cables connected with the server backboard according to the hardware wiring data; according to the number of the high-speed cables connected to the server backboard, determining the configuration requirement of a nonvolatile memory expression standard NVME (Non-Volatile Memory Expression Standard); and distributing server system resources according to the configuration requirements of the NVME. The method is used for achieving the effect of improving the resource allocation flexibility of the server system.

Description

Technical Field

[0001] The present application relates to the technical field of server hardware, and in particular to a method and device for allocating server system resources. Background Art

[0002] In modern data centers and cloud computing environments, the flexibility and scalability of server systems are critical to meeting diverse business needs. The configuration of server systems, especially the number of hard disks and their wiring relationships, directly affects the system's storage performance, data redundancy capabilities, and overall system reliability.

[0003] At present, most white-label server products on the market use fixed hardware configuration solutions, that is, the number of hard disks and their connection methods with the motherboard, such as the high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) channel allocation, which are determined at the factory, and the compatibility with the system basic input / output system (Basic Input / Output System, BIOS) or baseboard management controller (Baseboard Management Controller, BMC) is ensured through hardware design. As the core components of system management and control, BIOS and BMC perform initialization and resource management based on preset configuration information, thereby ensuring that the system configuration matches the wiring relationship.

[0004] However, when users change the hard disk configuration or wiring method, it may lead to serious consequences such as system startup failure, performance degradation, or even data loss. Summary of the invention

[0005] The embodiments of the present application provide a server system resource allocation method and device to achieve the effect of improving allocation flexibility.

[0006] In a first aspect, an embodiment of the present application provides a server system resource allocation method, comprising:

[0007] Get the hardware wiring data of the server backplane;

[0008] Determine the number of high-speed cables connected to the server backplane based on the hardware wiring data;

[0009] Determine the Non-Volatile Memory Express (NVME) configuration requirements based on the number of high-speed cables connected to the server backplane;

[0010] Allocate server system resources according to NVME configuration requirements.

[0011] In a possible implementation, determining the number of high-speed cables connected to a server backplane according to hardware wiring data includes:

[0012] According to the hardware wiring data, the number of high-speed cables connected to the server backplane corresponding to the hardware wiring data is queried from the cable in-position register table.

[0013] In a possible implementation, according to the number of high-speed cables connected to the server backplane, the configuration requirements of the non-volatile memory expression standard NVME are determined, including:

[0014] If the number of high-speed cables connected to the server backplane is 4, the NVME configuration requirement is determined to be 8NVME;

[0015] If the number of high-speed cables connected to the server backplane is 8, the NVME configuration requirement is determined to be 16NVME;

[0016] If the number of high-speed cables connected to the server backplane is 12, the NVME configuration requirement is determined to be 24 NVME.

[0017] In a possible implementation, allocating server system resources according to the configuration requirements of NVME includes:

[0018] According to the configuration requirements of NVME and the basic input and output system BIOS adaptation relationship table, the high-speed serial computer expansion bus standard PCIE interface and NVME virtual PIN interface (Virtual Pin Port, VPP) address are allocated.

[0019] In a possible implementation, according to the configuration requirements of NVME and the basic input and output system BIOS adaptation relationship table, the high-speed serial computer expansion bus standard PCIE interface and the NVME virtual PIN interface address are allocated, including:

[0020] From the BIOS adaptation relationship table, query the PCIE interface and NVME virtual PIN interface address corresponding to the NVME configuration requirements;

[0021] According to the query results, configure the PCIE interface as the NVME virtual PIN interface address.

[0022] In a possible implementation, obtaining hardware wiring data of a server backplane includes:

[0023] Obtain the hardware wiring data of the server backplane through the IIC data transmission channel.

[0024] In a second aspect, an embodiment of the present application provides a server system resource allocation device, including:

[0025] An acquisition module is used to acquire hardware wiring data of a server backplane;

[0026] A determination module, used to determine the number of high-speed cables connected to the server backplane according to hardware wiring data;

[0027] The determination module is also used to determine the configuration requirements of the non-volatile memory expression standard NVME according to the number of high-speed cables connected to the server backplane;

[0028] The allocation module is used to allocate server system resources according to the configuration requirements of NVME.

[0029] In a possible implementation, the determination module is specifically configured to query the number of high-speed cables connected to the server backplane corresponding to the hardware wiring data from a cable in-place register table according to the hardware wiring data.

[0030] In a possible implementation, the determination module is specifically configured to determine that the configuration requirement of the NVME is 8NVME if the number of high-speed cables connected to the server backplane is 4;

[0031] If the number of high-speed cables connected to the server backplane is 8, the NVME configuration requirement is determined to be 16NVME;

[0032] If the number of high-speed cables connected to the server backplane is 12, the NVME configuration requirement is determined to be 24 NVME.

[0033] In a possible implementation, the allocation module is specifically used to allocate the high-speed serial computer expansion bus standard PCIE interface and the NVME virtual PIN interface address according to the configuration requirements of the NVME and the basic input and output system BIOS adaptation relationship table.

[0034] In a possible implementation, the allocation module is specifically used to query the PCIE interface and NVME virtual PIN interface address corresponding to the configuration requirements of NVME from the BIOS adaptation relationship table;

[0035] According to the query results, configure the PCIE interface as the NVME virtual PIN interface address.

[0036] In a possible implementation, the acquisition module is specifically configured to acquire hardware wiring data of a server backplane through an IIC data transmission channel.

[0037] In a third aspect, an embodiment of the present application provides an electronic device, including: a memory, a processor;

[0038] Memory stores computer-executable instructions;

[0039] The processor executes the computer-executable instructions stored in the memory, so that the processor executes the above first aspect and / or various possible implementations of the first aspect.

[0040] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the first aspect above and / or various possible implementations of the first aspect.

[0041] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the above first aspect and / or various possible implementation methods of the first aspect.

[0042] The server system resource allocation method and device provided in the embodiments of the present application obtain the hardware wiring data of the server backplane, determine the number of high-speed cables connected to the server backplane based on the hardware wiring data, determine the configuration requirements of NVME, and then allocate system resources according to the configuration requirements of NVME, thereby achieving the effect of flexible allocation of system resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0044] Figure 1 A schematic diagram of the server system resource allocation scenario provided for this application;

[0045] Figure 2 Schematic diagram of the server system resource allocation method provided in this application Figure 1 ;

[0046] Figure 3 Schematic diagram of the server system resource allocation method provided in this application Figure 2 ;

[0047] Figure 4 A schematic diagram of the structure of a server system resource allocation device provided in this application;

[0048] Figure 5 A schematic diagram of the structure of an electronic device provided in this application.

[0049] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0050] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0051] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0052] The configuration of the server system, especially the number of hard disks and their wiring relationship, directly affects the system's storage performance, data redundancy, and overall system reliability. Therefore, ensuring the precise matching of the server system configuration and wiring relationship is the basis for achieving efficient operation and maintenance and resource optimization. With the widespread application of white-label server products, users' demand for customized system configuration is increasing. How to flexibly adjust the hardware configuration to adapt to different application scenarios has become a key issue that needs to be solved in the field of server design and manufacturing.

[0053] Figure 1 A schematic diagram of the server system resource allocation scenario provided in this application. Figure 1 As shown in the figure, the number of hard disks (such as backplanes) and the way they are connected to the motherboard of white-label server products are determined at the factory. As core components of system management and control, BIOS and BMC perform initialization and resource management based on preset configuration information, thereby ensuring that the server system configuration matches the wiring relationship.

[0054] Combined with the above scenarios, it can be seen that in the prior art, the system can run stably under a specific configuration through preset wiring relationships and resource allocation. However, when users need to adjust the number of hard disks or change the wiring relationship according to specific application scenarios, the existing hardware configuration solutions are often unable to adapt to such changes. Since BIOS / BMC lacks the ability to dynamically perceive changes in hardware configuration, once the user tries to change the hard disk configuration or wiring method, the system may not be able to correctly identify and allocate the necessary PCIE resources, resulting in serious consequences such as system startup failure, performance degradation, and even data loss. This not only limits users' customized needs for server systems, but also increases the cost and complexity of operation and maintenance, affecting the market competitiveness of servers.

[0055] The server system resource allocation method and device provided in the present application allocate system resources according to the actual hardware wiring conditions and the mapping relationship between the preset wiring conditions and the system resource allocation, thereby achieving the effect of improving the flexibility of system resource allocation, meeting user customization requirements, and reducing system operation and maintenance costs and complexity.

[0056] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0057] Figure 2 Schematic diagram of the server system resource allocation method provided in this application Figure 1 .like Figure 2 As shown, the method takes the BIOS of the server as the execution subject and includes the following steps:

[0058] S101. Obtain hardware wiring data of a server backplane.

[0059] Specifically, the backplane complex programmable logic device (CPLD) detects the presence signal of the multi-channel input / output (MCIO), that is, the hardware wiring data. The hardware wiring data is used to reflect whether the MCIO is connected to a high-speed cable.

[0060] The BIOS communicates with the BMC and requests to obtain the hardware wiring data from the register of the backplane CPLD. Specifically, the BIOS sends a query request to the BMC, and the BMC reads the hardware wiring data in the register of the backplane CPLD and returns the data to the BIOS.

[0061] S102: Determine the number of high-speed cables connected to the server backplane according to the hardware wiring data.

[0062] S103. Determine the configuration requirements of the non-volatile memory expression standard NVME according to the number of high-speed cables connected to the server backplane.

[0063] Specifically, after receiving the hardware connection data returned from the BMC, the BIOS determines whether the MCIO is connected to a high-speed cable according to the hardware connection data.

[0064] If the MCIO is connected to a high-speed cable, the BIOS determines that the backplane is an all-in-one slot (ANYBP) configuration, which means that the backplane supports simultaneous connection of NVME configuration and Serial Advanced Technology Attachment (SATA) configuration. If the MCIO is not connected to a high-speed cable, the BIOS determines that the backplane is a SATA configuration. In other words, the BIOS can determine the number of high-speed cables connected to the server backplane based on the hardware wiring data, and then determine how many NVME configurations there are on the backplane.

[0065] S104. Allocate server system resources according to the configuration requirements of NVME.

[0066] Specifically, after determining the specific configuration of the backplane, the BIOS allocates server system resources according to the configuration requirements of NVME. If the backplane is configured as ANYBP, the BIOS will dynamically allocate the corresponding PCIE interface resources to the NVME device according to the number of NVME configurations, while ensuring that the SATA device can also obtain the required system resources. If the backplane is configured as SATA, the BIOS will mainly allocate system resources to SATA devices. In this process, the BIOS will adjust the system configuration to achieve the purpose of system adaptation and ensure that the server can run efficiently and stably.

[0067] In the server system resource allocation method provided in this embodiment, the BIOS obtains the hardware wiring data in the backplane CPLD register through communication with the BMC, and determines the NVME configuration requirements based on these data, and then allocates the server system resources to achieve adaptive configuration of the system, so that the server system configuration matches the wiring relationship, thereby improving the flexibility of system resource allocation.

[0068] Figure 3 Schematic diagram of the server system resource allocation method provided in this application Figure 2 ,like Figure 3 As shown, in this embodiment Figure 2 Based on the embodiment, the server system resource allocation method is described in detail with the BIOS of the server as the execution subject. The method includes:

[0069] S201. Obtain hardware wiring data of a server backplane through an IIC data transmission channel.

[0070] Specifically, the BMC obtains the hardware wiring data from the 0X0D register of the backplane CPLD through the IIC data transmission channel to improve the efficiency of obtaining data, and the BIOS obtains the hardware wiring data from the BMC.

[0071] S202: Determine the number of high-speed cables connected to the server backplane according to the hardware wiring data.

[0072] Specifically, the BIOS may query the number of high-speed cables connected to the server backplane corresponding to the hardware wiring data from the cable in-place register table according to the hardware wiring data.

[0073] The cable presence register table shows the specific position of the high-speed cable installed on the backplane. Specifically, 1 indicates that the high-speed cable is in place, and 0 indicates that the high-speed cable is not in place.

[0074] For example, 0X0F (binary 00001111) indicates that MCIO4-MCIO1 are both installed with high-speed cables; 0X00 (binary 00000000) indicates that MCIO4-MCIO1 are not installed with high-speed cables; 0X01 (binary 00000001) indicates that MCIO1 is installed with a high-speed cable; 0X06 (binary 00000110) indicates that MCIO3 and MCIO2 are installed with high-speed cables. Currently, the values ​​corresponding to normal 8 / 16 / 24 NVME are only 0X0F and 0X00.

[0075] For a three-level cascaded backplane, that is, three backplanes, each backplane has a different IIC physical address. The BMC can obtain the wiring status of the high-speed cable from the 0X0D register of the CPLD of each backplane to obtain the hardware wiring data of the backplane.

[0076] If the obtained hardware wiring data is 0X0F 0X00 0X00, it indicates that only MCIO4-MCIO1 of backplane 1 are installed with high-speed cables. If the obtained hardware wiring data is 0X0F 0X0F 0X00, it indicates that MCIO4-MCIO1 of backplane 1 and backplane 2 are installed with high-speed cables. If the obtained hardware wiring data is 0X0F 0X0F 0X0F, it indicates that MCIO4-MCIO1 of backplane 1, backplane 2, and backplane 3 are installed with high-speed cables. In other words, based on the hardware wiring data, the BIOS can query the number and specific locations of high-speed cables connected to the server backplane corresponding to the hardware wiring data from the cable in-position register table.

[0077] S203. Determine the configuration requirements of NVME according to the number of high-speed cables connected to the server backplane.

[0078] Specifically, if the number of high-speed cables connected to the server backplane is 4, the NVME configuration requirement is determined to be 8NVME. If the number of high-speed cables connected to the server backplane is 8, the NVME configuration requirement is determined to be 16NVME. If the number of high-speed cables connected to the server backplane is 12, the NVME configuration requirement is determined to be 24NVME.

[0079] Based on the introduction of the cable in-place register table, it can be understood that if the number of high-speed cables connected to the server backplane is 4, only MCIO4-MCIO1 of backplane 1 are installed with high-speed cables, and the NVME configuration requirement is 8NVME. If the number of high-speed cables connected to the server backplane is 8, MCIO4-MCIO1 of backplane 1 and backplane 2 are installed with high-speed cables, and the NVME configuration requirement is 16NVME. If the number of high-speed cables connected to the server backplane is 12, MCIO4-MCIO1 of backplane 1, backplane 2, and backplane 3 are installed with high-speed cables, and the NVME configuration requirement is 24NVME.

[0080] S204. Allocate PCIE interface and NVME VPP address according to NVME configuration requirements and BIOS adaptation relationship table.

[0081] In this embodiment, the BIOS adaptation relationship table shows the mapping relationship between the NVME configuration requirements and the PCIE interface and the NVME VPP address. After the BIOS determines the system's NVME configuration requirements, it can determine the PCIE interface and NVME VPP address corresponding to the NVME configuration requirements by querying the BIOS adaptation relationship table, and then perform resource configuration.

[0082] Specifically, the BIOS can query the PCIE interface and the NVME virtual PIN interface address corresponding to the configuration requirement of the NVME from the BIOS adaptation relationship table; and configure the PCIE interface to the NVME virtual PIN interface address according to the query result.

[0083] For example, the BIOS determines that the configuration requirement of NVME is 8NVME, and according to the BIOS adaptation relationship table, the interface 4 and the interface 5 of the central processing unit (CPU) 1 can be configured as X4X4X4X4 respectively.

[0084] For another example, the BIOS determines that the configuration requirement of NVME is 16NVME. According to the BIOS adaptation relationship table, interface 2 and interface 5 of CPU0 can be configured as X4X4X4X4 respectively, and interface 4 and interface 5 of CPU1 can be configured as X4X4X4X4 respectively.

[0085] For example, the BIOS determines that the configuration requirement of NVME is 24NVME. According to the BIOS adaptation relationship table, interface 2 and interface 5 of CPU0 can be configured as X4X4X4X4 respectively, and interface 1, interface 2, interface 4 and interface 5 of CPU1 can be configured as X4X4X4X4 respectively.

[0086] In the server system resource allocation method provided in this embodiment, the BIOS obtains the hardware wiring data in the backplane CPLD register by communicating with the BMC, and determines the number of high-speed cables connected to the backplane based on these data, and then determines the configuration requirements of NVME. The BIOS allocates the PCIE interface and NVME VPP address according to the configuration requirements of NVME, which enhances the system's flexible configuration capabilities and can meet a variety of adaptation requirements.

[0087] In addition, the traditional backplane CPLD needs to rely on the mainboard CPLD to communicate with the CPU, and the communication link is backplane CPLD-mainboard CPLD-BMC-CPU. This communication method increases the complexity of the system. In the embodiment of the present application, based on the situation that each backplane CPLD has a hardware communication link with the BMC and there is in-band communication between the BMC and the CPU, the backplane CPLD does not need to rely on the mainboard CPLD to communicate with the CPU, and the communication link is backplane CPLD-BMC-CPU, which makes the communication more flexible and more applicable.

[0088] Figure 4 This is a schematic diagram of the structure of a server system resource allocation device provided by this application. Figure 4 As shown, the server system resource allocation device 10 of this embodiment is used to implement the operation corresponding to the server BIOS in any of the above method embodiments. The server system resource allocation device 10 provided in this embodiment includes:

[0089] An acquisition module 11 is used to acquire hardware wiring data of a server backplane;

[0090] A determination module 12, used to determine the number of high-speed cables connected to the server backplane according to the hardware wiring data;

[0091] The determination module 12 is further used to determine the configuration requirements of the non-volatile memory expression standard NVME according to the number of high-speed cables connected to the server backplane;

[0092] The allocation module 13 is used to allocate server system resources according to the configuration requirements of NVME.

[0093] In a possible implementation, the determination module 12 is specifically configured to query the number of high-speed cables connected to the server backplane corresponding to the hardware wiring data from the cable in-place register table according to the hardware wiring data.

[0094] In a possible implementation, the determination module 12 is specifically configured to determine that the configuration requirement of the NVME is 8NVME if the number of high-speed cables connected to the server backplane is 4;

[0095] If the number of high-speed cables connected to the server backplane is 8, the NVME configuration requirement is determined to be 16NVME;

[0096] If the number of high-speed cables connected to the server backplane is 12, the NVME configuration requirement is determined to be 24 NVME.

[0097] In a possible implementation, the allocation module 13 is specifically used to allocate a high-speed serial computer expansion bus standard PCIE interface and an NVME virtual PIN interface according to the configuration requirements of the NVME and the basic input and output system BIOS adaptation relationship table.

[0098] In a possible implementation, the allocation module 13 is specifically used to query the PCIE interface and NVME virtual PIN interface address corresponding to the configuration requirements of NVME from the BIOS adaptation relationship table;

[0099] According to the query results, configure the PCIE interface as the NVME virtual PIN interface address.

[0100] In a possible implementation manner, the acquisition module 11 is specifically configured to acquire hardware wiring data of a server backplane through an IIC data transmission channel.

[0101] The server system resource allocation device 10 provided in this embodiment can execute the method provided in the above method embodiment, and its implementation principle and technical effect are similar, which will not be described in detail in this embodiment.

[0102] Figure 5 This is a schematic diagram of the structure of an electronic device provided in this application. Figure 5 As shown, the electronic device 20 provided in this embodiment includes: a memory 21 and at least one processor 22. Optionally, the device 20 also includes a communication component 23. The memory 21, the processor 22 and the communication component 23 are connected via a bus 24.

[0103] In a specific implementation process, at least one processor 22 executes the computer-executable instructions stored in the memory 21, so that at least one processor 22 executes the above method.

[0104] The specific implementation process of the processor 22 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0105] In the above embodiments, it should be understood that the processor may be a CPU, or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. The general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc. The steps of the method disclosed in the invention may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0106] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (NVM), such as at least one disk storage.

[0107] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.

[0108] The present application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0109] The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above method is implemented.

[0110] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0111] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be an integral part of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (ASIC). Of course, the processor and the readable storage medium can also exist in a device as discrete components.

[0112] The division of units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0113] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0114] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0115] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0116] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0117] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A server system resource allocation method, characterized in that: include: Get the hardware wiring data of the server backplane; Determine the number of high-speed cables connected to the server backplane according to the hardware wiring data; Determine the configuration requirements of the non-volatile memory expression standard NVME according to the number of high-speed cables connected to the server backplane; Allocate server system resources according to the configuration requirements of the NVME.

2. The method according to claim 1, characterized in that Determine the number of high-speed cables connected to the server backplane according to the hardware wiring data, including: According to the hardware wiring data, the number of high-speed cables connected to the server backplane corresponding to the hardware wiring data is queried from a cable in-place register table.

3. The method according to claim 1, characterized in that According to the number of high-speed cables connected to the server backplane, the configuration requirements of the non-volatile memory expression standard NVME are determined, including: If the number of high-speed cables connected to the server backplane is 4, determine that the configuration requirement of NVME is 8NVME; If the number of high-speed cables connected to the server backplane is 8, it is determined that the configuration requirement of NVME is 16NVME; If the number of high-speed cables connected to the server backplane is 12, it is determined that the configuration requirement of NVME is 24NVME.

4. The method according to any one of claims 1 to 3, characterized in that: According to the configuration requirements of the NVME, server system resources are allocated, including: According to the configuration requirements of the NVME and the basic input and output system BIOS adaptation relationship table, the high-speed serial computer expansion bus standard PCIE interface and the NVME virtual PIN interface address are allocated.

5. The method according to claim 4, characterized in that According to the configuration requirements of the NVME and the basic input and output system BIOS adaptation relationship table, the high-speed serial computer expansion bus standard PCIE interface and the NVME virtual PIN interface address are allocated, including: From the BIOS adaptation relationship table, query the PCIE interface and NVME virtual PIN interface address corresponding to the configuration requirements of the NVME; According to the query result, the PCIE interface is configured as the NVME virtual PIN interface address.

6. The method according to any one of claims 1 to 3, characterized in that: Get the hardware wiring data of the server backplane, including: Obtain the hardware wiring data of the server backplane through the IIC data transmission channel.

7. A server system resource allocation device, characterized in that: include: An acquisition module is used to acquire hardware wiring data of a server backplane; A determination module, used to determine the number of high-speed cables connected to the server backplane according to the hardware wiring data; The determination module is further used to determine the configuration requirements of the non-volatile memory expression standard NVME according to the number of high-speed cables connected to the server backplane; The allocation module is used to allocate server system resources according to the configuration requirements of the NVME.

8. An electronic device, characterized in that: include: Memory, processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory, so that the processor performs the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 6 when executed by a processor.

10. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 6 when being executed by a processor.

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