Adapter identification circuit and control method thereof, storage medium and terminal equipment

Abstract

The invention provides an adapter identification circuit and a control method thereof, a storage medium and a terminal device, the adapter identification circuit comprises an interface circuit, the interface circuit is provided with a first power pin, the first power pin is used for accessing a power voltage, and the power voltage has a target value; the input end of the time delay circuit is coupled with the second power supply pin of the adapter, and the output end of the time delay circuit is coupled with the first power supply pin of an interface circuit; and the time delay circuit is used for enabling a first moment when the voltage of the first power supply pin reaches the target value to be later than a second moment when the voltage of the second power supply pin reaches the target value. According to the adapter identification circuit structure, the POP sound generated at the moment when the adapter is inserted can be eliminated, and the user experience is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an adapter identification circuit and a control method thereof, a storage medium, and a terminal device. Background Art

[0002] At present, in order to pursue mobile terminals, such as thin and waterproof features, mobile phone manufacturers have gradually cancelled the conventional 3.5mm headphone jack. This change has resulted in the mobile phone having only one Type C interface, which can be connected to either a charger or headphones. To achieve charging and listening to music at the same time, you need to use a Type C headphone & charging two-in-one adapter.

[0003] However, there is a popping sound (POP sound) at the earphone end when the adapter is inserted into the mobile phone. POP sound refers to the transient impact caused by various operations when the audio device is powered on and off, and after the power is stable. This POP sound impact may even burn the earphone, or reduce the quality of the earphone and shorten its life. POP sound can also impact the eardrum of the human body and affect sensory comfort. Summary of the invention

[0004] The adapter identification circuit structure in this application can eliminate the POP sound generated when the adapter is inserted, thereby improving the user experience.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] In a first aspect, an adapter identification circuit is provided, and the adapter identification circuit includes: an interface circuit, the interface circuit having a first power pin, the first power pin being used to connect to a power voltage, the power voltage having a target value; a delay circuit, the input end of the delay circuit being coupled to a second power pin of the adapter, the output end of the delay circuit being coupled to the first power pin of the interface circuit, the delay circuit being used to make a first moment when the voltage of the first power pin reaches the target value later than a second moment when the voltage of the second power pin reaches the target value.

[0007] Optionally, the adapter identification circuit further includes: a system on chip, wherein the system on chip identifies the charger type of the adapter at the first moment, and identifies the earphone parameters of the adapter between the first moment and the second moment.

[0008] Optionally, the interface circuit has an audio interface, and the audio interface is connected to an audio signal output by the power management chip.

[0009] Optionally, the interface circuit has a universal serial bus interface, and the universal serial bus interface is connected to a serial bus signal output by a power management chip.

[0010] Optionally, the interface circuit has a first configuration channel pin, the first configuration channel pin is coupled to a second configuration channel pin of the adapter, and the voltages on the first configuration channel pin and the second configuration channel pin are at a low level at the second moment.

[0011] Optionally, the interface circuit has a switch, and the switch is used to selectively access an audio signal or a serial bus signal.

[0012] Optionally, the delay circuit includes: an impedance unit, one end of which is coupled to the first power pin, and the other end of which is coupled to the second power pin; and an energy storage unit, one end of which is coupled to the first power pin, and the other end of which is grounded.

[0013] In a second aspect, the present application also discloses a control method based on the adapter identification circuit, the control method comprising: applying a first voltage signal to the second power pin so that the first moment when the voltage of the first power pin reaches the target value is later than the second moment when the voltage of the first power pin reaches the target value through the delay circuit; identifying the headphone parameters of the adapter between the first moment and the second moment; and controlling the on-chip system to identify the charger type of the adapter at the first moment.

[0014] According to a third aspect, a computer-readable storage medium is provided, on which a computer program is stored. The computer program is executed by a processor to execute any one of the methods provided in the second aspect.

[0015] According to a fourth aspect, a terminal device is provided, comprising any one of the adapter identification circuits provided in the first aspect.

[0016] According to a fifth aspect, a computer program product is provided, on which a computer program is stored, and the computer program is executed by a processor to execute any one of the methods provided in the second aspect.

[0017] In a sixth aspect, an embodiment of the present application further provides a chip (or a data transmission device), which includes any one of the adapter identification circuits provided in the first aspect.

[0018] In a seventh aspect, an embodiment of the present application further provides a system chip (or chip module) for use in a terminal, wherein the chip system includes any one of the adapter identification circuits provided in the first aspect.

[0019] In an eighth aspect, the present application also discloses an adapter, comprising: a second power pin for connecting a power supply voltage, the power supply voltage having a target value; a delay circuit, the input end of the delay circuit being coupled to the second power pin, the delay circuit being used to make the first moment when the voltage at its output end reaches the target value later than the second moment when the voltage at the second power pin reaches the target value.

[0020] Compared with the prior art, the technical solution of this application has the following beneficial effects:

[0021] In the technical solution of the present application, the adapter identification circuit includes an interface circuit, the interface circuit has a first power pin, the first power pin is used to access the power voltage, and the power voltage has a target value; a delay circuit, the input end of the delay circuit is coupled to the first power pin of the interface circuit, and the output end of the delay circuit is coupled to the first power pin of the interface circuit. The technical solution of the present application sets a delay circuit so that the first moment when the voltage of the first power pin reaches the target value is later than the second moment when the voltage of the second power pin reaches the target value, and the prerequisite for the charger type identification of the adapter is that the voltage of the first power pin reaches the target value, so that the identification of the earphone parameters of the adapter is earlier than the charger type identification, avoiding the transmission of the level signal on the charging path to the earphone to generate POP sound, thereby achieving the purpose of eliminating POP sound. In addition, the present application is simple and easy to implement, and can take into account the normal charging function of the terminal device and the normal playback function of the earphone, thereby improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a structural schematic diagram of an adapter identification circuit provided in an embodiment of the present application;

[0023] Figure 2 This is a schematic diagram of a connection structure between an adapter and a terminal device provided in an embodiment of the present application.

[0024] Figure 3 is a timing diagram of various control signals provided in an embodiment of the present application;

[0025] Figure 4 is a specific structural diagram of an adapter identification circuit provided in an embodiment of the present application;

[0026] Figure 5 is a flow chart of a control method of an adapter identification circuit provided by an embodiment of the present application;

[0027] Figure 6 is a schematic diagram of a specific structure of an adapter provided in an embodiment of the present application;

[0028] Figure 7 It is a schematic diagram of a specific application scenario provided by an embodiment of the present application. DETAILED DESCRIPTION

[0029] As described in the background technology, there is a popping sound (POP sound) at the earphone end when the adapter is inserted into the mobile phone. POP sound refers to the transient impact caused by various operations when the audio device is powered on and off, and after the power is stable. This POP sound impact may even burn the earphone, or reduce the quality of the earphone and shorten its life. POP sound can also impact the eardrum of the human body, affecting sensory comfort.

[0030] The technical solution of the present application sets a delay circuit so that the first moment when the voltage of the first power pin reaches the target value is later than the second moment when the voltage of the second power pin reaches the target value, and the prerequisite for the charger type identification of the adapter is that the voltage of the first power pin reaches the target value, so that the identification of the adapter's headphone parameters is earlier than the charger type identification, avoiding the transmission of the level signal on the charging path to the headphone to generate POP sound, thereby achieving the purpose of eliminating POP sound. In addition, the present application is simple and easy to implement, and can take into account the normal charging function of the terminal device and the normal playback function of the headphone, thereby improving the user experience.

[0031] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0032] Figure 1 The structure of an adapter identification circuit is shown. The adapter identification circuit 10 in the embodiment of the present invention can be used in a terminal device, such as a mobile phone.

[0033] The adapter identification circuit 10 can be used to transmit signals, such as audio signals or Universal Serial Bus (USB) signals, between the adapter 10 and internal circuits of a terminal device, such as a system on chip (SoC).

[0034] like Figure 1 As shown, the adapter identification circuit 10 includes an interface circuit 101 and a delay circuit 102. The interface circuit has a first power pin VBUS1, and the first power pin VBUS1 is used to access a power voltage, and the power voltage has a target value, such as 4V.

[0035] The input end of the delay circuit 102 is coupled to the second power pin VBUS2, and the output end of the delay circuit 102 is coupled to the first power pin VBUS1. The delay circuit 102 is used to make the first time when the voltage of the first power pin VBUS1 reaches the target value later than the second time when the voltage of the second power pin VBUS2 reaches the target value. The second power pin VBUS2 can be used to access an external power supply voltage, for example, access the power supply voltage through an external charger, so that the power supply voltage is connected to the first power pin VBUS1 through the delay circuit 102.

[0036] Compared with the prior art in which the first power pin VBUS1 and the second power pin VBUS2 are directly coupled, in the embodiment of the present application, the delay circuit 102 is set so that the first moment when the voltage of the first power pin VBUS1 reaches the target value is later than the second moment when the voltage of the second power pin VBUS2 reaches the target value, and the prerequisite for the charger type identification of the adapter 20 is that the voltage of the first power pin VBUS1 reaches the target value, so that the identification of the earphone parameters of the adapter 20 is earlier than the charger type identification, avoiding the transmission of the level signal on the charging path to the earphone to generate POP sound, thereby achieving the purpose of eliminating POP sound. In addition, the present application is simple and easy to implement, and can take into account the normal charging function of the terminal device and the normal playback function of the earphone, thereby improving the user experience.

[0037] For details, please refer to Figure 2 , the adapter 20 is connected to the terminal device 1 through the interface circuit 101 of the terminal device 1. The external interface of the terminal device 1 has a switch, such as Figure 2 The switch can selectively output the charging signal (signal connected to the USB_D+ / D- port) or the audio signal (signal connected to the HPL / R port) to the adapter 20.

[0038] The earphone 50 is connected to the terminal device 1 via the adapter 20 , and the charger 40 is connected to the terminal device 1 via the adapter 20 .

[0039] Specifically, the interface circuit 101 may include a switch TypeC Switch, a first power pin VBUS1, a first configuration channel (CC) pin CC1 & CC2, an audio interface HPL / R, a universal serial bus interface USB_D+ / D-, etc. Correspondingly, the adapter 20 has a corresponding access interface, a second power pin VBUS2, and second configuration channel pins CC3 & CC4.

[0040] The audio interface HPL / R accesses the audio signal output by the power management IC (PMIC). The universal serial bus interface USB_D+ / D- accesses the serial bus signal output by the power management chip. The access interface of the adapter 20 selectively couples the audio interface HPL / R and the universal serial bus interface USB_D+ / D- via the switch TypeC Switch to selectively access the audio signal or the universal serial bus signal. The second configuration channel pins CC3 & CC4 of the adapter 20 are directly coupled to the first configuration channel pins CC1 & CC2 of the interface circuit 101.

[0041] Different from the prior art in which the second power pin VBUS2 of the adapter 20 is directly coupled to the first power pin VBUS1 of the interface circuit 101 , in the embodiment of the present application, the second power pin VBUS2 of the adapter 20 is coupled to the first power pin VBUS1 of the interface circuit 101 via the delay circuit 102 .

[0042] In the prior art, after the adapter 20 is inserted into the terminal device 1 via the external interface, the voltage on the first power pin VBUS1 of the interface circuit 101 immediately reaches the target value, such as 4V, and the first configuration channel pins CC1 & CC2 of the interface circuit 101 are grounded. Among them, the condition for earphone recognition is that the voltage on the first configuration channel pins CC1 & CC2 is low, and the condition for charger type recognition is that the voltage on the first power pin VBUS1 exceeds the target value, such as 4V. This means that in the prior art, after the adapter 20 is inserted into the terminal device 1 via the external interface, the terminal device 1 is powered on, and the process of identifying the charger 40 is first executed and then the process of identifying the earphone 50 is executed. When the terminal device 1 executes the process of identifying the charger 40, several high-level signals will be generated on the universal serial bus interface USB_D+ / D- in the terminal device 1, such as the universal serial bus. The transmission path of these high-level signals on the earphone 50 is the same as that of the audio signal, and it is transmitted to the earphone 50 earlier than the earphone recognition. The earphone 50 will convert this signal into a sound signal and play it, generating a POP sound.

[0043] In this application, please refer to Figure 3As shown in the timing diagram, the voltage of the second power pin VBUS2 reaches the target value at the second moment T2. Since the delay circuit 102 is set, the first moment T1 when the voltage of the first power pin VBUS1 reaches the target value is later than the second moment T2. At the second moment T2, the voltage on the first configuration channel pins CC1 & CC2 is at a low level, and the voltage of the first power pin VBUS1 does not reach the target value, which means that the conditions for the terminal device 1 to perform earphone identification are met at this time, but the conditions for the terminal device 1 to perform charger identification are not met. Then the terminal device 1 can start earphone identification at the second moment T2, that is, identify the earphone parameters of the adapter 20 between the second moment T2 and the first moment T1. The charger type of the adapter 20 is identified at the first moment T1.

[0044] That is to say, in the present application, when the terminal device 1 performs the headphone identification and the charger identification, the headphone identification process is performed first, and then the charger identification process is performed. In this case, since the headphone identification is performed first, when a high-level signal is generated on the universal serial bus interface USB_D+ / D-, the path between the interface and the headphone is not connected, so the high-level signal will not be transmitted to the headphone 50, and thus no POP sound will be generated.

[0045] Specific as Figure 3 As shown, the serial bus interface USB_D+ / D- has a signal only at the first moment T1, when the charger identification process begins. During the earphone identification stage, that is, between the moment T2 and the moment T1, the serial bus interface USB_D+ / D- is at a low level, and no signal is transmitted to the earphone.

[0046] from Figure 3 It can be seen from the signal timing of the left channel of the middle earphone that there is no POP sound in the earphone during the entire stage of adapter identification (earphone identification and charger identification).

[0047] In a specific embodiment, the adapter identification circuit may further include a system on chip, and the system on chip identifies the charger type of the adapter at the first moment T1, and identifies the earphone parameters of the adapter between the first moment T1 and the second moment T2.

[0048] Specifically, after the adapter 20 is inserted into the terminal device 1, at the second time T2, the first configuration channel pins CC1 & CC2 of the terminal device 1 are shorted to the ground and are at a low level. The voltage on the first power pin VBUS1 will be at a high level after a period of time (first time T1) after the delay circuit 102 delays.

[0049] Refer to Figure 3In the timing of the first configuration channel pins CC1&CC2 and the second configuration channel pins CC3&CC4, before the first moment, the terminal device will switch between different modes, resulting in a change in the voltage on the first configuration channel pins CC1&CC2. Specifically, the terminal device can be an upstream facing port (UFP) device or a downstream facing port (DFP) device. The terminal device switches between DFP and UFP once every period of time, such as 50ms. When switching to DFP, such as at moment T5 and moment T3, the first configuration channel pins CC1&CC2 have a resistor pulled up to the power supply voltage or output a current source. When switching to UFP, such as at moment T4 and moment T2, the first configuration channel pins CC1&CC2 have a resistor pulled down to ground.

[0050] More specifically, the process of headphone parameter identification is as follows. The condition for headphone identification is that the voltage on the first configuration channel pins CC1 & CC2 is at a low level. Therefore, before identifying the relevant parameters of the headphone, it is necessary to first determine the level on the first configuration channel pins CC1 & CC2. For example, it is necessary to determine whether the level on the first configuration channel pins CC1 & CC2 is a low level. If the level on the first configuration channel pins CC1 & CC2 is a low level, the relevant parameters of the headphone are identified, and the switch TypeC Switch is controlled to couple the audio interface HPL / R to switch to the audio path, that is, to form an audio path between the terminal device 1 and the headphone 50. Specifically, the relevant parameters of the headphone are used to transmit the audio in the terminal device 1 to the headphone 50. For example, the relevant parameters of the headphone include impedance, sensitivity, frequency response range, etc.

[0051] Specifically, the earphone-related parameters may be the voltage on the first configuration channel pins CC1 & CC2, the pull-up resistor, the pull-down resistor, etc. Among them, the voltage on the first configuration channel pins CC1 & CC2 can be used to determine whether a device (such as earphones) has been inserted, the pull-down resistor on the first configuration channel pins CC1 & CC2 can be used to determine the direction, and the pull-up resistor can be used to detect the voltage on the first configuration channel pins CC1 & CC2, and then determine whether to flip and the current capacity.

[0052] Specifically, the levels on the second configuration channel pins CC3 & CC4 are all low levels in each stage, that is, the second configuration channel pins CC3 & CC4 are always grounded.

[0053] It should be noted that the headset in the embodiment of the present application can be a digital headset or an analog headset. The digital headset with Type C interface is an upstream facing port (UFP) device, and the terminal device 1 is a downstream facing port (DFP) device. The two CC pins of the digital headset have a load Rd. For analog headsets, the protocol requires that the two CC pins of the analog headset adapter be directly grounded.

[0054] For more principles of earphone recognition, please refer to the prior art and will not be elaborated here.

[0055] After the earphone parameter recognition is completed, at the first moment T1, the voltage of the first power pin VBUS1 reaches the target value. At this time, the on-chip system recognizes the charger type of the adapter at the first moment T1.

[0056] Specifically, the condition for the charger to be identified is that the voltage of the first power pin VBUS1 exceeds the target value, such as 4 V. Therefore, the system on chip needs to first determine the voltage on the first power pin VBUS1, and if it reaches the target value, identify the relevant parameters of the charger.

[0057] Specifically, the relevant parameters of the charger can be used for charging, that is, the relevant parameters of the charger are used to charge the terminal device 1. For example, the relevant parameters of the charger include output current, output voltage, and the like.

[0058] Specifically, the process of identifying the relevant parameters of the charger can also be called charger type identification. The specific identification process includes starting the timer and the primary detection. After starting the timer, if the terminal device does not support data connectivity detection (DCD), the next step will be started after the timeout. If supported, the terminal device applies a current on USB D+, such as 7-3 microamperes. If the terminal device is connected to an SDP (ordinary USB port), the SDP has a pull-down resistor on the USB D+ line. At this time, the voltage on USB D+ is within a certain range. As long as the voltage detected by the terminal device on USB D+ is less than a certain value (such as 0.8V) and maintained for a certain time (such as 10ms), the DCD detection is successful and the next step begins.

[0059] During the first detection, the terminal device applies a source voltage, such as 0.5-0.7V, to USB D+, and then starts to detect the voltage on USB D-. If the voltage on USB D- is less than the reference voltage (such as 0.25-0.4V), it means that the terminal device is connected to a normal USB port. If the voltage on USB D- is greater than the reference voltage, it means that the terminal device is connected to a dedicated charging port (Dedicate Charging Port, DCP). There may be two situations at this time. One is that the terminal device immediately starts enumeration, establishes a connection, and determines the charging current through configuration. The other is that the terminal device starts a secondary detection and applies another voltage, such as 0.5-0.7V, to USB D-. Then detect the voltage on USB D+. If the voltage on USB D+ is greater than the reference voltage, it means that the terminal device is connected to a dedicated charging port DCP. If the voltage on USB D+ is less than the reference voltage, it means that the terminal device is connected to a USB port with strong charging capabilities (Charging Downstream Port, CDP).

[0060] It should be noted that for more specific implementations of earphone identification and charger type identification, reference can be made to the prior art and will not be repeated here.

[0061] In a non-limiting embodiment of the present application, the delay circuit 102 may include an impedance unit and an energy storage unit. One end of the impedance unit is coupled to the first power pin VBUS1, and the other end of the impedance unit is coupled to the second power pin VBUS2. One end of the energy storage unit is coupled to the first power pin VBUS1, and the other end of the energy storage unit is grounded.

[0062] In the embodiment of the present application, after the second power pin VBUS2 of the adapter 20 is connected to the terminal device 1, the energy storage unit starts to charge. It takes a certain amount of time for the energy storage unit to be fully charged. After the energy storage unit is fully charged, it starts to discharge, and the voltage of the first power pin VBUS1 starts to rise. It can be seen that the process of charging and discharging the energy storage unit makes the first moment when the voltage of the first power pin VBUS1 reaches the target value later than the second moment when the voltage of the second power pin VBUS2 reaches the target value.

[0063] Please refer to Figure 4 , Figure 4 A specific structure of the delay circuit 102 is shown. The impedance unit is a resistor R1, and the energy storage unit is a capacitor C1. One end of the resistor R1 is coupled to the first power pin VBUS1, and the other end of the resistor R1 is coupled to the second power pin VBUS2. One end of the capacitor C1 is coupled to the first power pin VBUS1, and the other end of the capacitor C1 is grounded.

[0064] Specifically, the impedance of the resistor R1 and the capacitance of the capacitor C1 can be set according to the actual application scenario, for example, according to the required delay time (the time interval between the first moment and the second moment).

[0065] It should be noted that the impedance unit may also be any other feasible electronic component with impedance, and the energy storage unit may also be any other feasible electronic component with energy storage function, and the present application does not impose any limitation on this.

[0066] Specifically, the audio interface HPL / R of the adapter identification circuit 10 is selectively connected to the audio interface HPL / R of the power management chip PMIC via a switch (TypeC Switch). The universal serial bus interface USB_D+ / D- of the adapter identification circuit 10 is selectively connected to the universal serial bus interface USB_D+ / D- of the PMIC via a switch. The power management chip PMIC transmits signals, such as audio signals or universal serial bus (USB) signals, between the system on chip (SoC) in the terminal device 1.

[0067] The audio interface HPL / R of the adapter 20 is coupled to the audio interface HPL / R of the adapter identification circuit 10, and the universal serial bus interface USB_D+ / D- of the adapter 20 is coupled to the universal serial bus interface USB_D+ / D- of the adapter identification circuit 10. The second configuration channel pins CC3 & CC4 of the adapter 20 are directly coupled to the first configuration channel pins CC1 & CC2 of the adapter interface circuit 101. The adapter 20 can also be connected to an external charger 40 and earphones 50.

[0068] See also Figure 5 The method provided in this application specifically includes the following steps:

[0069] Step 501: Apply a first voltage signal to the second power pin.

[0070] After step 501 , the delay circuit can be used to make the first time when the voltage of the first power pin reaches the target value later than the second time when the voltage of the first power pin reaches the target value.

[0071] Step 502: Identify earphone parameters of the adapter between the first moment and the second moment.

[0072] Step 503: at the first moment, controlling the on-chip system to identify the charger type of the adapter.

[0073] It should be pointed out that the serial numbers of the steps in this embodiment do not limit the execution order of the steps.

[0074] It is understandable that, in a specific implementation, the above method can be implemented in the form of a software program, and the software program runs in a processor integrated inside a chip or a chip module. The method can also be implemented in the form of software combined with hardware, which is not limited in this application.

[0075] Specifically, each step of the above method can be performed by a terminal device, such as a mobile phone. Through the above steps, the terminal device can identify the earphone-related parameters of the adapter for outputting audio signals; the terminal device can identify the charger-related parameters for charging.

[0076] The interface circuit referred to in this embodiment can be specifically manifested as a Type C interface on the terminal device. The terminal device in this embodiment has only one Type C interface, and by inserting an adapter into the external interface, the terminal device can be connected to the headset and the charger at the same time.

[0077] In a non-limiting example, see Figure 6 The present application also discloses an adapter 70. The adapter 70 includes a second power pin VBUS2 and a delay circuit 701. The second power pin VBUS2 is used to access a power voltage, and the power voltage has a target value.

[0078] The input end of the delay circuit 701 is coupled to the second power pin VBUS2. The delay circuit 701 is used to make the first time when the voltage at its output end reaches the target value later than the second time when the voltage at the second power pin reaches the target value.

[0079] Specifically, the output end of the delay circuit 701 is coupled to the first power pin VBUS1 of the interface circuit 601 in the terminal device 60. Then, the delay circuit 701 makes the first moment when the voltage of the first power pin VBUS1 reaches the target value later than the second moment when the voltage of the second power pin VBUS2 reaches the target value.

[0080] Continue to refer to Figure 7 , Figure 7 The schematic diagram shows the connection between the adapter 70 and the terminal device 60. The second power pin VBUS2 can be connected to the power voltage through the charger 40, and the power voltage is connected to the first power pin VBUS1 after passing through the delay circuit 701.

[0081] In a specific application, the adapter 70 needs to be first inserted into the terminal device 60, and then the charger 40 is connected to the adapter 70. That is to say, the charger should be connected to the adapter 70 later than the adapter 70 is connected to the terminal device 60, so that the first moment when the voltage of the first power pin VBUS1 reaches the target value can be achieved later than the second moment when the voltage of the second power pin VBUS2 reaches the target value.

[0082] For more specific implementation methods of the embodiments of the present application, please refer to the aforementioned embodiments, which will not be repeated here.

[0083] Regarding the various modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, or hardware modules / units, or they can be partially software modules / units and partially hardware modules / units. For example, for various devices and products applied to or integrated in a chip, the various modules / units included therein can all be implemented in the form of hardware such as circuits, or at least some of the modules / units can be implemented in the form of software programs, which run on a processor integrated inside the chip, and the remaining (if any) modules / units can be implemented in the form of hardware such as circuits; for various devices and products applied to or integrated in a chip module, the various modules / units included therein can all be implemented in the form of hardware such as circuits, and different modules / units can be located in the same component of the chip module (such as a chip, circuit module, etc.) or in different components, or at least some of the modules / units can be implemented in the form of software programs. It is implemented in the form of a software program, which runs on a processor integrated inside the chip module, and the remaining (if any) modules / units can be implemented in hardware such as circuits; for various devices and products applied to or integrated in the terminal equipment, the various modules / units contained therein can be implemented in hardware such as circuits, and different modules / units can be located in the same component (for example, chip, circuit module, etc.) or in different components in the terminal equipment, or, at least some modules / units can be implemented in the form of a software program, which runs on a processor integrated inside the terminal equipment, and the remaining (if any) modules / units can be implemented in hardware such as circuits.

[0084] The present application also discloses a storage medium, which is a computer-readable storage medium and stores a computer program, which can be executed when the computer program is run. Figures 1 to 3 The steps of the method shown in . The storage medium may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc. The storage medium may also include a non-volatile memory (non-volatile) or a non-transitory memory, etc.

[0085] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0086] The "plurality" appearing in the embodiments of the present application refers to two or more.

[0087] The first, second, etc. descriptions appearing in the embodiments of the present application are only used for illustration and distinction of the description objects. There is no order, nor do they indicate any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0088] The "connection" that appears in the embodiments of the present application refers to various connection methods such as direct connection or indirect connection to achieve communication between devices, and the embodiments of the present application do not impose any limitations on this.

[0089] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination thereof. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means.

[0090] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0091] In the several embodiments provided in the present application, it should be understood that the disclosed methods, devices and systems can be implemented in other ways. For example, the device embodiments described above are merely schematic; for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0092] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0093] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0094] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform some steps of the method described in each embodiment of the present application.

[0095] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims

1. An adapter identification circuit, characterized in that: include: An interface circuit, wherein the interface circuit has a first power pin, wherein the first power pin is used to access a power voltage, and the power voltage has a target value; A delay circuit, wherein the input end of the delay circuit is coupled to the second power pin of the adapter, the output end of the delay circuit is coupled to the first power pin of the interface circuit, and the delay circuit is used to make the first moment when the voltage of the first power pin reaches the target value later than the second moment when the voltage of the second power pin reaches the target value.

2. The adapter identification circuit according to claim 1, characterized in that: Also includes: The system on chip identifies the charger type of the adapter at the first moment, and identifies the earphone parameters of the adapter between the first moment and the second moment.

3. The adapter identification circuit according to claim 1, characterized in that: The interface circuit has an audio interface, and the audio interface is connected to the audio signal output by the power management chip.

4. The adapter identification circuit according to claim 1, characterized in that: The interface circuit has a universal serial bus interface, and the universal serial bus interface is connected to the serial bus signal output by the power management chip.

5. The adapter identification circuit according to claim 1, characterized in that: The interface circuit has a first configuration channel pin, the first configuration channel pin is coupled to a second configuration channel pin of the adapter, and the voltages on the first configuration channel pin and the second configuration channel pin are at a low level at the second moment.

6. The adapter identification circuit according to claim 1, characterized in that: The interface circuit has a switch, and the switch is used for selectively accessing an audio signal or a serial bus signal.

7. The adapter identification circuit according to claim 1, characterized in that: The delay circuit comprises: an impedance unit, one end of the impedance unit is coupled to the first power pin, and the other end of the impedance unit is coupled to the second power pin; An energy storage unit, one end of which is coupled to the first power pin, and the other end of which is grounded.

8. An adapter, characterized in that: include: A second power supply pin, used for receiving a power supply voltage, wherein the power supply voltage has a target value; A delay circuit, wherein the input end of the delay circuit is coupled to the second power pin, and the delay circuit is used to make a first moment when the voltage at its output end reaches the target value later than a second moment when the voltage at the second power pin reaches the target value.

9. A control method based on the adapter identification circuit according to any one of claims 1 to 7, characterized in that: include: Applying a first voltage signal to the second power pin, so that a first time when the voltage of the first power pin reaches the target value is later than a second time when the voltage of the first power pin reaches the target value through the delay circuit; Identifying earphone parameters of the adapter between the first moment and the second moment; At the first moment, the on-chip system is controlled to identify the charger type of the adapter.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the control method according to claim 9 are executed.

11. A terminal device, characterized in that: The adapter comprises the adapter identification circuit as claimed in any one of claims 1 to 7.

12. A chip module, characterized in that: The adapter comprises the adapter identification circuit as claimed in any one of claims 1 to 7.

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