Splitting method of single-output combinational logic circuit
By splitting the single output combination logic circuit into the connection of two logic sub-circuits and using logic overlay operations to solve the logic expression of logic sub-circuit H, the inefficiency problem caused by the large number of input variables in the prior art is solved, and efficient logic circuit splitting and operation are achieved.
Patent Information
- Application Number
- CN202411563879.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-05
- Publication Date
- 2025-03-28
AI Technical Summary
The prior art is inefficient and difficult to deal with single-output combination logic circuits with a large number of input variables, mainly due to the exponential growth of input combinations and the time-consuming and memory-consuming problem of output search.
By splitting the single output combination logic circuit into the connection of two logic sub-circuits, the logic overlay operation is used to solve the logic expression of the logic sub-circuit H, which avoids the inefficient process of input expansion and output search.
When dealing with logic circuits with a large number of variables, this method improves computing efficiency, avoids the time-consuming and memory-consuming problems of input expansion and output search, is suitable for the splitting of multi-output logic circuits, and can further split the split sub-circuits.