A crosstalk-aware quantum program compilation framework system

Abstract

The application discloses a crosstalk-aware quantum program compiling framework system, which comprises a parameter optimization module, a crosstalk-aware mapping module and a quantum logic gate scheduling module which are connected in communication, wherein the parameter optimization module is used for optimizing the parameters of quantum logic gates in a quantum program to be executed, the crosstalk-aware mapping module is used for receiving the parameter optimization result of the parameter optimization module, determining an optimal mapping scheme of the quantum program to be executed by constructing a cost function, and the quantum logic gate scheduling module is used for determining the maximum independent set between quantum bits in the quantum program to be executed and a parallel quantum logic gate scheduling scheme of the maximum independent set according to the optimal mapping scheme, so as to realize the compilation of the quantum program to be executed. Through the crosstalk-aware quantum program compiling framework system, the crosstalk noise is perceived, and the quantum circuit mapping scheme is comprehensively optimized, so that the quantum program compiling process is accurate and efficient.

Description

Technical Field

[0001] This invention belongs to the field of quantum computing technology, specifically a crosstalk-aware quantum program compilation framework system. Background Technology

[0002] Quantum computing is currently considered to have the potential to catch up with or even surpass classical computing in fields such as quantum chemistry, artificial intelligence, and factorization. Currently, quantum computing has entered the era of noisy mesoscale quantum (NISQ) chips. Quantum computing simulation is a simulation program that uses numerical computation and computer science to simulate computations that follow the laws of quantum mechanics. As a simulation program, it uses the high-speed computing power of NISQ computers, based on the fundamental laws of quantum mechanics, to characterize the spatiotemporal evolution of quantum states.

[0003] While current technologies have demonstrated the superiority of quantum computing, fully utilizing the acceleration capabilities of NISQ computers to solve practical problems requires further improvements to quantum hardware performance. Challenges such as the limited number of qubits, the low operational depth of quantum circuits, and susceptibility to noise (e.g., crosstalk is a significant source of noise in quantum computing) are all significant hurdles that must be overcome. The insufficient number of qubits prevents fault-tolerant quantum computing and makes it susceptible to noise. Therefore, addressing crosstalk and other issues within the current resource-constrained context of NISQ computers is a crucial problem that urgently needs to be solved to verify the effectiveness of various NISQ-based quantum algorithms and facilitate their practical application. Summary of the Invention

[0004] The purpose of this invention is to provide a crosstalk-aware quantum program compilation framework system to address the shortcomings of existing technologies. By proposing a crosstalk-aware quantum program compilation framework system, it achieves accurate and efficient quantum program compilation by sensing crosstalk noise and comprehensively optimizing quantum circuit mapping schemes, thereby effectively promoting the development of quantum computing technology.

[0005] One embodiment of this application provides a crosstalk-aware quantum program compilation framework system, the system comprising: a parameter optimization module for communication connections, a crosstalk-aware mapping module, and a quantum logic gate scheduling module, wherein...

[0006] The parameter optimization module is used to optimize the parameters of quantum logic gates in the quantum program to be executed;

[0007] The crosstalk sensing mapping module is used to receive the parameter optimization results of the parameter optimization module and determine the optimal mapping scheme of the quantum program to be executed by constructing a cost function;

[0008] The quantum logic gate scheduling module is used to determine the maximum independent set of qubits in the quantum program to be executed and the parallel quantum logic gate scheduling scheme of the maximum independent set according to the optimal mapping scheme, so as to realize the compilation of the quantum program to be executed.

[0009] Optionally, the parameter optimization module includes:

[0010] The initial parameter optimization unit for dual quantum logic gates and the parallel parameter optimization unit for dual quantum logic gates, wherein,

[0011] The dual quantum logic gate initial parameter optimization unit is used to determine the optimal frequency of the dual quantum logic gate and the discreteness parameter of the frequency distribution of the dual quantum logic gate in the quantum program to be executed;

[0012] The parallel parameter optimization unit for dual quantum logic gates is used to optimize the coupler pulse frequency parameters of adjacent dual quantum logic gates.

[0013] Optionally, the dual quantum logic gate initial parameter optimization unit optimizes the parameters of the dual quantum logic gates in the quantum program to be executed using the following formula:

[0014]

[0015] Where W(t) represents the optimized frequency of the two quantum logic gate at time t, W off W represents the idle frequency of the coupler and the qubit. on The resonant frequency of the quantum logic gate is represented by erf, the error function is represented by σ, and the amplitude of the frequency waveform controlling the two quantum logic gates is represented by t. gate This indicates the execution time of a quantum logic gate.

[0016] Optionally, the crosstalk-aware mapping module includes:

[0017] The transformation unit is used to transform the quantum program to be executed into a directed acyclic graph;

[0018] The determination unit is used to combine the parameter optimization results and determine the optimal mapping scheme of the quantum program to be executed by traversing the directed acyclic graph.

[0019] Optionally, the determining unit includes:

[0020] The pre-gate determination subunit is used to determine the set of pre-quantum logic gates that cannot be directly executed in the topological sequence corresponding to the directed acyclic graph, based on the topological order of the directed acyclic graph and the execution time of the quantum logic gates.

[0021] The mapping determination subunit is used to sequentially traverse each dual quantum logic gate in the set of preceding quantum logic gates, construct a tree search structure based on SWAP gates, generate all mapping schemes that insert SWAP gates, and determine the optimal mapping scheme of the quantum program to be executed through a cost function.

[0022] Optionally, the cost function includes:

[0023]

[0024] Where D represents the cost function, d represents the distance cost of each SWAP gate, g represents the number of two quantum logic gates that need to be inserted into the SWAP gate, F represents the set of preceding quantum logic gates, and π l+1 For mapping π l The sub-items are represented by the mapping π. l The new mapping π obtained after inserting the SWAP gate l+1 , and These represent the two qubits that need to be inserted into the SWAP gate.

[0025] Optionally, the quantum logic gate scheduling module includes:

[0026] Crosstalk diagram determination unit, used to generate quantum logic gate crosstalk diagrams;

[0027] A crosstalk subgraph determination unit is used to determine the crosstalk subgraph of the quantum logic gate crosstalk graph;

[0028] The maximum independent set determination unit is used to obtain the maximum independent set of all the crosstalk subgraphs.

[0029] Another embodiment of this application provides a quantum computer operating system, which includes a crosstalk-aware quantum program compilation framework system according to the above description.

[0030] Another embodiment of this application provides a quantum computer, comprising:

[0031] A first quantum computing hardware device, wherein a crosstalk-aware quantum program compilation framework system according to the above-described method is provided on the first quantum computing hardware device; and

[0032] A second quantum computing hardware device, which communicates with the first quantum computing hardware device, includes a quantum chip, wherein the communication module of the crosstalk-aware quantum program compilation framework system sends the quantum program to be executed to the second quantum computing hardware device for compilation of the quantum program.

[0033] Another embodiment of this application provides a quantum computer-readable storage medium storing one or more quantum computer-executable instructions. When the quantum computer-executable instructions are executed by a quantum computer, the crosstalk-aware quantum program compilation framework system described above is implemented.

[0034] Compared with existing technologies, the crosstalk-aware quantum program compilation framework system disclosed in this invention includes a parameter optimization module for communication connections, a crosstalk-aware mapping module, and a quantum logic gate scheduling module. The parameter optimization module optimizes the parameters of the quantum logic gates in the quantum program to be executed. The crosstalk-aware mapping module receives the parameter optimization results from the parameter optimization module and determines the optimal mapping scheme for the quantum program to be executed by constructing a cost function. The quantum logic gate scheduling module determines the maximum independent set of qubits in the quantum program to be executed and the parallel quantum logic gate scheduling scheme of the maximum independent set based on the optimal mapping scheme, thereby realizing the compilation of the quantum program to be executed. By proposing a crosstalk-aware quantum program compilation framework system, it achieves accurate and efficient quantum program compilation by sensing crosstalk noise and comprehensively optimizing the quantum circuit mapping scheme, effectively promoting the development of quantum computing technology. Attached Figure Description

[0035] Figure 1 This is a structural block diagram of a quantum computer provided in an embodiment of the present invention;

[0036] Figure 2 This is a schematic architecture block diagram of a crosstalk-aware quantum program compilation framework system provided in an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of a quantum chip provided in an embodiment of the present invention;

[0038] Figure 4 This is a schematic block diagram of another crosstalk-aware quantum program compilation framework system provided in an embodiment of the present invention.

[0039] Explanation of reference numerals in the attached figures:

[0040] 10 - The first quantum computing hardware device,

[0041] 11-processor,

[0042] 12-Memory,

[0043] 100-Quantum Computer Operating System

[0044] 20 - Second quantum computing hardware device,

[0045] 21-Quantum chip,

[0046] A 200-crosstalk-aware quantum program compilation framework system

[0047] 201 - Parameter Optimization Module

[0048] 202-Crosstalk-aware mapping module,

[0049] 203 - Quantum Logic Gate Scheduling Module

[0050] 204 - Quantum Programming Framework Module. Detailed Implementation

[0051] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0052] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0053] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of the invention.

[0054] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0055] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0056] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0057] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0058] Figure 1 This is a structural block diagram of a quantum computer provided in an embodiment of the present invention, such as... Figure 1As shown, the quantum computer includes a first quantum computing hardware device 10 and a second quantum computing hardware device 20. A quantum computer operating system 100 is configured on the first quantum computing hardware device 10. The first quantum computing hardware device 10 may include a processor 11 and a memory 12. The quantum computer operating system 100 can be implemented through the processor 11 and the memory 12. The second quantum computing hardware device 20 communicates with the first quantum computing hardware device 10. The second quantum computing hardware device 20 includes a quantum chip 21.

[0059] The quantum computer operating system 100 may include a crosstalk-aware quantum program compilation framework system. The quantum computer operating system 100 generates an executable quantum program or quantum computing task. A communication module sends the executable quantum program to a second quantum computing hardware device 20 for compilation and execution.

[0060] The crosstalk-aware quantum program compilation framework system 200 in this embodiment can be applied to the quantum computer operating system 100, which is a computer program that manages quantum computing software and hardware resources. See below for further details. Figure 2 The relevant modules of each embodiment are described.

[0061] Figure 2 This is a schematic architectural block diagram of a crosstalk-aware quantum program compilation framework system provided in an embodiment of the present invention. Figure 2 As shown, the crosstalk-aware quantum program compilation framework system 200 may include: a parameter optimization module 201 with communication connections, a crosstalk-aware mapping module 202, and a quantum logic gate scheduling module 203. The parameter optimization module 201 optimizes the parameters of the quantum logic gates in the quantum program to be executed. The crosstalk-aware mapping module 202 receives the parameter optimization results from the parameter optimization module and determines the optimal mapping scheme for the quantum program to be executed by constructing a cost function. The quantum logic gate scheduling module 203 determines, based on the optimal mapping scheme, the maximum independent set of qubits in the quantum program to be executed and the parallel quantum logic gate scheduling scheme for the maximum independent set, thereby realizing the compilation of the quantum program to be executed.

[0062] Specifically, a quantum program to be executed can include a quantum circuit. A quantum program as a whole is a single quantum circuit. This can be understood as follows: a quantum program can consist of a quantum circuit, measurement operations on the qubits within the quantum circuit, registers to store the measurement results, and control flow nodes (jump instructions). A quantum circuit can contain dozens, hundreds, or even thousands of quantum logic gate operations. The execution process of a quantum program is the process of executing all the quantum logic gates according to a certain timing order, which is the chronological order in which individual quantum logic gates are executed.

[0063] In an optional implementation, the parameter optimization module 201 may include: a dual quantum logic gate initial parameter optimization unit and a dual quantum logic gate parallel parameter optimization unit, wherein the dual quantum logic gate initial parameter optimization unit is used to determine the optimal frequency of the dual quantum logic gate and the dispersion parameter of the frequency distribution of the dual quantum logic gate in the quantum program to be executed, and the parameters optimized by the dual quantum logic gate initial parameter optimization unit may also include the pulse parameters of the qubit, the pulse parameters of the quantum logic gate coupler, and the coupler pulse parameters between the qubit and the adjacent qubit, etc.

[0064] For example, the initial parameter optimization unit for a two-quantum logic gate can optimize the parameters of the two-quantum logic gate in the quantum program to be executed using the following formula:

[0065]

[0066] Where W(t) represents the optimized frequency of the two quantum logic gate at time t, W off W represents the idle frequency of the coupler and the qubit. on The resonant frequency of the quantum logic gate is represented by erf, the error function is represented by σ, and the amplitude of the frequency waveform controlling the two quantum logic gates is represented by t. gate This indicates the execution time of a quantum logic gate.

[0067] It should be noted that optimizing the parameters of a dual quantum logic gate usually involves optimizing a large number of parameters. Since the optimal parameters obtained through optimization are inconsistent when adjacent qubits are at different frequencies, in the initial parameter optimization process of a specific chip, for each qubit-coupler-qubit combination, it is necessary to obtain the parameters when the adjacent qubits are at their idle operating frequencies.

[0068] Specifically, the parallel parameter optimization unit for dual quantum logic gates can be used to optimize the coupler pulse frequency parameters of adjacent dual quantum logic gates. During quantum chip initialization, initial parameter optimization is performed on each dual quantum logic gate. During optimization, the frequencies of adjacent qubits can initially be set to their idle frequencies. This is because when two adjacent dual quantum logic gates are performing quantum computing tasks, the qubit states are in a mixed state; they are not at their idle frequencies, and the detuning between the qubits changes. This means that the initial crosstalk blocking between these two dual quantum logic gates is ineffective, therefore the parameters of the dual quantum logic gates need to be re-optimized. For example, the coupler pulse frequency parameter can be changed to the minimum value with the lowest crosstalk strength.

[0069] In an optional implementation manner, the crosstalk-aware mapping module 202 may include: a conversion unit configured to convert a to-be-executed quantum program into a directed acyclic graph; a determination unit configured to combine the parameter optimization result and determine an optimal mapping scheme of the to-be-executed quantum program by traversing the directed acyclic graph. The determination unit may include: a pre-gate determination subunit configured to determine a set of pre-quantum logic gates that cannot be directly executed in the corresponding topological sequence of the directed acyclic graph according to the topological order of the directed acyclic graph and the execution time of the quantum logic gates; a mapping determination subunit configured to sequentially traverse each two-qubit logic gate in the set of pre-quantum logic gates, construct a tree-type search structure based on SWAP gates, generate all mapping schemes with inserted SWAP gates, and determine the optimal mapping scheme of the to-be-executed quantum program through a cost function.

[0070] Exemplarily, first, based on the conversion unit, the to-be-executed quantum program is converted into a directed acyclic graph. Then, according to the topological order of the directed acyclic graph and the execution time of the quantum logic gates, a set of pre-quantum logic gates that cannot be directly executed in the corresponding topological sequence of the directed acyclic graph is determined, that is, the gates that cannot be executed in the frontmost layer are selected and defined as the set of pre-quantum logic gates (front_layer). Then, based on the mapping determination subunit, each two-qubit logic gate in the set of pre-quantum logic gates is sequentially traversed. If the current frontmost quantum logic gate cannot be directly executed under the current mapping, a SWAP gate is inserted. It should be noted that the SWAP gate needs to be inserted between the qubits connected by the coupler. For example, before the SWAP gate S ij , the mapping is π l : q i →Q i , q j →Q j . After inserting the SWAP gate, the mapping arrangement changes to π l+1 : q i →Q j , q j →Q i .

[0071] To find a more suitable mapping, a tree-type search structure based on SWAP gates is constructed, and all mapping schemes with inserted SWAP gates are listed. Among them, the nodes of the tree represent the mapping states, the edges represent the SWAP gates for changing the mapping, and the root node of the tree is the current mapping state π l . During the construction process, specific values of M and L are set according to the performance of the current hardware computing device; the forward look of the subsequent tree search is controlled by the tree depth L, and the breadth of the tree search is controlled by the number M of child nodes of each node; to reduce the complexity, M<S is also set, where S represents the number of all selectable SWAP gates.

[0072] Specifically, the tree search structure process based on SWAP gates is an iterative process, starting with the initial mapping π. l For example, first, obtain the quantum logic gates that cannot be directly executed and their corresponding mappings; second, perform a SWAP gate insertion operation on each of the two qubits of all quantum logic gates to be executed, and obtain a new mapping (π). l+1，1 , π l+1，2 , ..., π l+1，M Then, iteratively execute the second step until the (L-1) level mapping is obtained. For each SWAP gate S in the tree search structure based on SWAP gates... ij Insert it into the quantum program to be executed, and simultaneously calculate S ij Distance cost The above cost function may include:

[0073]

[0074] Where D represents the cost function, d represents the distance cost of each SWAP gate, g represents the number of two quantum logic gates that need to be inserted into the SWAP gate, F represents the set of preceding quantum logic gates, and π l+1 For mapping π l The sub-items are represented by the mapping π. l The new mapping π obtained after inserting the SWAP gate l+1 , and These represent the two qubits that need to be inserted into the SWAP gate.

[0075] In another alternative implementation, after obtaining the M nodes with the smallest distance based on the aforementioned cost function, a swap operation Sij is performed on the current mapping to obtain M child nodes. Finally, after obtaining the L×M search tree, the quality of the current mapping is evaluated starting from the last child node. The evaluation criteria can be determined by the following formula:

[0076]

[0077] Among them, C l，p The evaluation function representing the current mapping quality, C l+1，m C l，p sub-items, G l，p βP l，p G represents the gain and parallel parameter overhead of the two-bit quantum logic gate at node l, and G represents the value of the parallel parameter overhead in the mapping π. l，p The number of pre-executed quantum logic gates, P, represents the number of gates that can be executed in the mapping π. l，pThe number of parameters that need to be re-optimized due to the parallel execution of the first two quantum logic gates is given by β, which is the weighting coefficient of the number of parameters that need to be re-optimized in the mapping quality, and γ is the weighting coefficient of the sub-items of the current mapping, where γ∈(0,1).

[0078] Finally, when tracing back to the step of transforming the quantum program to be executed into a directed acyclic graph, the maximum C can be chosen. l+1，p The corresponding SWAP gate, after inserting SWAP gate p, yields a new mapping π. l，p Repeat the above steps until all non-directly executable quantum logic gates are remapped. This will give you all the mapping schemes for inserting SWAP gates, and you can then determine the optimal mapping scheme for the quantum program to be executed using the cost function described above.

[0079] Specifically, the quantum logic gate scheduling module 203 is used to determine the maximum independent set of qubits in the quantum program to be executed and the parallel quantum logic gate scheduling scheme of the maximum independent set according to the optimal mapping scheme, so as to realize the compilation of the quantum program to be executed.

[0080] In one optional implementation, the quantum logic gate scheduling module 203 may include: a crosstalk graph determination unit for generating a quantum logic gate crosstalk graph; a crosstalk subgraph determination unit for determining the crosstalk subgraphs of the quantum logic gate crosstalk graph; and a maximum independent set determination unit for obtaining the maximum independent set of all the crosstalk subgraphs.

[0081] Among them, the crosstalk graph determination unit is used to generate the quantum logic gate crosstalk graph G(V). g E g ), where node V g E represents a set of qubit-coupler-qubits representing two directly executable quantum logic gates. g The weight of an edge represents the parallel crosstalk effect between the qubit-coupler-qubit set; the weight of an edge represents the number of parameters that need to be re-optimized for the two quantum logic gates corresponding to the edge during parallel execution.

[0082] See Figure 3 , Figure 3 This is a schematic diagram of a quantum chip provided in an embodiment of the present invention, in which a V-shaped structure is constructed. g，9，10 Crosstalk diagram with V as the base point, where V g，9，10 E represents a qubit-coupler-qubit combination, where the weight of the two-qubit gate with parallel crosstalk to its neighboring nodes is 2, because only one coupler frequency needs to be re-optimized for its parameters. g，9，10，g，14，15 E g，9，10，g，4，5 The weight is 4, meaning that the frequency parameters of two couplers need to be re-optimized.

[0083] Secondly, the crosstalk subgraph is determined using the crosstalk subgraph determination unit to obtain the crosstalk subgraph corresponding to the quantum program to be executed. First, the mapped quantum program is converted into a directed acyclic graph (DAG), and then the DAG topological order of the quantum logic gates and the execution time t are used as the basis for the determination. g Determine the start execution time gτ and end execution time gτ+t for each quantum logic gate. g Then determine the execution time of all parallel quantum logic gates in the quantum program; if the execution time of the quantum logic gates satisfies the equation... This results in temporal overlap, meaning that the aforementioned quantum logic gates map π to the current qubit. l Parallel execution is then performed. All quantum logic gates that can be executed in parallel are selected, forming a crosstalk subgraph. The edges of the crosstalk subgraph represent the parallel crosstalk of the quantum logic gates, and the weight of each edge represents the number of coupler parameters that need to be optimized for parallel execution. Then, the maximum independent set of the crosstalk subgraph is obtained using the maximum independent set determination unit. If the executed quantum logic gates in the crosstalk subgraph have no interconnected edges, it indicates that there is no parallel crosstalk, meaning the executed quantum logic gates are independent and can reside in the same set. Corresponding nodes are deleted sequentially, and the maximum independent set is searched in the remaining crosstalk subgraph until the crosstalk subgraph is completely disconnected.

[0084] It should be noted that, to reduce the execution time of the quantum program, if the number of maximum independent sets is too large, the length of the quantum program will increase, and decoherence noise will become significant. To avoid this, the number of sets in the maximum independent set should be small. Specifically, in the process of obtaining the independent sets, we start with the number of maximum independent sets N, where N is initially set to 2, and perform the following steps:

[0085] 1) Search for the largest independent set. If the number of sets in the largest independent set is less than or equal to N, then stop.

[0086] 2) Otherwise, let K be the maximum number of re-optimization parameters allowed in the quantum chip control system. Select nodes from largest to smallest degree and put them into N different sets.

[0087] 3) For each set, calculate the number of re-optimization parameters of the crosstalk subgraphs corresponding to these nodes. If they are all less than K, then end; otherwise, update the number of sets in the maximum independent set to N+1 and repeat the above steps. Finally, determine the quantum logic gates in the different independent sets and execute them.

[0088] As can be seen, the scheduling scheme for quantum logic gates based on the quantum logic gate scheduling module can abstract the parallel crosstalk relationship between quantum logic gates into a crosstalk graph model and simplify it into solving the maximum independent set problem to select the maximum set of quantum logic gates without parallel crosstalk. By parallelizing as many dual quantum logic gates as possible through the above method, the execution time of the quantum program can be shortened while avoiding crosstalk.

[0089] Figure 4 This is a schematic block diagram of another crosstalk-aware quantum program compilation framework system provided in an embodiment of the present invention. Figure 4 As shown, the crosstalk-aware quantum program compilation framework system 200 may further include: a quantum programming framework module 204, which provides a quantum / classical hybrid programming language, a visual programming IDE, and generates a quantum program to be executed.

[0090] For example, the quantum programming framework module 204 may include a quantum programming framework unit and a quantum-classical hybrid compilation framework unit. The quantum programming framework unit provides a programming language and simulation computation interface, allowing users to write quantum programs based on the provided programming language and perform quantum algorithm simulations using the provided simulation computation interface. The quantum programming framework unit also provides various quantum circuit operation interfaces, such as quantum circuit printing, equivalent quantum circuit comparison, quantum circuit flipping, and conversion to other quantum programming languages. The quantum-classical hybrid compilation framework unit optimizes the compilation of user-written quantum-classical hybrid programs and adjusts the timing relationship between quantum and classical computations to improve the execution efficiency of the quantum-classical hybrid algorithm.

[0091] In another alternative embodiment, the crosstalk-aware quantum program compilation framework system described above can all be installed on... Figure 1 In the quantum computer shown.

[0092] As can be seen, the crosstalk-aware quantum program compilation framework system disclosed in this invention includes a parameter optimization module for communication connections, a crosstalk-aware mapping module, and a quantum logic gate scheduling module. The parameter optimization module optimizes the parameters of the quantum logic gates in the quantum program to be executed. The crosstalk-aware mapping module receives the parameter optimization results from the parameter optimization module and determines the optimal mapping scheme for the quantum program to be executed by constructing a cost function. The quantum logic gate scheduling module determines the maximum independent set of qubits in the quantum program to be executed and the parallel quantum logic gate scheduling scheme of the maximum independent set based on the optimal mapping scheme, thereby realizing the compilation of the quantum program to be executed. By proposing a crosstalk-aware quantum program compilation framework system, it achieves accurate and efficient quantum program compilation by sensing crosstalk noise and comprehensively optimizing the quantum circuit mapping scheme, effectively promoting the development of quantum computing technology.

[0093] This invention also provides a quantum computer-readable storage medium storing one or more quantum computer-executable instructions. When these quantum computer-executable instructions are executed by a quantum computer, the crosstalk-aware quantum program compilation framework system described above is implemented.

[0094] Therefore, the embodiments disclosed herein may include a crosstalk-aware quantum program compilation framework system, a quantum computer operating system, a quantum computer, and / or a quantum computer program product. The quantum computer program product may include a computer-readable storage medium on which executable commands of the quantum computer operating system are stored.

[0095] A quantum computer-readable storage medium can be a tangible device capable of holding and storing instructions used by an instruction execution device. A quantum computer-readable storage medium can be, for example, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of quantum computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof.

[0096] The executable instructions for the quantum computer described herein can be downloaded from a quantum computer-readable storage medium to individual quantum computing / processing devices, or via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external quantum computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each quantum computing / processing device receives computer-readable program instructions from the network and forwards these instructions to the computer-readable storage medium in the individual computing / processing device.

[0097] Executable instructions used to implement a quantum computer operating system can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code, intermediate code, or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as C or similar languages. The executable instructions can execute entirely on the quantum computer, partially on the quantum computer, as a standalone software package, partially on the local quantum computer and partially on a remote quantum computer, or entirely on a remote quantum computer or server. In cases involving remote quantum computers, the remote quantum computer can be connected to the local quantum computer via any type of network—including local area networks (LANs) or wide area networks (WANs), or it can be connected to an external quantum computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are personalized by utilizing state information of executable instructions from a quantum computer. These electronic circuits can execute executable instructions from the quantum computer, thereby implementing the various embodiments described herein.

[0098] Various aspects of the present invention are described herein with reference to block diagrams of a crosstalk-aware quantum program compilation framework system, a quantum computer operating system, a quantum computer, and a computer program product according to embodiments herein. It should be understood that each block of the block diagram, and combinations thereof, can be implemented by executable instructions of a quantum computer.

[0099] These quantum computer-executable instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a quantum computing machine such that, when executed by the processor of the quantum computer or other programmable data processing device, these instructions create means for implementing the functions / actions specified in one or more blocks of the block diagram. Alternatively, these executable instructions can be stored in a quantum computer-readable storage medium that causes the quantum computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the quantum computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / processes specified in one or more blocks of the block diagram.

[0100] Quantum computer-readable program instructions can also be loaded onto a quantum computer, other programmable quantum data processing device, or other quantum device to cause a series of processes to be executed on the quantum computer, other programmable quantum data processing device, or other quantum device to produce a process implemented by the quantum computer, thereby causing the instructions executed on the quantum computer, other programmable quantum data processing device, or other quantum device to implement the functions / processes specified in one or more blocks in the block diagram.

[0101] The block diagrams in the accompanying drawings illustrate the architecture, functionality, and processing of possible implementations of a quantum computer operating system, a quantum computer, and a computer program product according to various embodiments of the present invention. In this regard, each block in the block diagram may represent a module, segment, or portion of an instruction, which contains one or more quantum computer-executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram, and combinations of blocks, can be implemented using a dedicated hardware-based quantum system that performs the specified function or action, or using a combination of dedicated hardware and quantum computer instructions. It will be well known to those skilled in the art that implementation in hardware, implementation in software, and implementation using a combination of software and hardware are equivalent.

[0102] The above description, based on the embodiments shown in the figures, details the structure, features, and effects of the present invention. The above description is only a preferred embodiment of the present invention, but the present invention is not limited to the scope of implementation shown in the figures. Any changes made in accordance with the concept of the present invention, or equivalent embodiments modified to have equivalent changes, that do not exceed the spirit covered by the specification and figures, should be within the protection scope of the present invention.

Claims

1. A crosstalk-aware quantum program compilation framework system, comprising: The system includes: a communication connection parameter optimization module, a crosstalk sensing mapping module, and a quantum logic gate scheduling module, wherein... The parameter optimization module is used to optimize the parameters of quantum logic gates in the quantum program to be executed; The crosstalk sensing mapping module is used to receive the parameter optimization results of the parameter optimization module and determine the optimal mapping scheme of the quantum program to be executed by constructing a cost function. The quantum logic gate scheduling module is used to determine the maximum independent set among the qubits in the quantum program to be executed and the parallel quantum logic gate scheduling scheme of the maximum independent set according to the optimal mapping scheme, so as to realize the compilation of the quantum program to be executed. The quantum logic gate scheduling module includes: a crosstalk graph determination unit, used to generate a quantum logic gate crosstalk graph; a crosstalk subgraph determination unit, used to determine the crosstalk subgraphs of the quantum logic gate crosstalk graph; and a maximum independent set determination unit, used to obtain the maximum independent set of all the crosstalk subgraphs by the following method: setting an initial value N for the number of sets in the maximum independent set, searching for the maximum independent set, and stopping if the number of sets in the maximum independent set is less than or equal to N; otherwise, setting K... To determine the maximum number of re-optimization parameters allowed in the quantum chip control system, nodes are selected from largest to smallest degree and placed into N distinct sets. For each set, the number of re-optimization parameters in the crosstalk subgraph corresponding to these nodes is calculated. If all of these parameters are less than K, the process ends; otherwise, the maximum number of independent sets is updated to N+1, and the above steps are repeated. Here, the nodes in the quantum logic gate crosstalk graph represent the set of qubit-coupler-qubit pairs of directly executed dual quantum logic gates, and the edges in the quantum logic gate crosstalk graph represent the parallel crosstalk effect between the qubit-coupler-qubit pairs. The weight of each edge represents the number of parameters that need to be re-optimized for the two quantum logic gates corresponding to that edge during parallel execution.

2. The system of claim 1, wherein, The parameter optimization module includes: The initial parameter optimization unit for dual quantum logic gates and the parallel parameter optimization unit for dual quantum logic gates, wherein, The dual quantum logic gate initial parameter optimization unit is used to determine the optimal frequency of the dual quantum logic gate and the discreteness parameter of the frequency distribution of the dual quantum logic gate in the quantum program to be executed; The parallel parameter optimization unit for dual quantum logic gates is used to optimize the coupler pulse frequency parameters of adjacent dual quantum logic gates.

3. The system of claim 2, wherein, The dual quantum logic gate initial parameter optimization unit optimizes the parameters of the dual quantum logic gates in the quantum program to be executed using the following formula: in, express The optimized frequency of the dual quantum logic gates at specific times. Indicates the idle frequency of the coupler and the qubit. This represents the resonant frequency value of a quantum logic gate. Represents the error function. This indicates the amplitude of the frequency waveform change controlling the two quantum logic gates. This indicates the execution time of a quantum logic gate.

4. The system of claim 1, wherein, The crosstalk-aware mapping module includes: The transformation unit is used to transform the quantum program to be executed into a directed acyclic graph; A determination unit is used to combine the parameter optimization results and determine the optimal mapping scheme of the quantum program to be executed by traversing the directed acyclic graph.

5. The system of claim 4, wherein, The determining unit includes: The pre-gate determination subunit is used to determine the set of pre-quantum logic gates that cannot be directly executed in the topological sequence corresponding to the directed acyclic graph, based on the topological order of the directed acyclic graph and the execution time of the quantum logic gates. The mapping determination subunit is used to sequentially traverse each dual quantum logic gate in the set of preceding quantum logic gates, construct a tree search structure based on SWAP gates, generate all mapping schemes that insert SWAP gates, and determine the optimal mapping scheme of the quantum program to be executed through a cost function.

6. The system of claim 5, wherein, The cost function includes: in, Represents the cost function. This represents the distance cost of each swap door. This indicates a two-quantum logic gate that requires the insertion of a SWAP gate. Represents the set of pre-quantum logic gates. For mapping The sub-items are represented by the mapping. The new mapping obtained after inserting the SWAP gate , and These represent the two qubits that need to be inserted into the SWAP gate.

7. A quantum computer operating system, characterized by, The quantum computer operating system includes a crosstalk-aware quantum program compilation framework system according to any one of claims 1 to 6.

8. A quantum computer, characterized by include: A first quantum computing hardware device, wherein a crosstalk-aware quantum program compilation framework system according to any one of claims 1 to 6 is provided on the first quantum computing hardware device; and A second quantum computing hardware device, which communicates with the first quantum computing hardware device, includes a quantum chip, wherein the communication module of the crosstalk-aware quantum program compilation framework system sends the quantum program to be executed to the second quantum computing hardware device for compilation of the quantum program.

9. A quantum computer readable storage medium, characterized by, The storage medium stores one or more quantum computer-executable instructions, which, when executed by the quantum computer, implement a crosstalk-aware quantum program compilation framework system according to any one of claims 1 to 6.

Images