Low-voltage differential signal communication system and driver thereof

Abstract

The invention discloses low-voltage differential signal equipment and a driver thereof. The driver comprises an output circuit, a biasing circuit and a first clamping circuit, the output circuit comprises a push-pull circuit and a first tail current source arranged between the power supply end and the push-pull circuit; the bias circuit is provided with a bias current generating unit for providing first bias current; the first clamping circuit is used for providing a second bias current for the bias circuit; when the enable signal is a first level, the bias circuit provides a bias voltage with a first preset value for the first tail current source according to the sum of a first bias current and a second bias current, and the driver is in a normal state; when the enable signal is at a second level, the bias circuit provides a bias voltage with a second preset value for the first tail current source according to a second bias current, and the driver is in a high-resistance state; the second preset value is smaller than the voltage value of the power supply end and larger than the first preset value, so that the enabling speed when the output state of the LVDS driver is switched from the high-resistance state to the normal state is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low voltage differential signal communication system and a driver thereof. Background Art

[0002] LVDS (Low Voltage Differential Signaling) is a point-to-point high-speed differential electrical interface designed for applications that require ultra-low power consumption, low noise, and high data rates. Its core is the use of low voltage swing and high-speed differential transmission of data, which enables LVDS technology to achieve low power consumption and improved anti-interference capabilities while ensuring data transmission quality.

[0003] The transmission medium of LVDS technology is flexible and diverse. It can be a copper PCB (Printed Circuit Board) connection or a balanced cable, which makes LVDS have a wide range of application prospects in various electronic devices. Since LVDS adopts differential signal transmission, that is, a pair of signal lines are used to transmit differential signals, common mode noise and other types of interference are effectively suppressed, the signal-to-noise ratio of the signal is significantly improved, and the bit error rate is reduced. LVDS devices are usually composed of LVDS drivers and receivers. The main function of the LVDS driver is to convert the input single-ended signal into a differential signal with a low voltage swing and output it.

[0004] MLVDS (Multi-Point Low Voltage Differential Signaling) has all the advantages of LVDS technology and can be applied to multi-point bus systems. The LVDS communication system using MLVDS technology includes multiple LVDS drivers. There are generally at least two LVDS drivers on the same cable. Therefore, these LVDS drivers need to have an output enable function to ensure that only one selected LVDS driver outputs a signal at the same time on the same cable, and the unselected LVDS driver outputs a high-impedance state Hi-z.

[0005] Figure 1 The figure shows the working timing diagram of two LVDS drivers outputting signals alternately. Figure 1 If two LVDS drivers of an LVDS communication system use the same cable to transmit signals alternately, when one of the LVDS drivers switches from unselected to selected, it needs to be awakened from the high-impedance state Hi-z. Therefore, it takes a period of time T1 to enable the correct signal stably, which will limit the operating frequency of the LVDS communication system.

[0006] Therefore, a new low voltage differential signal communication system and its driver are yet to be proposed to solve the above problems. Summary of the invention

[0007] In view of the above problems, an object of the present invention is to provide a low voltage differential signal communication system and a driver thereof, so as to improve the enabling speed when the output of the low voltage differential signal driver switches from a high impedance state to a normal state.

[0008] According to one aspect of the present invention, a low voltage differential signal driver is provided, the driver having two output states, a high impedance state and a normal state, the driver comprising an output circuit, a bias circuit and a first clamping circuit; the output circuit comprising a push-pull circuit and a first tail current source arranged between a power supply terminal and the push-pull circuit, the push-pull circuit being used to generate a first output signal and a second output signal according to a first input signal and a second input signal; the bias circuit being used to provide a bias voltage to the first tail current source, the bias circuit having a bias current generating unit for providing a first bias current; the first clamping circuit being connected to the bias circuit and being used to provide a second bias current to the bias circuit bias current; wherein the turning on and off of the bias current generating unit is controlled by an enable signal, when the enable signal is at a first level, the bias current generating unit is turned on, so that the bias circuit provides a bias voltage of a first preset value to the first tail current source according to the sum of the first bias current and the second bias current, and the driver is in a normal state; when the enable signal is at a second level, the bias current generating unit is turned off, so that the bias circuit provides a bias voltage of a second preset value to the first tail current source according to the second bias current, and the driver is in a high-impedance state; the second preset value is less than the voltage value of the power supply terminal and greater than the first preset value.

[0009] Optionally, the output circuit also includes a second tail current source arranged between the push-pull circuit and the ground terminal, and the driver also includes: a common-mode feedback circuit, used to compare the common-mode feedback voltage of the first output signal and the second output signal with a reference voltage to provide a bias voltage to the second tail current source according to the comparison result; a second clamping circuit, connected to the common-mode feedback circuit, used to provide a bias voltage of a third preset value to the second tail current source when the enable signal is at a second level, and the third preset value is greater than the voltage value of the ground terminal and less than the range of the bias voltage provided by the common-mode feedback circuit when the driver is in a normal state.

[0010] Optionally, the bias circuit includes the bias current generating unit and a second transistor, the bias current generating unit includes a first current source, a first switch, a second switch, a first transistor and a third transistor; the first current source, the first switch and the first transistor are sequentially connected between a power supply terminal and a ground terminal, the control terminal of the first switch receives an enable signal, and the control terminal of the first transistor is connected to its first terminal; the second switch is connected between the control terminal of the first transistor and the ground terminal, and its control terminal receives an inverted signal of the enable signal; the second transistor and the third transistor are sequentially connected between the power supply terminal and the ground terminal, the control terminal of the second transistor provides a bias voltage to the first tail current source, the control terminal of the second transistor is connected to its second terminal, and the control terminal of the third transistor is connected to the control terminal of the first transistor.

[0011] Optionally, the first clamping circuit includes a second current source and a fourth transistor, which are connected between the power supply terminal and the ground terminal in sequence, the control terminal of the fourth transistor is connected to its first terminal, and the second current source provides a second bias current; a fifth transistor, which is connected between the middle node of the second transistor and the third transistor and the ground terminal, the control terminal of the fifth transistor is connected to the middle node of the second current source and the fourth transistor, and the first terminal of the fifth transistor provides a fourth bias current.

[0012] Optionally, a current value of the first bias current is greater than a current value of the second bias current.

[0013] Optionally, the common-mode feedback circuit includes a first resistor and a second resistor, which are connected in sequence between a positive differential output terminal and a negative differential output terminal, the positive differential output terminal provides the first output signal, and the negative differential output terminal provides the second output signal; an error amplifier, wherein the positive input terminal is connected to an intermediate node between the first resistor and the second resistor, the negative input terminal receives a reference voltage, the output terminal provides the second bias voltage to the second tail current source, and the intermediate node between the first resistor and the second resistor provides the common-mode feedback voltage.

[0014] Optionally, the second clamping circuit includes a third current source and a sixth transistor, which are connected between the power supply terminal and the ground terminal in sequence, the third current source provides a fifth bias current, and the control terminal of the sixth transistor is connected to its first terminal; a third switch is connected between the control terminal of the sixth transistor and the output terminal of the error amplifier, and the control terminal of the third switch receives the inverted signal of the enable signal.

[0015] Optionally, the first tail current source includes a seventh transistor, and the second tail current source includes an eighth transistor.

[0016] Optionally, the first tail current source includes a seventh transistor, the second tail current source includes an eighth transistor, the push-pull circuit includes ninth to twelfth transistors, the seventh transistor, the ninth transistor, the tenth transistor and the eighth transistor are sequentially connected between the power supply terminal and the ground terminal, the control terminal of the seventh transistor receives the first bias voltage, the control terminals of the ninth transistor and the tenth transistor receive the first input signal, the control terminal of the eighth transistor receives the second bias voltage, the intermediate node between the ninth transistor and the tenth transistor is the negative differential output terminal, the eleventh transistor and the twelfth transistor are sequentially connected between the intermediate node between the seventh transistor and the ninth transistor and the intermediate node between the tenth transistor and the eighth transistor, the control terminals of the eleventh transistor and the twelfth transistor receive the second input signal, and the intermediate node between the eleventh transistor and the twelfth transistor is the positive differential output terminal.

[0017] According to another aspect of the present invention, a low voltage differential signal communication system is provided, comprising at least one group of low voltage differential signal transmission lines, one end of each group of low voltage differential signal transmission lines being connected to a low voltage differential signal receiving end, and the other end being connected to at least two low voltage differential signal drivers as described above.

[0018] The present invention provides an LVDS communication system and a driver thereof, wherein the LVDS driver has two output states, a high impedance state and a normal state. When the output is in the high impedance state, the voltage value of the first bias voltage is slightly higher than the voltage value of the first bias voltage in the normal state and is lower than the voltage value of the power supply end, so that when the output state of the LVDS driver is switched from the high impedance state to the normal state, the discharge time of the first gate parasitic capacitance is reduced, so that the first bias voltage can be quickly restored to the voltage value in the normal state, thereby improving the enabling speed when the output of the LVDS driver is switched from the high impedance state to the normal state, and reducing the operating frequency limit of the LVDS communication system using the above-mentioned LVDS driver.

[0019] In a preferred embodiment, when the output state of the LVDS driver is a high-impedance state, the voltage value of the second bias voltage is close to the voltage range of the second bias voltage in the normal state and is greater than the ground voltage, so as to reduce the charging time of the second gate parasitic capacitance when the output state of the LVDS driver is switched from the high-impedance state to the normal state, so that the second bias voltage can be quickly restored to the voltage value in the normal state, thereby further improving the enabling speed when the output state of the LVDS driver is switched from the high-impedance state to the normal state, and further reducing the operating frequency limit of the LVDS communication system using the above-mentioned LVDS driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0021] Figure 1 The working timing diagram of two LVDS drivers outputting signals alternately is shown;

[0022] Figure 2 A circuit diagram of an LVDS driver is shown;

[0023] Figure 3 A circuit diagram of an LVDS driver according to an embodiment of the present invention is shown;

[0024] Figure 4 The LVDS driver according to the embodiment of the present invention is shown. Figure 2 The working timing comparison diagram of the LVDS driver is shown in the figure. DETAILED DESCRIPTION

[0025] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements or modules are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0026] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0027] At the same time, certain words are used in this patent specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.

[0028] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0029] Figure 2 A schematic diagram of a LVDS driver circuit is shown. Figure 2 , the LVDS driver 100 includes a bias circuit, an output circuit, and a common-mode feedback circuit.

[0030] Specifically, the bias circuit includes a current source I1, transistors M1-M3, and switches S1-S3. Among them, transistors M1 and M2 form a current mirror, the current source I1, switch S1, and transistor M1 are sequentially connected between the power supply voltage VDD and the ground terminal, transistors M3 and M2 are sequentially connected between the power supply voltage VDD and the ground terminal, the control end of transistor M1 is connected to its first end and the control end of transistor M2, a switch S2 is further connected between the control end of transistor M1 and the ground terminal, switch S3 is connected between the first end and the second end of transistor M3, the control end of transistor M3 is connected to its second end, the control end of switch S1 receives an enable signal EN, the control ends of switches S2 and S3 receive an enable signal ENB, and the enable signal EN is inverted with the enable signal ENB.

[0031] The output circuit includes transistors M4-M9, transistors M4 and M3 form a current mirror, transistors M4, M6, M8 and M5 are connected between the power supply voltage VDD and the ground terminal in sequence, transistors M7 and M9 are connected between the middle node of transistors M4 and M6 and the middle node of transistors M8 and M5 in sequence, the control end of transistor M4 is connected to the control end of transistor M3, the control ends of transistors M6 and M8 receive input signal Vin1, and the control ends of transistors M7 and M9 receive input signal Vin2. The middle node of transistors M7 and M9 provides output signal Vout+ as a positive differential output end, and the middle node of transistors M6 and M8 provides output signal Vout- as a negative differential output end. The input signal Vin1 is inverted with the input signal Vin2.

[0032] The common-mode feedback circuit includes resistors R1 and R2 and an error amplifier 110. The resistors R1 and R2 are connected between the positive differential output terminal and the negative differential output terminal in sequence, the positive input terminal of the error amplifier 110 is connected to the middle node of the resistors R1 and R2, the negative input terminal receives the reference voltage Vref, and the output terminal is connected to the control terminal of the transistor M5.

[0033] Furthermore, the positive differential output terminal and the negative differential output terminal of the LVDS driver 100 are also connected to the LVDS receiving terminal. The LVDS receiving terminal includes a resistor Rt, capacitors CL1 and CL2, the resistor Rt is connected between the positive differential output terminal and the negative differential output terminal, the capacitor CL1 is connected between the positive differential output terminal and the ground terminal, the capacitor CL2 is connected between the negative differential output terminal and the ground terminal, and the current flowing through the resistor Rt is the driving current Iout.

[0034] When the enable signal EN is at a high level, the bias circuit turns on switch S1, turns off switches S2 and S3, and transistor M2 provides a bias current to transistor M3, so that the control terminal of transistor M3 provides a bias voltage Vbp1 with a voltage value equal to VDD-|Vgs3| (Vgs3 represents the voltage difference between the gate terminal and the source terminal of transistor M3), so as to turn on transistor M4 to provide tail current Is, so that the output circuit can normally generate output signals Vout+ and Vout-; when the enable signal EN is at a low level, the bias circuit turns off switch S1, turns on switches S2 and S3, turns off transistors M2 and M3, and completely turns off the bias current path. At this time, the bias voltage Vbp1 is the power supply voltage VDD, and transistor M4 is turned off. When the enable signal EN is at a high level, the common mode feedback circuit generates a bias voltage Vbn1 according to the comparison result of the common mode feedback voltage of the output signals Vout+ and Vout- and the reference voltage Vref, so that the common mode feedback voltage is stable near the reference voltage Vref. The common-mode feedback circuit also turns off the transistor M5 when the enable signal EN is at a low level. At this time, the bias voltage Vbn1 is equal to the ground voltage GND.

[0035] In order to meet the requirements of output swing and operating frequency, the tail current Is provided by the transistor M4 as an output current source needs to be very large, generally selected as 3.5mA. Therefore, the width-to-length ratio of the transistor M4 is very large, which makes the transistor M4 have a large gate parasitic capacitance Cp1. The gate parasitic capacitance Cp1 causes the bias circuit to take a long time to discharge the bias voltage Vbp1, i.e., the control terminal voltage of the transistor M4, from the power supply voltage VDD to the required potential VDD-|Vgs3| during the enabling process, which greatly delays the enabling time of the LVDS driver 100. In addition, the transistor M5 as a current source also has a gate parasitic capacitance Cp2. The gate parasitic capacitance Cp2 causes the common-mode feedback circuit to take a long time to charge the bias voltage Vbn1 from the ground voltage GND to the required potential during the enabling process, thereby extending the stabilization time of the common-mode feedback loop, resulting in an increase in the enabling time required for the LVDS driver 100.

[0036] In view of the above problems, the present invention provides a new LVDS driver to solve the above problems.

[0037] Figure 3 FIG. 4 is a circuit diagram of an LVDS driver according to an embodiment of the present invention.

[0038] See also Figure 3 The LVDS driver 200 provided in the embodiment of the present invention has two output states: a high impedance state and a normal state. The LVDS driver 200 includes an output circuit 210, a bias circuit 220, a first clamp circuit 230, a common mode feedback circuit 240 and a second clamp circuit 250.

[0039] The output circuit 210 includes a first tail current source, a push-pull circuit, and a second tail current source connected in sequence between a power supply terminal and a ground terminal. The first tail current source is used to generate a first tail current Is according to a bias voltage Vbp2, and the second tail current source is used to generate a second tail current according to a bias voltage Vbn2. The push-pull circuit is used to generate output signals Vout+ and Vout- according to input signals Vin1 and Vin2. When the LVDS driver 200 is in a normal state, the input signals Vin1 and Vin2 are inverted signals, and the output signals Vout+ and Vout- are differential output signals.

[0040] The bias circuit 220 is used to provide a bias voltage Vbp2 to the first tail current source. The bias circuit 220 has a bias current generating unit for providing a bias current I4. The first clamp circuit 230 is connected to the bias circuit 220 and is used to provide a bias current I5 to the bias circuit 220. The enable signal EN controls the on and off of the bias current generating unit. When the enable signal EN is at a first level, the bias current generating unit is turned on, so that the bias circuit 220 provides a bias voltage Vbp2 of a first preset value to the first tail current source according to the sum of the bias current I4 and the bias current I5, and the LVDS driver 200 is in a normal state; when the enable signal EN is at a second level, the bias current generating unit is turned off, so that the bias circuit 220 provides a bias voltage Vbp2 of a second preset value to the first tail current source according to the bias current I5, and the LVDS driver 200 is in a high impedance state. Wherein, the second preset value is less than the voltage value VDD of the power supply terminal and greater than the first preset value.

[0041] The common-mode feedback circuit 240 is used to compare the common-mode feedback voltage of the output signals Vout+ and Vout- with the reference voltage Vref when the LVDS driver 200 is in a normal state, so as to provide a bias voltage Vbn2 to the second tail current source according to the comparison result, so as to adjust the output signals Vout+ and Vout- through the bias voltage Vbn2, so that the common-mode feedback voltage of the output signals Vout+ and Vout- is stabilized near the reference voltage Vref.

[0042] The second clamp circuit 250 is connected to the common mode feedback circuit 240, and is used to provide a bias voltage Vbn2 of a third preset value to the second tail current source when the enable signal EN is at a second level. The third preset value is greater than the voltage value of the ground terminal and less than the range of the bias voltage Vbn2 provided by the common mode feedback circuit 240 when the LVDS driver 200 is in a normal state.

[0043] The push-pull circuit includes transistors M6-M9, the first tail current source is implemented by transistor M4, for example, and the second tail current source is implemented by transistor M5, for example. Transistor M3 and transistor M4 form a current mirror, and the mirror ratio of the current mirror formed by transistors M3 and M4 is 1:M. For example, M>10. Transistors M4, M6, M8 and M5 are connected between the power supply terminal and the ground terminal in sequence, transistors M7 and M9 are connected between the middle node of transistors M4 and M6 and the middle node of transistors M8 and M5 in sequence, the control end of transistor M4 is connected to the control end of transistor M3, the control end of transistor M5 receives the bias voltage Vbn2, the control ends of transistors M6 and M8 receive the input signal Vin1, the control ends of transistors M7 and M9 receive the input signal Vin2, the middle node of transistors M7 and M9 provides the output signal Vout+ as the positive differential output end, and the middle node of transistors M6 and M8 provides the output signal Vout- as the negative differential output end.

[0044] The bias circuit 220 further includes a transistor M2, and the bias current generating unit includes a current source I1, transistors M1, M3, and switches S1-S2. Among them, the transistors M1 and M2 form a current mirror, and the current source I1 is used to provide the bias current I1. The current source I1, the switch S1, and the transistor M1 are sequentially connected between the power supply terminal and the ground terminal, the transistor M3 and the transistor M2 are sequentially connected between the power supply terminal and the ground terminal, the control end of the transistor M1 is connected to its first end and the control end of the transistor M2, the control end of the transistor M3 is connected to its first end, the control end of the transistor M3 provides a bias voltage Vbp2 to the first tail current source, and a switch S2 is also connected between the control end of the transistor M1 and the ground terminal, the control end of the switch S1 receives an enable signal EN, the control end of the switch S2 receives an enable signal ENB, and the second end of the transistor M2 provides a bias current I4. The enable signal ENB is in phase with the enable signal EN, I4=k1*I1 (k1>0), k1 is equal to the mirror ratio of the current mirror formed by the transistors M2 and M1, and k1=1 for example.

[0045] The first clamp circuit 230 includes transistors M10-M11 and a current source I2, and the current source I2 is used to provide a bias current I2. The current source I2 and the transistor M11 are connected between the power supply terminal and the ground terminal in sequence, the transistor M10 is connected between the middle node of the transistors M3 and M2 and the ground terminal, the control terminal of the transistor M10 is connected to the middle node of the current source I2 and the transistor M11, the control terminal of the transistor M11 is connected to its first terminal, and the first terminal of the transistor M10 provides a bias current I5. Wherein, I5=k2*I2(k2>0), for example, k2=1.

[0046] Optionally, the current value of bias current I4 is much greater than the current value of bias current I5. For example, the current value of bias current I4 can be set to be about ten times the current value of bias current I5. By setting the current values ​​of I5 and I4 to I5<I4, the LVDS driver 200 will not generate large power consumption in the high impedance state.

[0047] When the LVDS driver 200 is in a high impedance state, the second end of the transistor M3 receives the bias current I5, and at this time, the bias voltage Vbp2 is equal to the first preset value, namely VDD-|Vgs3_a| (Vgs3_a represents the voltage difference between the gate terminal and the source terminal of the transistor M3 under the influence of the bias current I5). When the LVDS driver 200 is in a normal state, the second end of the transistor M3 receives the bias current I4 and the bias current I5, and at this time, the bias voltage Vbp2 is equal to the second preset value, namely VDD-|Vgs3_b| (Vgs3_b represents the voltage difference between the gate terminal and the source terminal of the transistor M3 under the influence of the sum of the bias currents I4 and I5).

[0048] The common-mode feedback circuit 240 includes resistors R1 and R2 and an error amplifier 231. The resistors R1 and R2 are connected between the positive differential output terminal and the negative differential output terminal in sequence, the positive input terminal of the error amplifier 231 is connected to the middle node of the resistors R1 and R2, the negative input terminal receives the reference voltage Vref, and the output terminal provides a bias voltage Vbn2 to the second tail current source.

[0049] The second clamp circuit 250 includes a current source I3 and a transistor M12 connected in sequence between the power supply terminal VDD and the ground terminal, the current source I3 provides a bias current I3, the control terminal of the transistor M12 is connected to its first terminal, and a switch S3 is further connected between the control terminal of the transistor M12 and the output terminal of the error amplifier 231, and the control terminal of the switch S3 receives an enable signal ENB. The third preset value is equal to Vgs12 (Vgs12 represents the voltage difference between the gate terminal and the source terminal of the transistor M12 under the influence of the bias current I3).

[0050] The working principle of the LVDS driver 200 is as follows: when the enable signal EN is at the second level, the LVDS driver 200 is in a high-impedance state, the switch S2 is turned on, and the transistor M2 is turned off. At this time, although the bias current I4 provided to the transistor M3 is turned off, the bias current I5 provided to the transistor M3 is not turned off, but flows to the ground through the transistor M10. Therefore, the bias voltage Vbp2 is not pulled up to the voltage value VDD at the power supply end, but is pulled to VDD-|Vgs3_a| under the influence of the bias current I5 flowing through the transistor M10, and is maintained by the gate parasitic capacitance Cp1 of the transistor M4. At the same time, the switch S3 is turned on, and the voltage value of the bias voltage Vbn2 is clamped at Vgs12, and is maintained by the gate parasitic capacitance Cp2 of the transistor M5. When the enable signal EN is switched from the second level to the first level, the transistors M1 and M2 are turned on, the bias voltage Vbp2 is quickly pulled down to VDD-|Vgs3_b| by the bias current I4 flowing through the transistor M2, the tail current Is of the transistor M4 is stabilized to a preset value (the preset value is, for example, 3.5 mA), the output of the LVDS driver 200 is stabilized in a normal state, and at the same time, the switch S3 is turned off, the bias voltage Vbn2 is provided by the error amplifier 231, and the common-mode feedback loop quickly stabilizes. For example, the first level is a high level, and the second level is a low level.

[0051] Figure 4 LVDS driver and Figure 2 The working timing comparison diagram of the LVDS driver is shown in the figure.

[0052] See also Figure 4 When the enable signal EN switches from a low level to a high level, indicating that the output state of the LVDS driver needs to switch from a high impedance state to a normal state, the bias voltage Vbp2 of the LVDS driver 200 provided by the present application reaches a second voltage value within a first time T3, and Figure 2 The bias voltage Vbp1 provided by the LVDS driver 100 shown reaches a second voltage value within the second time T2. It can be seen from the figure that the first time T3 is much smaller than the second time T2. Therefore, the enabling speed of the LVDS driver 200 provided in the present application is faster when the output state is switched from a high-impedance state to a normal state.

[0053] Optionally, transistors M3-M4 and transistors M6-M7 are P-channel Metal-Oxide-Semiconductor (PMOS for short), transistors M1-M2, M5 and M8-M12 are N-channel Metal-Oxide-Semiconductor (NMOS for short), the first end of the PMOS is the source end, the second end is the drain end, and the control end is the gate end, the first end of the NMOS is the drain end, the second end is the source end, and the control end is the gate end.

[0054] The LVDS driver 200 provided in the embodiment of the present invention has two output states, namely a high-impedance state and a normal state. When the output state is the high-impedance state, the voltage value of the bias voltage Vbp2 is slightly higher than the voltage value of the bias voltage Vbp2 in the normal state and is lower than the voltage value VDD of the power supply terminal, and the voltage value of the bias voltage Vbn2 is close to the voltage range of the bias voltage Vbn2 in the normal state and is higher than the ground voltage GND, so that when the output state of the LVDS driver 200 is switched from the high-impedance state to the normal state, the discharge time of the gate parasitic capacitance Cp1 is reduced, so that the bias voltage Vbp2 can be quickly restored to the voltage value in the normal state, and the charging time of the gate parasitic capacitance Cp2 is reduced, so that the bias voltage Vnp2 can be quickly restored to the voltage value in the normal state, thereby improving the enabling speed when the output of the LVDS driver 200 is switched from the high-impedance state to the normal state, and reducing the operating frequency limit of the LVDS communication system using the LVDS driver 200.

[0055] Furthermore, the present invention also provides an LVDS communication system, which includes at least one group of low voltage differential signal transmission lines, one end of each group of low voltage differential signal transmission lines is connected to the LVDS receiving end, and the other end is connected to at least two LVDS drivers 200, wherein a group of low voltage differential signal transmission lines includes two transmission lines to transmit output signals Vout+ and Vout- respectively. The LVDS receiving end can be, for example, Figure 2 The LVDS receiver is shown.

[0056] When a group of low voltage differential signal transmission lines are transmitting signals, only one of the at least two LVDS drivers 200 is in a normal state, and the others are in a high impedance state. When the LVDS driver 200 is in a high impedance state, the connection between it and the low voltage differential signal transmission line is disconnected, and the transistors M6-M9 are turned off by the voltage at their control terminals so that the push-pull circuit has no signal output.

[0057] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention and their equivalents.

Claims

1. A low voltage differential signal driver, the driver having two output states: a high impedance state and a normal state, the driver comprising an output circuit, a bias circuit and a first clamping circuit; The output circuit comprises a push-pull circuit and a first tail current source arranged between a power supply terminal and the push-pull circuit, wherein the push-pull circuit is used to generate a first output signal and a second output signal according to a first input signal and a second input signal; The bias circuit is used to provide a bias voltage to the first tail current source, and the bias circuit has a bias current generating unit for providing a first bias current; The first clamping circuit is connected to the bias circuit and is used to provide a second bias current to the bias circuit; Wherein, the turning on and off of the bias current generating unit is controlled by an enable signal. When the enable signal is at a first level, the bias current generating unit is turned on, so that the bias circuit provides a bias voltage of a first preset value to the first tail current source according to the sum of the first bias current and the second bias current, and the driver is in a normal state; when the enable signal is at a second level, the bias current generating unit is turned off, so that the bias circuit provides a bias voltage of a second preset value to the first tail current source according to the second bias current, and the driver is in a high-impedance state; The second preset value is smaller than the voltage value of the power supply end and larger than the first preset value.

2. The driver according to claim 1, wherein the output circuit further comprises a second tail current source arranged between the push-pull circuit and the ground terminal, and the driver further comprises: a common-mode feedback circuit, configured to compare a common-mode feedback voltage of the first output signal and the second output signal with a reference voltage, so as to provide a bias voltage to the second tail current source according to a comparison result; A second clamping circuit is connected to the common-mode feedback circuit, and is used to provide a bias voltage of a third preset value to the second tail current source when the enable signal is at a second level, and the third preset value is greater than the voltage value of the ground terminal and less than the range of the bias voltage provided by the common-mode feedback circuit when the driver is in a normal state.

3. The driver according to claim 1, wherein: The bias circuit includes the bias current generating unit and a second transistor, wherein the bias current generating unit includes a first current source, a first switch, a second switch, a first transistor and a third transistor; The first current source, the first switch, and the first transistor are sequentially connected between a power supply terminal and a ground terminal, a control terminal of the first switch receives an enable signal, and a control terminal of the first transistor is connected to a first terminal thereof; The second switch is connected between the control terminal and the ground terminal of the first transistor, and the control terminal thereof receives an inverted signal of the enable signal; The second transistor and the third transistor are connected between the power supply terminal and the ground terminal in sequence. The control terminal of the second transistor provides a bias voltage to the first tail current source. The control terminal of the second transistor is connected to its second terminal. The control terminal of the third transistor is connected to the control terminal of the first transistor.

4. The driver according to claim 3, wherein: The first clamping circuit comprises: A second current source and a fourth transistor are connected between the power supply terminal and the ground terminal in sequence, and the control terminal of the fourth transistor is connected to the first terminal thereof; A fifth transistor is connected between an intermediate node between the second transistor and the third transistor and a ground terminal, and a control terminal of the fifth transistor is connected to an intermediate node between the second current source and the fourth transistor.

5. The driver according to claim 1, wherein: A current value of the first bias current is greater than a current value of the second bias current.

6. The driver according to claim 2, wherein: The common mode feedback circuit comprises: A first resistor and a second resistor are connected in sequence between a positive differential output terminal and a negative differential output terminal, the positive differential output terminal provides the first output signal, and the negative differential output terminal provides the second output signal; An error amplifier, wherein the positive input terminal is connected to the middle node between the first resistor and the second resistor, the negative input terminal receives a reference voltage, the output terminal provides a bias voltage to the second tail current source, and the middle node between the first resistor and the second resistor provides the common-mode feedback voltage.

7. The driver according to claim 3, wherein: The second clamping circuit comprises: A third current source and a sixth transistor are connected between the power supply terminal and the ground terminal in sequence, and the control terminal of the sixth transistor is connected to the first terminal thereof; The third switch is connected between the control terminal of the sixth transistor and the output terminal of the error amplifier, and the control terminal of the third switch receives an inverted signal of the enable signal.

8. The driver according to claim 1, wherein: The first tail current source includes a seventh transistor, and the second tail current source includes an eighth transistor.

9. The driver according to claim 8, wherein: The push-pull circuit includes ninth to twelfth transistors, The seventh transistor, the ninth transistor, the tenth transistor and the eighth transistor are sequentially connected between the power supply terminal and the ground terminal, the control terminals of the ninth transistor and the tenth transistor receive the first input signal, and the middle node between the ninth transistor and the tenth transistor is the negative differential output terminal. The eleventh transistor and the twelfth transistor are connected in sequence between the intermediate node of the seventh transistor and the ninth transistor and the intermediate node of the tenth transistor and the eighth transistor, the control end of the eleventh transistor and the twelfth transistor receives the second input signal, and the intermediate node of the eleventh transistor and the twelfth transistor is the positive differential output end.

10. A low voltage differential signal communication system, comprising: At least one set of low voltage differential signal transmission lines, One end of each group of the low voltage differential signal transmission lines is connected to a low voltage differential signal receiving end, and the other end is connected to at least two low voltage differential signal drivers according to any one of claims 1 to 9.

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